Wake-up circuit, SOC system and wake-up method thereof

Abstract

This invention provides a wake-up circuit, comprising: an asynchronous module that executes a set task based on an external clock and generates an end flag as a wake-up signal; a mode selection module that starts system mode recognition based on the wake-up signal and generates a high-frequency enable signal when in idle mode and a low-frequency enable signal when in sleep mode; a low-frequency source clock generation module that generates a low-frequency source clock when woken up by the low-frequency enable signal; a low-frequency source clock stabilization module that generates a low-frequency stable signal after the low-frequency source clock generation module is woken up for a first set time; a high-frequency source clock generation module that generates a high-frequency source clock when woken up by either the high-frequency enable signal or the low-frequency stable signal; and a high-frequency source clock stabilization module that generates a high-frequency stable signal after the high-frequency source clock generation module is woken up for a second set time. The wake-up circuit provided by this invention solves the problem of existing sleep modes requiring a separate pin for external wake-up, which leads to the occupation of circuit pins.

Description

Technical Field

[0001] This invention relates to the field of low-power design, and in particular to a wake-up circuit, a SOC system, and a wake-up method thereof. Background Technology

[0002] To ensure low-power operation of electronic devices, SOC (System on Chip) circuits are generally designed with idle or sleep modes. When the circuit finishes processing all tasks, it will enter idle or sleep mode. When the circuit needs to process tasks again, it can be woken up by a wake-up signal to return to the working mode.

[0003] In a typical SOC circuit, there are two source clocks: a low-frequency one and a high-frequency one. When the circuit is in idle mode, the high-frequency source clock is turned off, while the low-frequency source clock continues to operate normally. When a functional module operating in the low-frequency domain completes a task within a set time, it generates a wake-up signal to wake up the circuit. Thus, in this mode, only the functional modules operating in the high-frequency domain are put into sleep mode. When the circuit is in sleep mode, both the high-frequency and low-frequency source clocks are turned off. In this case, the circuit can only be woken up by an external wake-up signal.

[0004] Although the sleep mode shuts down both the high-frequency and low-frequency source clocks, resulting in low circuit power consumption, it requires a separate external port for wake-up. When the circuit package has a limited number of pins, there may not be any extra pins available as wake-up pins for external wake-up. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a wake-up circuit, a SOC system and a wake-up method thereof, to solve the problem that the SOC circuit sleep mode requires a separate pin for external wake-up, resulting in the occupation of circuit pins.

[0006] To achieve the above and other related objectives, the present invention provides a wake-up circuit for use in a SOC system, the wake-up circuit comprising:

[0007] The asynchronous module executes a set task based on an external clock and generates an end flag as a wake-up signal when the set task is completed;

[0008] The mode selection module is connected to the output of the asynchronous module. It starts system mode recognition based on the wake-up signal and generates a high-frequency enable signal when the SOC system is in idle mode and a low-frequency enable signal when the SOC system is in sleep mode.

[0009] A low-frequency source clock generation module is connected to the output of the mode selection module, and is awakened by the low-frequency enable signal to generate a low-frequency source clock.

[0010] A low-frequency source clock stabilization module is connected to the output terminal of the low-frequency source clock generation module. After the low-frequency source clock generation module is woken up, it stabilizes the low-frequency source clock and generates a low-frequency stable signal after a first set time.

[0011] A high-frequency source clock generation module is connected to the output of the mode selection module and the low-frequency source clock stabilization module, and generates a high-frequency source clock based on the high-frequency enable signal or the low-frequency stabilization signal being woken up.

[0012] A high-frequency source clock stabilization module is connected to the output terminal of the high-frequency source clock generation module. After the high-frequency source clock generation module is woken up, it stabilizes the high-frequency source clock and generates a high-frequency stable signal after a second set time.

[0013] Optionally, the asynchronous module includes an asynchronous communication module, wherein the end flag includes an address matching completion flag or a data transmission termination flag.

[0014] Optionally, the mode selection module performs system mode recognition based on the data stored in the CPU status register and the mode status register.

[0015] Optionally, the low-frequency source clock generation module is implemented using a low-frequency oscillator, and the low-frequency source clock stabilization module is implemented using at least one counter; the high-frequency source clock generation module is implemented using a high-frequency oscillator, and the high-frequency source clock stabilization module is implemented using at least one counter.

[0016] Optionally, the wake-up circuit further includes: a clock division and control module, connected to the output terminals of the low-frequency source clock generation module and the high-frequency source clock generation module, performing frequency division processing on the low-frequency source clock and the high-frequency source clock to generate multiple working clocks, and performing output control on the multiple working clocks based on the low-frequency stable signal and the high-frequency stable signal.

[0017] The present invention also provides a SOC system, the SOC system comprising: a wake-up circuit as described in any of the preceding claims.

[0018] The present invention also provides a wake-up method for a SOC system, the wake-up method comprising:

[0019] The asynchronous module executes a set task based on an external clock and generates an end flag as a wake-up signal when the set task is completed;

[0020] The mode selection module begins system mode recognition based on the wake-up signal;

[0021] If the SOC system is in sleep mode, the mode selection module generates a low-frequency enable signal, which wakes up the low-frequency source clock generation module and generates a low-frequency source clock. The low-frequency source clock stabilization module stabilizes the low-frequency source clock after a first set time and generates a low-frequency stable signal. The high-frequency source clock generation module is woken up based on the low-frequency stable signal and generates a high-frequency source clock. The high-frequency source clock stabilization module stabilizes the high-frequency source clock after a second set time and generates a high-frequency stable signal.

[0022] If the SOC system is in idle mode, the mode selection module generates a high-frequency enable signal, which wakes up the high-frequency source clock generation module and generates a high-frequency source clock. The high-frequency source clock stabilization module stabilizes the high-frequency source clock after a second set time and generates a high-frequency stable signal.

[0023] If the SOC system is in working mode, the mode selection module will generate invalid output.

[0024] Optionally, the asynchronous module includes an asynchronous communication module, wherein the method for generating the wake-up signal includes: the asynchronous communication module generating an address matching completion flag bit as the wake-up signal when address matching is completed, or the asynchronous communication module generating a data transmission termination bit as the wake-up signal when data transmission is completed.

[0025] Optionally, the method for performing system pattern recognition includes: the mode selection module determines whether the SOC system is in a working state or a non-working state based on the data stored in the CPU status register, and when it is determined that the SOC system is in a non-working state, it determines whether the SOC system is in an idle mode or a hibernation mode based on the data stored in the mode status register.

[0026] Optionally, the method for generating the low-frequency stable signal includes: the low-frequency source clock stabilization module starts counting when the low-frequency source clock generation module is woken up, and generates the low-frequency stable signal when the count value reaches a first set value;

[0027] The method for generating the high-frequency stable signal includes: the high-frequency source clock stabilization module starts counting when the high-frequency source clock generation module is woken up, and generates the high-frequency stable signal when the count value reaches a second set value.

[0028] Optionally, the wake-up method further includes: a clock division and control module performing frequency division processing on the low-frequency source clock to generate at least one low-frequency working clock, and generating a low-frequency gating signal based on the low-frequency stable signal to control the output of the low-frequency working clock; and performing frequency division processing on the high-frequency source clock to generate at least one high-frequency working clock, and generating a high-frequency gating signal based on the high-frequency stable signal to control the output of the high-frequency working clock.

[0029] As described above, the wake-up circuit, SOC system, and wake-up method of the present invention utilize an asynchronous module to generate a wake-up signal, which can wake up not only the idle mode of the SOC system but also the sleep mode of the SOC system. Since the asynchronous module does not require additional package pins, it avoids the problem of not having enough package pins to achieve external wake-up when the circuit package pins are limited. Moreover, the asynchronous module does not require the participation of the high and low frequency source clocks of the SOC system when it is working. Therefore, after completing the corresponding task, the SOC system can turn off the high and low frequency source clocks and enter the sleep mode, thereby reducing system power consumption. Attached Figure Description

[0030] Figure 1 The diagram shown is a schematic of the wake-up circuit of the present invention.

[0031] Figure 2 The diagram shown is a schematic of the SOC system of the present invention.

[0032] Component designation explanation

[0033] 10 SOC System

[0034] 100 Wake-up Circuit

[0035] 101 Asynchronous Modules

[0036] 102 Mode Selection Module

[0037] 103 Low-frequency clock generation module

[0038] 104 Low-frequency source clock stabilization module

[0039] 105 High-Frequency Clock Generation Module

[0040] 106 High-Frequency Source Clock Stabilization Module

[0041] 107 Clock Division and Control Module

[0042] 200 CPU circuit

[0043] 300 Functional Circuit 1 - Functional Circuit n

[0044] 400 Data Processing Circuit Detailed Implementation

[0045] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0046] Please see Figures 1 to 2 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation, the shape, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0047] like Figure 1 As shown, this embodiment provides a wake-up circuit 100, which can be applied to a SOC system; the wake-up circuit 100 includes: an asynchronous module 101, a mode selection module 102, a low-frequency source clock generation module 103, a low-frequency source clock stabilization module 104, a high-frequency source clock generation module 105, and a high-frequency source clock stabilization module 106; furthermore, the wake-up circuit 100 also includes: a clock frequency division and control module 107.

[0048] The asynchronous module 101 executes a set task based on an external clock and generates an end flag as a wake-up signal WK when the set task is completed.

[0049] Since the asynchronous module 101 does not require a low-frequency source clock, a high-frequency source clock, or their derived clocks to operate, it can work normally in idle or sleep mode and generate an end flag upon completion of the set task. This embodiment utilizes the aforementioned characteristics of the asynchronous module 101, reusing it as a wake-up signal generation circuit to achieve wake-up from idle or sleep mode. It should be noted that the asynchronous module 101 is an existing module in the SOC system; therefore, the wake-up scheme in this embodiment does not occupy any additional package pins.

[0050] As an example, asynchronous module 101 includes an asynchronous communication module, such as an asynchronous I2C module or an asynchronous UART module; wherein, the end flag includes an address matching completion flag or a data transmission termination flag. Of course, asynchronous module 101 can also be other asynchronous functional modules besides asynchronous communication modules, which has no substantial impact on this embodiment.

[0051] The mode selection module 102 is connected to the output of the asynchronous module 101. It begins system mode recognition based on the wake-up signal WK, and generates a high-frequency enable signal EN_HF when the SOC system is in idle mode, and a low-frequency enable signal EN_LF when the SOC system is in sleep mode. Furthermore, the mode selection module 102 also generates an invalid enable signal, such as no output, when the SOC system is in working mode.

[0052] As an example, the mode selection module 102 performs system mode recognition based on the data stored in the CPU status register and the mode status register; specifically, the mode selection module 102 determines whether the CPU is working based on the data stored in the CPU status register, thereby determining whether the SOC system is in a working state or a non-working state, and when it is determined that the SOC system is in a non-working state, it determines whether the SOC system is in an idle mode or a hibernation mode based on the data stored in the mode status register.

[0053] If the mode selection module 102 is woken up based on the wake-up signal WK and reads the data stored in the CPU status register, and if the data stored in the CPU status register is "START", it means that the CPU is working. Then the mode selection module 102 determines that the SOC system is in working state and generates an invalid enable signal.

[0054] If the data stored in the CPU status register is "STOP", it means that the CPU has stopped working. Then the mode selection module 102 determines that the SOC system is in a non-working state. At this time, the mode selection module 102 reads the data stored in the mode status register.

[0055] If the data stored in the mode status register is "0", the mode selection module 102 determines that the SOC system is in idle mode and generates a high-frequency enable signal EN_HF;

[0056] If the data stored in the mode status register is "1", the mode selection module 102 determines that the SOC system is in sleep mode and generates a low-frequency enable signal EN_LF.

[0057] The low-frequency source clock generation module 103 is connected to the output of the mode selection module 102, and is awakened based on the low-frequency enable signal EN_LF to generate the low-frequency source clock CLK_LF.

[0058] As an example, the low-frequency source clock generation module 103 is implemented using a low-frequency oscillator, the frequency of which can be designed according to specific requirements, and this embodiment does not impose any restrictions on it.

[0059] The low-frequency source clock stabilization module 104 is connected to the output terminal of the low-frequency source clock generation module 103. It is used to stabilize the low-frequency source clock CLK_LF and generate the low-frequency stable signal Flag_LF after the low-frequency source clock generation module 103 is woken up.

[0060] As an example, the low-frequency source clock stabilization module 104 is implemented using at least one counter, which starts counting when the low-frequency source clock generation module 103 is woken up, and generates a low-frequency stabilization signal Flag_LF when the count value reaches a first set value. In practical applications, the length of the first set time can be designed according to the magnitude of the first set value, based on specific requirements.

[0061] The high-frequency source clock generation module 105 is connected to the output of the mode selection module 102 and the output of the low-frequency source clock stabilization module 104. It is awakened by the high-frequency enable signal EN_HF or the low-frequency stabilization signal Flag_LF and generates the high-frequency source clock CLK_HF.

[0062] As an example, the high-frequency source clock generation module 105 is implemented using a high-frequency oscillator, the frequency of which can be designed according to specific requirements, and this embodiment does not impose any restrictions on it.

[0063] The high-frequency source clock stabilization module 106 is connected to the output terminal of the high-frequency source clock generation module 105. It is used to stabilize the high-frequency source clock CLK_HF and generate the high-frequency stable signal Flag_HF after the high-frequency source clock generation module 105 is woken up and after a second set time.

[0064] As an example, the high-frequency source clock stabilization module 106 is implemented using at least one counter, which starts counting when the high-frequency source clock generation module 105 is woken up, and generates a high-frequency stabilization signal Flag_HF when the count value reaches a second set value. In practical applications, the length of the second set time can be designed according to the magnitude of the second set value, depending on specific requirements; in addition, the first set value and the second set value can be the same or different, but generally they are different, and the first set value is less than the second set value.

[0065] The clock division and control module 107 is connected to the output of the low-frequency source clock generation module 103 and the output of the high-frequency source clock generation module 105. It is also connected to the output of the low-frequency source clock stabilization module 104 and the high-frequency source clock stabilization module 106. It is used to divide the low-frequency source clock CLK_LF and the high-frequency source clock CLK_HF to generate multiple working clocks, and to control the output of the multiple working clocks based on the low-frequency stabilization signal Flag_LF and the high-frequency stabilization signal Flag_HF.

[0066] In practical applications, the clock division and control module 107 divides the low-frequency source clock CLK_LF and the high-frequency source clock CLK_HF according to specific requirements to generate the required working clock frequency, such as CPU clock, system clock, internal function clock, peripheral clock, etc.

[0067] Correspondingly, such as Figure 2 As shown, this embodiment also provides a SOC system 10, which includes a wake-up circuit 100 as described above.

[0068] Furthermore, the SOC system 10 also includes a CPU circuit 200 and multiple functional circuits 300, such as functional circuits 1 to n (n>1), which are connected to the output of the clock divider and control module 107; wherein, the CPU circuit 200 and the multiple functional circuits 300 execute their own set tasks based on the corresponding working clock.

[0069] In addition, when the asynchronous module 101 is an asynchronous communication module, the SOC system 10 also includes a data processing circuit 400, which is connected to the output terminal of the asynchronous module 101 and the output terminal of the clock division and control module 107. It receives and stores the communication data transmitted by the asynchronous module 101 based on the corresponding working clock. Of course, the data processing circuit 400 can also perform corresponding data processing on the received communication data according to specific needs.

[0070] Accordingly, this embodiment also provides a wake-up method for a SOC system, which includes steps 1) and 2); further, the wake-up method also includes step 3). The SOC system is the SOC system 10 described above.

[0071] Step 1) The asynchronous module 101 executes the set task based on the external clock CLK_EXT, and generates an end flag as a wake-up signal WK when the set task is completed.

[0072] As an example, asynchronous module 101 includes an asynchronous communication module, such as an asynchronous I2C module or an asynchronous UART module; in this case, the method for generating a wake-up signal includes: the asynchronous communication module generating an address matching completion flag bit as a wake-up signal WK when address matching is completed, or the asynchronous communication module generating a data transmission termination bit as a wake-up signal WK when data transmission is completed.

[0073] Step 2) The mode selection module 102 starts system mode recognition based on the wake-up signal WK.

[0074] As an example, the method for performing system pattern recognition includes: the pattern selection module 102 determines whether the SOC system is in a working state or a non-working state based on the data stored in the CPU status register, and when the SOC system is determined to be in a non-working state, it determines whether the SOC system is in an idle mode or a hibernation mode based on the data stored in the mode status register. The specific determination method can be found in the previous text and will not be repeated here.

[0075] 2-1) If the SOC system is in sleep mode (at this time, both the low-frequency source clock generation module 103 and the high-frequency source clock generation module 105 are turned off), the mode selection module 102 generates a low-frequency enable signal EN_LF, which wakes up the low-frequency source clock generation module 103 and generates a low-frequency source clock CLK_LF. The low-frequency source clock stabilization module 104 stabilizes the low-frequency source clock CLK_LF after a first set time and generates a low-frequency stabilization signal Flag_LF. The high-frequency source clock generation module 105 is woken up based on the low-frequency stabilization signal Flag_LF and generates a high-frequency source clock CLK_HF. The high-frequency source clock stabilization module 106 stabilizes the high-frequency source clock CLK_HF after a second set time and generates a high-frequency stabilization signal Flag_HF. In this way, the SOC system is woken up from sleep mode and enters working mode.

[0076] As an example, the method for generating the low-frequency stable signal Flag_LF includes: the low-frequency source clock stabilization module 104 starts counting when the low-frequency source clock generation module 103 is woken up, and generates the low-frequency stable signal Flag_LF when the count value reaches a first set value.

[0077] As an example, a method for generating a high-frequency stable signal Flag_HF includes: the high-frequency source clock stabilization module 106 starts counting when the high-frequency source clock generation module 105 is woken up, and generates the high-frequency stable signal Flag_HF when the count value reaches a second set value.

[0078] In practical applications, a first set time can be designed using a first set value and a second set time can be designed using a second set value, depending on specific needs. The first set value and the second set value can be the same or different, but in general they are different, and the first set value is less than the second set value.

[0079] 2-2) If the SOC system is in idle mode (at this time, the low-frequency source clock generation module 103 is working normally and the high-frequency source clock generation module 105 is turned off), the mode selection module 102 generates a high-frequency enable signal EN_HF, which wakes up the high-frequency source clock generation module 105 and generates a high-frequency source clock CLK_HF. The high-frequency source clock stabilization module 106 stabilizes the high-frequency source clock CLK_HF after a second set time and generates a high-frequency stabilization signal Flag_HF. In this way, the SOC system is woken up from the idle mode and enters the working mode.

[0080] 2-3) If the SOC system is in working mode (at this time, both the low-frequency source clock generation module 103 and the high-frequency source clock generation module 105 are working normally), the mode selection module 102 will generate an invalid output. If there is no output, the low-frequency source clock generation module 103 and the high-frequency source clock generation module 105 will not be enabled.

[0081] Step 3) The clock division and control module 107 divides the low-frequency source clock CLK_LF to generate at least one low-frequency operating clock, and generates a low-frequency gating signal based on the low-frequency stable signal Flag_LF to control the output of the low-frequency operating clock; and divides the high-frequency source clock CLK_HF to generate at least one high-frequency operating clock, and generates a high-frequency gating signal based on the high-frequency stable signal Flag_HF to control the output of the high-frequency operating clock; thereby providing the corresponding operating clock for the corresponding circuit.

[0082] In summary, the wake-up circuit, SOC system, and wake-up method of this invention utilize an asynchronous module to generate a wake-up signal, which can wake up not only the SOC system from its idle mode but also from its sleep mode. Because the asynchronous module requires no additional package pins, it avoids the problem of insufficient package pins for external wake-up when circuit package pins are limited. Furthermore, the asynchronous module does not require the participation of the SOC system's high and low frequency source clocks during operation; therefore, the SOC system can turn off the high and low frequency source clocks and enter sleep mode after completing its tasks, thereby reducing system power consumption. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0083] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A wake-up circuit, applied in a SOC system, characterized in that, The wake-up circuit includes: The asynchronous module executes a set task based on an external clock and generates an end flag as a wake-up signal when the set task is completed; The mode selection module is connected to the output of the asynchronous module. It starts system mode recognition based on the wake-up signal and generates a high-frequency enable signal when the SOC system is in idle mode and a low-frequency enable signal when the SOC system is in sleep mode. A low-frequency source clock generation module is connected to the output of the mode selection module, and is awakened by the low-frequency enable signal to generate a low-frequency source clock. A low-frequency source clock stabilization module is connected to the output terminal of the low-frequency source clock generation module. After the low-frequency source clock generation module is woken up, it stabilizes the low-frequency source clock and generates a low-frequency stable signal after a first set time. A high-frequency source clock generation module is connected to the output of the mode selection module and the low-frequency source clock stabilization module, and generates a high-frequency source clock based on the high-frequency enable signal or the low-frequency stabilization signal being woken up. A high-frequency source clock stabilization module is connected to the output terminal of the high-frequency source clock generation module. After the high-frequency source clock generation module is woken up, it stabilizes the high-frequency source clock and generates a high-frequency stable signal after a second set time.

2. The wake-up circuit of claim 1, wherein, The asynchronous module includes an asynchronous communication module, wherein the end flag includes an address matching completion flag or a data transmission termination flag.

3. The wake-up circuit of claim 1, wherein, The mode selection module performs system mode recognition based on the data stored in the CPU status register and the mode status register.

4. The wake-up circuit of claim 1, wherein, The low-frequency source clock generation module is implemented using a low-frequency oscillator, and the low-frequency source clock stabilization module is implemented using at least one counter; the high-frequency source clock generation module is implemented using a high-frequency oscillator, and the high-frequency source clock stabilization module is implemented using at least one counter.

5. The wake-up circuit according to any one of claims 1 to 4, characterized in that, The wake-up circuit further includes a clock division and control module, which is connected to the output terminals of the low-frequency source clock generation module and the high-frequency source clock generation module. The module performs frequency division processing on the low-frequency source clock and the high-frequency source clock to generate multiple working clocks, and performs output control on the multiple working clocks based on the low-frequency stable signal and the high-frequency stable signal.

6. A SOC system, characterized by, The SOC system includes: a wake-up circuit as described in any one of claims 1-5.

7. A wake-up method of a SOC system, the method comprising: The wake-up method includes: The asynchronous module executes a set task based on an external clock and generates an end flag as a wake-up signal when the set task is completed; The mode selection module begins system mode recognition based on the wake-up signal; If the SOC system is in sleep mode, the mode selection module generates a low-frequency enable signal, which wakes up the low-frequency source clock generation module and generates a low-frequency source clock. The low-frequency source clock stabilization module stabilizes the low-frequency source clock after a first set time and generates a low-frequency stable signal. The high-frequency source clock generation module is woken up based on the low-frequency stable signal and generates a high-frequency source clock. The high-frequency source clock stabilization module stabilizes the high-frequency source clock after a second set time and generates a high-frequency stable signal. If the SOC system is in idle mode, the mode selection module generates a high-frequency enable signal, which wakes up the high-frequency source clock generation module and generates a high-frequency source clock. The high-frequency source clock stabilization module stabilizes the high-frequency source clock after a second set time and generates a high-frequency stable signal. If the SOC system is in working mode, the mode selection module will generate invalid output.

8. The wake-up method of the SOC system according to claim 7, wherein, The asynchronous module includes an asynchronous communication module, wherein the method for generating the wake-up signal includes: the asynchronous communication module generating an address matching completion flag bit as the wake-up signal when address matching is completed, or the asynchronous communication module generating a data transmission termination bit as the wake-up signal when data transmission is completed.

9. The wake-up method for a SOC system according to claim 7, characterized in that, The method for performing system pattern recognition includes: the mode selection module determines whether the SOC system is in a working state or a non-working state based on the data stored in the CPU status register, and when it is determined that the SOC system is in a non-working state, it determines whether the SOC system is in an idle mode or a hibernation mode based on the data stored in the mode status register.

10. The wake-up method of the SOC system according to claim 7, wherein, The method for generating the low-frequency stable signal includes: the low-frequency source clock stabilization module starts counting when the low-frequency source clock generation module is woken up, and generates the low-frequency stable signal when the count value reaches a first set value; The method for generating the high-frequency stable signal includes: the high-frequency source clock stabilization module starts counting when the high-frequency source clock generation module is woken up, and generates the high-frequency stable signal when the count value reaches a second set value.

11. The wake-up method of the SOC system according to any one of claims 7-10, wherein, The wake-up method further includes: a clock division and control module performing frequency division processing on the low-frequency source clock to generate at least one low-frequency working clock, and generating a low-frequency gating signal based on the low-frequency stable signal to output control the low-frequency working clock; and performing frequency division processing on the high-frequency source clock to generate at least one high-frequency working clock, and generating a high-frequency gating signal based on the high-frequency stable signal to output control the high-frequency working clock.

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