Microcode patch loading method for a processor

Abstract

The application provides a microcode patch loading method of a processor, comprising the following steps: a security module checks whether there is a valid microcode patch in an external memory; if yes, the security module writes the valid microcode patch into a special memory area corresponding to a processor core on the memory, and sets a microcode patch flag bit of the special memory area to be valid; a reset of the processor core is released; the processor core checks whether the microcode patch flag bit of the special memory area is valid, if yes, the processor core acquires and authenticates the valid microcode patch from the special memory area, if the authentication is successful, the processor core loads the valid microcode patch and updates a microcode patch version number. The application can optimize a microcode patch loading process and increase system security.

Description

Technical Field

[0001] This invention relates to the field of processor technology, and in particular to a method for loading microcode patches for processors. Background Technology

[0002] Microcode, also known as microinstructions, is a series of relatively simple instructions broken down from complex instructions within a Complex Instruction Set Computing (CSIC) architecture. Given the size and complexity of microcode, it may contain errors. Therefore, modern processors support fixing microcode errors through software-based microcode patches. Microcode patches are released by processor manufacturers in the form of firmware.

[0003] Regarding the timing of microcode patch loading, there are currently three approaches:

[0004] (1) Actively loaded during the BIOS (Basic Input Output System) startup phase;

[0005] (2) Actively loaded during the OS (Operating System) startup phase;

[0006] (3) Under the OS, hot loading is achieved through kernel drivers.

[0007] Microcode patches need to be loaded every time the system starts. Typically, the system combines "BIOS loading + OS boot loading + OS hot-loading," and the microcode patch versions loaded at different stages may be different. This means that different versions of microcode patches need to be loaded multiple times during the system startup process. This is detrimental to system security. Summary of the Invention

[0008] In view of this, the present invention provides a microcode patch loading method for processors, which can optimize the microcode patch loading process and increase system security.

[0009] This invention provides a microcode patch loading method for a processor, the processor including a processor core and a security module, the security module being connected to external memory, and the microcode patch loading method comprising:

[0010] During the processor startup phase, the security module checks whether there is a valid microcode patch in the external memory;

[0011] If a valid microcode patch exists, the security module writes the valid microcode patch into a dedicated memory region in memory corresponding to the processor core, and sets the microcode patch flag of the dedicated memory region to be valid. If no valid microcode patch exists, the security module sets the microcode patch flag of the dedicated memory region to be invalid.

[0012] The security module releases the processor core from reset;

[0013] The processor core checks whether the microcode patch flag in the dedicated memory area is valid. If the microcode patch flag is valid, it retrieves and authenticates the valid microcode patch from the dedicated memory area. If the authentication is successful, it loads the valid microcode patch and updates the microcode patch version number.

[0014] Optionally, the security module checks whether a valid microcode patch exists in the external memory, including:

[0015] Check if there are microcode patches in the external storage;

[0016] If a microcode patch exists, determine whether the microcode patch is complete. If the microcode patch is complete, determine that a valid microcode patch exists in the external memory. If the microcode patch is incomplete, determine that a valid microcode patch does not exist in the external memory.

[0017] If no microcode patch is found, it is determined that there is no valid microcode patch in the external memory.

[0018] Optionally, the microcode patch loading method further includes:

[0019] If the microcode patch flag is invalid, the processor kernel will not load the microcode patch.

[0020] Optionally, the microcode patch loading method further includes:

[0021] After entering the BIOS / OS boot stage, the processor core obtains the version number of the microcode patch to be loaded from a specified location in memory, determines whether the microcode patch to be loaded is a new version based on the version number, and if the microcode patch to be loaded is a new version, it authenticates the microcode patch to be loaded. If the authentication is successful, the microcode patch to be loaded is loaded and the microcode patch version number is updated.

[0022] The processor core sends an interrupt request to the security module;

[0023] In response to the interrupt request, the security module writes the microcode patch to be loaded into the external memory.

[0024] Optionally, the microcode patch loading method further includes:

[0025] If the microcode patch to be loaded is not a new version of the microcode patch, the processor kernel will not load the microcode patch to be loaded.

[0026] Optionally, the external memory reserves two microcode patch storage areas for storing the most recently written microcode patch and the microcode patch written before the most recently written microcode patch.

[0027] If the two microcode patch storage areas are empty, the security module will write the microcode patch to be loaded into either of the microcode patch storage areas.

[0028] If one of the two microcode patch storage areas is occupied, the security module will write the microcode patch to be loaded into the other unoccupied microcode patch storage area.

[0029] If both microcode patch storage areas are occupied, the security module writes the microcode patch to be loaded into the most recent microcode patch storage area, overwriting the most recent microcode patch written earlier.

[0030] Optionally, if the processor includes multiple processor cores, each processor core sends an interrupt request to the security module;

[0031] In response to the first interrupt request received, the security module writes the microcode patch to be loaded into the external memory. In response to subsequent interrupt requests, it checks whether the microcode patch version is updated. If the version is updated, the microcode patch is written into the external memory; otherwise, no operation is performed.

[0032] Optionally, the microcode patch loading method further includes:

[0033] Before the processor core retrieves the version number of the microcode patch to be loaded from a specified location in memory, the processor core retrieves the microcode patch to be loaded from a disk or network, and then writes the microcode patch to be loaded to a specified location in memory.

[0034] The processor core writes the physical address at the specified location into the MSR used to control the loading of microcode patches, thereby triggering the processor core to retrieve the version number of the microcode patch to be loaded from the specified location in memory.

[0035] Optionally, the processor core authenticates the microcode patch to be loaded, including:

[0036] The processor core retrieves the microcode patch to be loaded from a specified location in memory;

[0037] The microcode patch to be loaded is decrypted and its signature verified.

[0038] Optionally, the microcode patch loading method further includes:

[0039] After loading the microcode patch to be loaded, check whether the MSR used to indicate the microcode patch version number has been updated to determine whether the microcode patch to be loaded has been loaded successfully.

[0040] The microcode patch loading method provided by this invention, starting from the second patch loading, during the processor startup phase, the processor kernel will actively load the valid microcode patch stored in the external memory, which is beneficial to optimizing the patch loading process in the subsequent BIOS and OS startup phases and improving system security. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the processor structure in one embodiment of the present invention;

[0042] Figure 2 This is a flowchart illustrating a microcode patch loading method for a processor according to an embodiment of the present invention.

[0043] Figure 3 This is a schematic diagram illustrating how a security module of an embodiment of the present invention handles multiple processor core interrupt requests;

[0044] Figure 4 This is a schematic diagram of the external memory microcode patch version update process in one embodiment of the present invention. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0046] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0047] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0048] First, it should be noted that for the entire processor system, the system startup process is as follows: the processor starts first, and then the BIOS / OS starts.

[0049] Figure 1 This is a schematic diagram of the processor used in an embodiment of the present invention. Figure 1 As shown, taking a single-core processor as an example, the processor includes a processor core, a security module, and a memory controller. Besides containing regular instructions and cache resources, the processor core also includes ROM for storing microcode and a microcode patch buffer (which can be RAM) for storing microcode patches. The security module controls the processor's boot process, can access dedicated memory areas corresponding to each processor core, and can also access external memory. The processor core's microcode can interact with the security module via interrupts. The memory controller is used to write data from inside the processor to memory and retrieve data from memory into the processor.

[0050] One embodiment of the present invention provides a microcode patch loading method for a processor, the processor including a processor core and a security module, the security module being connected to external memory, referenced... Figure 2 The microcode patch loading method includes the following steps:

[0051] S2001, during the processor startup phase, the security module checks whether there is a valid microcode patch in the external memory;

[0052] S2002: If a valid microcode patch exists, the security module writes the valid microcode patch into the dedicated memory area corresponding to the processor core and sets the microcode patch flag of the dedicated memory area to be valid. If no valid microcode patch exists, the security module sets the microcode patch flag of the dedicated memory area to be invalid.

[0053] S2003, the security module releases the processor core reset;

[0054] S2004, the processor kernel checks whether the microcode patch flag of the dedicated memory region is valid;

[0055] S2005: If the microcode patch flag is valid, the processor core retrieves and authenticates the valid microcode patch from a dedicated memory area.

[0056] S2006: If authentication is successful, the processor kernel loads a valid microcode patch and updates the microcode patch version number.

[0057] In step S2001, during the initial startup of the processor, the processor core is in a reset state, meaning the microcode has not yet begun execution. The processor's security module (also known as the security processor) starts first and checks whether a valid microcode patch exists in the external memory before releasing the processor core from reset.

[0058] As one implementation, the security module checks whether a valid microcode patch exists in the external storage, including:

[0059] Check the external storage for microcode patches;

[0060] If a microcode patch exists, determine whether the microcode patch is complete. If the microcode patch is complete, determine that a valid microcode patch exists in the external storage. If the microcode patch is incomplete, determine that a valid microcode patch does not exist in the external storage.

[0061] If no microcode patch is available, it is determined that there is no valid microcode patch in the external storage.

[0062] The reason for the incomplete microcode patch is that during the process of writing the microcode patch to external memory, a sudden power outage caused the writing process to be interrupted, resulting in an incomplete microcode patch.

[0063] In step S2002, the microcode patch flag can be represented by 1 bit, where "1" indicates valid and "0" indicates invalid. If a valid microcode patch exists in the external memory, the patch_valid flag of the dedicated memory area is set to 1; if no valid microcode patch exists in the external memory, the patch_valid flag of the dedicated memory area is set to 0.

[0064] In step S2003, the security module releases the processor core reset, the processor core enters the working state, and begins to execute microcode.

[0065] Steps S2004–S2006 are implemented by the processor kernel executing the microcode. The processor kernel executes the microcode, first checking if the microcode patch flag bit `patch_valid` in the dedicated memory area is 1. If `patch_valid` is 1, the microcode copies the microcode patch from the dedicated memory area to the microcode patch temporary storage area on the processor kernel and authenticates the validity of the microcode patch. The authentication process includes decrypting the microcode patch and verifying its signature. If authentication is successful, the microcode loads the microcode patch, updates the microcode patch version number, and finally, the microcode controls the processor kernel to start executing the system program. If `patch_valid` is 0, the microcode does not load the microcode patch and directly controls the processor kernel to start executing the system program.

[0066] In the above process, if the microcode patch flag is invalid, the processor kernel will not load the microcode patch.

[0067] Additionally, it should be noted that the processor core has many processor-specific registers (MSRs) with different functional characteristics. For example, writing the microcode patch version number into the MSR, which represents the microcode patch version number, can update the microcode patch version number.

[0068] In this embodiment, the external memory is non-volatile memory (NVM), such as Flash.

[0069] Steps S2001 to S2006 load the microcode patch during the processor startup phase. After completing the above process, the processor core begins executing the system program and enters the BIOS / OS startup phase.

[0070] Continue to refer to Figure 2 After the processor boot phase ends, the BIOS / OS boot phase begins. During the BIOS / OS boot phase, the microcode patch loading method also includes the following steps:

[0071] In step S2010, the processor core retrieves the version number of the microcode patch to be loaded from a specified location in memory. Based on the version number, it determines whether the microcode patch to be loaded is a new version. If it is a new version, it continues to the next step S2011. If the microcode patch to be loaded is not a new version, the processor core does not load the microcode patch.

[0072] S2011, the processor kernel authenticates the microcode patch to be loaded. If the authentication is successful, the process continues to the next step S2012. If the authentication fails, the processor kernel does not load the microcode patch to be loaded.

[0073] In step S2011, the processor core retrieves the microcode patch to be loaded from a designated location in memory, copies the microcode patch from PA to a dedicated memory region corresponding to the processor core (this dedicated memory region is accessible only to the processor core microcode and security module) and a microcode patch temporary storage area located on the processor core, and then authenticates the legitimacy of the microcode patch. The authentication process includes decryption and signature verification. Typical embodiments include the microcode itself decrypting the signature verification microcode patch, the security module decrypting the signature verification microcode patch, or a combination of the microcode and the security module decrypting the signature verification microcode patch.

[0074] S2012, the processor core loads the microcode patch to be loaded and updates the microcode patch version number;

[0075] In S2013, the processor core sends an interrupt request to the security module to notify the security module to write the microcode patch to be loaded into external memory.

[0076] In S2014, the security module responds to the interrupt request by writing the microcode patch to be loaded into external memory.

[0077] In step S2014, if the processor has only one processor core, the security module receives only one interrupt request and, in response to the interrupt request, writes the microcode patch to be loaded into external memory.

[0078] If the processor includes multiple processor cores, each processor core will send an interrupt request to the security module, see reference. Figure 3 , Figure 3 This illustrates a scenario where the security module responds to interrupts from multiple processor cores. Upon receiving the first interrupt request, the security module writes the microcode patch to be loaded to external memory. In response to subsequent interrupt requests, it checks if the microcode patch version is updated. If the version is updated, it writes the microcode patch to external memory; otherwise, it does nothing. In reality, since the microcode patches to be loaded from multiple processor cores are identical, there will be no microcode patch version update. In other words, the security module does not perform any operation in response to subsequent interrupt requests.

[0079] Steps S2010 to S2013 described above are implemented by the processor core executing microcode. In one embodiment, before step S2010, the following steps are also included:

[0080] In S2008, the processor core retrieves the microcode patch to be loaded from the disk or network, and then writes the patch to be loaded to a specified location in memory, assuming that the physical address of the specified location is PA. The microcode patch to be loaded is a microcode patch released by the processor manufacturer and cryptographically signed using the chip root key.

[0081] In S2009, the processor core writes the physical address PA to the processor-specific register MSR, which controls the loading of microcode patches, to trigger the processor core to retrieve the version number of the microcode patch to be loaded from a specified location in memory.

[0082] The steps S2008 to S2009 described above are implemented by the processor core executing the BIOS / OS system program.

[0083] It should also be noted that after loading the microcode patch, the processor kernel checks whether the MSR, which indicates the microcode patch version number, has been updated to determine whether the microcode patch was loaded successfully. This step is also implemented by the processor kernel executing the BIOS / OS system program.

[0084] The above process loads the microcode patch during the BIOS / OS boot phase. Once this process is complete, the entire patch loading process is finished.

[0085] Furthermore, in this embodiment, the external memory reserves two microcode patch storage areas for storing the most recently written microcode patch and the microcode patch written before the most recently written microcode patch.

[0086] If both microcode patch storage areas are empty, the security module will write the microcode patch to be loaded into either of the microcode patch storage areas.

[0087] If one of the two microcode patch storage areas is occupied, the security module will write the microcode patch to be loaded into the other microcode patch storage area that is not occupied.

[0088] If both microcode patch storage areas are occupied, the security module will write the microcode patch to be loaded into the storage area of ​​the most recent microcode patch written before the most recent one, overwriting the most recent microcode patch written before the most recent one.

[0089] Figure 4 The diagram illustrates the microcode patch version update process for external memory (using Flash as an example). The original version of the microcode patch is initially stored in the external memory. When the chip manufacturer releases a new microcode patch version n, this patch is loaded under the BIOS / OS. At this time, the security module writes the new microcode patch version n into the microcode patch reservation area in the Flash memory. Similarly, when the chip manufacturer releases a new microcode patch version n+x1, the security module overwrites the initial microcode patch version and retains the slightly newer microcode patch version n.

[0090] It is understandable that the most recently written microcode patch is the current latest version of the microcode patch, and the microcode patch written before that most recently is the current second-to-last version of the microcode patch. Each time a microcode patch is written, the written microcode patch to be loaded becomes the new current latest version of the microcode patch, while the original current latest version of the microcode patch becomes the current second-to-last version of the microcode patch accordingly.

[0091] The reason for reserving two microcode patch storage areas in external storage is to prevent damage to the previously written microcode patch from being corrupted due to an abnormal power outage during the microcode patch writing process of the security module, thus compromising the security of the entire system. The security module loads the valid and most recently written microcode patch during each system startup.

[0092] During each processor startup phase, the security module checks whether there is a valid microcode patch in the external memory. First, it checks whether the most recently written microcode patch (i.e., the latest version of the microcode patch) is a valid microcode patch. Only if the most recently written microcode patch is invalid (e.g., it failed to write due to a sudden power outage) will it check whether the most recently written microcode patch (i.e., the second newest version of the microcode patch) is a valid microcode patch.

[0093] It should also be noted that the patch loading process in this embodiment of the invention is applicable to both the first-time patch loading and non-first-time patch loading scenarios.

[0094] Specifically, when the system loads the patch for the first time, the external memory is empty. The security module will set the microcode patch flag in the dedicated memory area to be invalid, so the patch is not loaded during the processor startup phase. The microcode patch needs to be loaded during the BIOS / OS startup phase.

[0095] However, starting with the second patch load, since external memory will no longer be empty, each subsequent system startup involves the processor core actively loading the valid microcode patch stored in external memory during the processor boot phase. Then, during the BIOS / OS boot phase, a new version of the microcode patch is only loaded under the BIOS / OS when it becomes available. The security module then writes this new version of the microcode patch to external memory, dynamically updating the version of the valid microcode patch. This way, the latest version of the valid microcode patch stored in external memory can be directly loaded on the next system startup.

[0096] Therefore, the microcode patch loading method of this invention, starting from the second patch loading, can load the valid microcode patch stored in external memory only in the earliest stage of each system startup. The fixed process of BIOS and OS does not need to load the microcode patch again. Only when a new version of the microcode patch needs to be loaded does the microcode patch need to be loaded in BIOS / OS, and the security module saves the new version of the microcode patch to external memory so that it can be loaded at the next system startup. This not only reduces the number of microcode patch loading times, but also enhances system security.

[0097] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0098] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for loading microcode patches for a processor, characterized in that, The processor includes a processor core and a security module, the security module being connected to external memory, and the microcode patch loading method includes: During the processor startup phase, the security module checks whether there is a valid microcode patch in the external memory; If a valid microcode patch exists, the security module writes the valid microcode patch into a dedicated memory region in memory corresponding to the processor core, and sets the microcode patch flag of the dedicated memory region to be valid. If no valid microcode patch exists, the security module sets the microcode patch flag of the dedicated memory region to be invalid. The security module releases the processor core from reset; The processor core checks whether the microcode patch flag in the dedicated memory area is valid. If the microcode patch flag is valid, it retrieves and authenticates the valid microcode patch from the dedicated memory area. If the authentication is successful, it loads the valid microcode patch and updates the microcode patch version number.

2. The microcode patch loading method according to claim 1, characterized in that, The security module checks whether a valid microcode patch exists in the external memory, including: Check if there are microcode patches in the external storage; If a microcode patch exists, determine whether the microcode patch is complete. If the microcode patch is complete, determine that a valid microcode patch exists in the external memory. If the microcode patch is incomplete, determine that a valid microcode patch does not exist in the external memory. If no microcode patch is found, it is determined that there is no valid microcode patch in the external memory.

3. The microcode patch loading method according to claim 1, characterized in that, The microcode patch loading method also includes: If the microcode patch flag is invalid, the processor kernel will not load the microcode patch.

4. The microcode patch loading method according to claim 3, characterized in that, The microcode patch loading method also includes: After entering the BIOS / OS boot stage, the processor core obtains the version number of the microcode patch to be loaded from a specified location in memory, determines whether the microcode patch to be loaded is a new version based on the version number, and if the microcode patch to be loaded is a new version, it authenticates the microcode patch to be loaded. If the authentication is successful, the microcode patch to be loaded is loaded and the microcode patch version number is updated. The processor core sends an interrupt request to the security module; In response to the interrupt request, the security module writes the microcode patch to be loaded into the external memory.

5. The microcode patch loading method according to claim 4, characterized in that, The microcode patch loading method also includes: If the microcode patch to be loaded is not a new version of the microcode patch, the processor kernel will not load the microcode patch to be loaded.

6. The microcode patch loading method according to claim 4, characterized in that, The external memory reserves two microcode patch storage areas for storing the most recently written microcode patch and the microcode patch written before the most recently written one. If the two microcode patch storage areas are empty, the security module will write the microcode patch to be loaded into either of the microcode patch storage areas. If one of the two microcode patch storage areas is occupied, the security module will write the microcode patch to be loaded into the other unoccupied microcode patch storage area. If both microcode patch storage areas are occupied, the security module writes the microcode patch to be loaded into the most recent microcode patch storage area, overwriting the most recent microcode patch written earlier.

7. The microcode patch loading method according to claim 4, characterized in that, If the processor includes multiple processor cores, each processor core sends an interrupt request to the security module; In response to the first interrupt request received, the security module writes the microcode patch to be loaded into the external memory. In response to subsequent interrupt requests, it checks whether the microcode patch version is updated. If the version is updated, the microcode patch is written into the external memory; otherwise, no operation is performed.

8. The microcode patch loading method according to claim 4, characterized in that, The microcode patch loading method also includes: Before the processor core retrieves the version number of the microcode patch to be loaded from a specified location in memory, the processor core retrieves the microcode patch to be loaded from a disk or network, and then writes the microcode patch to be loaded to a specified location in memory. The processor core writes the physical address of the specified location into a processor-specific register used to control the loading of microcode patches, thereby triggering the processor core to retrieve the version number of the microcode patch to be loaded from the specified location in memory.

9. The microcode patch loading method according to claim 4, characterized in that, The processor core authenticates the microcode patch to be loaded, including: The processor core retrieves the microcode patch to be loaded from a specified location in memory; The microcode patch to be loaded is decrypted and its signature verified.

10. The microcode patch loading method according to claim 4, characterized in that, The microcode patch loading method also includes: After loading the microcode patch to be loaded, check whether the processor-specific register used to indicate the microcode patch version number has been updated to determine whether the microcode patch to be loaded has been successfully loaded.

Images