A GPIO-based AUX channel signal simulation method

Abstract

The application is suitable for the field of circuit design, and provides an AUX channel signal simulation method based on GPIO, which comprises the following steps: firstly, a memory space is specified to define register information; a processor simulates the communication mechanism of AUX to control the GPIO interface to send a single-ended AUX communication request signal; then a differential signal conversion chip converts the GPIO signal to a receiving device; finally, a double-speed acquisition method is used to acquire the reply signal, and the read binary data is decoded to obtain the required data. The AUX channel signal simulation method has high data acquisition accuracy, high speed, low error rate, simple processor principle, small space occupation, and low hardware requirement.

Description

Technical Field

[0001] This invention belongs to the field of circuit design technology, and in particular relates to a method for simulating AUX channel signals based on GPIO. Background Technology

[0002] The AUX (Auxiliary) channel, as a half-duplex, differential signal bidirectional auxiliary transmission channel, has good anti-interference capabilities and is typically used to transmit control commands or audio and video data. It has wide applications in inter-device communication, such as the DP (Display Port) interface reading and writing the DPCD (Display Port Configuration Data) and EDID (Extended Display Identification Data) information of the display device through the AUX channel. In some applications, the processor needs to communicate with the device through the AUX channel, but the processor may lack an AUX channel interface, making communication impossible and rendering the design unfeasible.

[0003] When a processor cannot provide an AUX channel interface, but the device requires an AUX channel for communication, it is usually necessary to change the processor chip type. The design changes are often very significant, or even require a complete overhaul, which has a huge impact on the development and implementation of the project.

[0004] Another approach is to drive the AUX interface chip via a bus interface (such as USB, local bus, or PCIe interface) to provide access to the AUX auxiliary channel. However, this approach is more complex to implement, requires more software driver work, has higher hardware costs, and is not feasible for some processors because they cannot provide the corresponding bus interface. Summary of the Invention

[0005] In view of the above problems, the purpose of this invention is to provide a GPIO-based AUX channel signal simulation method, which aims to solve the technical problem of system design where the device needs an AUX channel for communication, but the processor lacks an AUX channel.

[0006] The present invention adopts the following technical solution:

[0007] The GPIO-based AUX channel signal simulation method includes the following steps:

[0008] Step S1: Set the register information at the specified memory address;

[0009] Step S2: The processor parses the instruction in the register and controls the processor's GPIO interface to send a single-ended AUX communication request signal according to the instruction. The request signal is converted into a standard differential AUX interface signal through a differential signal conversion chip and sent to the receiving device.

[0010] Step S3: The processor listens to the GPIO interface. If the GPIO interface receives a reply signal from the receiving device within the set waiting time, the processor collects the reply signal. Otherwise, the current AUX communication ends due to no response after timeout.

[0011] Step S4: The processor parses the collected response signal according to the format. If the response signal is an ACK, the processor obtains the response data in the response signal; otherwise, it returns to step S2 to continue sending the request signal.

[0012] Step S5: Write the response data to the defined shared memory area.

[0013] Furthermore, the specific process of step S2 is as follows:

[0014] S21. After the processor obtains the instruction from the shared communication area according to the register settings, it generates a request signal for the simulated AUX channel according to the instruction, and converts the request signal into binary format through Manchester encoding. It then controls the processor's GPIO interface to send the encoded request signal. The request signal for the AUX channel is in half-duplex communication mode, and the communication is in a question-and-answer manner.

[0015] S22. The encoded request signal is converted into a standard differential AUX interface signal through a differential signal conversion chip and sent to the receiving device to wait for a signal reply.

[0016] Furthermore, in step S3, the receiving device also uses Manchester encoding to encode the response signal and sends it to the processor's GPIO interface, and the processor uses a double-rate acquisition method to acquire the response signal.

[0017] Furthermore, the specific process of step S4 is as follows:

[0018] S41. For the response signal collected in each cycle, compare the signals of the first and second halves of the cycle. When the signal changes from high to low from the first half of the cycle to the second half of the cycle, the transmitted data is 0; otherwise, the transmitted data is 1.

[0019] S42. Parse the binary reply signal according to the data format of the AUX channel protocol. If the reply signal is ACK, it means that the reply signal is complete. If the reply signal is NACK, it means that the reply signal is incomplete. At this time, return to step S2 to continue sending the request signal. If the reply signal is DEFFER, it means that the receiving device is not ready to accept the request. At this time, also return to step S2 to continue sending the request signal.

[0020] The beneficial effects of this invention are as follows: This invention adopts a hardware approach using a GPIO interface and an external single-ended to differential level differential signal conversion chip. It simulates the AUX communication protocol through software-driven GPIO interface to realize the AUX channel interface, and uses a dual-speed acquisition method to acquire timing signals, thus solving the problem of missing processor AUX channels. Since processors typically have a certain number of GPIO interface resources, and external differential signal conversion chips are very inexpensive, experimental verification shows that this method has a fast acquisition rate, low error rate, simple implementation principle, and extremely low hardware requirements. Therefore, this invention has a good overall cost advantage. Attached Figure Description

[0021] Figure 1 This is a flowchart of the AUX channel signal simulation method based on GPIO provided in an embodiment of the present invention;

[0022] Figure 2 This is a schematic diagram of an external connection for a differential signal conversion chip;

[0023] Figure 3 This is a simulation diagram of the AUX channel signal. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0025] To illustrate the technical solution described in this invention, specific embodiments are described below.

[0026] like Figure 1 As shown, the GPIO-based AUX channel signal simulation method provided in this embodiment includes the following steps:

[0027] Step S1: Set the information of each register at the specified memory address.

[0028] This embodiment uses the example of a missing AUX channel signal on a DP display interface to describe the process of this method.

[0029] The CPU defines register information at a specified memory address and starts the MCU (Microcontroller Unit). The MCU is built into the GPU chip, and this step is implemented by the CPU. Subsequent steps S2-S5 are implemented by the MCU in the GPU.

[0030] Specifically, when the MCU is running in flash mode, the program needs to be moved to SRAM (Static Random-Access Memory) before execution. In order to facilitate communication and transmission between the CPU and the MCU and save memory, the high 256 bytes of the SRAM register set in the CPU are defined for instruction transmission and data reception.

[0031] The registers defined by the CPU at specified addresses in memory include: MCU program identifier register: used to detect the presence of an MCU program; address register addr: used to store a 20-bit address code for the operation function, status, and control mode of the display interface AUX; command register cmd: used to define the native AUX or I... 2 C AUX signal read / write transmission; Data length register len: used to store the actual number of read / write data and increment by 1; Data register aux_data: used to store DPCD and EDID data read / written; Reply register aux_status: used to store the status of the DPTX terminal reply; Status register status: used to control the MCU reset operation.

[0032] Step S2: The processor parses the instruction in the register and controls the processor's GPIO interface to send a single-ended AUX communication request signal according to the instruction. The request signal is converted into a standard differential AUX interface signal through a differential signal conversion chip and sent to the receiving device.

[0033] Most processors contain abundant GPIO (General-purpose input / output) interfaces. In this embodiment, for example... Figure 2 As shown, the GPU is connected to an external differential signal conversion chip. The MCU within the GPU, based on the instruction to read the registers, controls the GPIO interface, which converts the signal into a standard differential AUX interface signal via the differential signal conversion chip, and sends it to the AUX channel, awaiting a response from the receiving device.

[0034] The specific process for this step is as follows:

[0035] S21. After the processor obtains the instruction from the shared communication area according to the register settings, it generates a request signal for the simulated AUX channel according to the instruction, and converts the request signal into binary format using Manchester encoding. It then controls the processor's GPIO interface to send the encoded request signal. The request signal for the AUX channel is in half-duplex communication mode, and the communication is in a question-and-answer manner.

[0036] After obtaining instructions from the CPU's shared communication area, the MCU sends a request signal to the DPTX terminal. The format of the request and reply protocol follows the following: Synchronization Header (SYNC) + Synchronization End (SYNC END) + Command (CMD) + Data (DATA) + Communication End (STOP). After preparing the request signal to be sent, the data is converted into binary format using Manchester encoding and then sent through the GPIO interface.

[0037] S22. The encoded request signal is converted into a standard differential AUX interface signal through a differential signal conversion chip and sent to the receiving device to wait for a signal reply.

[0038] The GPIO interface requires two pins for signal transmission: one for simulating the AUX signal waveform and the other for switching the AUX channel direction. After receiving the coded request signal from the MCU, it sends it to the DP AUX channel via the SP3485E differential signal converter chip to await a response. In the diagram, the two pins of the GPIO interface are GPIO1 and GPIO2. The output signals of the SP3485E chip are AUX_N and AUX_P. The simulation diagram of the GPIO simulating the transmission and acquisition of the analog AUX channel signal is shown below. Figure 3 As shown.

[0039] Step S3: The processor listens to the GPIO interface. If the GPIO interface receives a reply signal from the receiving device within the set waiting time, the processor collects the reply signal. Otherwise, the current AUX communication ends due to no response after timeout.

[0040] The MCU waits for a response from the receiving device, determining the presence of a reply signal by monitoring changes in the GPIO interface level. When the GPIO interface return signal level changes, it indicates that the receiving device has begun responding, and at this point, double-rate acquisition is used to acquire binary data. Otherwise, it indicates that the receiving device has not responded, and AUX communication terminates prematurely due to timeout.

[0041] In this step, the receiving device also uses Manchester encoding to encode the response signal and sends it to the processor's GPIO interface. Manchester encoding uses high and low level changes to represent bits 0 and 1; a high-to-low transition represents "1," and a low-to-high transition represents "0." Each bit corresponds to one cycle of the encoding, and one cycle includes a set of high-to-low or low-to-high level transitions. Since the processor does not have an interrupt mechanism when acquiring the returned response signal, accurate signal acquisition timing is a key issue. This step employs a double-rate acquisition method to acquire the returned Manchester encoded signal, increasing the number of samples to better reduce acquisition errors.

[0042] For the DP display interface instance, the process of acquiring the response signal is as follows:

[0043] S31. Before a valid response signal is received, the GPIO pin is in a high-impedance state, and the level is determined by the pull-up and pull-down resistors and remains unchanged. When the level signal starts to change, it indicates that the receiving device has started to respond with a valid signal.

[0044] S32. After acquiring a valid response signal, the changing level signal is stored. This step uses a double-rate acquisition method, so four sets of signals can be acquired in one cycle. In half a cycle, i.e., one level, one, two, or three sets of data can be acquired due to the influence of error.

[0045] S33. When the current half-cycle acquisition is 1 group, the second half-cycle acquisition is at most 3 groups. When more than 3 groups are acquired, it indicates that the next cycle has begun. When the current half-cycle acquisition is 2 groups, in order to reduce the impact of cumulative error, the acquisition data of the second half-cycle is adjusted to 2 groups, which is the standard acquisition signal. When the current half-cycle acquisition is 3 groups, the second half-cycle acquisition is at most 2 groups. When more than 2 groups are acquired, the next cycle has begun.

[0046] Step S4: The processor parses the collected response signal according to the format. If the response signal is an ACK, the processor obtains the response data in the response signal; otherwise, it returns to step S2 to continue sending the request signal.

[0047] After receiving a valid reply signal from the receiving device, the MCU parses the reply signal data. If the reply signal is ACK, it means that the reply has been successfully sent; otherwise, it returns to step S2 to resend the request.

[0048] The specific process for this step is as follows:

[0049] S41. For the response signal collected in each cycle, compare the signals of the first and second halves of the cycle. When the signal changes from high to low from the first half of the cycle to the second half of the cycle, the transmitted data is 0; otherwise, the transmitted data is 1.

[0050] S42. Parse the binary reply signal according to the data format of the AUX channel protocol. If the reply signal is ACK, it means that the reply signal is complete. If the reply signal is NACK, it means that the reply signal is incomplete. At this time, return to step S2 to continue sending the request signal. If the reply signal is DEFFER, it means that the receiving device is not ready to accept the request. At this time, also return to step S2 to continue sending the request signal.

[0051] Step S5: Write the response data to the defined shared memory area.

[0052] In summary, this invention provides a GPIO-based AUX channel signal simulation method. It employs the processor's GPIO interface and an external single-ended to differential level converter chip in hardware, and uses software to drive the GPIO interface to simulate the AUX communication protocol, thus realizing the AUX channel interface and solving the problem of missing AUX channels in the processor. Since processors typically have a certain number of GPIO interface resources, and external single-ended to differential level converter chips are very inexpensive, this solution has a significant overall cost advantage.

[0053] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for simulating AUX channel signals based on GPIO, characterized in that, The method includes the following steps: Step S1: Set the register information at the specified memory address; Step S2: The processor parses the instruction in the register and controls the processor's GPIO interface to send a single-ended AUX communication request signal according to the instruction. The request signal is converted into a standard differential AUX interface signal through a differential signal conversion chip and sent to the receiving device. Step S3: The processor listens to the GPIO interface. If the GPIO interface receives a reply signal from the receiving device within the set waiting time, the processor collects the reply signal. Otherwise, the current AUX communication ends due to no response after timeout. Step S4: The processor parses the collected response signal according to the format. If the response signal is an ACK, the processor obtains the response data in the response signal; otherwise, it returns to step S2 to continue sending the request signal. Step S5: Write the response data to the defined shared memory area.

2. The GPIO-based AUX channel signal simulation method as described in claim 1, characterized in that, The specific process of step S2 is as follows: S21. After the processor obtains the instruction from the shared communication area according to the register settings, it generates a request signal for the simulated AUX channel according to the instruction, and converts the request signal into binary format through Manchester encoding. It then controls the processor's GPIO interface to send the encoded request signal. The request signal for the AUX channel is in half-duplex communication mode, and the communication is in a question-and-answer manner. S22. The encoded request signal is converted into a standard differential AUX interface signal through a differential signal conversion chip and sent to the receiving device to wait for a signal reply.

3. The GPIO-based AUX channel signal simulation method as described in claim 2, characterized in that, In step S3, the receiving device also uses Manchester encoding to encode the response signal and sends it to the processor's GPIO interface. The processor uses a double-rate acquisition method to acquire the response signal.

4. The GPIO-based AUX channel signal simulation method as described in claim 3, characterized in that, The specific process of step S4 is as follows: S41. For the response signal collected in each cycle, compare the signals of the first and second halves of the cycle. When the signal changes from high to low from the first half of the cycle to the second half of the cycle, the transmitted data is 0; otherwise, the transmitted data is 1. S42. Parse the binary reply signal according to the data format of the AUX channel protocol. If the reply signal is ACK, it means that the reply signal is complete. If the reply signal is NACK, it means that the reply signal is incomplete. At this time, return to step S2 to continue sending the request signal. If the reply signal is DEFFER, it means that the receiving device is not ready to accept the request. At this time, also return to step S2 to continue sending the request signal.

5. The GPIO-based AUX channel signal simulation method as described in claim 1, characterized in that, In step S1, the registers include the MCU program identifier register, address register, command register, data length register, data register, reply register, and status register.

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