Data processing method, data processing apparatus, electronic device, and storage medium

Abstract

A data processing method, a data processing device, an electronic device and a storage medium. The electronic device comprises a plurality of nodes connected in communication with each other, and the plurality of nodes comprise a first node, the first node comprising a first processor core, an inter-node consistency extension unit and a directory snoop extension filter for the inter-node consistency extension unit, the directory snoop extension filter comprising a first consistency directory, and the inter-node consistency extension unit is configured for inter-node interconnection. The inter-node consistency extension unit is configured to, in response to a first processor core included in the first node generating a first access request for first data whose storage address is outside the first node, querying the first consistency directory of the directory snoop extension filter to determine at least whether the first data is cached within the first node. The electronic device can reduce the transmission amount between nodes caused by snoop requests and improve system performance.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a data processing method, a data processing apparatus, an electronic device, and a storage medium. Background Technology

[0002] Currently, in computer systems with multiple processors and multiple caches, caches can store large amounts of data, which may be exclusive or may contain copies of the same data at different addresses. When different caches operate on data at the same cached address, consistency issues arise. To address this problem, many techniques have emerged to maintain data consistency. For example, when multiple caches store the same data copies, if a processor wants to modify data stored in one cache, the copies of that data in other caches will be marked invalid to avoid consistency errors. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a data processing method, the data processing method comprising: generating a first access request for first data whose storage address is located outside the first node by a first processor core included in a first node, wherein the first node further comprises a first node consistency extension unit and a directory snooping extension filter for the first node consistency extension unit, the directory snooping extension filter including a first consistency directory, and the first node consistency extension unit being configured for inter-node interconnection; the first node consistency extension unit querying the first consistency directory of the directory snooping extension filter to at least determine whether the first data is cached within the first node.

[0004] For example, in a data processing method according to at least one embodiment of the present disclosure, the first node further includes a first cache for the first processor core, a second processor core, and a second cache for the second processor core; the data processing method further includes: in response to the first node consistency extension unit querying the first consistency directory to find the first data and determining that the second cache has cached the first data, the directory listening extension filter sends a listening request to the second cache; the second cache returns the first data to the first cache in response to the listening request.

[0005] For example, in a data processing method according to at least one embodiment of the present disclosure, the second node includes a memory controller, a directory snooping filter for the memory controller, and a system memory controlled by the memory controller. The directory snooping filter includes a second consistency directory, and the storage address of the first data is located in the system memory of the second node. The data processing method further includes: in response to the second cache responding to the snooping request, returning the first data to the first cache; the first processor core issuing a read response confirmation message; the first node consistency extension unit updating the first consistency directory of the directory snooping extension filter according to the cache consistency status of the first data, and forwarding the read response confirmation message to the memory controller of the second node, so that the memory controller updates the second consistency directory of the directory snooping filter according to the cache consistency status of the first data.

[0006] For example, in a data processing method according to at least one embodiment of the present disclosure, the second node includes a memory controller and a system memory controlled by the memory controller, the storage address of the first data is located in the system memory of the second node, and the first node further includes a first cache for the first processor core; the data processing method further includes: in response to a query by the first node consistency extension unit that the directory entry of the first consistency directory does not match the first data, the first node consistency extension unit forwards the first access request to the memory controller of the second node.

[0007] For example, the data processing method according to at least one embodiment of the present disclosure further includes: in response to the memory controller of the second node reading the first data from the system memory and returning it to the first node consistency extension unit, the first node consistency extension unit returning the first data to the first cache to cache the first data in the first cache, and the first node consistency extension unit updating the first consistency directory according to the cache consistency status of the first data.

[0008] For example, in a data processing method according to at least one embodiment of the present disclosure, the second node further includes a directory snooping filter for the memory controller, the directory snooping filter including a second consistency directory; the data processing method further includes: in response to the memory controller of the second node reading the first data from the system memory and returning it to the first node inter-consistency extension unit, the memory controller updating the second consistency directory according to the cache consistency status of the first data.

[0009] For example, in a data processing method according to at least one embodiment of the present disclosure, the second node further includes a second inter-node consistency extension unit configured for inter-node interconnection; the data processing method further includes: the first inter-node consistency extension unit and the second inter-node consistency extension unit communicating with each other to transmit requests and responses between the first node and the second node.

[0010] For example, the data processing method according to at least one embodiment of the present disclosure further includes: replacing or evicting the directory item corresponding to the first data from the first consistency directory in response to a replacement or eviction operation of the first consistency directory.

[0011] For example, the data processing method according to at least one embodiment of the present disclosure further includes: notifying the directory listening filter in response to replacing or expelling the directory item corresponding to the first data from the first consistency directory.

[0012] For example, in a data processing method according to at least one embodiment of the present disclosure, the first inter-node consistency extension unit communicates with the directory listening extension filter through the exchange unit of the first node.

[0013] At least one embodiment of this disclosure also provides an electronic device, the electronic device including a plurality of nodes communicatively connected to each other, wherein the plurality of nodes includes a first node, the first node including a first processor core, a first inter-node consistency extension unit and a directory snooping extension filter for the first inter-node consistency extension unit, the directory snooping extension filter including a first consistency directory, the first inter-node consistency extension unit being configured for inter-node interconnection; the first inter-node consistency extension unit being configured to, in response to a first access request generated by the first processor core included in the first node for first data whose storage address is located outside the first node, query the first consistency directory of the directory snooping extension filter to at least determine whether the first data is cached within the first node.

[0014] For example, in an electronic device according to at least one embodiment of the present disclosure, the first node further includes a first cache for the first processor core, a second processor core, and a second cache for the second processor core; the directory listening extended filter is configured to issue a listening request to the second cache in response to the first consistency directory hitting the first data and determining that the second cache has cached the first data by querying the first consistency extended unit between the first nodes; the second cache is configured to return the first data to the first cache in response to the listening request.

[0015] For example, in an electronic device according to at least one embodiment of the present disclosure, the plurality of nodes further includes a second node, the second node including a memory controller, a directory snooping filter for the memory controller, and a system memory controlled by the memory controller, the directory snooping filter including a second consistency directory, the storage address of the first data being located in the system memory of the second node; the first processor core is configured to issue a read response confirmation message in response to the second cache responding to the snooping request and returning the first data to the first cache; the first node consistency extension unit is further configured to update the first consistency directory of the directory snooping extension filter according to the cache consistency status of the first data, and forward the read response confirmation message to the memory controller of the second node; the memory controller is configured to update the second consistency directory of the directory snooping filter according to the cache consistency status of the first data.

[0016] For example, in an electronic device according to at least one embodiment of the present disclosure, the plurality of nodes further includes a second node, the second node including a memory controller and a system memory controlled by the memory controller, the storage address of the first data being located in the system memory of the second node; the first node further includes a first cache for the first processor core; the first node consistency extension unit is further configured to forward the first access request to the memory controller of the second node in response to a query by the first node consistency extension unit that the directory entry of the first consistency directory does not match the first data.

[0017] For example, in an electronic device according to at least one embodiment of the present disclosure, the first inter-node consistency extension unit is further configured to, in response to the memory controller of the second node reading the first data from the system memory and returning it to the first inter-node consistency extension unit, return the first data to the first cache to cache the first data in the first cache, and update the first consistency directory according to the cache consistency status of the first data.

[0018] For example, in an electronic device according to at least one embodiment of the present disclosure, the second node further includes a directory snooping filter for the memory controller, the directory snooping filter including a second consistency directory; the memory controller is configured to, in response to the memory controller of the second node reading the first data from the system memory and returning it to the first node inter-consistency extension unit, update the second consistency directory according to the cache consistency status of the first data.

[0019] For example, in an electronic device according to at least one embodiment of the present disclosure, the second node further includes a second inter-node consistency extension unit configured for inter-node interconnection; the first inter-node consistency extension unit and the second inter-node consistency extension unit are also configured to communicate with each other to transmit requests and responses between the first node and the second node.

[0020] For example, in an electronic device according to at least one embodiment of the present disclosure, the first inter-node consistency extension unit is configured to replace or evict the directory item corresponding to the first data from the first consistency directory in response to a replacement or eviction operation of the first consistency directory.

[0021] For example, in an electronic device according to at least one embodiment of the present disclosure, the first inter-node consistency extension unit is further configured to notify the directory snooping filter in response to replacing or evictping a directory item corresponding to the first data from the first consistency directory.

[0022] For example, in an electronic device according to at least one embodiment of the present disclosure, the first node further includes a switching unit, and the first node consistency extension unit communicates with the directory listening extension filter through the switching unit of the first node.

[0023] At least one embodiment of this disclosure also provides a data processing apparatus including a memory and at least one processor. The memory is configured to store computer-executable instructions; the at least one processor is configured to execute the computer-executable instructions, wherein the computer-executable instructions, when executed by the at least one processor, implement the method as described in any of the above embodiments.

[0024] At least one embodiment of this disclosure also provides a non-transitory storage medium for non-transitory storage of computer-executable instructions, wherein, when the computer-executable instructions are executed by at least one processor, the method described in any of the above embodiments is implemented. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0026] Figure 1 A schematic diagram of a processor node is shown;

[0027] Figure 2 A schematic diagram illustrating an exemplary directory organization structure for a consistent directory with a directory listener filter is shown.

[0028] Figure 3A This diagram illustrates a processing flow for data access requests between nodes in an exemplary two-node system.

[0029] Figure 3B This diagram illustrates another processing flow for data access requests between nodes in an exemplary two-node system.

[0030] Figure 4 A schematic diagram of a processor node of an electronic device according to at least one embodiment of the present disclosure is shown;

[0031] Figure 5A A schematic diagram of a read request processing flow in a dual-node system of an electronic device according to an embodiment of the present disclosure is shown.

[0032] Figure 5B A schematic diagram of a read request processing flow in a dual-node system of an electronic device according to an embodiment of the present disclosure is shown.

[0033] Figure 5C A schematic diagram of an electronic device according to an embodiment of the present disclosure is shown, wherein the electronic device in this embodiment is a multi-node system;

[0034] Figure 6 A schematic diagram of a processor node of an electronic device according to at least another embodiment of the present disclosure is shown;

[0035] Figure 7 A schematic diagram of a data processing apparatus provided in one embodiment of the present disclosure is shown;

[0036] Figure 8 A schematic diagram of a non-transitory storage medium provided in one embodiment of the present disclosure is shown. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0038] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0039] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and known components have been omitted.

[0040] In multiprocessor (or multiprocessor core) systems, techniques such as snooping and filtering have been proposed to improve the efficiency of data consistency maintenance. Snooping and filtering techniques can help track the cache states in multiple caches, including states such as a single or multiple copies of a certain data in a cache, or the data only existing in main memory.

[0041] In a multi-processor (or processor core) multi-cache computer system, a directory listener filter tracks the state of the processor cache and stores the tracked state information in the listener filter. When the consistency agent listens on the bus and detects a consistent transaction, it queries the cache consistency information tracked in the listener filter and issues the corresponding listener request to complete the consistency maintenance.

[0042] Figure 1 A schematic diagram of a processor node 100 is shown, which is, for example, a single processor chip or an independent part of a processor chip, and together with other processor nodes constitutes a larger system, such as an electronic device.

[0043] like Figure 1 As shown, processor node 100 is a basic multiprocessor multi-cache system that uses directory sniffing filters to maintain cache coherency. Processor node 100 includes n+1 processor cores 10 to 1n, n+1 caches (hereinafter also referred to as "caches") 20 to 2n, a coherent interconnect bus 14, m+1 memory controllers 40 to 4m, m+1 system memory 30 to 3m, and m+1 directory sniffing filters (or "coherent directory sniffing filters") 50 to 5m, where n and m are both integers greater than or equal to 0.

[0044] For example, each of caches 20 to 2n is configured to store data storage information corresponding to at least one piece of data. For example, caches 20 to 2n can be multiple dedicated caches used by processor cores 10 to 1n respectively. In addition, the processor node 100 may also include a shared cache for processor cores 10 to 1n.

[0045] like Figure 1 As shown, the above m+1 memory controllers 40-4m correspond to the m+1 system memories 30-3m respectively; the above m+1 memory controllers 40-4m correspond to the m+1 directory snooping filters 50-5m respectively. These memory controllers are used to manage and control access to and operation of the system memories, and as consistency nodes, they connect the corresponding directory snooping filters and system memories to the consistency interconnect bus 14.

[0046] These directory listener filters are used to maintain the consistency of data in the corresponding system memory within the caches 20-2n. More specifically, directory listener filters 50-5m help track the cached data status in caches 20-2n; for example, for a given piece of data, the cached data status may include: one or more single copies of the cached data in caches 20-2n, multiple copies of the cached data, or the data existing only in main memory. Directory listener filters 10-1n track the cached data status of caches 20-2n in processor cores 10-1n and store the tracked status information in the directories of directory listener filters 10-1n. When the consistency broker listens to the bus and detects a consistent transaction, it queries the tracked status information in directory listener filters 10-1n and issues a corresponding listener request to complete the consistency maintenance.

[0047] For example, such as Figure 1 As shown, the coherence interconnect bus 14 is directly coupled to caches 20-2n and also directly coupled to memory controllers 40-4m. The coherence interconnect bus 14 is a common communication trunk for information transmission; for example, the coherence interconnect bus 14 is a transmission harness composed of electronic components such as wires in the chip.

[0048] like Figure 1 As shown, the processor node 100 also includes a consistency extension unit 15, which is used to communicate with other processor nodes (e.g., chips) and maintain data cache consistency among multiple nodes by querying the aforementioned directory listener filters 10 to 1n.

[0049] Figure 2 This diagram illustrates a directory organization structure for a consistent directory with a directory listener filter. For example... Figure 2As shown, the directory is a data table containing multiple directory entries (or target items). Each directory entry can include the following data items:

[0050] • Directory validity bit: Indicates whether the directory entry is valid.

[0051] • Owner ID: If the data stored at the address corresponding to this directory entry is exclusively occupied by a certain cache, the ID of that cache is recorded, and when other caches access the data stored at this address, they can directly send a listening request to the cache that exclusively occupies the data.

[0052] • Directory vector: Indicates which nodes in the system have a copy of the data stored at that address in their processor core cache. Directory vectors can be used for precise recording, such as recording whether every cache in the system caches the data, or for fuzzy recording, such as recording only which nodes or even which region of nodes cache the data.

[0053] • Cache status information: indicates the data backup status of the data stored at the address corresponding to the directory entry in the corresponding cache, such as shared state, exclusive state, modified state, etc.

[0054] • Directory address flag: Indicates the address information corresponding to the data stored at the address of the directory entry. It usually records the high N bits of the address.

[0055] Depending on which MSI / MESI / MOESI protocol the system cache state uses, the request type and listener type will differ.

[0056] Figure 3A and Figure 3B These are schematic diagrams illustrating a data access process between nodes. To simplify the explanation, each node is... Figure 1 A simplified version of the processor node, in which parts not covered in the following description are omitted.

[0057] In a multi-node system, the "requesting node" refers to the node that sends the access request, while the "home node" refers to the node where the memory to be accessed by the access request resides. That is, the requesting node and the home node are relative to a particular operation and are not fixed.

[0058] for Figure 3A and Figure 3BIn such a two-node system, for example, in operation 1, the left node's processor core 0 sends a read request to access the right node's memory. In operation 1, the left node is the requesting node, and the right node is the home node. Similarly, in operation 2, the left node's processor core 0 sends a read request to access the left node's memory. In operation 2, both the requesting node and the home node refer to the left node. And in operation 3, the right node's processor core 0 sends a read request to access the left node's memory. In operation 3, the right node is the requesting node, and the left node is the home node.

[0059] exist Figure 3A and Figure 3B In the scenario shown, a non-limiting description is given using the left node as the requesting node and the right node as the home node. The requesting node and home node are functionally identical; however, the diagram schematically shows the processor core and inter-chip coherence extension unit for the requesting node, while the home node schematically shows its corresponding system memory.

[0060] Figure 3A The following describes the operation that involves the processor kernel within the requesting node reading certain data for the first time, but the directory listener filter query misses the result.

[0061] (a) The requesting node processor core 0 on the left generates a read request for the first data in the system memory 0 in the home node on the right, that is, to read the first data. The read request is sent to the inter-chip consistency extension unit of the requesting node through the inter-chip consistency extension unit of the home node on the right, and then sent to the memory controller 0 by the inter-chip consistency extension unit in the home node.

[0062] (b) The memory controller 0 of the home node queries the directory listener filter 0 associated with it to see if there is any consistency information about the first data in the directory. The query result is a miss.

[0063] (c) The home node's memory controller 0 transmits a read request for the first data to the home node's system memory 0;

[0064] (d) The home node's system memory 0 returns the first data read to the home node's memory controller 0;

[0065] (e) The memory controller 0 of the home node marks the cache state of this first data in the directory of the directory listener filter 0 associated with it;

[0066] (f) Furthermore, after receiving the first data, the memory controller 0 of the home node returns the first data to the processor core 0 of the requesting node through the inter-chip consistency extension unit of the home node and the inter-chip consistency extension unit of the requesting node, so that the first data is cached in the cache of the processor core 0 of the requesting node.

[0067] Figure 3B The operation involving another processor core n within the requesting node reading the aforementioned data from the same address again, and the directory listener filter query being hit, is explained in detail below.

[0068] (a) Another processor core n of the requesting node on the left issues a read request for the first data with the same address, that is, it also wants to read the first data. The read request is sent through the inter-chip consistency extension unit of the requesting node to the inter-chip consistency extension unit of the home node on the right, and then sent to the memory controller 0 in the home node.

[0069] (b) The memory controller 0 of the home node queries the directory listener filter 0 associated with it to see if there is consistency information about the first data in the directory. The query result is a hit, and it is determined that the processor core 0 of the requesting node has the first data cached.

[0070] (c) The memory controller 0 of the home node sends a listening request to the processor core 0 of the requesting node based on the query directory listening filter 0 and the result of the query being hit.

[0071] (d) After receiving the above listening request, the processor core 0 of the requesting node responds by directly returning the cached first data to the processor core n of the requesting node;

[0072] (e) After the processor core n of the requesting node receives the first data, it sends a read response confirmation message to the memory controller 0 of the home node.

[0073] (f) The memory controller 0 of the home node updates the directory of the associated directory listener filter 0 according to the read response confirmation message, that is, updates the cache state of the first data. At this time, the first data is cached in both the processor core 0 and the processor core n of the requesting node and the state of the first data is, for example, "shared".

[0074] In this disclosure, "memory address" refers to a physical address in system memory (e.g., RAM); for example, a cache temporarily stores a copy of data in system memory.

[0075] The inventors of this disclosure noted during their research that, when data needs to be read across nodes, even if the processor core (cache) issuing the data read request and the processor core (cache) that already caches the data are located within the same node, the data read request still needs to be sent from the requesting node to the home node (i.e., the node pointed to by the storage address of the data), and the home node needs to send a listen request to the requesting node again. This operation increases inter-chip transmission volume and squeezes inter-chip transmission bandwidth, and also increases the overall access latency, which is very detrimental to latency-sensitive requests. Generally, the inter-chip communication bus is the bandwidth bottleneck of the entire system transmission. If redundant transmissions squeeze the inter-chip transmission bandwidth, it will undoubtedly exacerbate the inter-chip transmission pressure and reduce system performance.

[0076] Based on the above understanding, at least one embodiment of this disclosure provides a data processing method and an electronic device.

[0077] This disclosure provides at least one embodiment of an electronic device comprising a plurality of nodes communicatively connected to each other. The plurality of nodes includes a first node, which includes a first processor core, an inter-node consistency extension unit, and a directory snooping extension filter for the inter-node consistency extension unit. The directory snooping extension filter includes a first consistency directory. The inter-node consistency extension unit is configured to interconnect the nodes. The inter-node consistency extension unit is configured to, in response to a first access request generated by the first processor core included in the first node for first data whose storage address is located outside the first node, query the first consistency directory of the directory snooping extension filter to at least determine whether the first data is cached within the first node.

[0078] Corresponding to the above-mentioned electronic device, at least one embodiment of this disclosure provides a data processing method, which includes the following steps: a first processor core included in a first node generates a first access request for first data whose storage address is located outside the first node; and a first consistency directory of a directory listening extended filter is queried by a first node consistency extension unit to at least determine whether the first data is cached within the first node.

[0079] In the embodiments described above, the first node can be any one of multiple nodes in an electronic device, such as a single chip or a portion thereof. The first node itself is a multi-processor, multi-cache system, for example, including multiple processor cores and one or more caches corresponding to each of the multiple processor cores. A directory listening extended filter is used throughout the first node.

[0080] The aforementioned "first data" can refer to any data that is the object of the current operation.

[0081] For example, multiple nodes in the electronic device in the above embodiments of this disclosure may be identical to each other, for example, all having the same architecture as the first node, including an inter-node consistency extension unit and a corresponding (i.e., a directory snooping filter operated by the inter-node consistency extension unit).

[0082] The electronic system and data processing method provided by the above embodiments of this disclosure can reduce inter-chip listening requests and alleviate the bandwidth occupation pressure of inter-node (e.g., inter-chip) transmission. Since the data flow between nodes is reduced, the power consumption of cross-chip transmission is reduced. In addition, in some embodiments, access latency can be effectively shortened, and in some embodiments, cross-chip directory maintenance requests can be reduced to alleviate the bandwidth pressure of inter-chip transmission. All of these improve the overall system performance.

[0083] In at least one embodiment, for example, the first node further includes a first cache for a first processor core, a second processor core, and a second cache for the second processor core. The directory listening extended filter is configured to send a listening request to the second cache in response to the first consistency directory being queried by the first node consistency extension unit and the first data being found and the second cache having cached the first data. The second cache is configured to return the first data to the first cache in response to the listening request.

[0084] In at least one embodiment, for example, the plurality of nodes further includes a second node, the second node including a memory controller, a directory snooping filter for the memory controller, and system memory controlled by the memory controller, the directory snooping filter including a second consistency directory, the storage address of the first data being located in the system memory of the second node; a first processor core is configured to return the first data to a first cache in response to a second cache response snooping request and issue a read response acknowledgment message; the first node consistency extension unit is further configured to update the first consistency directory of the directory snooping extension filter according to the cache consistency status of the first data, and forward the read response acknowledgment message to the memory controller of the second node; the memory controller is configured to update the second consistency directory of the directory snooping filter according to the cache consistency status of the first data.

[0085] In at least one embodiment, for example, the plurality of nodes further includes a second node, the second node including a memory controller and a system memory controlled by the memory controller, the storage address of the first data being located in the system memory of the second node; the first node further includes a first cache for the first processor core; the first node consistency extension unit is further configured to forward a first access request to the memory controller of the second node in response to a query by the first node consistency extension unit that the directory entry of the first consistency directory does not match the first data.

[0086] In at least one embodiment, for example, the first node consistency extension unit is further configured to, in response to the memory controller of the second node reading first data from the system memory and returning it to the first node consistency extension unit, return the first data to the first cache for caching the first data by the first cache, and update the first consistency directory according to the cache consistency status of the first data.

[0087] In at least one embodiment, for example, the second node further includes a directory snooping filter for the memory controller, the directory snooping filter including a second consistency directory; the memory controller is configured to, in response to the memory controller of the second node reading first data from the system memory and returning it to the first node inter-consistency extension unit, update the second consistency directory according to the cache consistency status of the first data.

[0088] In at least one embodiment, for example, the second node further includes a second node consistency extension unit configured for inter-node interconnection; the first node consistency extension unit and the second node consistency extension unit are also configured to communicate with each other to transmit requests and responses between the first node and the second node.

[0089] In at least one embodiment, for example, the first node consistency extension unit is configured to replace or evict the directory item corresponding to the first data from the first consistency directory in response to a replacement or eviction operation of the first consistency directory.

[0090] In at least one embodiment, for example, the first node consistency extension unit is further configured to notify the directory listener filter in response to replacing or evictping the directory item corresponding to the first data from the first consistency directory.

[0091] In at least one embodiment, for example, the first node further includes a switching unit, through which the inter-node consistency extension unit communicates with the directory listening extension filter.

[0092] Corresponding to the above embodiments, the data processing method according to the embodiments of this disclosure further includes corresponding steps, which will not be repeated here.

[0093] Some embodiments and examples of this disclosure will now be described with reference to the accompanying drawings.

[0094] Figure 4A schematic diagram of a processor node of an electronic device according to at least one embodiment of the present disclosure is shown. The electronic device includes a plurality of processor nodes, including node 200, which is, for example, an example of "first node" or "second node" in this disclosure. Processor node 200 is, for example, a single processor chip or an independent portion of a processor chip, and constitutes the electronic device together with other processor nodes. In embodiments of the present disclosure, the plurality of nodes may have... Figure 4 The same or similar architecture is shown.

[0095] For example, multiple chips in this electronic device can be packaged using a multi-chip module (MCM) or a chiplet. MCM (Multi-Chip Module) packaging technology encapsulates multiple independent chips within a single module. A chiplet refers to breaking down a complete chip design into multiple smaller modules (chips), each module being called a chiplet; these chiplets can be designed and manufactured independently, and then integrated together using interconnect technology to form a complete chip system.

[0096] In embodiments of this disclosure, a node refers, for example, to a chip that includes one or more processor cores, one or more memories, and one or more (inter-chip) coherence extension units.

[0097] like Figure 4 As shown, processor node 200 is a multi-processor, multi-cache system that uses directory sniffing filters to maintain cache coherency. Processor node 200 includes n+1 processor cores 110–11n, n+1 caches (hereinafter also referred to as "caches") 120–12n, a coherency interconnect bus 114, m+1 memory controllers 140–14m, m+1 system memory 130–13m, m+1 directory sniffing filters 150–15m, a coherency extension unit 115, and a directory sniffing extension filter 15X, where n and m are both integers greater than or equal to 0.

[0098] Here, directory snooping filters 150-15m are examples of the "directory snooping filters" in this disclosure, including a second consistent directory; directory snooping extended filter 15X is an example of the above-mentioned "directory snooping extended filter", including a first consistent directory; and consistency extension unit 115 is an example of the above-mentioned "inter-node consistency extension unit".

[0099] The directory structure of the first consistency directory and the second consistency directory can be referenced for example. Figure 2The scenario shown is not limited to this one. For example, during operation, the consistency directory is stored in static random access memory (SRAM). For instance, if the SRAM has an access linewidth of 128 bits, meaning each read / write operation is performed at a 128-bit granularity, then each read / write operation results in four directory entries. The organization of SRAM can vary, and the embodiments of this disclosure do not limit this; for example, reads and writes can be performed at other granularities. Furthermore, the embodiments of this disclosure do not specifically limit the content and bit width covered by each directory entry.

[0100] For example, each of caches 120 to 12n is configured to store data storage information corresponding to at least one piece of data. For example, caches 120 to 12n can be multiple dedicated caches used by processor cores 110 to 11n respectively. In addition, the processor node 200 may also include shared caches for processor cores 110 to 11n, for example, one shared cache shared by every two processor cores.

[0101] like Figure 4 As shown, the above m+1 memory controllers 140-14m correspond to m+1 system memories 130-13m respectively; the above m+1 memory controllers 140-14m correspond to m+1 directory snooping filters 150-15m respectively. These memory controllers are used to manage and control access to and operation of the system memories, and as consistency nodes, they connect the corresponding directory snooping filters and system memories to the consistency interconnect bus 114.

[0102] These directory snooping filters are used to maintain the consistency of data in the corresponding system memory within the aforementioned caches 120-12n. More specifically, directory snooping filters 150-15m can help track the cached data status in caches 120-12n; for example, for a given piece of data, the cached data status may include: one or more caches 120-12n containing only a single copy of the cached data, multiple copies of the cached data, or the data existing only in main memory. Directory snooping filters 150-15n and directory snooping extended filter 15X track the cached data status of caches 120-12n in processor cores 110-11n and store the tracked status information in the directories of directory snooping filters 150-15n and directory snooping extended filter 15X. When the consistency broker snooping bus detects a consistent transaction, it queries directory snooping extended filter 15X or, if necessary, directory snooping filters 150-15n for the tracked status information and issues a corresponding snooping request to complete consistency maintenance.

[0103] For example, such as Figure 4As shown, the coherence interconnect bus 114 is directly coupled to caches 120-12n and also directly coupled to memory controllers 140-14m. The coherence interconnect bus 114 is a common communication trunk for information transmission; for example, the coherence interconnect bus 114 is a transmission harness composed of electronic components such as wires in the chip.

[0104] like Figure 4 As shown, in processor node 200, coherence extension unit 115 is used for inter-node communication, that is, to communicate with other processor nodes (e.g., chips) in the system, and is also connected to directory listener extension filter 15X to manage listener requests within node 200 by querying directory listener extension filter 15X.

[0105] Although Figure 4 The specific number of directory snooping filters, processor cores, memory controllers, caches, and system memory is shown, but embodiments of this disclosure are not limited to these specific numbers, which can be set to any value as needed.

[0106] The electronic devices in at least one embodiment of this disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle terminals (e.g., vehicle navigation terminals), wearable electronic devices, etc.; fixed terminals such as digital TVs, desktop computers, smart home devices, etc.; and server devices such as local area network servers, wide area network servers, cloud servers, etc.

[0107] For example, in at least one embodiment of this disclosure, the system memory can be main memory (e.g., DRAM) or external memory connected to the processor node 200, such as hard disk, floppy disk, optical disk, USB flash drive, etc.

[0108] For example, memory controllers, directory snooping filters, and consistency extension units can be implemented using software, hardware, firmware, or any feasible combination thereof. For instance, they can include logic devices such as registers, latches, flip-flops, caches, inverters, etc. For example, the processor core can be a central processing unit (CPU) or other processing units with data processing and / or program execution capabilities, such as a field-programmable gate array (FPGA) or a tensor processing unit (TPU); for example, the CPU can be based on x86, RISC-V, or ARM architectures.

[0109] The embodiments disclosed herein do not limit the type of processor core, the microarchitecture used, the instruction set, etc. For example, the x86 instruction set and any corresponding microarchitecture can be used, the Arm instruction set and any corresponding microarchitecture can be used, or the RISC-V instruction set and any corresponding microarchitecture can be used, etc.

[0110] Similarly, the embodiments of this disclosure do not limit the types of caches, system memory, etc. It should be noted that, in the embodiments of this disclosure, the dedicated cache of the processor core refers to the cache that can only be accessed by that processor (e.g., L1 cache, L2 cache), while the shared cache (e.g., L3 cache or last-level cache) can be accessed by multiple processor cores.

[0111] For example, when processor core 110 needs to read certain data, it first accesses at least one dedicated cache 120 used by processor core 110. When the dedicated cache 120 does not store the data that processor core 110 needs to read (i.e., when the lookup cache is missing), processor core 110 then accesses the next-level cache. When all dedicated caches have been accessed and the required data is not obtained, processor core 110 can continue to access at least one shared cache (not shown in the figure) or a system memory (e.g., system memory 130) used by processor core 110.

[0112] For example, each cache includes a cache control module that can access each storage unit in the cache to read the content stored in that unit and then parse that content. When determining whether the data to be read in a read request issued by the processor core is stored in a certain cache, the cache control module performs this determination. That is, the cache control module reads and parses the content from the storage unit, compares the parsed content with the data to be read determined based on the read request, and thus determines whether the data stored in the storage unit matches the data to be read.

[0113] Figure 5A and Figure 5B These are schematic diagrams illustrating the process of data access between nodes according to at least one embodiment of this disclosure. For the sake of simplicity, each node is... Figure 4 The illustrated embodiment is a simplified version of the processor node, with parts omitted from the following description.

[0114] Figure 5A and Figure 5BThe schematic diagram relates to an electronic device according to at least one embodiment of the present disclosure, wherein the electronic device in the embodiment is a multi-node system, such as a two-node system or two nodes in a multi-node system, the two nodes being, for example, examples of the first node and the second node in the present disclosure. Similarly, a "requesting node" refers to the node that sends an access request, while a "home node" refers to the node where the memory to be accessed by the access request resides.

[0115] In the above system, each of the multiple nodes has, for example, multiple processor cores (processor core 0 to processor core n) and two or more caches corresponding to each processor core (not shown in the figure). The multiple nodes communicate with each other through their respective inter-chip consistency extension units. Moreover, each node includes a directory listening extension filter, which includes a consistency directory.

[0116] Figure 5A The following describes the operation that involves the processor kernel within the requesting node reading certain data for the first time, but the directory listener filter query misses the result.

[0117] (a) The requesting node processor core 0 on the left generates a read request for the first data in the system memory located in the home node on the right, i.e., to read the first data, and the read request is sent to the memory controller 0 of the home node on the right.

[0118] (b) The inter-segment consistency extension unit of the requesting node receives the read request, and then queries the consistency directory of the directory listening extension filter of the inter-segment consistency extension unit for the first data. The query result is a miss.

[0119] (c) The inter-chip consistency extension unit of the requesting node forwards the read request to the home node, and the inter-chip consistency extension unit of the home node forwards the read request to the memory controller 0 of the home node.

[0120] (d) The memory controller 0 of the home node queries the first data in the consistency directory of the corresponding directory listener filter 0, and the query result is a miss.

[0121] (e) The memory controller 0 of the home node sends a read request to the system memory 0;

[0122] (f) The home node's system memory 0 returns the first data to be read;

[0123] (g) After the memory controller 0 of the home node receives the first data, the first data will be returned to the cache of the processor core 0 of the requesting node, and the cache status will be marked in the consistency directory of the memory controller 0 in the corresponding directory listener filter 0.

[0124] (h) At the same time, the home node's memory controller 0 returns the first data to be read to the requesting node's processor core 0;

[0125] (i) When the returned first data passes through the inter-segment consistency extension unit of the requesting node, the inter-segment consistency extension unit of the requesting node marks the cached state of the first data in the consistency directory of the directory extension listener filter 0 corresponding to the inter-segment consistency extension unit.

[0126] At this time, the consistency directory of the directory listener extension filter of the inter-chip consistency extension unit of the requesting node and the consistency directory of the directory listener filter 0 corresponding to memory controller 0 both record that the above data is cached in the cache of the processor core 0 of the requesting node, for example, in the state of "Exclusive".

[0127] Figure 5B The operation involving another processor core n within the requesting node reading the aforementioned data from the same address again, and the directory listener filter query being hit, is explained in detail below.

[0128] (a) Another processor core n of the requesting node on the left issues a read request for the first data with the same address, that is, it also wants to read the first data. The read request is sent to the memory controller 0 of the home node on the right through the inter-chip consistency extension unit of the requesting node.

[0129] (b) The inter-chip consistency extension unit of the requesting node receives the read request, and then queries the consistency directory of the directory listening extension filter of the inter-chip consistency extension unit for the first data. If the query result is a hit, it is determined that the first data has been cached in the cache of processor core 0 in the requesting node.

[0130] (c) The inter-chip consistency extension unit of the requesting node sends a listen request to the processor core 0 of the requesting node;

[0131] (d) The processor core 0 of the requesting node directly returns the cached first data to the processor core n of the requesting node, and the cache of the processor core n of the requesting node caches the first data.

[0132] (e) The processor core n of the requesting node sends a read response confirmation message to the inter-chip consistency extension unit of the requesting node;

[0133] (f) The requesting node's inter-segment consistency extension unit updates the consistency directory of the directory listening extension filter 0 corresponding to the first data;

[0134] (g) The inter-chip consistency extension unit of the requesting node sends an update request to the directory listener filter 0 corresponding to the memory controller 0 of the home node.

[0135] (h) After passing through the inter-chip consistency extension unit of the home node, the directory listener filter 0 corresponding to the memory controller 0 of the home node receives the directory update request and updates the consistency directory of the directory listener filter 0.

[0136] At this time, the consistency directory of the directory listener extension filter of the inter-chip consistency extension unit of the requesting node and the consistency directory of the directory listener filter 0 corresponding to memory controller 0 both record that the above data is simultaneously cached in the cache of processor core 0 and the cache of processor core n of the requesting node, for example, in the state of "shared".

[0137] exist Figure 5B In the scenario shown, when a processor core (processor core n) in a node requests data that is already cached in the cache of another processor core (processor core 0) in the same node, the directory snooping extended filter of the inter-chip consistency extension unit of that node queries its consistency directory hit. At this point, it only needs to send a snooping request to processor core 0, so that processor core 0 can directly return the data it wants to read to processor core n. Therefore, the snooping request is only transmitted within the node and will not be transmitted as... Figure 3B As shown, inter-chip transmission is required, thus reducing the amount of data transmitted between chips.

[0138] In at least one embodiment, due to capacity limitations, after the system has been running for a period of time, the consistency directory of the inter-chip consistency extension unit may replace or evict directory entries that may not be currently used (or are not frequently used) according to a certain replacement algorithm or eviction algorithm in order to fill in new directory entries. This operation may result in a query miss for the replaced or evictped directory entry shortly after the replacement or eviction. At this time, the inter-chip consistency extension unit will send the corresponding data read request to the home node for processing.

[0139] Figure 5C If the consistency directory of the inter-chip consistency extension unit within the requesting node has been replaced or evicted, and another processor core n reads the aforementioned data from the same address again (i.e., Figure 5A The following is a detailed explanation of how to handle situations where the directory listener filter query fails to find the data involved.

[0140] (a) Another processor core n of the requesting node on the left issues a read request for the first data with the same address, that is, it also wants to read the first data. The read request is sent to the memory controller 0 of the home node on the right through the inter-chip consistency extension unit of the requesting node.

[0141] (b) The inter-segment consistency extension unit of the requesting node receives the read request, and then queries the consistency directory of the directory listening extension filter of the inter-segment consistency extension unit for the first data. The query result is a miss.

[0142] (c) The inter-chip consistency extension unit of the requesting node forwards the read request to the home node, and the inter-chip consistency extension unit of the home node forwards the read request to the memory controller 0 of the home node.

[0143] (d) The memory controller 0 of the home node queries the first data in the consistency directory of the corresponding directory listener filter 0, and the query result is a hit.

[0144] (e) Based on the state that the query result is a hit, the memory controller 0 of the home node determines that the first data has been cached in the cache of the processor core 0 in the requesting node, and sends a listening request to the processor core 0 of the requesting node. The listening request reaches the processor core 0 of the requesting node through the inter-chip consistency extension unit of the home node and the inter-chip consistency extension unit of the requesting node.

[0145] (f) The processor core 0 of the requesting node directly returns the cached first data to the processor core n of the requesting node based on the above listening request;

[0146] (g) The requesting node's processor core n sends a read response confirmation message to the home node's memory controller 0;

[0147] (h) When the read response confirmation message passes through the inter-segment consistency extension unit of the requesting node, the inter-segment consistency extension unit of the requesting node updates the consistency directory of its corresponding directory listening extension filter according to the cache state of the read data.

[0148] (i) The read response confirmation message is sent to the memory controller 0 of the home node via the inter-slice consistency extension unit of the home node. When the memory controller 0 of the home node receives the read response confirmation message, it updates the consistency directory of its corresponding directory listener filter 0 according to the cache status of the read data.

[0149] At this time, the consistency directory of the directory listener extension filter of the inter-chip consistency extension unit of the requesting node and the consistency directory of the directory listener filter 0 corresponding to memory controller 0 both record the above data again, which is simultaneously cached in the cache of processor core 0 and the cache of processor core n of the requesting node, for example, in the state of "shared".

[0150] As can be seen, even when the inter-shard consistency extension unit of the requesting node misses the corresponding consistency directory in the event of replacement or eviction, and Figure 3BCompared to the previous scenario, the amount of data transmitted between nodes (or between chips) is the same, without putting additional pressure on bandwidth. Moreover, after refilling the consistency directory corresponding to the inter-chip consistency extension unit, the bandwidth pressure of inter-node transmission can be alleviated in subsequent operations, the overall access latency can be shortened, and system performance can be improved.

[0151] The size of the consistency directory of the inter-chip consistency extension unit is not necessarily the same as the size of the consistency directory corresponding to the home node's memory controller. For example, the size of the consistency directory of the inter-chip consistency extension unit can be smaller. Even if the consistency directory of the inter-chip consistency extension unit is replaced or evicted due to capacity limitations, it is not necessary to notify the processor core and the consistency directory corresponding to the home node's memory controller. However, the consistency directory corresponding to the home node's memory controller needs to maintain the accuracy of its records at all times. This means that for data targeted by a replacement or eviction operation, if the inter-chip consistency extension unit performs a consistency directory lookup and misses, the consistency directory lookup performed by the home node's memory controller will still succeed; if the home node's memory controller performs a consistency directory lookup and misses, then the consistency directory lookup performed by the inter-chip consistency extension unit will inevitably fail. The advantages of this setting include:

[0152] (1) Maintaining the consistency directory of the inter-chip consistency extension unit is relatively simple;

[0153] (2) It can reduce cross-chip directory maintenance requests and alleviate the pressure on inter-chip transmission bandwidth.

[0154] If the consistency directory corresponding to the inter-chip consistency extension unit is evicted or downgraded, the corresponding processor core and the memory controller of the home node should be notified to maintain the same consistency directory. In this case, the home node directory may not need to be evicted or downgraded, and such an operation may affect / degrade system performance.

[0155] In some embodiments of this disclosure, the maintenance of the consistent directory of the directory snooping extended filter is not limited to replacing or evicting the directory snooping filter corresponding to the memory controller of the home node as mentioned above. In some examples, the directory snooping filter corresponding to the memory controller of the home node may also be notified.

[0156] In at least some embodiments of this disclosure, the directory snooping extended filter interfaces with the inter-chip consistency extended unit. However, the connection location of the directory snooping extended filter is not limited to the inter-chip consistency extended unit, and it can also interface with other units in the system.

[0157] Figure 6A schematic diagram of a processor node 300 of an electronic device according to at least one embodiment of the present disclosure is shown. The electronic device includes a plurality of processor nodes, the plurality of processor nodes including node 300. The processor node 300 is, for example, a single processor chip or a separate part of a processor chip, and constitutes the electronic device together with other processor nodes.

[0158] like Figure 6 As shown, processor node 300 is a multi-processor, multi-cache system that uses directory snooping filters to maintain cache coherency. Processor node 300 includes n+1 processor cores 210–21n, n+1 caches (hereinafter also referred to as "caches") 220–22n, a coherency interconnect bus 214, m+1 memory controllers 240–24m, m+1 system memories 230–23m, m+1 directory snooping filters 250–25m, a coherency extension unit 215, and a directory snooping extension filter 25X, where n and m are both integers greater than or equal to 0. Here, directory snooping filters 250–25m are examples of the aforementioned "directory snooping filters," and directory snooping extension filter 25X is an example of the aforementioned "directory snooping extension filter."

[0159] Except for the differences described below, processor node 300 is the same as processor node 200, so it will not be described again.

[0160] like Figure 6 As shown, in processor node 300, the coherence extension unit 215 is used to communicate with other processor nodes (e.g., chips) and is communicatively connected to the switching unit 210; the directory listener extension filter 25X is also communicatively connected to the switching unit 210. The coherence extension unit 215 and the directory listener extension filter 25X communicate indirectly through the switching unit 210, thereby allowing hierarchical management of listener requests for node 300 by querying the directory listener extension filter 25X. The switching unit 210 is connected to the coherence interconnect bus 214 and configured to control communication within node 300 via the coherence interconnect bus 214; furthermore, inter-node interconnection can also be accomplished through the switching unit 210 and the coherence extension unit 215 together.

[0161] Some embodiments of this disclosure also provide another data processing apparatus. Figure 7 This is a schematic diagram of a data processing apparatus provided for some embodiments of the present disclosure.

[0162] like Figure 7 As shown, the data processing apparatus 500 according to an embodiment of the present disclosure may include a processor 501 and a memory 502, which can be interconnected via a bus 503.

[0163] Processor 501 can perform various actions and processes according to the program or code stored in memory 502. Specifically, processor 501 can be an integrated circuit chip with signal processing capabilities. For example, the processor 501 can be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), off-the-shelf programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, capable of implementing or executing the various methods and steps disclosed in the embodiments of this disclosure. The general-purpose processor can be a microprocessor or any conventional processor, and can be an x86 architecture or an ARM architecture, etc.

[0164] The memory 502 is used for non-temporary storage of computer-executable instructions, and the processor 501 is used to execute the computer-executable instructions. When the computer-executable instructions are executed by the processor 501, they implement the data processing method provided in at least one embodiment of this disclosure.

[0165] For example, memory 502 may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM) used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct memory bus random access memory (DRRAM). It should be noted that the memory of the methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0166] Embodiments of this disclosure also provide a non-transitory storage medium, which can be a non-transitory computer-readable storage medium. The non-transitory storage medium is used to non-transitory store computer-executable instructions that, when executed by a computer, implement the data processing methods provided in some embodiments of this disclosure.

[0167] Figure 8 This is a schematic diagram of a non-transitory storage medium provided in some embodiments of this disclosure.

[0168] like Figure 8As shown, the non-temporary storage medium 600 can non-temporarily store computer-executable instructions 610, which, when executed by a computer, implement the data processing method provided in any embodiment of this disclosure.

[0169] Similarly, the non-transitory storage medium in the embodiments of this disclosure may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. It should be noted that the memory used in the methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0170] Embodiments of this disclosure also provide a computer program product or non-transitory storage medium, the computer program product including computer instructions, or the computer instructions stored in the non-transitory storage medium. A processor of a computer device reads the computer instructions, executes the computer instructions, and causes the computer device to perform a data processing method according to any embodiment of this disclosure.

[0171] The technical effects of the aforementioned data processing device and non-transitory storage medium are the same as those of the aforementioned data processing method, and will not be repeated here.

[0172] It should be noted that the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing at least one executable instruction for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0173] In general, the various exemplary embodiments of this disclosure can be implemented in hardware or dedicated circuitry, software, firmware, logic, or any combination thereof. Some aspects can be implemented in hardware, while others can be implemented in firmware or software that can be executed by a controller, microprocessor, or other computing device. When aspects of embodiments of this disclosure are illustrated or described as block diagrams, flowcharts, or using some other graphical representation, it will be understood that the blocks, apparatuses, systems, techniques, or methods described herein can be implemented as non-limiting examples in hardware, software, firmware, dedicated circuitry or logic, general-purpose hardware or controllers or other computing devices, or some combination thereof.

[0174] The following points should be noted regarding this disclosure:

[0175] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0176] (2) For clarity, the thickness and dimensions of layers or structures are enlarged in the drawings used to describe embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element, or there may be intermediate elements present.

[0177] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0178] The above description is only a specific embodiment of this disclosure, but the protection scope of this disclosure is not limited thereto. The protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. A data processing method, comprising: A first processor core included in the first node generates a first access request for first data whose storage address is located outside the first node. The first node further includes a first node consistency extension unit and a directory snooping extension filter for the first node consistency extension unit. The directory snooping extension filter includes a first consistency directory. The first node consistency extension unit is configured for inter-node interconnection and manages snooping requests within the first node through the directory snooping extension filter. The first node consistency extension unit queries the first consistency directory of the directory listening extension filter to at least determine whether the first data is cached within the first node; The first node further includes a first cache for the first processor core, a second processor core, and a second cache for the second processor core. The data processing method further includes: in response to the first node consistency extension unit querying the first consistency directory to find the first data and determining that the second cache has already cached the first data, the directory listening extension filter sends the listening request to the second cache; the second cache responds to the listening request and returns the first data to the first cache.

2. The data processing method according to claim 1, wherein, The second node includes a memory controller, a directory snooping filter for the memory controller, and system memory controlled by the memory controller. The directory snooping filter includes a second consistency directory, and the storage address of the first data is located in the system memory of the second node. The data processing method further includes: In response to the second cache responding to the listening request, the first cache returns the first data, and the first processor core issues a read response confirmation message. The first node consistency extension unit updates the first consistency directory of the directory listener extension filter according to the cache consistency status of the first data, and forwards the read response confirmation message to the memory controller of the second node, so that the memory controller updates the second consistency directory of the directory listener filter according to the cache consistency status of the first data.

3. The data processing method according to claim 1, wherein, The second node includes a memory controller and a system memory controlled by the memory controller, wherein the storage address of the first data is located in the system memory of the second node. The first node also includes a first cache for the first processor core. The data processing method further includes: In response to the first node's inter-node consistency extension unit querying the directory entry of the first consistency directory and finding no match for the first data, the first node's inter-node consistency extension unit forwards the first access request to the memory controller of the second node.

4. The data processing method according to claim 3 further includes: In response to the memory controller of the second node reading the first data from the system memory and returning it to the first node consistency extension unit, the first node consistency extension unit returns the first data to the first cache to cache the first data in the first cache, and the first node consistency extension unit updates the first consistency directory according to the cache consistency status of the first data.

5. The data processing method according to claim 4, wherein, The second node also includes a directory listener filter for the memory controller, the directory listener filter including a second consistency directory. The data processing method further includes: In response to the memory controller of the second node reading the first data from the system memory and returning it to the consistency extension unit between the first nodes, the memory controller updates the second consistency directory according to the cache consistency status of the first data.

6. The data processing method according to claim 2 or 3, wherein, The second node also includes a second inter-node consistency extension unit, which is configured for inter-node interconnection. The data processing method further includes: The first node consistency extension unit and the second node consistency extension unit communicate with each other to transmit requests and responses between the first node and the second node.

7. The data processing method according to claim 2 or 5 further includes: In response to a replacement or eviction operation in the first consistency directory, the directory item corresponding to the first data is replaced or evictioned from the first consistency directory.

8. The data processing method according to claim 7 further includes: In response to replacing or evicting the directory item corresponding to the first data from the first consistency directory, the directory listening filter is notified.

9. The data processing method according to claim 1, wherein, The first node consistency extension unit communicates with the directory listening extension filter through the first node's exchange unit.

10. An electronic device comprising a plurality of nodes communicatively connected to each other, wherein, The plurality of nodes includes a first node, which includes a first processor core, a first inter-node consistency extension unit, and a directory listening extension filter for the first inter-node consistency extension unit. The directory listening extension filter includes a first consistent directory. The first inter-node consistency extension unit is configured for inter-node interconnection and manages listening requests within the first node through the directory listening extension filter. The first node consistency extension unit is configured to, in response to a first access request generated by a first processor core included in the first node for first data whose storage address is located outside the first node, query the first consistency directory of the directory listening extension filter to at least determine whether the first data is cached within the first node; The first node further includes a first cache for the first processor core, a second processor core, and a second cache for the second processor core. The directory listening extended filter is configured to send the listening request to the second cache in response to the first node consistency extension unit querying the first consistency directory to find the first data and determining that the second cache has already cached the first data. The second cache is configured to return the first data to the first cache in response to the listening request.

11. The electronic device according to claim 10, wherein, The plurality of nodes further includes a second node, which includes a memory controller, a directory snooping filter for the memory controller, and a system memory controlled by the memory controller. The directory snooping filter includes a second consistency directory, and the storage address of the first data is located in the system memory of the second node. The first processor core is configured to, in response to the second cache responding to the listen request, return the first data to the first cache and issue a read response confirmation message; The first node consistency extension unit is also configured to update the first consistency directory of the directory listening extension filter according to the cache consistency status of the first data, and forward the read response confirmation message to the memory controller of the second node; The memory controller is configured to update the second consistency directory of the directory listener filter based on the cache consistency status of the first data.

12. The electronic device according to claim 10, wherein, The plurality of nodes further includes a second node, which includes a memory controller and a system memory controlled by the memory controller, wherein the storage address of the first data is located in the system memory of the second node. The first node also includes a first cache for the first processor core. The first inter-node consistency extension unit is further configured to forward the first access request to the memory controller of the second node in response to a query by the first inter-node consistency extension unit that the directory entry of the first consistency directory does not match the first data.

13. The electronic device according to claim 12, wherein, The first inter-node consistency extension unit is further configured to, in response to the memory controller of the second node reading the first data from the system memory and returning it to the first inter-node consistency extension unit, return the first data to the first cache to cache the first data in the first cache, and update the first consistency directory according to the cache consistency status of the first data.

14. The electronic device according to claim 13, wherein, The second node also includes a directory listener filter for the memory controller, the directory listener filter including a second consistency directory. The memory controller is configured to, in response to the memory controller of the second node, read the first data from the system memory and return it to the first node inter-consistency extension unit, and update the second consistency directory according to the cache consistency status of the first data.

15. The electronic device according to claim 11 or 12, wherein, The second node also includes a second inter-node consistency extension unit, which is configured for inter-node interconnection. The first inter-node consistency extension unit and the second inter-node consistency extension unit are also configured to communicate with each other to transmit requests and responses between the first node and the second node.

16. The electronic device according to claim 11 or 14, wherein, The first inter-node consistency extension unit is configured to replace or evict the directory item corresponding to the first data from the first consistency directory in response to a replacement or eviction operation of the first consistency directory.

17. The electronic device according to claim 16, wherein, The first inter-node consistency extension unit is further configured to notify the directory listener filter in response to replacing or evicting the directory item corresponding to the first data from the first consistency directory.

18. The electronic device according to claim 10, wherein, The first node also includes a switching unit. The inter-node consistency extension unit communicates with the directory listening extension filter through the exchange unit of the first node.

19. A data processing apparatus, comprising: Memory, configured to store computer-executable instructions; as well as At least one processor configured to execute the computer-executable instructions, The computer-executable instructions, when executed by the at least one processor, implement the method according to any one of claims 1-9.

20. A non-transitory storage medium for non-transitory storage of computer-executable instructions, wherein, When the computer-executable instructions are executed by at least one processor, the method according to any one of claims 1-9 is implemented.

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