A decentralized multi-PEA architecture CGRA reconfigurable processor

Abstract

This application relates to a decentralized multi-PEA architecture CGRA reconfigurable processor, comprising multiple routers and multiple processing unit arrays interconnected via multiple routers. The routers are used for data transmission between the multiple processing unit arrays. Each processing unit array is used to control itself to execute a first preset task based on pre-stored first control information, or to transmit pre-stored second control information to other processing unit arrays via the routers. The processing unit arrays of this application autonomously acquire control information to achieve their own configuration and computation, and can also transmit control information to other processing unit arrays via the routers, thereby controlling the configuration and computation of other processing unit arrays. This achieves processor decentralization, reduces the interaction between the processor and the main core, and allows the processor to add more processing unit arrays to increase computing power.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a CGRA reconfigurable processor with a decentralized multi-PEA architecture. Background Technology

[0002] As algorithms iterate and update, higher demands are placed on processor computing power. Increasing the number of PEAs (Processing Element Arrays) within a chip to enhance processor computing power has become a major focus in multi-core / many-core processors and massively parallel computing architectures, and has become a mainstream solution in large-scale chip design. Traditional multi-PEA processors can use the main core controller to call upon each PEA to complete complex calculations.

[0003] However, during the operation, as the number of PEAs in the processor increases, and the number and frequency of control interactions between the main core controller and each PEA also increase, the control pressure on the main core controller gradually increases. Furthermore, the upper limit of the number of PEAs in this type of processor is relatively low, resulting in the processor's computing power not being able to meet actual needs. Summary of the Invention

[0004] Therefore, it is necessary to provide a decentralized multi-PEA architecture CGRA reconfigurable processor that can improve processor computing power to address the above-mentioned technical problems.

[0005] In a first aspect, this application provides a reconfigurable processor, which includes multiple routers and multiple processing unit arrays, the multiple processing unit arrays being interconnected through multiple routers;

[0006] Routers are used to transmit data between multiple processing unit arrays;

[0007] The processing unit array is used to control itself to execute a first preset task according to the first pre-stored control information, or to transmit the second pre-stored control information to other processing unit arrays through a router. The second control information is used to instruct other processing unit arrays to execute a second preset task.

[0008] In one embodiment, the above-mentioned processing unit array includes a multiplexer, a control core, a data storage, and multiple processing units. The multiplexer is connected to a router, the control core, and the data storage, respectively, and the control core is connected to an array of multiple processing units.

[0009] A multiplexer is used to transmit data between a router and the control core or between a router and a data storage device based on a selection signal.

[0010] A data storage device is used to store the first control information and the second control information;

[0011] The control core is used to control the processing unit to execute a first preset task according to the first control information, or to transmit the second control information to the control core of other processing unit arrays through a multiplexer and a router. The second control information is used to instruct the control core of other processing unit arrays to control the processing units in other processing unit arrays to execute the second preset task.

[0012] In one embodiment, the above-described processing unit array further includes registers, which are connected to a multiplexer and a control core, respectively.

[0013] Multiplexers are also used to transmit data between routers and registers based on selection signals;

[0014] The register is used to store the control instructions, iteration information, and data information corresponding to the first control information.

[0015] In one embodiment, the above-mentioned register includes a control information storage register, which is connected to the multiplexer and the control core respectively;

[0016] A multiplexer is specifically used to transmit data between a router and a control information storage register based on a selection signal.

[0017] The control information register is used to store control commands.

[0018] In one embodiment, the register includes an iteration information storage register; the iteration information storage register is connected to a multiplexer;

[0019] A multiplexer is specifically used to transmit data between a router and a control information storage register based on a selection signal.

[0020] The iteration information storage register is used to store iteration information.

[0021] In one embodiment, the above-mentioned register includes a data information storage register, which is connected to a multiplexer;

[0022] A multiplexer is specifically used to transmit data between a router and a data storage register based on a selection signal.

[0023] Data information storage register, used to store data information.

[0024] In one embodiment, the above-mentioned processing unit array further includes a configuration information memory, which is connected to a multiplexer and a plurality of processing units respectively.

[0025] A multiplexer is used to transmit data between a router and a configuration information storage device based on a selection signal.

[0026] Configuration information storage is used to store configuration information required by multiple processing units.

[0027] In one embodiment, the reconfigurable processor further includes a total memory and a main core controller, the total memory being connected to a router, and the main core controller being connected to the router.

[0028] Total memory is used to store the first and second control information required by the reconfigurable processor;

[0029] The main core controller is used to control the total memory to transmit the first control information and the second control information to any processing unit array through the router.

[0030] In one embodiment, the control core is also used to modify the address information of the registers in order to control the data memory to interact with the main memory.

[0031] In a second aspect, this application also provides an electronic device that includes a reconfigurable processor as described in the first aspect above.

[0032] The aforementioned decentralized multi-PEA architecture CGRA reconfigurable processor includes multiple routers and multiple processing unit arrays, which are interconnected through multiple routers. Routers are used for data transmission between the multiple processing unit arrays. Each processing unit array is used to control itself to execute a first preset task based on pre-stored first control information, or to transmit pre-stored second control information to other processing unit arrays via routers. The second control information instructs other processing unit arrays to execute a second preset task. In this embodiment, the processing unit arrays autonomously acquire control information to achieve their own configuration and computation. Furthermore, they can transmit control information to other processing unit arrays via routers, thereby controlling the configuration and computation of other processing unit arrays. This achieves processor decentralization, reduces interaction between the processor and the main core, and allows the processor to add more processing unit arrays to increase computing power. Attached Figure Description

[0033] Figure 1 This is one of the structural block diagrams of processors in related technologies;

[0034] Figure 2 This is the second block diagram of the processor structure in related technologies;

[0035] Figure 3 This is the third block diagram of the processor structure in related technologies;

[0036] Figure 4This is the fourth block diagram of the processor structure in related technologies;

[0037] Figure 5 This is a block diagram of a reconfigurable processor in one embodiment;

[0038] Figure 6 This is one of the structural block diagrams of the processing unit array in one embodiment;

[0039] Figure 7 This is a second structural block diagram of the processing unit array in one embodiment;

[0040] Figure 8 This is one of the block diagrams of the register in one embodiment;

[0041] Figure 9 This is a second structural block diagram of the register in one embodiment;

[0042] Figure 10 This is the third structural block diagram of the register in one embodiment;

[0043] Figure 11 This is the third structural block diagram of the processing unit array in one embodiment;

[0044] Figure 12 Here is a block diagram of the reconfigurable processor in another embodiment;

[0045] Figure label:

[0046] Router 10, processing unit array 20, multiplexer 210, control core 220, data memory 230, processing unit 240, register 250, control information storage register 251, iteration information storage register 252, data information storage register 253, configuration information memory 260, total memory 30, main core controller 40. Detailed Implementation

[0047] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0048] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0049] First, before introducing the technical solutions of the embodiments of this application in detail, the technical background on which the embodiments of this application are based will be introduced.

[0050] As algorithms iterate and update, applications demand increasingly higher computing power. Therefore, such as Figure 1 As shown, a series of reconfigurable processors, represented by CGRA (Coarse-grained Reconfigurable Architecture), need to increase the number of PEAs and design multi-PEA architecture reconfigurable processors to improve computing power.

[0051] On-chip interconnects (IoCs) have gained significant attention in multi-core / many-core processor chips and massively parallel computing architectures due to their excellent scalability, predictable latency, high bandwidth and parallelism, high reusability, low power consumption, and good placement and routing, and have become a mainstream solution for large-scale chip design. For example... Figure 2 As shown, it is an excellent choice for implementing a scalable, distributed, multi-PEA reconfigurable architecture.

[0052] The on-chip network architecture enables multi-PEA reconfigurable processors to be effectively expanded, but the number of expanded PEAs is still limited by the main core.

[0053] Traditional multi-PEA processor chips rely on a master controller to call upon each PEA to perform complex calculations. This design is primarily based on the Pareto Principle (80 / 20 rule): 80% of an application's execution time is concentrated in 20% of its code. However, this design becomes increasingly unsuitable as the number of PEAs increases, as does the frequency and number of control interactions between the master controller and each PEA.

[0054] The increasing proportion of interaction time between the controller and the PEA has given rise to decentralized design solutions: such as Figure 3 As shown, the control functions implemented by the main controller are partially transferred to each PEA, allowing the PEAs to achieve autonomous control, reducing the control pressure on the main core and the interaction time with each PEA.

[0055] like Figure 4As shown, by combining on-chip network design and decentralized design, a distributed multi-PEA CGRA hardware accelerator can be realized. This design has high scalability and efficiently increases the number of PEAs. The decentralized design also increases the upper limit of deployable PEAs, further enhancing the architecture's computing power.

[0056] However, having the core responsible for computational acceleration implement control functions increases the cost, overhead, and energy consumption of the hardware design. How to balance decentralized design and achieve as much decoupling as possible between the main controller and hardware accelerators as possible while minimizing resource overhead is currently the main challenge facing decentralized design.

[0057] Based on this, this application provides a decentralized multi-PEA architecture CGRA reconfigurable processor, which aims to solve the above-mentioned technical problems.

[0058] This application provides a reconfigurable processor, please refer to [link to relevant documentation]. Figure 5 The reconfigurable processor 10 includes multiple routers 10(R) and multiple processing unit arrays 20 (PEA), which are interconnected through multiple routers 10.

[0059] The router 10 in this embodiment can be used to transmit data between multiple processing unit arrays 20. The processing unit arrays 20 can be used to control themselves to execute a first preset task according to pre-stored first control information, or to transmit pre-stored second control information to other processing unit arrays through the router, wherein the second control information is used to instruct other processing unit arrays to execute a second preset task.

[0060] The first control information includes first configuration data and first computation data. The second control information, used for transmission to other processing unit arrays, includes second configuration data and second computation data. The first preset task may include a configuration task and a computation task. The second preset task may include a configuration task and a computation task.

[0061] The aforementioned reconfigurable processor includes multiple routers and multiple processing unit arrays, which are interconnected via multiple routers. Routers are used for data transmission between the multiple processing unit arrays. Each processing unit array is used to control itself to execute a first preset task based on pre-stored first control information, or to transmit pre-stored second control information to other processing unit arrays via routers. The second control information instructs other processing unit arrays to execute a second preset task. In this embodiment, the processing unit arrays autonomously acquire control information to achieve their own configuration and computation. Furthermore, they can transmit control information to other processing unit arrays via routers, thereby controlling the configuration and computation of other processing unit arrays. This achieves processor decentralization, reduces interaction between the processor and the main core, and allows the processor to add more processing unit arrays to increase computing power.

[0062] In one exemplary embodiment, based on the above embodiments, please refer to... Figure 6 The processing unit array 20 in this embodiment includes a multiplexer 210, a control core 220, a data storage 230 (Shared Memory), and multiple processing units 240. The multiplexer 210 is connected to the router 10, the control core 220 (Ctrl_PE), and the data storage 230, respectively. The control core 220 is connected to the array composed of the multiple processing units 240.

[0063] The multiplexer 210 in this embodiment can be used to transmit data between router 10 and control core 220 or between router 10 and data storage 230 according to the selection signal.

[0064] The data storage device 230 can be used to store the first control information and the second control information;

[0065] The data memory 230 can store first control information and second control information, and the data memory 230 can be transmitted to other processing unit arrays through the multiplexer 210.

[0066] The control core 220 can be used to control the processing unit 240 to perform a first preset task according to the first control information, or to transmit the second control information to the control core 220 of other processing unit arrays through the multiplexer 210 and the router 10. The second control information is used to instruct the control core 220 of other processing unit arrays to control the processing unit 240 (PE) in other processing unit arrays to perform the second preset task.

[0067] Each processing unit array 20 includes multiple processing units 240, and each processing unit array 20 includes a small control core 220. The control core 220 can control the data memory 230 to interact with the outside world through the multiplexer 210.

[0068] In this embodiment, each processing unit array is configured with a simple control core, enabling each processing unit array to autonomously acquire control information, thereby enabling its own configuration and computation. Furthermore, it can transmit control information to other processing unit arrays through a router, thereby controlling other processing unit arrays to perform configuration and computation. This achieves processor decentralization, reduces the interaction between the processor and the main core, and allows the processor to add more processing unit arrays to improve computing power.

[0069] In one exemplary embodiment, based on the above embodiments, please refer to... Figure 7 The processing unit array 20 in this embodiment further includes a register 250, which is connected to the multiplexer 210 and the control core 220, respectively, wherein:

[0070] The multiplexer 210 in this embodiment is also used to transmit data between the router 10 and the register 250 according to the selection signal.

[0071] Register 250 can be used to store control instructions, iteration information, and data information corresponding to the first control information. The control instructions are used to control whether the processing unit array is started and whether the operation or configuration task is started. The iteration information includes the number of iterations for the operation or configuration, and the data information includes weight data and stimulus data required for the operation.

[0072] In this embodiment, the registers in the processing unit array can store control instructions, iteration information and data information corresponding to the first control information and control instructions, iteration information and data information corresponding to the second control information, which can realize fast data transmission between processing unit arrays to achieve high-speed operation.

[0073] In one exemplary embodiment, based on the above embodiments, please refer to... Figure 8 In this embodiment of the application, register 250 includes a control information storage register 251 (Control Reg), which is connected to both the multiplexer 210 and the control core 220. Wherein:

[0074] In this embodiment, the multiplexer 210 is specifically used to transmit data between the router 10 and the control information storage register 251 according to the selection signal. The control information register 251 can be used to store control commands. The control core 220 can modify the Control Reg to enable the PEA to perform data interaction between the shared memory and external systems, and to control whether the PEA module starts working.

[0075] In this embodiment, the control information storage register can store control information, and the control core only needs to modify the address information in the control information storage register to change the object of action. The control information storage register can control the data interaction between the data memory in the processing unit array and the outside, as well as control whether the PEA module starts working. Therefore, this embodiment does not require additional control signals to select the multiplexer, and only needs to use the address information stored in the control information storage register.

[0076] In one exemplary embodiment, based on the above embodiments, please refer to... Figure 9 In this embodiment, register 250 includes an iteration information storage register 252 (Iter_Reg). The iteration information storage register is connected to multiplexer 210, wherein:

[0077] In this embodiment, the multiplexer 210 is specifically used to transmit data between the router 10 and the control information storage register 252 according to the selection signal. The iteration information storage register 252 is used to store iteration information. The iteration information includes the number of iterations for calculation or configuration. The control core 220 can also modify the address information of the iteration information storage register 252.

[0078] In this embodiment of the application, the iteration information storage register can store the number of iterations of the operation or configuration, and can accurately calculate the number of operations during the operation.

[0079] In one exemplary embodiment, based on the above embodiments, please refer to... Figure 10 In this embodiment of the application, register 250 includes a data information storage register 253 (Global_Reg), which is connected to multiplexer 210. Wherein:

[0080] The multiplexer 210 in this embodiment is specifically used to transmit data between the router 10 and the data information storage register 253 according to a selection signal. The data information storage register 253 can be used to store data information, including weight data and stimulus data required for calculation.

[0081] In this embodiment, the data information storage register can store the weight data and incentive data required for the operation, which can improve the efficiency of data storage and transmission.

[0082] In one exemplary embodiment, based on the above embodiments, please refer to... Figure 11 The processing unit array 20 in this embodiment further includes a configuration information memory 260 (Context Memory), which is connected to the multiplexer 210 and multiple processing units 240 (PE).

[0083] The multiplexer 210 in this embodiment can be used to transmit data between the router 10 and the configuration information memory 260 according to a selection signal. The configuration information memory 260 can be used to store configuration information required by multiple processing units 240. The operation mode of the processing unit 240 depends on the configuration information of each PE stored in the configuration information memory 260.

[0084] In this embodiment, the configuration information storage can store the configuration information required by multiple processing units, and can realize automatic configuration of processing units under the control of the control core, thereby achieving decentralization of each processing unit.

[0085] In one exemplary embodiment, based on the above embodiments, please refer to... Figure 12 The reconfigurable processor in this embodiment further includes a total memory 30 (Buffer Pool memory) and a main core controller 40 (RISC-V processor). The total memory 30 is connected to the router 10, and the main core controller 40 is connected to the router 10. Wherein:

[0086] The total memory 30 can be used to store the first control information and the second control information required by the reconfigurable processor; the main core controller 40 can be used to control the total memory 30 to transmit the first control information and the second control information to any processing unit array 20 through the router 10.

[0087] The reconfigurable processor in this embodiment includes a 4x4 two-dimensional array. The first row and first column of the array houses a RISC-V processor responsible for task allocation and synchronization. The second row and second column of the array contains a buffer pool memory responsible for storing all configuration and data information required by the processing module. The other nodes on the array have the same architecture, enabling highly scalable reconfigurable processing with parallel computing capabilities. Units on the nodes can interact with each other and transmit configuration information via an on-chip network.

[0088] In an exemplary embodiment, based on the above embodiments, the control core 220 of this application embodiment is further used to modify the address information of the register 250 to control the data memory 230 to perform data interaction with the total memory 30.

[0089] This application's embodiments break down data transmission barriers by unifying the address space and adding multiplexers. The reconfigurable processor in this application's embodiments can achieve arbitrary data transfer between PEA registers and SharedMemory storage modules via a RISC-CV processor. It also allows PEAs to directly call registers of other PEAs or their own without going through the RISC-CV processor, configuring their functions and transferring data. The principle behind this design is that after unifying the address space of various registers and storage modules, only the address information in the Control Reg needs to be modified to change the object being acted upon. Therefore, this application's embodiments do not require additional control signals to select multiplexers; they only need to use the address information already stored in the registers.

[0090] This application also provides an electronic device including a reconfigurable processor. The reconfigurable processor includes: multiple routers and multiple processing unit arrays, the multiple processing unit arrays being interconnected via the multiple routers;

[0091] Routers are used to transmit data between multiple processing unit arrays;

[0092] The processing unit array is used to control itself to execute a first preset task according to the first pre-stored control information, or to transmit the second pre-stored control information to other processing unit arrays through a router. The second control information is used to instruct other processing unit arrays to execute a second preset task.

[0093] In an exemplary embodiment, the above-mentioned processing unit array includes a multiplexer, a control core, a data storage, and multiple processing units. The multiplexer is connected to the router, the control core, and the data storage, respectively, and the control core is connected to the array composed of multiple processing units.

[0094] A multiplexer is used to transmit data between a router and the control core or between a router and a data storage device based on a selection signal.

[0095] A data storage device is used to store the first control information and the second control information;

[0096] The control core is used to control the processing unit to execute a first preset task according to the first control information, or to transmit the second control information to the control core of other processing unit arrays through a multiplexer and a router. The second control information is used to instruct the control core of other processing unit arrays to control the processing units in other processing unit arrays to execute the second preset task.

[0097] In an exemplary embodiment, the above-described processing unit array further includes registers, which are connected to the multiplexer and the control core, respectively.

[0098] Multiplexers are also used to transmit data between routers and registers based on selection signals;

[0099] The register is used to store the control instructions, iteration information, and data information corresponding to the first control information.

[0100] In an exemplary embodiment, the above-mentioned register includes a control information storage register, which is connected to both the multiplexer and the control core.

[0101] A multiplexer is specifically used to transmit data between a router and a control information storage register based on a selection signal.

[0102] The control information register is used to store control commands.

[0103] In an exemplary embodiment, the above-mentioned register includes an iteration information storage register; the iteration information storage register is connected to a multiplexer;

[0104] A multiplexer is specifically used to transmit data between a router and a control information storage register based on a selection signal.

[0105] The iteration information storage register is used to store iteration information.

[0106] In an exemplary embodiment, the above-mentioned register includes a data information storage register, which is connected to a multiplexer;

[0107] A multiplexer is specifically used to transmit data between a router and a data storage register based on a selection signal.

[0108] Data information storage register, used to store data information.

[0109] In an exemplary embodiment, the above-described processing unit array further includes a configuration information memory, which is connected to a multiplexer and a plurality of processing units respectively.

[0110] A multiplexer is used to transmit data between a router and a configuration information storage device based on a selection signal.

[0111] Configuration information storage is used to store configuration information required by multiple processing units.

[0112] In one exemplary embodiment, the reconfigurable processor further includes a total memory and a main core controller, the total memory being connected to a router, and the main core controller being connected to the router.

[0113] Total memory is used to store the first and second control information required by the reconfigurable processor;

[0114] The main core controller is used to control the total memory to transmit the first control information and the second control information to any processing unit array through the router.

[0115] In one exemplary embodiment, the control core described above is also used to modify the address information of the registers in order to control the data memory to interact with the main memory.

[0116] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0117] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A reconfigurable processor, characterized in that, The reconfigurable processor includes multiple routers and multiple processing unit arrays, the multiple processing unit arrays being interconnected through the multiple routers; The router is used for data transmission between the plurality of the processing unit arrays; The processing unit array is configured to control itself to execute a first preset task according to pre-stored first control information, or to transmit pre-stored second control information to other processing unit arrays via the router, wherein the second control information is used to instruct the other processing unit arrays to execute a second preset task; The processing unit array includes a multiplexer, a control core, a data storage, and multiple processing units. The multiplexer is connected to the router, the control core, and the data storage, respectively. The control core is connected to the array composed of the multiple processing units. The multiplexer is used to perform data transmission between the router and the control core or between the router and the data storage according to the selection signal; The data storage device is used to store the first control information and the second control information; The control core is used to control the processing unit to execute the first preset task according to the first control information, or to transmit the second control information to the control core of the other processing unit array through the multiplexer and the router. The second control information is used to instruct the control core of the other processing unit array to control the processing units in the other processing unit array to execute the second preset task.

2. The reconfigurable processor according to claim 1, characterized in that, The processing unit array also includes registers, which are connected to the multiplexer and the control core, respectively. The multiplexer is also used to perform data transmission between the router and the register according to the selection signal; The register is used to store the control instructions, iteration information, and data information corresponding to the first control information.

3. The reconfigurable processor according to claim 2, characterized in that, The register includes a control information storage register, which is connected to the multiplexer and the control core respectively. The multiplexer is specifically used to transmit data between the router and the control information storage register according to the selection signal; The control information register is used to store the control instructions.

4. The reconfigurable processor according to claim 2, characterized in that, The register includes an iteration information storage register; the iteration information storage register is connected to the multiplexer. The multiplexer is specifically used to transmit data between the router and the control information storage register according to the selection signal; The iteration information storage register is used to store the iteration information.

5. The reconfigurable processor according to claim 2, characterized in that, The register includes a data information storage register, which is connected to the multiplexer; The multiplexer is specifically used to perform data transmission between the router and the data information storage register according to the selection signal; The data information storage register is used to store the data information.

6. The reconfigurable processor according to any one of claims 1-5, characterized in that, The processing unit array further includes a configuration information memory, which is connected to the multiplexer and the plurality of processing units respectively. The multiplexer is used to transmit data between the router and the configuration information storage according to the selection signal; The configuration information storage is used to store the configuration information required by the multiple processing units.

7. The reconfigurable processor according to any one of claims 2-5, characterized in that, The reconfigurable processor further includes a total memory and a main core controller, wherein the total memory is connected to the router, and the main core controller is connected to the router. The total memory is used to store the first control information and the second control information required by the reconfigurable processor; The main core controller is used to control the total memory to transmit the first control information and the second control information to any of the processing unit arrays through the router.

8. The reconfigurable processor according to claim 7, characterized in that, The control core is also used to modify the address information of the register in order to control the data memory to interact with the main memory.

9. An electronic device, characterized in that, The electronic device includes a reconfigurable processor as claimed in any one of claims 1 to 8.

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