Chip large-scale parallel electrical detection method based on data dimension reduction and k-means++ algorithm

Abstract

The application relates to a chip large-scale parallel electrical detection method based on data dimension reduction and a K-means++ algorithm, which comprises the following steps: step 1, acquiring detection data of multiple chips collected in a large-scale electrical detection process; step 2, pre-processing the detection data of the chips to obtain a data set; step 3, constructing an adjacency graph according to the data set and constructing an adjacency matrix according to the adjacency graph; step 4, performing feature dimension reduction processing on the data set according to the adjacency matrix to obtain a dimension-reduced data sample corresponding to each sample in the data set; step 5, determining an optimal cluster number of a clustering algorithm; and step 6, performing clustering processing on the dimension-reduced data sample by using a K-means++ clustering method according to the optimal cluster number to obtain a clustering result, and determining a detection result of the chips according to the clustering result. The method can process the data of each chip in a large-scale chip in parallel and output a classification result of the chips.

Description

Technical Field

[0001] This invention belongs to the field of electrical testing technology for chips, specifically relating to a large-scale parallel electrical testing method for chips based on data dimensionality reduction and the K-means++ algorithm. Background Technology

[0002] Electrical testing of chips is the process of testing and sorting the electrical characteristics of chips during the manufacturing process. With the continuous development of chip manufacturing technology and the expansion of production capacity, more and more companies are realizing the importance of large-scale electrical testing.

[0003] On the one hand, as the application fields of chips continue to expand and diversify, the market's requirements for chips are also increasing. From artificial intelligence and the Internet of Things to 5G communications, the demand for high-performance, low-power, stable, and reliable chips is constantly growing across various fields. Faced with such a huge market demand, companies need to ensure that the chips they produce meet high-quality standards.

[0004] On the other hand, as chip size continues to shrink and integration increases, the number of components on the chip is also increasing dramatically. This makes the electrical characteristics and operating states of a single chip more complex.

[0005] Therefore, the traditional method of testing the electrical performance of each chip individually can no longer meet the demands of production speed and quality. To address these challenges, companies have begun to adopt large-scale electrical testing technologies.

[0006] Large-scale electrical testing (LDP) technology for chips does not have a fixed number of chips required; the number of chips tested simultaneously is determined by the specific algorithm and project requirements. LDP technology allows for the simultaneous testing of hundreds or even thousands of chips, thereby improving testing efficiency and throughput. This technology can not only screen out potentially defective chips but also provide more accurate electrical performance indicators and statistical data, offering engineers crucial information for improvement and decision-making.

[0007] However, the signals output during large-scale electrical testing of chips are characterized by numerous data features, high dimensionality, and massive data volume. Traditional chip electrical testing methods can only process the electrical performance data of a single chip serially, and batch testing using traditional chip electrical testing methods is time-consuming. Summary of the Invention

[0008] To address the aforementioned problems in existing technologies, this invention provides a large-scale parallel electrical testing method for chips based on data dimensionality reduction and the K-means++ algorithm. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a method for large-scale parallel electrical testing of chips based on data dimensionality reduction and the K-means++ algorithm, comprising: Step 1: Acquire test data from multiple chips collected during large-scale electrical testing; Step 2: Preprocess the detection data of the chip to obtain a dataset; Step 3: Construct an adjacency graph based on the dataset, and construct an adjacency matrix based on the adjacency graph; Step 4: Based on the adjacency matrix, perform feature dimensionality reduction on the dataset to obtain the dimensionality-reduced data sample corresponding to each sample in the dataset; Step 5: Determine the optimal number of clusters for the clustering algorithm; Step 6: Based on the optimal number of clusters, use the K-means++ clustering method to cluster the dimensionality-reduced data samples to obtain the clustering results, and determine the chip detection results based on the clustering results.

[0009] Compared with the prior art, the beneficial effects of the present invention are as follows: The present invention provides a large-scale parallel electrical testing method for chips based on data dimensionality reduction and the K-means++ algorithm. It utilizes the Laplace eigenmap dimensionality reduction algorithm to encode all the complex, multi-dimensional testing data of multiple chips obtained during large-scale electrical testing into an adjacency matrix. Then, it processes all data in parallel through matrix transformation, mapping it to a low-dimensional space. Next, it uses the K-means++ algorithm to further cluster the dimensionality-reduced data, obtaining the clustering results of the chip testing data. Finally, based on a pre-established mapping relationship between the chip testing data clustering results and fault categories, it obtains the chip testing results. This method can process the data of each chip in a large-scale chip system in parallel and output the chip classification results.

[0010] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of a large-scale parallel electrical detection method for chips based on data dimensionality reduction and K-means++ algorithm provided in an embodiment of the present invention; Figure 2 This is a flowchart of a large-scale parallel electrical testing method for chips based on data dimensionality reduction and K-means++ algorithm provided in an embodiment of the present invention; Figure 3This is a schematic diagram of the process for determining the optimal number of clusters provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the Kmeans++ algorithm provided in an embodiment of the present invention. Detailed Implementation

[0012] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following describes in detail, with reference to the accompanying drawings and specific embodiments, a chip large-scale parallel electrical detection method based on data dimensionality reduction and K-means++ algorithm proposed according to the present invention.

[0013] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0014] Please see Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of a large-scale parallel electrical detection method for chips based on data dimensionality reduction and the K-means++ algorithm provided in an embodiment of the present invention. Figure 2 This is a flowchart illustrating a large-scale parallel electrical testing method for chips based on data dimensionality reduction and the K-means++ algorithm, provided by an embodiment of the present invention. The large-scale parallel electrical testing method for chips based on data dimensionality reduction and the K-means++ algorithm in this embodiment includes: Step 1: Acquire test data from multiple chips collected during large-scale electrical testing; Optionally, the chip's test data includes: power consumption, frequency, voltage, current, temperature, AC test parameters frequency response, amplitude response and phase response, and pin resistance.

[0015] Step 2: Preprocess the chip's detection data to obtain a dataset; In an optional embodiment, step 2 includes: Step 2.1: Fill in missing values ​​in the chip's detection data; During chip testing, chip defects may cause some test data to be undetectable. In such cases, it is necessary to fill in the undetectable data according to the actual situation to facilitate subsequent data processing.

[0016] For example, if the pin resistance of the chip is infinite due to an open circuit, the pin resistance of the chip can be filled with a set ultra-large resistance value.

[0017] Step 2.2: Normalize the detection data of the chip after filling to obtain a dataset.

[0018] To avoid the influence of different feature weights due to different units, before performing Laplacian feature reduction, each feature component of the chip's detection data is mapped to the interval [0, 1] by linear function normalization. The normalization formula is as follows: (1); in, This represents the normalized value. This represents a specific feature component of the chip's detection data; and These represent the maximum and minimum values ​​of this feature component in the detection data of all chips, respectively.

[0019] In this embodiment, the preprocessed chip detection data is recorded as... ,in, The dataset consists of multiple chips, with n samples and s data feature dimensions for each sample.

[0020] Step 3: Construct an adjacency graph based on the dataset, and then construct an adjacency matrix based on the adjacency graph; In this embodiment, n points By constructing a graph, connecting the nearest points of each point and establishing adjacency relationships, and then using the Laplacian kernel function to determine the weights between adjacent points, the feature information of all n sample points is encoded into the adjacency matrix. Using the adjacency matrix for feature dimensionality reduction enables parallel processing of information during the dimensionality reduction process.

[0021] In an optional embodiment, step 3 includes: Step 3.1: Calculate the distance between samples in the dataset; Optionally, for each pair of samples, the distance between them is calculated using Euclidean distance, with the following formula: (2); In the formula, For samples in the dataset , For samples in the dataset .

[0022] Step 3.2: Consider two samples whose distance does not exceed a preset distance threshold as adjacent points, and construct an adjacency graph based on the adjacent points; In this embodiment, a preset distance threshold is used. This threshold is used to determine the range of adjacent points, and it can be adjusted based on the specific problem and the range of feature data values. For each sample, distances less than or equal to... Other samples are considered its adjacent points, and adjacency relationships are constructed, that is, Then an adjacency graph is constructed.

[0023] Step 3.3: Use the Laplace kernel function to determine the weights between adjacent nodes, set the weights between non-adjacent nodes to 0, and construct the adjacency matrix based on all weights.

[0024] In this embodiment, an adjacency matrix is ​​used. To represent an adjacency graph, where the adjacency matrix is... The rows and columns represent samples, and the matrix elements indicate whether there are edges connecting the samples.

[0025] If there are edges connecting samples, they are considered adjacent nodes, and the weights between adjacent nodes are set as follows: (3); In the formula, For samples in the dataset , For samples in the dataset , For the sample and samples The weights between them This is a constant for weight calculation. It is an adjacency matrix. Norm operations.

[0026] If there is no edge connection between samples, they are considered non-adjacent points, and the weight between non-adjacent points is set to 0.

[0027] Step 4: Based on the adjacency matrix, perform feature dimensionality reduction on the dataset to obtain the dimensionality-reduced data sample corresponding to each sample in the dataset; Alternatively, by using the adjacency matrix Perform matrix transformations and solve using the Lagrange multiplier method under constraints to obtain the solution matrix. The goal of Laplacian eigenmaps is to reduce the dimensionality of the data matrix, where the matrix... Each row vector It is sample data In the target Vector representation in a dimensional subspace.

[0028] In an optional embodiment, step 4 includes: Step 4.1: Construct the objective function for Laplacian eigenmap optimization based on the adjacency matrix; In this embodiment, the objective function is: (4); In the formula, For samples in the dataset and samples The weights between them For samples in the dataset The corresponding dimensionality reduction data samples, For samples in the dataset The corresponding dimensionality reduction data samples; Norm operations; Step 4.2: Simplify the objective function to obtain the simplified equivalent mathematical model; In this embodiment, the derivation process for simplifying the objective function is as follows:

[0029]

[0030]

[0031]

[0032]

[0033]

[0034]

[0035]

[0036] (5); Therefore, the simplified equivalent mathematical model is: (6); In the formula, For a dimensionality-reduced data matrix, a diagonal matrix Let be the degree matrix of the graph. , Let be the Laplace matrix of the graph. It is the identity matrix. Let be the trace of the matrix.

[0037] Among them, the limiting conditions This ensures that the optimization problem has a solution and that the mapped data points will not be compressed into a subspace of less than m dimensions.

[0038] Step 4.3: Solve the equivalent mathematical model using the Lagrange multiplier method to obtain the dimensionality-reduced data matrix of the dataset, and determine the dimensionality-reduced data sample corresponding to each sample in the dataset based on the dimensionality-reduced data matrix.

[0039] In this embodiment, the process of solving the equivalent mathematical model using the Lagrange multiplier method is as follows:

[0040]

[0041]

[0042] (7); in, It is a diagonal matrix. , All are real symmetric matrices, and their transposes are equal to themselves.

[0043] For individual The vector, equation (7) can be written as: Based on the relationship between matrix eigenvalues ​​and eigenvectors, we know that finding the matrix... of The eigenvectors corresponding to the smallest non-zero eigenvalues , That is Dimensionally reduced data down to m dimensions.

[0044] Step 5: Determine the optimal number of clusters for the clustering algorithm; Optionally, the elbow method is used to determine the number of clusters K, with its core metric being SSE (sum of the squared errors), expressed as: (8); in, It is the i-th cluster. yes The sample points in yes center of mass ( (mean of all samples in the sample) It represents the clustering error of all samples, indicating the quality of the clustering results.

[0045] The core idea is as follows: as the number of clusters k increases, the sample division becomes more detailed, and the degree of aggregation of each cluster gradually increases, thereby gradually reducing the sum of squared errors (SSE).

[0046] When k is less than the true number of clusters, increasing k significantly increases the aggregation of each cluster, leading to a large decrease in SSE. As k approaches the true number of clusters, the increase in aggregation from further increasing k diminishes rapidly, thus the decrease in SSE also slows down sharply. Subsequently, as the value of k continues to increase, the downward trend of SSE tends to level off. Therefore, the relationship between SSE and k graphically resembles an elbow shape, and the k value corresponding to this elbow is generally considered to be the true number of clusters in the data.

[0047] To avoid the ambiguity of subjective judgment, this embodiment uses the silhouette coefficient index for scoring. The silhouette coefficient takes into account the density within clusters and the separation between clusters; the closer the value is to 1, the better the sample clustering.

[0048] Please see Figure 3 The flowchart illustrating the process of determining the optimal number of clusters provided in the embodiment of the present invention, in an optional embodiment, includes step 5: Step 5.1: Determine the maximum number of clusters based on the types of chip faults. Number of clusters The initial value is 1; Step 5.2: Based on the current number of clusters, perform Kmeans++ clustering on each dimensionality-reduced data sample to obtain the corresponding clustering results; Step 5.3: Calculate the silhouette coefficient for each dimensionality-reduced data sample based on the clustering results; The silhouette coefficient of each dimensionality-reduced data sample is calculated using the following formula: (9); In the formula, The silhouette coefficients of the dimensionality-reduced data samples. To reduce the inter-cluster dissimilarity of data samples, This represents the average distance from a dimensionality-reduced data sample to other dimensionality-reduced data samples in the same cluster.

[0049] In this embodiment, The smaller the value, the more likely the dimensionality-reduced data sample should be clustered into that cluster. Also known as intra-cluster dissimilarity of dimensionality-reduced data samples. All dimensionality reduction data samples The mean is called the cluster. Cluster dissimilarity. Dimensionally reduced data samples from one cluster to other clusters. Average distance of all samples This is referred to as the dimensionality-reduced data sample of the cluster and the cluster. The dissimilarity is denoted as , The larger the value, the less likely the dimensionality-reduced data sample belongs to other clusters.

[0050] For the silhouette coefficients of each dimensionality-reduced data sample When expanded, it is as follows: (10); It can be seen that the silhouette coefficient of the dimensionality reduction data sample is in the range of [-1, 1], and the larger the value, the more reasonable it is. A value close to 1 indicates that the clustering of the dimensionality-reduced data samples is reasonable; A value close to -1 indicates that the dimensionality-reduced data samples should be classified into a different cluster; if... If the value is approximately 0, it indicates that the dimensionality-reduced data sample lies on the boundary between the two clusters.

[0051] Step 5.4: Calculate the silhouette coefficient of the clustering result based on the silhouette coefficient of each dimension-reduced data sample; In this embodiment, the silhouette coefficient of the clustering result is the mean silhouette coefficient of all dimensionality-reduced data samples, and the calculation formula is as follows: (11); In the formula, The silhouette coefficient is the result of clustering. This represents the number of samples in the dataset.

[0052] Step 5.5: Let Repeat steps 5.2-5.4 until... This yields the silhouette coefficients of multiple clustering results; Step 5.6: Select the number of clusters corresponding to the maximum value among the silhouette coefficients of multiple clustering results as the optimal number of clusters.

[0053] In this embodiment, As a metric for judging the reasonableness and effectiveness of clustering results, a value closer to 1 indicates better clustering of the samples. Therefore, the silhouette coefficient is chosen to optimize the clustering results. The largest The value is the optimal choice for the number of clusters.

[0054] Step 6: Based on the optimal number of clusters, use the K-means++ clustering method to cluster the dimensionality-reduced data samples to obtain the clustering results, and determine the chip detection results based on the clustering results.

[0055] After determining the optimal number of clusters After that, you can begin implementing large-scale parallel clustering of chip electrical performance using the Kmeans++ algorithm. Please refer to [link to relevant documentation]. Figure 4 The schematic diagram of the Kmeans++ algorithm provided in the embodiment of the present invention shown below, in an optional embodiment, includes step 6 as follows: Step 6.1: Randomly select one dimensionality-reduced data sample from the set of dimensionality-reduced data samples as the centroid of the first cluster; That is, from the dimensionality-reduced data sample space One sample is randomly selected from the middle. As the first cluster center of mass .

[0056] Step 6.2: Determine the nearest cluster centroid for the unselected dimensionality-reduced data sample, and calculate the Euclidean distance between the unselected dimensionality-reduced data sample and the nearest cluster centroid; In this embodiment, the Euclidean distance is: .

[0057] Step 6.3: Calculate the probability that each dimensionality-reduced data sample is selected as the cluster centroid of the next cluster, and use the roulette wheel method to select the cluster centroid of the next cluster; In this embodiment, the dimensionality reduction data sample The probability of being selected as the centroid of the next cluster. The calculation formula is as follows: (12).

[0058] The specific steps for selecting the next cluster centroid using the roulette wheel method are as follows: Step 1: Calculate the cumulative probability. For dimensionality reduction data samples arrive The arithmetic sum of the probabilities of being chosen is calculated using the following formula: (13); Step 2: Random selection, i.e., given a random number. If inequalities exist If true, then select the first option. A sample of dimensionality-reduced data As the cluster centroid of the next cluster.

[0059] Step 6.4: Repeat steps 6.2-6.3 until a selection is made. The centroid of each cluster is obtained. Clusters, The optimal number of clusters; In this embodiment, The centroid of each cluster is denoted as .

[0060] Step 6.5: Based on the dimensionality reduction data samples and The Euclidean distance between the centroids of each cluster is used to cluster the dimensionality-reduced data samples into the corresponding clusters. In this embodiment, for each dimensionality-reduced data sample in the set of dimensionality-reduced data samples Calculate its destination respectively Calculate the Euclidean distance between the centroids of each cluster and assign them to the cluster with the smallest distance.

[0061] Step 6.6: After the dimensionality reduction data samples are clustered, recalculate the cluster centroid of each cluster; In this embodiment, for each cluster Recalculate cluster centroid The calculation formula is as follows: (14).

[0062] Step 6.7: Repeat steps 6.5-6.6 until the position of the cluster centroid of each cluster no longer changes, and obtain the clustering results; Step 6.8: Based on the clustering results, use the pre-established mapping relationship between the clustering results of chip detection data and the fault categories to determine the chip detection results.

[0063] In this embodiment, the clustering result, that is, the cluster partitioning result, is as follows: The chips are divided into clusters.

[0064] In an optional embodiment, step 6.8 includes: Step i: Label all chip inspection data within a production cycle with normal category labels and specific fault category labels according to the actual electrical performance of the chips. Then, perform clustering operations on the labeled inspection data using data dimensionality reduction and K-means++ algorithms to obtain a set of clustering results. ; Step ii: For the clustering results Each cluster in Calculate the frequency of labels for all cluster points, and select the label with the highest frequency as the cluster. The actual category labels are then used to calculate the clusters. Cluster centroid The coordinates of each point within the cluster and the distance from the cluster centroid average distance ,get and ,in, (15); Step iii: Clustering results based on the detection data of unlabeled chips The cluster centroids of the clusters are calculated. Calculate the cluster centroid From the centroid of each cluster to The distance between the centroids of each cluster is expressed as: Take set minimum value ,judge and Size relationship; Step iv: If Then the clustering result The corresponding chip category is The corresponding actual category label; if Then in the current set Delete from middle We get a new set, and take the minimum value in the new set. ,judge and Based on the size relationship, repeat this step until the clustering result is obtained. The corresponding chip category.

[0065] It should be noted that the clustering result is not yet determined if the new set is empty. If the clustering result corresponds to the category of the chip, then the clustering result is considered to be... The corresponding chip category is unknown.

[0066] It is worth noting that, in terms of data distribution, the output data during large-scale electrical testing of chips shows that there are many normal values, a small distribution range, high overlap, and high density. The number of abnormal data is significantly less than that of normal values, and the distribution is more discrete. Therefore, chips in the normal category can be determined first based on the clustering results of the test data. Then, based on the pre-established mapping relationship between the clustering results of chip test data and the fault category, the fault category detection result of the chip can be determined.

[0067] The present invention discloses a large-scale parallel electrical testing method for chips based on data dimensionality reduction and the K-means++ algorithm. This method utilizes the Laplace eigenmap dimensionality reduction algorithm to encode all the complex, multi-dimensional testing data of multiple chips obtained during large-scale electrical testing into an adjacency matrix. Then, it processes all data in parallel through matrix transformation, mapping it to a low-dimensional space. Next, it uses the K-means++ algorithm to further cluster the dimensionality-reduced data, obtaining the clustering results of the chip testing data. Finally, based on a pre-established mapping relationship between the chip testing data clustering results and fault categories, the chip testing results are obtained. This method can process the data of each chip in a large-scale chip system in parallel and output the chip classification results.

[0068] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element.

[0069] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for large-scale parallel electrical testing of chips based on data dimensionality reduction and K-means++ algorithm, characterized in that, include: Step 1: Acquire test data from multiple chips collected during large-scale electrical testing; Step 2: Preprocess the detection data of the chip to obtain a dataset; Step 3: Construct an adjacency graph based on the dataset, and construct an adjacency matrix based on the adjacency graph; Step 4: Based on the adjacency matrix, perform feature dimensionality reduction on the dataset to obtain the dimensionality-reduced data sample corresponding to each sample in the dataset; Step 5: Determine the optimal number of clusters for the clustering algorithm. include: Step 5.1: Determine the maximum number of clusters based on the types of chip faults. Number of clusters The initial value is 1; Step 5.2: Based on the current number of clusters, perform Kmeans++ clustering on each dimensionality-reduced data sample to obtain the corresponding clustering results; Step 5.3: Calculate the silhouette coefficient of each dimensionality-reduced data sample based on the clustering results; Step 5.4: Calculate the silhouette coefficient of the clustering result based on the silhouette coefficient of each dimension-reduced data sample; Step 5.5: Let Repeat steps 5.2-5.4 until... This yields the silhouette coefficients of multiple clustering results; Step 5.6: Select the number of clusters corresponding to the maximum value among the silhouette coefficients of the multiple clustering results as the optimal number of clusters; Step 6: Based on the optimal number of clusters, use the K-means++ clustering method to cluster the dimensionality-reduced data samples to obtain clustering results. Determine the chip detection results based on the clustering results, including: Step 6.1: Randomly select one dimensionality-reduced data sample from the set of dimensionality-reduced data samples as the centroid of the first cluster; Step 6.2: Determine the nearest cluster centroid for the unselected dimensionality-reduced data sample, and calculate the Euclidean distance between the unselected dimensionality-reduced data sample and the nearest cluster centroid; Step 6.3: Calculate the probability that each dimensionality-reduced data sample is selected as the cluster centroid of the next cluster, and use the roulette wheel method to select the cluster centroid of the next cluster; Step 6.4: Repeat steps 6.2-6.3 until a selection is made. The centroid of each cluster is obtained. Clusters, The optimal number of clusters; Step 6.5: Based on the dimensionality reduction data sample and The Euclidean distance between the centroids of each cluster is used to cluster the dimensionality-reduced data samples into the corresponding clusters. Step 6.6: After the dimensionality reduction data samples are clustered, the cluster centroid of each cluster is recalculated; Step 6.7: Repeat steps 6.5-6.6 until the position of the cluster centroid of each cluster no longer changes, and obtain the clustering result; Step 6.8: Based on the clustering results, determine the chip detection results by utilizing the pre-established mapping relationship between the chip detection data clustering results and the fault categories.

2. The chip large-scale parallel electrical testing method based on data dimensionality reduction and K-means++ algorithm according to claim 1, characterized in that, The chip's detection data includes: power consumption, frequency, voltage, current, temperature, AC test parameters frequency response, amplitude response and phase response, and pin resistance.

3. The chip large-scale parallel electrical testing method based on data dimensionality reduction and K-means++ algorithm according to claim 1, characterized in that, Step 2 includes: Step 2.1: Fill in missing values ​​in the detection data of the chip; Step 2.2: Normalize the detection data of the chip after filling to obtain the data set.

4. The chip large-scale parallel electrical testing method based on data dimensionality reduction and K-means++ algorithm according to claim 1, characterized in that, Step 3 includes: Step 3.1: Calculate the distance between samples in the dataset; Step 3.2: Consider two samples whose distance does not exceed a preset distance threshold as adjacent points, and construct the adjacency graph based on the adjacent points; Step 3.3: Use the Laplace kernel function to determine the weights between adjacent nodes, set the weights between non-adjacent nodes to 0, and construct the adjacency matrix based on all weights.

5. The chip large-scale parallel electrical testing method based on data dimensionality reduction and K-means++ algorithm according to claim 4, characterized in that, The weights between adjacent points are calculated using the following formula: ； In the formula, For samples in the dataset , For samples in the dataset , For the sample and samples The weights between them This is a constant for weight calculation. It is an adjacency matrix. Norm operations.

6. The chip large-scale parallel electrical testing method based on data dimensionality reduction and K-means++ algorithm according to claim 1, characterized in that, Step 4 includes: Step 4.1: Based on the adjacency matrix, construct the objective function for Laplacian eigenmap optimization; Step 4.2: Simplify the objective function to obtain the simplified equivalent mathematical model; Step 4.3: Solve the equivalent mathematical model using the Lagrange multiplier method to obtain the dimensionality-reduced data matrix of the data set, and determine the dimensionality-reduced data sample corresponding to each sample in the data set based on the dimensionality-reduced data matrix.

7. The chip large-scale parallel electrical testing method based on data dimensionality reduction and K-means++ algorithm according to claim 6, characterized in that, The objective function is: ； In the formula, For samples in the dataset and samples The weights between them For samples in the dataset The corresponding dimensionality reduction data samples, For samples in the dataset The corresponding dimensionality reduction data samples; Norm operations; The equivalent mathematical model is: ； In the formula, For a dimensionality-reduced data matrix, Let be the degree matrix of the graph. Let be the Laplace matrix of the graph. It is the identity matrix. Let be the trace of the matrix.

8. The chip large-scale parallel electrical testing method based on data dimensionality reduction and K-means++ algorithm according to claim 1, characterized in that, The silhouette coefficient of each dimensionality-reduced data sample is calculated using the following formula: ； In the formula, The silhouette coefficients of the dimensionality-reduced data samples. To reduce the inter-cluster dissimilarity of data samples, The average distance from a dimensionality-reduced data sample to other dimensionality-reduced data samples in the same cluster; The silhouette coefficient of the clustering result is calculated according to the following formula: ； In the formula, The silhouette coefficient is the result of clustering. This represents the number of samples in the dataset.

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