Test method and device of layout verification tool, equipment and storage medium

Abstract

A test method and device of a layout verification tool, equipment and a storage medium, wherein the test method of the layout verification tool comprises: obtaining multiple groups of connectivity test layouts based on a connection relationship truth table; performing layout and schematic consistency verification processing on the multiple groups of connectivity test layouts to obtain a verification result; and obtaining a test result of the layout verification tool based on a preset test rule and the verification result. The embodiment of the present application performs layout and schematic consistency verification processing on multiple groups of connectivity test layouts to obtain a verification result, so that the test result of the layout verification tool can be obtained based on the preset test rule and the verification result, so as to detect the correctness of the connection relationship definition in the layout verification tool, so as to ensure the consistency of the connection relationship in the layout verification tool and the connection relationship truth table, and thus facilitate the correct performance of the layout verification.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of integrated circuit / computer-aided design, and more particularly to a testing method, apparatus, device, and storage medium for a layout verification tool. Background Technology

[0002] Layout design and verification are crucial steps in the integrated circuit design flow. Efficient and accurate verification can significantly improve the efficiency of integrated circuit design and greatly reduce the risk of design failure. Among these, layout and schematic design are essential components. Figure 1 Layout Versus Schematic (LVS) is a crucial part of layout verification. During LVS, the circuit netlist extracted from the layout is compared with the circuit netlist extracted from the circuit diagram. This involves checking whether the node connections and corresponding components in the two netlists match, ensuring that the circuit implemented in the layout is completely consistent with the designed circuit.

[0003] Specifically, the layout is composed of a Geographic Data Structures (GDS) hierarchy. GDS hierarchy information is obtained and the layout is drawn using the metal option table in the Design Rule Manual (DRM). Layout verification tools, such as the LVS deck (layout-to-schematic comparison program), are then used to verify the layout. The LVS deck must strictly adhere to the metal option table definitions in the Design Rule Manual for device identification. The consistency between the connection definitions in the LVS deck and the metal option table is crucial for both the layout and the schematic. Figure 1 The correctness of consistency verification is crucial.

[0004] However, how to effectively detect the correctness of the layout verification tool definition has become an urgent problem to be solved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a testing method, apparatus, device and storage medium for a layout verification tool, which detects the correctness of the connection relationship definition in the layout verification tool, and helps to ensure the consistency between the connection relationship and the connection relationship truth table in the layout verification tool.

[0006] To address the aforementioned problems, embodiments of the present invention provide a testing method for a layout verification tool, comprising: obtaining multiple sets of connectivity test layouts based on a connectivity truth table; and performing layout and principle analysis on the multiple sets of connectivity test layouts. Figure 1 Consistency verification is performed to obtain verification results; based on preset test rules and the verification results, test results of the layout verification tool are obtained.

[0007] Optionally, before obtaining multiple sets of connectivity test layouts based on the connectivity truth table, the testing method of the layout verification tool further includes: obtaining the underlying layout corresponding to a single device based on the connectivity truth table; performing preliminary verification processing on the underlying layout to verify the device description at the bottom layer and the connection relationship between the device and the first metal layer; and obtaining multiple sets of connectivity test layouts based on the connectivity truth table when the result of the preliminary verification processing is correct.

[0008] Optionally, if the result of the preliminary verification process is negative, the process can be returned to the process package library to modify the underlying layout of the device.

[0009] Optionally, the connectivity test layout includes: a complete layout corresponding to a single device as the first test layout, a complete layout corresponding to a pseudo device as the second test layout, and a layout with incorrect connections as the third test layout.

[0010] Optionally, the preset test rules include: the verification result corresponding to the first test layout and the second test layout is verification passed, and the verification result corresponding to the third test layout is verification failed.

[0011] Optionally, the step of obtaining the multiple sets of connectivity test layouts includes: obtaining the first test layout based on the connectivity truth table; replacing each layer in the first test layout with a pseudo layer to obtain the second test layout; obtaining all erroneous connectivity relationships that do not satisfy the connectivity relationships in the first test layout; and obtaining the third test layout based on the erroneous connectivity relationships.

[0012] Optionally, the layout verification tool has a verification definition file; based on the verification definition file, the layout and schematic of the multiple sets of connectivity test layouts are performed. Figure 1 The consistency verification process is performed to obtain the verification result. The steps for obtaining the test result of the layout verification tool based on the preset test rules and the verification result include: determining whether the verification result is consistent with the preset test rules; if so, determining that the test has passed; otherwise, determining that the test has failed, and checking and modifying the verification definition file.

[0013] Optionally, the layout verification tool is a layout and principle verification tool. Figure 1 Consistency verification tools.

[0014] Accordingly, embodiments of the present invention also provide a testing apparatus for a layout verification tool, comprising: a test layout acquisition module, used to obtain multiple sets of connectivity test layouts based on a connectivity truth table; and a verification module, used to perform layout and principle verification on the multiple sets of connectivity test layouts. Figure 1The consistency verification process obtains the verification results; the test result acquisition module is used to obtain the test results of the layout verification tool based on the preset test rules and the verification results.

[0015] Accordingly, embodiments of the present invention also provide an apparatus, including at least one memory and at least one processor, wherein the memory stores one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the testing method of the layout verification tool described in the embodiments of the present invention.

[0016] Accordingly, embodiments of the present invention also provide a storage medium storing one or more computer instructions, which are used to implement the testing method of the layout verification tool described in the embodiments of the present invention.

[0017] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0018] In the testing method of the layout verification tool provided in this embodiment of the invention, multiple sets of connectivity test layouts are obtained based on the truth table of metal connection relationships, and the layout and principle of the multiple sets of connectivity test layouts are then analyzed. Figure 1 Consistency verification is performed to obtain verification results. Based on preset test rules and the verification results, test results of the layout verification tool can be obtained to detect the correctness of the connection relationship definition in the layout verification tool, so as to ensure the consistency between the connection relationship in the layout verification tool and the connection relationship truth table, thereby helping to ensure the correct performance of layout verification.

[0019] The test apparatus for the layout verification tool provided in this embodiment of the invention includes a test layout acquisition module for obtaining multiple sets of connectivity test layouts based on the metal connection relationship truth table, and a verification module for performing layout and principle verification on the multiple sets of connectivity test layouts. Figure 1 The consistency verification process obtains the verification results, and the test result acquisition module can obtain the test results of the layout verification tool based on the preset test rules and the verification results. This allows the correctness of the connection relationship definition in the layout verification tool to be detected, ensuring the consistency between the connection relationship and the connection relationship truth table in the layout verification tool, thereby helping to ensure the correctness of the layout verification. Attached Figure Description

[0020] Figure 1 This is a flowchart of an embodiment of the testing method for the layout verification tool of the present invention;

[0021] Figure 2 This is a functional block diagram of an embodiment of the testing device for the layout verification tool of the present invention;

[0022] Figure 3This is a hardware structure diagram of an embodiment of the device provided by the present invention. Detailed Implementation

[0023] As the background technology shows, how to effectively detect the correctness of the layout verification tool definition has become an urgent problem to be solved.

[0024] Specifically, taking LVS deck as an example, LVS deck defines the connection relationships, and when using LVS deck to verify layout and principle consistency, the defined connection relationships are used as the benchmark for verification. Currently, the metal layers are usually manually drawn based on the connection relationship truth table to check the consistency between the connection relationships defined by LVS deck and the connection relationship truth table.

[0025] However, the number of connections in the layout is large, making manual layout drawing slow and inefficient. Furthermore, the same layout cannot be paired with different combinations of connections, making it impossible to effectively verify the correctness of connections in the LVS deck.

[0026] To address the aforementioned technical problems, embodiments of the present invention provide a testing method for a layout verification tool. (See reference...) Figure 1 The diagram shows a flowchart of an embodiment of the testing method for the layout verification tool of the present invention.

[0027] As an example, the testing method for layout verification tools includes the following basic steps:

[0028] Step S4: Based on the truth table of connectivity relationships, obtain multiple sets of connectivity test layouts;

[0029] Step S5: Perform layout and schematic analysis on multiple sets of connectivity test layouts. Figure 1 Consistency verification is performed to obtain the verification results;

[0030] Step S6: Based on the preset test rules and verification results, obtain the test results of the layout verification tool.

[0031] It should be noted that in this embodiment, before performing step S4, the following steps are also included:

[0032] Execution step S1: Based on the truth table of connection relationships, obtain the underlying layout corresponding to a single device;

[0033] Continue to refer to Figure 1 Step S2: Perform preliminary verification processing on the bottom layer layout, which is suitable for verifying the device description at the bottom layer and the connection relationship between the device and the first metal layer.

[0034] If the initial verification result is correct, proceed to step S4: Based on the truth table of the connection relationship, obtain multiple sets of connectivity test layouts.

[0035] In the testing method of the layout verification tool provided in this embodiment of the invention, multiple sets of connectivity test layouts are obtained based on the truth table of metal connection relationships, and the layout and principle of the multiple sets of connectivity test layouts are then analyzed. Figure 1 Consistency verification is performed to obtain verification results. Based on preset test rules and verification results, test results of the layout verification tool can be obtained to check the correctness of the connection relationship definition in the layout verification tool, so as to ensure the consistency between the connection relationship in the layout verification tool and the connection relationship truth table, thereby helping to ensure the correct performance of layout verification.

[0036] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0037] refer to Figure 1 Step S4: Based on the truth table of connection relationships, obtain multiple sets of connectivity test layouts.

[0038] Multiple sets of connectivity test layouts are used for subsequent testing of the layout verification tool.

[0039] Specifically, in this embodiment, the layout verification tool is a layout and a principle verification tool. Figure 1 The consistency verification tool subsequently utilizes multiple sets of connectivity test layouts to verify the layout and schematics. Figure 1 The connectivity definition of the consistency verification tool is tested for correctness.

[0040] In this embodiment, the connectivity test layout includes: a complete layout corresponding to a single device as the first test layout, a complete layout corresponding to a pseudo device as the second test layout, and a layout with incorrect connections as the third test layout.

[0041] The connectivity test layout includes a first test layout, a second test layout, and a third test layout, which can simulate all possible layout types during the actual layout verification process, thereby ensuring the completeness of subsequent testing of the layout verification tool.

[0042] In this embodiment, multiple sets of connectivity test layouts are subsequently used to test the layout and principles. Figure 1 The connectivity definition of the consistency verification tool is tested. Therefore, the complete layout corresponding to a single device refers to: the bottom layout of the single device, the multiple metal layers connected from bottom to top, and the corresponding pattern of the conductive plugs used to connect adjacent metal layers. In other words, the first test layout is a test layout that can meet the function of the device and can realize the normal electrical connection between the device and the external circuit. That is, the first test layout is the correct connectivity layout.

[0043] The complete layout corresponding to the pseudo-device serves as the second test layout. The pseudo-device is used to increase the graphic density of the layout, and its connectivity is identical to that of a single device. By verifying the connectivity of the pseudo-device, the correctness of the connectivity of the devices corresponding to it is ensured.

[0044] A faulty connection layout refers to any layout that could potentially cause metal wires to break and prevent proper electrical connections. Obtaining this faulty connection layout allows for subsequent verification of whether layout validation tools can correctly validate it and obtain the corresponding verification results.

[0045] In this embodiment, the steps of obtaining multiple sets of connectivity test layouts include: obtaining a first test layout based on a connectivity truth table; replacing each layer in the first test layout with a pseudo layer to obtain a second test layout; obtaining all erroneous connectivity relationships that do not satisfy the connectivity relationships in the first test layout; and obtaining a third test layout based on the erroneous connectivity relationships.

[0046] Specifically, based on all correct connection relationships in the connection truth table, the first test layout and the second test layout are obtained.

[0047] As an example, Table 1 shows a schematic diagram of a metal option table.

[0048]

[0049] Table 1

[0050] Specifically, the steps of obtaining all erroneous connections that do not satisfy the connection relationships in the first test layout, and obtaining the third test layout based on these erroneous connections, include: removing connection layers one by one from the first test layout to obtain multiple sets of corresponding third test layouts. In other words, an exhaustive method is used to list all erroneous connections that do not conform to the correct connection relationships, and then multiple sets of third test layouts are obtained based on these erroneous connections.

[0051] refer to Figure 1 In this embodiment, before obtaining multiple sets of connectivity test layouts based on the connectivity truth table, the test method of the layout verification tool further includes: performing step S1: obtaining the underlying layout corresponding to a single device based on the connectivity truth table.

[0052] Obtain the underlying layout corresponding to a single device so that the underlying layout can be preliminarily verified before obtaining multiple sets of connectivity test layouts. This will determine whether the underlying layout is consistent with the schematic, thereby ensuring the correctness of the underlying layout and improving the accuracy of subsequent tests using layout verification tools.

[0053] In this embodiment, the underlying layout corresponding to a single device includes: the layout of the front-end device and the layout of the first layer of metal (m1) and the contact hole plug that are electrically connected to the front-end device.

[0054] The following explanation uses a MOS device as an example. The layout of the front-end device includes the active region (AA), gate, source region, and drain region.

[0055] Continue to refer to Figure 1 Step S2: Perform preliminary verification processing on the bottom layer layout, which is suitable for verifying the device description at the bottom layer and the connection relationship between the device and the first metal layer.

[0056] Before obtaining multiple sets of connectivity test layouts, the underlying layout is preliminarily verified to verify the underlying devices and connections in advance. This ensures that the underlying layout is consistent with the schematic and guarantees the correctness of the underlying layout in the subsequent sets of connectivity test layouts. Consequently, only the connections in the test layouts need to be verified, which improves the efficiency of subsequent test layout verification.

[0057] Specifically, a layout verification tool is used to perform preliminary verification processing on the underlying layout.

[0058] Continue to refer to Figure 1 If the initial verification result is correct, proceed to step S4: Based on the truth table of the connection relationship, obtain multiple sets of connectivity test layouts to ensure the correctness of the underlying layouts in the multiple sets of connectivity test layouts.

[0059] Continue to refer to Figure 1 If the initial verification result is negative, step S3 is executed to return to the process package library (PDKlibrary) to modify the underlying layout of the device.

[0060] Modifying the underlying layout of the device ensures consistency between the underlying layout and the schematic, thereby guaranteeing the correctness of the underlying layout and improving the accuracy of subsequent tests using layout verification tools.

[0061] Continue to refer to Figure 1 Step S5: Perform layout and schematic analysis on multiple sets of connectivity test layouts. Figure 1 Consistency verification is performed to obtain the verification results.

[0062] Obtain the verification results so that the layout verification tool can be tested based on the preset test rules and the verification results.

[0063] Specifically, the layout verification tool has a verification definition file, which is used to define the metal connection relationships. In this embodiment, the verification definition file is obtained based on the connection relationship truth table.

[0064] Accordingly, in this embodiment, based on the verification definition file, the layout and schematic of multiple sets of connectivity test layouts are performed. Figure 1 The consistency verification process is then performed to obtain the verification results. In other words, the consistency between multiple sets of connectivity test layouts and the verification definition files is verified.

[0065] Accordingly, based on the verification definition file, the layout and principles are utilized. Figure 1 A consistency verification tool to verify multiple sets of connectivity test layouts.

[0066] As an example, after verifying multiple sets of connectivity test layouts, a verification result file is obtained. The verification result file includes: the verification result file QA_results main_layer corresponding to the first test layout, the verification result file QA_results dummy_layer corresponding to the second test layout, and the verification result file QA_results bad_pattern corresponding to the third test layout.

[0067] Continue to refer to Figure 1 Step S6: Based on the preset test rules and verification results, obtain the test results of the layout verification tool.

[0068] The verification results are compared with the preset test rules to determine whether the connectivity definition of the layout verification tool is correct.

[0069] In this embodiment, based on the truth table of metal connection relationships, multiple sets of connectivity test layouts are obtained, and layout and schematic diagrams are then performed on these multiple sets of connectivity test layouts. Figure 1 Consistency verification is performed to obtain verification results. Based on preset test rules and verification results, test results of the layout verification tool can be obtained to check the correctness of the connection relationship definition in the layout verification tool, so as to ensure the consistency between the connection relationship in the layout verification tool and the connection relationship truth table, thereby helping to ensure the correct performance of layout verification.

[0070] In this embodiment, the preset test rules include: the verification result corresponding to the first test layout and the second test layout is verification passed, and the verification result corresponding to the third test layout is verification failed.

[0071] In this embodiment, the steps for obtaining the test results of the layout verification tool based on preset test rules and verification results include: determining whether the verification results are consistent with the preset test rules; if so, determining that the test has passed; otherwise, determining that the test has failed, and checking and modifying the verification definition file.

[0072] As an example, based on preset test rules, the verification result file is checked to obtain the test result file QA_report of the layout verification tool. Based on the content of the test result file, it is determined whether the test passed or failed.

[0073] Accordingly, the present invention also provides a testing device for a layout verification tool. Figure 2 This is a functional block diagram of an embodiment of the testing device for the layout verification tool of the present invention.

[0074] In this embodiment, the testing device 10 of the layout verification tool includes: a test layout acquisition module 101, used to obtain multiple sets of connectivity test layouts based on a connection relationship truth table; and a verification module 102, used to perform layout and principle verification on the multiple sets of connectivity test layouts. Figure 1 The consistency verification process is performed to obtain the verification results; the test result acquisition module 103 is used to obtain the test results of the layout verification tool based on the preset test rules and verification results.

[0075] The test layout acquisition module 101 is used to obtain multiple sets of connectivity test layouts based on the truth table of metal connection relationships, and the verification module 102 is used to perform layout and principle verification on the multiple sets of connectivity test layouts. Figure 1 The consistency verification process obtains the verification results, so that the test result acquisition module 103 can obtain the test results of the layout verification tool based on the preset test rules and verification results, so as to detect the correctness of the connection relationship definition in the layout verification tool, so as to ensure the consistency between the connection relationship and the connection relationship truth table in the layout verification tool, and thus help to ensure the correctness of the layout verification.

[0076] The test layout acquisition module 101 is used to obtain multiple sets of connectivity test layouts based on the connection relationship truth table. These multiple sets of connectivity test layouts are used to test the layout verification tool.

[0077] Specifically, in this embodiment, the layout verification tool is a layout and a principle verification tool. Figure 1 A consistency verification tool with multiple connectivity test layouts for verifying the layout and schematics. Figure 1 The connectivity definition of the consistency verification tool is tested for correctness.

[0078] In this embodiment, the connectivity test layout includes: a complete layout corresponding to a single device as the first test layout, a complete layout corresponding to a pseudo device as the second test layout, and a layout with incorrect connections as the third test layout.

[0079] The connectivity test layout includes a first test layout, a second test layout, and a third test layout, which can simulate all possible layout types during the actual layout verification process, thereby ensuring the completeness of subsequent testing of the layout verification tool.

[0080] In this embodiment, multiple sets of connectivity test layouts are used to test the layout and principles. Figure 1 The connectivity definition of the consistency verification tool is tested. Therefore, the complete layout corresponding to a single device refers to: the bottom layout of the single device, the multiple metal layers connected from bottom to top, and the corresponding pattern of the conductive plugs used to connect adjacent metal layers. In other words, the first test layout is a test layout that can meet the function of the device and can realize the normal electrical connection between the device and the external circuit. That is, the first test layout is the correct connectivity layout.

[0081] The complete layout corresponding to the pseudo-device serves as the second test layout. The pseudo-device is used to increase the graphic density of the layout, and its connectivity is identical to that of a single device. By verifying the connectivity of the pseudo-device, the correctness of the connectivity of the devices corresponding to it is ensured.

[0082] A faulty connection layout refers to any layout that could cause metal wires to break and prevent proper electrical connections. By obtaining the faulty connection layout, the verification module 102 can confirm whether the layout verification tool can correctly verify the faulty connection layout and obtain the corresponding verification results.

[0083] In this embodiment, the test layout acquisition module 101 is used to obtain a first test layout based on a truth table of connection relationships; replace each layer in the first test layout with a pseudo layer to obtain a second test layout; acquire all erroneous connection relationships that do not satisfy the connection relationships in the first test layout; and obtain a third test layout based on the erroneous connection relationships.

[0084] Specifically, the test layout acquisition module 101 obtains the first test layout and the second test layout based on all correct connection relationships in the connection relationship truth table.

[0085] Specifically, the steps of the test layout acquisition module 101 in acquiring all erroneous connection relationships that do not satisfy the connection relationships in the first test layout, and obtaining the third test layout based on the erroneous connection relationships, include: removing connection layers one by one from the first test layout to obtain multiple sets of corresponding third test layouts. In other words, the test layout acquisition module 101 uses an exhaustive method to list all erroneous connection relationships that do not conform to the correct connection relationships, and then obtains multiple sets of third test layouts based on the erroneous connection relationships.

[0086] Continue to refer to Figure 2 In this embodiment, the test tool of the layout verification tool further includes: a bottom layout acquisition module 104, used to obtain the bottom layout corresponding to a single device based on the connection relationship truth table; and a preliminary verification module 105, used to perform preliminary verification processing on the bottom layout, suitable for verifying the device description at the bottom layer and the connection relationship between the device and the first metal layer.

[0087] The underlying layout acquisition module 104 obtains the underlying layout corresponding to a single device so that the preliminary verification module 105 can perform preliminary verification processing on the underlying layout before obtaining multiple sets of connectivity test layouts, thereby ensuring the correctness of the underlying layout and improving the correctness of testing the layout verification tool accordingly.

[0088] In this embodiment, the underlying layout corresponding to a single device includes: the layout of the front-end device and the layout of the first layer of metal and contact hole plugs that are electrically connected to the front-end device.

[0089] The following explanation uses a MOS device as an example. The layout of the front-end device includes the active region (AA), gate, source region, and drain region.

[0090] The preliminary verification module 105 is used to perform preliminary verification processing on the underlying layout before obtaining multiple sets of connectivity test layouts, thereby verifying the underlying devices and connection relationships in advance to ensure the correctness of the underlying layout in the multiple sets of connectivity test layouts obtained by the test layout acquisition module 101. As a result, the verification module 102 can only verify the connection relationships in the test layout, which is beneficial to improving the efficiency of the verification module 102 in verifying the test layout.

[0091] Specifically, a layout verification tool is used to perform preliminary verification processing on the underlying layout.

[0092] Continue to refer to Figure 2 When the preliminary verification result output by the preliminary verification module 105 is correct, the test layout acquisition module 101 obtains multiple sets of connectivity test layouts based on the truth table of connectivity relationships, thereby ensuring the correctness of the underlying layout in the multiple sets of connectivity test layouts.

[0093] Continue to refer to Figure 2 The test apparatus 10 also includes a layout correction module 106, which is used to return to the process package library (PDK library) to modify the underlying layout of the device when the result of the preliminary verification process output by the preliminary verification module 105 is negative.

[0094] Modifying the underlying layout of the device ensures consistency between the underlying layout and the schematic, thereby guaranteeing the correctness of the underlying layout and improving the accuracy of subsequent tests using layout verification tools.

[0095] Verification module 102 is used to perform layout and schematic analysis on multiple sets of connectivity test layouts. Figure 1 The consistency verification process is performed to obtain the verification results, so that the test result acquisition module 103 can obtain the test results of the layout verification tool based on the preset test rules and verification results.

[0096] Specifically, the layout verification tool has a verification definition file, which is used to define the metal connection relationships. In this embodiment, the verification definition file is obtained based on the connection relationship truth table.

[0097] Accordingly, in this embodiment, the verification module 102 performs layout and principle analysis on multiple sets of connectivity test layouts based on the verification definition file. Figure 1 The consistency verification process is then performed to obtain the verification results. In other words, the verification module 102 verifies the consistency between multiple sets of connectivity test layouts and the verification definition files.

[0098] Accordingly, based on the verification definition file, the layout and principles are utilized. Figure 1 A consistency verification tool to verify multiple sets of connectivity test layouts.

[0099] As an example, after verifying multiple sets of connectivity test layouts, the verification module 102 obtains a verification result file, which includes: the verification result file QA_results main_layer corresponding to the first test layout, the verification result file QA_results dummy_layer corresponding to the second test layout, and the verification result file QA_results bad_pattern corresponding to the third test layout.

[0100] The test result acquisition module 103 is used to obtain the test results of the layout verification tool based on the preset test rules and verification results, and then compare the verification results with the preset test rules to determine whether the connectivity definition of the layout verification tool is correct.

[0101] In this embodiment, the test layout acquisition module 101 obtains multiple sets of connectivity test layouts based on the truth table of metal connection relationships. The verification module 102 is used to perform layout and principle verification on the multiple sets of connectivity test layouts. Figure 1 The consistency verification process obtains the verification results, so that the test result acquisition module 103 can obtain the test results of the layout verification tool based on the preset test rules and verification results, so as to detect the correctness of the connection relationship definition in the layout verification tool, so as to ensure the consistency between the connection relationship and the connection relationship truth table in the layout verification tool, and thus help to ensure the correctness of the layout verification.

[0102] In this embodiment, the preset test rules include: the verification result corresponding to the first test layout and the second test layout is verification passed, and the verification result corresponding to the third test layout is verification failed.

[0103] In this embodiment, the test result acquisition module 103 is used to determine whether the verification result is consistent with the preset test rules; if so, the test is deemed to have passed; otherwise, the test is deemed to have failed, and the verification definition file is checked and modified.

[0104] As an example, the test result acquisition module 103 checks the verification result file based on preset test rules to obtain the test result file QA_report of the layout verification tool. Based on the content of the test result file, it determines whether the test passed or failed.

[0105] To address the technical problem, this embodiment of the invention also provides a device that can implement the testing method for the layout verification tool provided in this embodiment of the invention by loading the above-described testing method for the layout verification tool in the form of a program.

[0106] An optional hardware structure for the terminal device provided in this embodiment of the invention can be as follows: Figure 3 As shown, it includes: at least one processor 01, at least one communication interface 02, at least one memory 03, and at least one communication bus 04.

[0107] In this embodiment, the number of processor 01, communication interface 02, memory 03 and communication bus 04 is at least one, and processor 01, communication interface 02 and memory 03 communicate with each other through communication bus 04.

[0108] Communication interface 02 can be an interface for a communication module used for network communication, such as the interface of a GSM module. Processor 01 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention.

[0109] Memory 03 may include high-speed RAM memory, and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0110] The memory 03 stores one or more computer instructions, which are executed by the processor 01 to implement the testing method of the layout verification tool provided in this embodiment of the invention.

[0111] It should be noted that the aforementioned terminal device may also include other devices (not shown) that may not be essential to understanding the content disclosed in the embodiments of the present invention; given that these other devices may not be essential for understanding the content disclosed in the embodiments of the present invention, the embodiments of the present invention will not describe them one by one.

[0112] This invention also provides a storage medium storing one or more computer instructions for implementing the testing method of the layout verification tool provided in this invention.

[0113] Embodiments of the present invention can be implemented by various means, such as hardware, firmware, software, or combinations thereof. In a hardware configuration, the method according to an exemplary embodiment of the present invention can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, etc.

[0114] In firmware or software configuration, embodiments of the present invention can be implemented in the form of modules, processes, functions, etc. Software code can be stored in a memory unit and executed by a processor. The memory unit is located inside or outside the processor and can send data to and receive data from the processor via various known means.

[0115] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A testing method for a layout verification tool, characterized in that, include: Based on the truth table of connection relationships, multiple sets of connectivity test layouts are obtained; The truth table of connection relationships is a truth table of metal connection relationships; The layout verification tool has a verification definition file, which is used to define the metal connection relationships; Based on the verification definition file, the multiple sets of connectivity test layouts are subjected to layout and schematic consistency verification to obtain the verification results. Based on the preset test rules and the verification results, the test results of the layout verification tool are obtained to determine whether the connectivity definition of the layout verification tool is correct.

2. The testing method for the layout verification tool as described in claim 1, characterized in that, Before obtaining multiple sets of connectivity test layouts based on the connectivity truth table, the test method of the layout verification tool further includes: obtaining the underlying layout corresponding to a single device based on the connectivity truth table; The underlying layout is subjected to preliminary verification processing, which is suitable for verifying the device description at the bottom layer and the connection relationship between the device and the first metal layer; If the result of the preliminary verification process is correct, multiple sets of connectivity test layouts are obtained based on the connection relationship truth table.

3. The testing method for the layout verification tool as described in claim 2, characterized in that, If the result of the preliminary verification process is negative, return to the process package library to modify the underlying layout of the device.

4. The testing method for the layout verification tool as described in claim 1, characterized in that, The connectivity test layout includes: a complete layout corresponding to a single device as the first test layout, a complete layout corresponding to a pseudo device as the second test layout, and a layout with incorrect connections as the third test layout.

5. The testing method for the layout verification tool as described in claim 4, characterized in that, The preset test rules include: the verification result corresponding to the first test layout and the second test layout is verification passed, and the verification result corresponding to the third test layout is verification failed.

6. The testing method for the layout verification tool as described in claim 4, characterized in that, The steps for obtaining the multiple sets of connectivity test layouts include: obtaining the first test layout based on the connectivity truth table; replacing each layer in the first test layout with a pseudo layer to obtain the second test layout; obtaining all erroneous connectivity relationships that do not satisfy the connectivity relationships in the first test layout; and obtaining the third test layout based on the erroneous connectivity relationships.

7. The testing method for the layout verification tool as described in any one of claims 1 to 6, characterized in that, The steps for obtaining the test results of the layout verification tool based on the preset test rules and the verification results include: determining whether the verification results are consistent with the preset test rules; if so, determining that the test has passed; otherwise, determining that the test has failed, and checking and modifying the verification definition file.

8. The testing method for the layout verification tool as described in any one of claims 1 to 6, characterized in that, The layout verification tool is a layout and schematic consistency verification tool.

9. A testing apparatus for a layout verification tool, characterized in that, include: The test layout acquisition module is used to obtain multiple sets of connectivity test layouts based on the connection relationship truth table; The truth table of connection relationships is a truth table of metal connection relationships; The layout verification tool includes a verification definition file, which is used to define the metal connection relationships. The verification module is used to perform layout and schematic consistency verification processing on the multiple sets of connectivity test layouts based on the verification definition file, and obtain the verification results. The test result acquisition module is used to obtain the test results of the layout verification tool based on preset test rules and the verification results, so as to determine whether the connectivity definition of the layout verification tool is correct.

10. A device, characterized in that, It includes at least one memory and at least one processor, the memory storing one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the test method of the layout verification tool as described in any one of claims 1-8.

11. A storage medium, characterized in that, The storage medium stores one or more computer instructions, which are used to implement the test method of the layout verification tool as described in any one of claims 1-8.

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