Pixel circuit and display device

Abstract

The application discloses a pixel circuit and a display device, the pixel circuit comprising a light-emitting time control module, a current control module, a light-emitting module and a filter module; the output end of the light-emitting time control module is connected with the input end of the filter module, the output end of the filter module is connected with the control end of the current control module, the light-emitting time control module is used for controlling the potential of the control end of the current control module according to a first data signal and a sweep signal, so as to control the light-emitting time of the light-emitting module, and the filter module is used for filtering out the interference signal in the output signal of the output end of the light-emitting time control module; the current control module is used for driving the light-emitting module to emit light according to the voltage of the control end and the input end thereof. The technical scheme provided by the embodiment of the application can filter out the interference signal in the signal output by the light-emitting time control module, so as to ensure the quality of the effective signal transmitted to the control end of the current control module.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a pixel circuit and a display device. Background Technology

[0002] With the continuous development of display technology, micro light emitting diodes (Micro-LEDs) are widely used in the display field due to their advantages such as wide color gamut, fast response speed, high brightness and long life.

[0003] Currently, Micro-LED display devices typically include pixel circuits and light-emitting elements, with the pixel circuits driving the light-emitting elements to emit light. However, the performance of pixel circuits in existing technologies is not ideal, and they suffer from poor stability. Summary of the Invention

[0004] This invention provides a pixel circuit and a display device to improve the stability of the pixel circuit.

[0005] According to one aspect of the present invention, a pixel circuit is provided, comprising: a light emission timing control module, a current control module, a light emission module, and a filtering module;

[0006] The output terminal of the light emission time control module is connected to the input terminal of the filter module, and the output terminal of the filter module is connected to the control terminal of the current control module. The light emission time control module is used to control the potential of the control terminal of the current control module according to the first data signal and the frequency sweep signal, so as to control the light emission time of the light emission module. The filter module is used to filter out interference signals in the output signal of the output terminal of the light emission time control module.

[0007] The current control module and the light-emitting module are connected between the first power line and the second power line. The current control module is used to drive the light-emitting module to emit light according to the voltage of its control terminal and input terminal.

[0008] Optionally, the filtering module includes a first switching unit and a second switching unit. The input terminals of the first switching unit and the second switching unit are connected to serve as the input terminals of the filtering module, and the output terminals of the first switching unit and the second switching unit are connected to serve as the output terminals of the filtering module.

[0009] The first switching unit and the second switching unit are alternately turned on.

[0010] Optionally, the first switching unit includes a first transistor, and the second switching unit includes a second transistor;

[0011] The gate of the first transistor is connected to the first clock signal line, the first terminal of the first transistor is connected to the output terminal of the light emission timing control module, and the second terminal of the first transistor is connected to the control terminal of the current control module; the gate of the second transistor is connected to the second clock signal line, the first terminal of the second transistor is connected to the output terminal of the light emission timing control module, and the second terminal of the second transistor is connected to the control terminal of the current control module.

[0012] Preferably, the first clock signal transmitted on the first clock signal line and the second clock signal transmitted on the second clock signal line are complementary signals.

[0013] Optionally, the first switching unit includes a first transistor and a third transistor, the second switching unit includes a second transistor and a fourth transistor, and the filtering module further includes a fifth transistor;

[0014] The gates of the first transistor and the third transistor are both connected to a first clock signal line, and the gates of the second transistor and the fourth transistor are both connected to a second clock signal line. The first terminal of the first transistor is connected to the output terminal of the light emission timing control module, the second terminal of the first transistor is connected to the first terminal of the fourth transistor, and the second terminal of the fourth transistor is connected to the control terminal of the current control module. The first terminal of the second transistor is connected to the output terminal of the light emission timing control module, the second terminal of the second transistor is connected to the first terminal of the third transistor, and the second terminal of the third transistor is connected to the control terminal of the current control module.

[0015] The first terminal of the fifth transistor is connected to the second terminal of the first transistor, the second terminal of the fifth transistor is connected to the first terminal of the third transistor, and the gate of the fifth transistor is connected to the first voltage control signal line.

[0016] Preferably, the first clock signal transmitted on the first clock signal line and the second clock signal transmitted on the second clock signal line are complementary signals.

[0017] Optionally, the emission timing control module includes a first driving unit, a coupling unit, a first reset unit, and a first voltage writing unit; the first voltage writing unit is used to transmit a fixed voltage to the control terminal of the first driving unit, the coupling unit is used to couple the first data signal and the sweep frequency signal to the control terminal of the first driving unit, the first driving unit is connected between the first power line and the input terminal of the filter module, the first terminal of the first reset unit is connected to the first initialization signal line, the second terminal of the first reset unit is connected to the input terminal of the filter module, and the first reset unit is used to reset the voltage at the control terminal of the current control module;

[0018] Preferably, the light emission timing control module further includes a first light emission control unit, a first end of the first light emission control unit is connected to a second end of the first driving unit, the first end of the first driving unit is connected to the voltage transmitted on the first power line, and the second end of the first light emission control unit is connected to the input end of the filter module as the output end of the light emission timing control module.

[0019] Optionally, the light emission time control module further includes a first compensation unit and a second voltage writing unit, wherein the first compensation unit is connected between the second end of the first driving unit and the control end, and the second voltage writing unit is connected between the first power line and the first end of the first driving unit.

[0020] Preferably, the first end of the first voltage writing unit is connected to the first initialization signal line, and the second end of the first voltage writing unit is connected to the control end of the first driving module.

[0021] Optionally, the first driving unit includes a sixth transistor, the first reset unit includes a seventh transistor, the first voltage writing unit includes an eighth transistor, the coupling unit includes a ninth transistor, a tenth transistor, a first capacitor and a second capacitor, the first compensation unit includes an eleventh transistor, the second voltage writing unit includes a twelfth transistor and a thirteenth transistor, and the first light-emitting control unit includes a fourteenth transistor.

[0022] The gate of the ninth transistor is connected to the first scan line, the first terminal of the ninth transistor is connected to the first data line, and the second terminal of the ninth transistor is connected to the gate of the sixth transistor through the first capacitor; the gate of the tenth transistor is connected to the first light emission control signal line, the first terminal of the tenth transistor is connected to the sweep frequency signal line, and the second terminal of the tenth transistor is connected to the gate of the sixth transistor through the second capacitor; the gate of the seventh transistor is connected to the reset signal line, the first terminal of the seventh transistor is connected to the first initialization signal line, and the second terminal of the seventh transistor is connected to the input terminal of the filter module; the gate of the eighth transistor is connected to the second scan line, the first terminal of the eighth transistor is connected to the first initialization signal line, and the second terminal of the eighth transistor is connected to the gate of the sixth transistor;

[0023] The gates of the eleventh transistor and the twelfth transistor are both connected to the first scan line. The first terminal of the eleventh transistor is connected to the second terminal of the sixth transistor, and the second terminal of the eleventh transistor is connected to the gate of the sixth transistor. The first terminal of the twelfth transistor is connected to the first power line, and the second terminal of the twelfth transistor is connected to the first terminal of the sixth transistor. The gate of the thirteenth transistor is connected to the first light emission control signal line, the first terminal of the thirteenth transistor is connected to the first power line, and the second terminal of the thirteenth transistor is connected to the first terminal of the sixth transistor.

[0024] The gate of the fourteenth transistor is connected to the first light-emitting control signal line, the first terminal of the fourteenth transistor is connected to the second terminal of the sixth transistor, and the second terminal of the fourteenth transistor is connected to the input terminal of the filter module.

[0025] Optionally, the current control module includes a second light-emitting control unit and a first storage unit. The control terminal of the second light-emitting control unit is connected to the output terminal of the filter module as the control terminal of the current control module, and the first storage unit is connected to the control terminal of the second light-emitting control unit. The current control module also includes a second driving unit, a third voltage writing unit, a second storage unit, and a third light-emitting control unit. The first terminal of the second light-emitting control unit is connected to the first power line, the second terminal of the second light-emitting control unit is connected to the first terminal of the second driving unit, and the second terminal of the second driving unit is connected to the light-emitting module through the third light-emitting control unit.

[0026] The third voltage writing unit is used to write the second data signal transmitted on the second data line to the control terminal of the second driving unit, and the second storage unit is connected to the control terminal of the second driving unit.

[0027] Preferably, the current control module further includes an initialization unit, which is connected between the second initialization signal line and the control terminal of the second drive unit;

[0028] Preferably, the current control module further includes a second compensation unit, which is connected between the control terminal and the second terminal of the second drive unit;

[0029] Preferably, the current control module further includes a second reset unit, which is connected between the second initialization signal line and the control terminal of the second light-emitting control unit.

[0030] Optionally, the second light-emitting control unit includes a fifteenth transistor, the second driving unit includes a sixteenth transistor, the third voltage writing unit includes a seventeenth transistor, the initialization unit includes an eighteenth transistor, the second compensation unit includes a nineteenth transistor, the third light-emitting control unit includes a twentieth transistor, the first storage unit includes a third capacitor, the second storage unit includes a fourth capacitor, and the light-emitting module includes a light-emitting diode;

[0031] The gate of the fifteenth transistor is connected to the output terminal of the filter module, the first terminal of the fifteenth transistor is connected to the first power line, the second terminal of the fifteenth transistor is connected to the first terminal of the sixteenth transistor, the second terminal of the sixteenth transistor is connected to the first terminal of the twentieth transistor, the second terminal of the twentieth transistor is connected to the first terminal of the light-emitting diode, the second terminal of the light-emitting diode is connected to the second power line, and the gate of the twentieth transistor is connected to the second light-emitting control signal line.

[0032] The gates of the seventeenth transistor and the nineteenth transistor are both connected to the second scan line. The first terminal of the seventeenth transistor is connected to the second data line. The second terminal of the seventeenth transistor is connected to the first terminal of the sixteenth transistor. The first terminal of the nineteenth transistor is connected to the gate of the sixteenth transistor. The second terminal of the nineteenth transistor is connected to the second terminal of the sixteenth transistor. The gate of the eighteenth transistor is connected to the third scan line. The first terminal of the eighteenth transistor is connected to the second initialization signal line. The second terminal of the eighteenth transistor is connected to the gate of the sixteenth transistor.

[0033] The first terminal of the third capacitor and the first terminal of the fourth capacitor are both connected to the first power line. The second terminal of the third capacitor is connected to the gate of the fifteenth transistor, and the second terminal of the fourth capacitor is connected to the gate of the sixteenth transistor.

[0034] According to another aspect of the present invention, a display device is provided, including the pixel circuit provided in any embodiment of the present invention.

[0035] This invention provides a filtering module between the output terminal of the light emission timing control module and the control terminal of the current control module. This module can filter out interference signals in the signal output by the light emission timing control module (e.g., the light emission timing control signal), ensuring the quality of the effective signal transmitted to the control terminal of the current control module. This prevents interference signals in the output signal of the light emission timing control module from affecting the potential of the control terminal of the current control module, thus preventing abnormal phenomena such as unstable light emission of the light emission module. This improves the stability of the potential of the control terminal of the current control module, enabling the light emission module to emit light continuously and stably, improving the display effect, and further enhancing the stability of the pixel circuit.

[0036] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 A schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0039] Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0040] Figure 3 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0041] Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0042] Figure 5 A schematic diagram of another pixel circuit provided in an embodiment of the present invention.

[0043] Figure 6 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0044] Figure 7 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0045] Figure 8 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0046] Figure 9 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0047] Figure 10 A driving timing waveform diagram of a pixel circuit provided in an embodiment of the present invention;

[0048] Figure 11 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0049] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0050] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0051] As described in the background section, existing pixel circuits suffer from poor stability. The inventors have discovered that the reason for this problem is that there are many parasitic capacitances and resistances in the signal transmission path of the pixel circuit, which can easily couple to form high-frequency signals. This can cause interference with the effective signal, resulting in unstable light emission from the light-emitting element, reducing the stability of the pixel circuit and affecting the display effect.

[0052] To address the aforementioned problems, embodiments of the present invention provide a pixel circuit that can be used to drive light-emitting elements such as Micro-LEDs or OLEDs, thereby improving the stability of the pixel circuit. Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention, with reference to... Figure 1The pixel circuit includes: a light emission timing control module 10, a current control module 20, a light emission module 30, and a filter module 40; the output terminal of the light emission timing control module 10 is connected to the input terminal of the filter module 40, and the output terminal of the filter module 40 is connected to the control terminal N1 of the current control module 20. The light emission timing control module 10 is used to output a light emission timing control signal according to the first data signal Vdata_t and the sweep frequency signal SWEEP, and the filter module 40 is used to filter out interference signals in the light emission timing control signal; the current control module 20 and the light emission module 30 are connected between the first power line L1 and the second power line L2. The current control module 20 is used to drive the light emission module 30 to emit light, and controls the voltage of its own control terminal N1 according to the light emission timing control signal to control the light emission time of the light emission module 30.

[0053] Specifically, the first power line L1 is used to transmit the first power supply voltage VDD, and the second power line L2 is used to transmit the second power supply voltage VSS. When the discharge path between the first power line L1 and the second power line L2 is open, the current control module 20 generates a drive signal based on the second data signal Vdata_I to drive the light-emitting module 30 to emit light. The drive signal generated by the current control module 20 can be a current signal. During the light-emitting process of the light-emitting module 30, the displayed grayscale depends on the duration of light emission. In other words, the duration of the drive signal generated by the current control module 20 determines the grayscale displayed by the light-emitting module 30. The longer the drive signal is maintained, the longer the light emission time of the light-emitting module 30, and the higher the corresponding grayscale; conversely, the shorter the drive signal is maintained, the shorter the light emission time of the light-emitting module 30, and the lower the corresponding grayscale.

[0054] In this embodiment, the duration of the drive signal generated by the current control module 20 can be controlled by the light emission time control module 10. During the light emission phase, the sweep frequency signal SWEEP is coupled into the light emission time control module 10. The light emission time control module 10 can control its own conduction time according to the first data signal Vdata_t and the sweep frequency signal SWEEP. When the sweep frequency signal SWEEP turns on the light emission time control module 10, the light emission time control module 10 outputs a light emission time control signal, thereby controlling the voltage of the control terminal N1 of the current control module 20. When the current control module 20 turns off according to the voltage of its control terminal N1, the discharge path between the first power line L1 and the second power line L2 is broken, the current control module 20 has no drive current output, and the light emission module 30 is turned off, thus realizing the control of the light emission time of the light emission module 30.

[0055] A filtering module 40 is disposed between the output terminal of the light emission timing control module 10 and the control terminal N1 of the current control module 20, and is used to filter out interference signals in the output signal of the light emission timing control module 10. For example, during the light emission stage, when the light emission timing control module 10 is turned on according to the sweep frequency signal SWEEP, it transmits the first power supply voltage VDD (light emission timing control signal) to the output terminal of the light emission timing control module 10. In the transmission path of the first power supply voltage VDD, interference signals generated by leakage current, parasitic capacitance resistance, or external coupling signals may be present. The filtering module 40 can filter out these interference signals. Furthermore, the process of the light emission timing control module 10 outputting the light emission timing control signal is affected by the first data signal Vdata_t and the sweep frequency signal SWEEP. Therefore, the filtering module 40 can also filter out interference signals in the first data signal Vdata_t and the sweep frequency signal SWEEP, thereby improving the potential stability of the control terminal N1 of the current control module 20 and preventing display abnormalities caused by potential instability of the control terminal N1 of the current control module 20, thus improving the stability of the pixel circuit.

[0056] This invention provides a filtering module between the output terminal of the light emission timing control module and the control terminal of the current control module. This module can filter out interference signals in the signal output by the light emission timing control module (e.g., the light emission timing control signal), ensuring the quality of the effective signal transmitted to the control terminal of the current control module. This prevents interference signals in the output signal of the light emission timing control module from affecting the potential of the control terminal of the current control module, thus preventing abnormal phenomena such as unstable light emission of the light emission module. This improves the stability of the potential of the control terminal of the current control module, enabling the light emission module to emit light continuously and stably, improving the display effect, and further enhancing the stability of the pixel circuit.

[0057] Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 2 Based on the above technical solution, optionally, the filtering module 40 includes a first switching unit 401 and a second switching unit 402. The input terminal of the first switching unit 401 and the input terminal of the second switching unit 402 are connected to serve as the input terminal of the filtering module 40, and the output terminal of the first switching unit 401 and the output terminal of the second switching unit 402 are connected to serve as the output terminal of the filtering module 40.

[0058] In this process, the frequency of the interference signal in the output signal of the light emission time control module 10 is greater than the frequency of the effective signal. The first switch unit 401 and the second switch unit 402 are alternately turned on, so that the signal at the output terminal of the light emission time control module 10 is alternately transmitted to the control terminal N1 of the current control module 20 through the first switch unit 401 and the second switch unit 402. The interference signal is filtered out during the alternating transmission process.

[0059] In this embodiment, the structure of the filtering module 40 can be varied. Any structure that can filter out interference signals is within the scope of protection of this invention.

[0060] Figure 3 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, specifically illustrating one structure of the filter module 40, see reference. Figure 3 Based on the above technical solution, optionally, the first switching unit 401 includes a first transistor M1, and the second switching unit 402 includes a second transistor M2; the gate of the first transistor M1 is connected to a first clock signal line, the first electrode of the first transistor M1 is connected to the output terminal of the light emission timing control module 10, and the second electrode of the first transistor M1 is connected to the control terminal N1 of the current control module 20; the gate of the second transistor M2 is connected to a second clock signal line, the first electrode of the second transistor M2 is connected to the output terminal of the light emission timing control module 10, and the second electrode of the second transistor M2 is connected to the control terminal N1 of the current control module 20.

[0061] Among them, the first clock signal CK1 transmitted on the first clock signal line and the second clock signal CK2 transmitted on the second clock signal line are complementary signals. Here, both the first clock signal CK1 and the second clock signal CK2 are high-frequency AC pulse signals.

[0062] In this embodiment, the first transistor M1 and the second transistor M2 are transistors of the same type, such as both being P-channel transistors. Since the timing of the first clock signal CK1 and the second clock signal CK2 is complementary, the first transistor M1 and the second transistor M2 are alternately turned on. That is, when the first transistor M1 is on, the second transistor M2 is off; when the second transistor M2 is on, the first transistor M1 is off, and so on, alternating in operation. The alternately turned first transistor M1 and the second transistor M2 form a chopper circuit. After the signal at the output of the light emission timing control module 10 passes through the filtering module 40, the high-frequency signal components in the signal are filtered out to the high-frequency region of the first clock signal CK1 and the second clock signal CK2, and the effective signal components in this signal are transmitted to the control terminal N1 of the current control module 20, improving the stability of the signal transmitted to the control terminal N1 of the current control module 20, which is beneficial for maintaining the potential stability of the control terminal N1 of the current control module 20. Furthermore, the filtering module 40 has a simple structure, which helps to reduce the layout space occupied and achieve a high PPI.

[0063] Figure 4 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention, specifically illustrating another structure of the filtering module 40, see reference. Figure 2 and Figure 4Optionally, the first switching unit 401 includes a first transistor M1 and a third transistor M3, the second switching unit 402 includes a second transistor M2 and a fourth transistor M4, and the filtering module 40 further includes a fifth transistor M5; the gates of the first transistor M1 and the third transistor M3 are both connected to a first clock signal line, the gates of the second transistor M2 and the fourth transistor M4 are both connected to a second clock signal line, the first terminal of the first transistor M1 is connected to the output terminal of the light emission timing control module 10, the second terminal of the first transistor M1 is connected to the first terminal of the fourth transistor M4, and the second terminal of the fourth transistor M4 is connected to the control terminal N1 of the current control module 20; the first terminal of the second transistor M2 is connected to the output terminal of the light emission timing control module 10, the second terminal of the second transistor M2 is connected to the first terminal of the third transistor M3, and the second terminal of the third transistor M3 is connected to the control terminal N1 of the current control module 20; the first terminal of the fifth transistor M5 is connected to the second terminal of the first transistor M1, the second terminal of the fifth transistor M5 is connected to the first terminal of the third transistor M3, and the gate of the fifth transistor M5 is connected to a first voltage control signal line.

[0064] Specifically, the fifth transistor M5 is positioned as a common transistor between the first transistor M1 and the third transistor M3, and between the second transistor M2 and the fourth transistor M4, to conduct the path between the first transistor M1 and the third transistor M3, and the path between the second transistor M2 and the fourth transistor M4. The first transistor M1 and the third transistor M3 can be transistors of the same type, and the second transistor M2 and the fourth transistor M4 can also be transistors of the same type. Taking a scenario where all four transistors are P-channel transistors, the timing of the first clock signal CK1 and the second clock signal CK2 is complementary. Therefore, the signal path composed of the first transistor M1, the fifth transistor M5, and the third transistor M3, and the signal path composed of the second transistor M2, the fifth transistor M5, and the fourth transistor M4 are alternately activated. The two alternately conducting signal paths have a chopping function. After the signal at the output of the emission timing control module 10 passes through the filtering module 40, the high-frequency signal components in the signal are filtered out to the high-frequency region of the first clock signal CK1 and the second clock signal CK2. Furthermore, the effective signal components are transmitted to the control terminal N1 of the current control module 20, improving the stability of the signal transmitted to the control terminal N1 and helping to maintain the potential stability of the control terminal N1. In addition, the filtering module 40 has a simple structure, which helps to reduce the layout space occupied and achieve high PPI.

[0065] The voltage transmitted on the first voltage control signal line can be a low-level signal VGL, which keeps the fifth transistor M5 in a normally open state. Alternatively, the voltage transmitted on the first voltage control signal line can be a light emission control signal EM, which turns the fifth transistor M5 on at least during the light emission phase, and forcibly disconnects the light emission timing module 10 from the current control module 20 during the non-light emission phase to prevent signal coupling between the two from affecting the light emission stability.

[0066] Of course, in other embodiments, the transistor types in the first switching unit 401 and the second switching unit 402 may also be different. By setting the timing of the first clock signal CK1 and the second clock signal CK2, it can still be ensured that the first switching unit 401 and the second switching unit 402 are turned on alternately. The specific working process will not be described in detail here.

[0067] On the other hand, in existing technologies, for digitally driven pixel circuits, the change in grayscale refers to the change in the duration difference between high and low level digital signals. However, due to the discrete nature of digital signals, the continuity of grayscale is poor, making it difficult to effectively expand the grayscale. Analog-driven pixel circuits, on the other hand, utilize voltage and current within a certain range to achieve grayscale expansion. Since voltage and current are analog signals, they have good continuity, enabling continuous grayscale. However, the current is easily affected by the characteristics of transistors in the pixel circuit, preventing complete grayscale expansion. Therefore, both digital and analog driving technologies suffer from the problem of incomplete grayscale expansion. To address this, this invention provides a hybrid digital-analog driving pixel circuit that enables coordinated operation of both digital and analog driving, combining the advantages of both methods to achieve stable pixel circuit operation and better grayscale expansion.

[0068] Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 5 Based on the above technical solutions, the light emission timing control module 10 includes a first driving unit 101, a coupling unit 102, a first reset unit 104, and a first voltage writing unit 103. The first voltage writing unit 103 is used to transmit a fixed voltage to the control terminal G1 of the first driving unit 101. The coupling unit 102 is used to couple the first data signal Vdata_t and the sweep frequency signal SWEEP to the control terminal G1 of the first driving unit 101. The first driving unit 101 is connected between the first power line L1 and the input terminal of the filter module 40. The first terminal of the first reset unit 104 is connected to the first initialization signal line, and the second terminal of the first reset unit 104 is connected to the input terminal of the filter module 40. The first reset unit 104 is used to reset the voltage of the control terminal N1 of the current control module 20.

[0069] Specifically, the first voltage writing unit 103 writes a fixed voltage V1 to the control terminal G1 of the first driving unit 101 to initialize the potential of the control terminal G1 of the first driving unit 101. Here, the fixed voltage V1 can be the first power supply voltage VDD, or other voltages that can turn off the first driving unit 101. Afterwards, the first data signal Vdata_t is written to the first terminal of the coupling unit 102, and there is a voltage difference between the two ends of the coupling unit 102. When the first reset unit 104 is turned on, the first reset unit 104 transmits the first initialization voltage Vref1 on the first initialization signal line to the output terminal of the light emission time control module 10. After the first initialization voltage Vref1 passes through the filtering module 40, the interference signal in the first initialization voltage Vref1 is filtered out. The current control module 20 is turned on according to the first initialization voltage Vref1, and the discharge path between the first power line L1 and the second power line L2 is turned on. The current control module 20 outputs a driving current according to the second data signal Vdata_I and the first power supply voltage VDD to drive the light emission module 30 to emit light.

[0070] During the illumination process of the light-emitting module 30, the sweep frequency signal SWEEP changes from high level to low level or from low level to high level. As the level of the sweep frequency signal SWEEP changes, the voltage change at its first end is coupled to the second end under the coupling effect of the coupling unit 102. When the voltage at the second end of the coupling unit 102 is sufficient to turn on the first driving unit 101, the first power supply voltage VDD is transmitted to the input end of the filter module 40. After the filter module 40 filters out the interference signal in the first power supply voltage VDD, the current control module 20 turns off the first power supply voltage VDD according to its control terminal N1, thereby controlling the light-emitting module 30 to turn off, thus achieving the purpose of controlling the illumination time of the light-emitting module 30.

[0071] In this embodiment, the current control module 20 generates a driving current based on the second data signal Vdata_I. The driving current output by the module determines the driving capability of the current control module 20, thereby controlling the magnitude of the driving current output by the current control module 20. In other words, the magnitude of the driving current of the light-emitting module 30 is controlled by the current control module 20. The first driving unit 101 in the light-emitting time control module 10 can control its own conduction duration based on the magnitude of the first data signal Vdata_t and the sweep frequency signal SWEEP. In other words, the current control of the first driving unit 101 is converted into time control by the external sweep frequency signal SWEEP. The brightness of the light emission is adjusted by changing the conduction time of the current control module 20 to achieve different grayscale displays. This makes the grayscale unfolding continuous, which is more conducive to the unfolding of grayscale and makes up for the problem of discontinuous grayscale unfolding in the prior art. Furthermore, by setting the filter module 40, the pixel circuit is made to work stably, which is beneficial to improving the reliability of grayscale modulation. For example, when the drive current output by the current control module 20 is constant, under the control of the sweep frequency signal SWEEP, the longer the conduction time of the first drive unit 101, the larger the grayscale of the display (the brighter the corresponding display brightness).

[0072] Furthermore, since the first data signal Vdata_t is indirectly written to the control terminal G1 of the first driving unit 101 through the coupling unit 102, the conduction state of the first driving unit 101 does not need to be set according to the magnitude of the first data signal Vdata_t. There is no voltage requirement between the first data signal Vdata_t and the first power supply voltage VDD. The first power supply voltage VDD can be flexibly set, thus reducing the pixel voltage span and reducing the bias voltage on the device, which is beneficial to improving the reliability of the pixel circuit.

[0073] In this embodiment, the first data signal Vdata_t is provided by the first data line, and the sweep frequency signal SWEEP can share the first data line with the first data signal Vdata_t, or the two can be set separately. This embodiment does not impose any restrictions on this.

[0074] Figure 6 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 6 Based on the above technical solution, optionally, the light emission time control module 10 further includes a first light emission control unit 105. The first end of the first light emission control unit 105 is connected to the second end D11 of the first driving unit 101. The first end S11 of the first driving unit 101 is connected to the voltage transmitted on the first power line L1. The second end of the first light emission control unit 105 is connected to the input end of the filter module 40 as the output end of the light emission time control module 10.

[0075] The first light-emitting control unit 105 is used to control the on / off state of the path between the output terminal of the light-emitting time control module 10 and the control terminal N1 of the current control module 20, thereby improving the reliability of the light-emitting module 30.

[0076] Continue to refer to Figure 6 The light emission time control module 10 also includes a first compensation unit 106 and a second voltage writing unit 107. The first compensation unit 106 is connected between the second terminal D1 and the control terminal G1 of the first driving unit 101, and the second voltage writing unit 107 is connected between the first power line L1 and the first terminal S11 of the first driving unit 101.

[0077] The first voltage writing unit 103 is connected to the first initialization signal line at its first end, and to the control terminal of the first driving module 101 at its second end. The second end of the first voltage writing unit 103 transmits the first initialization voltage Vref1 to the control terminal G1 of the first driving unit 101 to initialize the potential of the control terminal G1, preventing residual voltage from the previous frame from affecting the illumination of the current frame, and simultaneously putting the first driving unit 101 in a conducting state. Then, the second voltage writing unit 107 and the first compensation unit 106 are turned on, and the first power supply voltage VDD is written to the control terminal G1 of the first driving unit 101 through the first driving unit 101 and the first compensation unit 106. When the potential of the control terminal G1 of the first driving unit 101 is VDD + Vth1, the first driving unit 101 is turned off, where Vth1 is the threshold voltage of the first driving unit 101. The control terminal G1 of the first driving unit 101 forms a stable potential (i.e., VDD + Vth1). At the same time, the first data signal Vdata_t is written to the first terminal of the coupling unit 102. The voltage difference between the two terminals of the coupling unit 102 is VDD+Vth1-Vdata_t, thereby realizing threshold compensation for the first driving unit 101, ensuring the accuracy of converting the first data signal Vdata_t into a time control signal, and improving the reliability of controlling the current control module 20.

[0078] Figure 7 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 7Based on the above technical solutions, optionally, the current control module 20 includes a second light-emitting control unit 201 and a first storage unit 202. The control terminal of the second light-emitting control unit 201 is connected to the output terminal of the filter module 40 as the control terminal N1 of the current control module 20. The first storage unit 202 is connected to the control terminal of the second light-emitting control unit 201. The current control module 20 also includes a second driving unit 203, a third voltage writing unit 204, a second storage unit 205, and a third light-emitting control unit 208. The first terminal of the second light-emitting control unit 201 is connected to the first power line L1. The second terminal of the second light-emitting control unit 201 is connected to the first terminal S21 of the second driving unit 203. The second terminal D21 of the second driving unit 203 is connected to the light-emitting module 30 through the third light-emitting control unit 208.

[0079] The third voltage writing unit 204 is used to write the second data signal Vdata_I transmitted on the second data line to the control terminal G2 of the second driving unit 203. The second storage unit 205 is connected to the control terminal G2 of the second driving unit 203 to store the voltage of the control terminal G2 of the second driving unit 203. The second light-emitting control unit 201 and the third light-emitting control unit 208 are used to control the conduction state of the discharge path between the first power line L1 and the light-emitting module 30.

[0080] Figure 8 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 8 Based on the above technical solution, the current control module 20 may optionally further include an initialization unit 206 and a second compensation unit 207. The initialization unit 206 is connected between the second initialization signal line and the control terminal G2 of the second driving unit 203; the second compensation unit 207 is connected between the control terminal G2 and the second terminal D21 of the second driving unit 203. The second voltage writing unit 204 is connected between the second data line and the first terminal S2 of the second driving unit 203. During the voltage writing stage, the second data signal Vdata_I transmitted on the second data line is written to the control terminal G2 of the second driving unit 203 through the second voltage writing unit 204, the second driving unit 203, and the second compensation unit 207, thereby achieving threshold compensation for the second driving unit 203.

[0081] Continue to refer to Figure 8 The current control module 20 may further include a second reset unit 209, used to initialize the potential of the control terminal of the second light-emitting control unit 201 to prevent residual charge from the previous frame from affecting the display of the current frame. The second reset unit 209 is connected between the second initialization signal line and the control terminal of the second light-emitting control unit 201.

[0082] Figure 9This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention, showing the specific structure of the pixel circuit. (Refer to...) Figure 9 The first driving unit 101 includes a sixth transistor M6, the first reset unit 104 includes a seventh transistor M7, the first voltage writing unit 103 includes an eighth transistor M8, the coupling unit 102 includes a ninth transistor M9, a tenth transistor M10, a first capacitor C1, and a second capacitor C2, the first compensation unit 105 includes an eleventh transistor M11, the second voltage writing unit 107 includes a twelfth transistor M12 and a thirteenth transistor M13, and the first light-emitting control unit 105 includes a fourteenth transistor M14; the gate of the ninth transistor M9 is connected to the first scan line, the first electrode of the ninth transistor M9 is connected to the first data line, and the second electrode of the ninth transistor M9 is connected to the gate of the sixth transistor M6 through the first capacitor C1; the gate of the tenth transistor M10 is connected to the first light-emitting control signal line, the first electrode of the tenth transistor M10 is connected to the sweep frequency signal line, and the second electrode of the tenth transistor M10 is connected to the gate of the sixth transistor M6 through the second capacitor C2; the gate of the seventh transistor M7 is connected to... The reset signal line, the first terminal of the seventh transistor M7 is connected to the first initialization signal line, the second terminal of the seventh transistor M7 is connected to the input terminal of the filter module 40, the gate of the eighth transistor M8 is connected to the second scan line, the first terminal of the eighth transistor M8 is connected to the first initialization signal line, and the second terminal of the eighth transistor M8 is connected to the gate of the sixth transistor M6; the gates of the eleventh transistor M11 and the twelfth transistor M12 are both connected to the first scan line, the first terminal of the eleventh transistor M11 is connected to the second terminal of the sixth transistor M6, the second terminal of the eleventh transistor M11 is connected to the gate of the sixth transistor M6, the first terminal of the twelfth transistor M12 is connected to the first power supply line L1, the second terminal of the twelfth transistor M12 is connected to the first terminal of the sixth transistor M6, the gate of the thirteenth transistor M13 is connected to the first light emission control signal line, the first terminal of the thirteenth transistor M13 is connected to the first power supply line L1, and the second terminal of the thirteenth transistor M13 is connected to the first terminal of the sixth transistor M6.

[0083] In this configuration, the ninth transistor M9 and the first capacitor C1 form a first coupling sub-unit, which is used to couple the first data signal Vdata_t to the gate of the sixth transistor M6; the tenth transistor M10 and the second capacitor C2 form a second coupling sub-unit, which is used to couple the sweep frequency signal SWEEP to the gate of the sixth transistor M6.

[0084] The gate of the fourteenth transistor M14 is connected to the first light-emitting control signal line, the first terminal of the fourteenth transistor M14 is connected to the second terminal of the sixth transistor M6, and the second terminal of the fourteenth transistor M14 is connected to the input terminal of the filter module 40.

[0085] The second light-emitting control unit 201 includes a fifteenth transistor M15, the second driving unit 203 includes a sixteenth transistor M16, the third voltage writing unit 204 includes a seventeenth transistor M17, the initialization unit 206 includes an eighteenth transistor M18, the second compensation unit 207 includes a nineteenth transistor M19, the third light-emitting control unit 208 includes a twentieth transistor M20, the first storage unit 202 includes a third capacitor C3, the second storage unit 205 includes a fourth capacitor C4, and the light-emitting module 30 includes a light-emitting diode (LED).

[0086] The gate of the fifteenth transistor M15 is connected to the output terminal of the filter module 40. The first terminal of the fifteenth transistor M15 is connected to the first power supply line L1. The second terminal of the fifteenth transistor M15 is connected to the first terminal of the sixteenth transistor M16. The second terminal of the sixteenth transistor M16 is connected to the first terminal of the twentieth transistor M20. The second terminal of the twentieth transistor M20 is connected to the first terminal of the light-emitting diode (LED). The second terminal of the LED is connected to the second power supply line L2. The gate of the twentieth transistor M20 is connected to the second light-emitting control signal line. The gate of the seventeenth transistor M17 and the nineteenth transistor... The gates of all transistors M19 are connected to the second scan line. The first terminal of the seventeenth transistor M17 is connected to the second data line. The second terminal of the seventeenth transistor M17 is connected to the first terminal of the sixteenth transistor M16. The first terminal of the nineteenth transistor M19 is connected to the gate of the sixteenth transistor M16. The second terminal of the nineteenth transistor M19 is connected to the second terminal of the sixteenth transistor M16. The gate of the eighteenth transistor M18 is connected to the third scan line. The first terminal of the eighteenth transistor M18 is connected to the second initialization signal line. The second terminal of the eighteenth transistor M18 is connected to the gate of the sixteenth transistor M16.

[0087] The first terminal of the third capacitor C3 and the first terminal of the fourth capacitor C4 are both connected to the first power line L1. The second terminal of the third capacitor C3 is connected to the gate of the fifteenth transistor M15, and the second terminal of the fourth capacitor C4 is connected to the gate of the sixteenth transistor M16.

[0088] Figure 10 A driving timing waveform diagram of a pixel circuit provided in an embodiment of the present invention is applicable to... Figure 9 The pixel circuit shown is for reference. Figure 9 and Figure 10 Taking all transistors as P-type transistors as an example, the working process of the pixel circuit provided in this embodiment of the invention includes at least a voltage writing stage T1, a voltage normalization stage T2, a reset stage T3, and a light emission stage T4. The voltage writing stage T1 includes at least an initialization stage t1, a second voltage writing stage t2, and a first voltage writing stage t3.

[0089] During the initialization phase t1, the reset signal line is configured to transmit a high-level reset signal Set, the third scan signal line is configured to transmit a low-level third scan signal S3, the second scan signal line is configured to transmit a high-level second scan signal S2, the first scan signal line is configured to transmit a high-level first scan signal S1, the first light emission control signal line is configured to transmit a high-level first light emission control signal EM1, and the second light emission control signal line is configured to transmit a high-level second light emission control signal EM2. Therefore, the eighteenth transistor M18 is turned on, and the second initialization voltage Vref2 transmitted on the second initialization signal line is written to the gate of the sixteenth transistor M16, thus initializing the gate potential of the sixteenth transistor M16.

[0090] During the second voltage writing phase t2, the reset signal line is configured to transmit a high-level reset signal Set, the third scan signal line is configured to transmit a high-level third scan signal S3, the second scan signal line is configured to transmit a low-level second scan signal S2, the first scan signal line is configured to transmit a high-level first scan signal S1, the first light emission control signal line is configured to transmit a high-level first light emission control signal EM1, and the second light emission control signal line is configured to transmit a high-level second light emission control signal EM2. Therefore, the eighth transistor M8, the seventeenth transistor M17, and the nineteenth transistor M19 are turned on. The second data signal Vdata_I is written to the gate of the sixteenth transistor M16 through the seventeenth transistor M17, the sixteenth transistor M16, and the nineteenth transistor M19. The gate potential of the sixteenth transistor M16 is Vdata_I + Vth16, and it is stored in the fourth capacitor C4, where Vth16 is the threshold voltage of the sixteenth transistor M16, thus achieving threshold compensation for the sixteenth transistor M16. Simultaneously, the first initialization voltage Vref1 transmitted on the first initialization signal line is written to the gate of the sixth transistor M6 through the eighth transistor M8, thereby initializing the gate potential of the sixth transistor M6. At this time, the sixth transistor M6 is in the on state.

[0091] During the first voltage writing phase t3, the reset signal line is configured to transmit a high-level reset signal Set, the third scan signal line is configured to transmit a high-level third scan signal S3, the second scan signal line is configured to transmit a high-level second scan signal S2, the first scan signal line is configured to transmit a low-level first scan signal S1, the first light emission control signal line is configured to transmit a high-level first light emission control signal EM1, and the second light emission control signal line is configured to transmit a high-level second light emission control signal EM2. Therefore, the ninth transistor M9, the eleventh transistor M11, and the twelfth transistor M12 are turned on, and the first power supply voltage VDD is transmitted on the first power supply line L1 to charge the gate of the sixth transistor M6 until the gate potential of the sixth transistor M6 reaches VDD+Vth6, at which point the sixth transistor M6 is turned off, where Vth6 is the threshold voltage of the sixth transistor M6. At this time, the gate voltage of the sixth transistor M6 stabilizes at VDD+Vth6, achieving threshold compensation for the sixth transistor M6. At the same time, the first data signal Vdata_t is written to the first terminal of the first capacitor C1 through the ninth transistor M9. At this time, the voltage difference across the first capacitor C1 is VDD+Vth6-Vdata_t.

[0092] In this embodiment, an open-state capacitance exists between the gate and the second electrode of the sixth transistor M6. When the second electrode of the sixth transistor M6 is directly connected to the first power line L1, this open-state capacitance is also directly connected to the first power line L1. After data writing is completed, charge flows through this open-state capacitance, affecting the charging and discharging rate of the gate of the sixth transistor M6, resulting in reduced accuracy in controlling the light emission time and hindering grayscale expansion. In this embodiment, by setting a second voltage writing module 107, the open-state capacitance can be placed in a floating state after data writing (both the twelfth transistor M12 and the thirteenth transistor M13 are cut off), which is equivalent to having no capacitance at the gate of the sixth transistor M6. This does not affect the charging and discharging rate of the sixth transistor M6 and allows for better control of the light emission time of the light-emitting module 30.

[0093] In stage t4, the remaining sub-pixels undergo initialization stage t1, second voltage writing stage t2, and first voltage writing stage t3, completing the data writing for all pixel rows.

[0094] During the voltage normalization phase T2, the signal on the first data line transitions from the first data signal Vdata_t to the high level SWEEP-H of the sweep signal SWEEP. In this embodiment, the high level SWEEP-H of the sweep signal SWEEP is greater than or equal to the maximum value of the first data signal Vdata_t. Under the coupling effect of the first capacitor C1, the first data signal Vdata_t is coupled to the gate of the sixth transistor M6, thus realizing the writing of the first data signal Vdata_t.

[0095] During the reset phase T3, the reset signal line is configured to transmit a low-level reset signal Set, the third scan signal line is configured to transmit a high-level third scan signal S3, the second scan signal line is configured to transmit a high-level second scan signal S2, the first scan signal line is configured to transmit a high-level first scan signal S1, the first light emission control signal line is configured to transmit a high-level first light emission control signal EM1, and the second light emission control signal line is configured to transmit a high-level second light emission control signal EM2. Therefore, the seventh transistor M7 is turned on, and the first initialization voltage Vref on the first initialization signal line is transmitted to the gate of the fifteenth transistor M15 after passing through the filter module 40, controlling the fifteenth transistor M15 to turn on, so that the first power supply voltage VDD is transmitted to the first terminal of the sixteenth transistor M16. The filter module 40 can filter out interference signals in the first initialization voltage Vref1 signal, ensuring the stability of the gate potential of the fifteenth transistor M15.

[0096] During the light-emitting stage T4, the reset signal line is configured to transmit a high-level reset signal Set, the third scan signal line is configured to transmit a high-level third scan signal S3, the second scan signal line is configured to transmit a high-level second scan signal S2, the first scan signal line is configured to transmit a high-level first scan signal S1, the first light-emitting control signal line is configured to transmit a low-level first light-emitting control signal EM1, and the second light-emitting control signal line is configured to transmit a low-level second light-emitting control signal EM2. Therefore, the twentieth transistor M20, the tenth transistor M10, the thirteenth transistor M13, and the fourteenth transistor M14 are turned on. The sixteenth transistor M16 generates a drive current based on the first power supply voltage VDD and the second data signal Vdata_I, driving the light-emitting module 30 to emit light. The drive current can be expressed by the following formula:

[0097]

[0098] Where μ is the electron mobility of the sixteenth transistor M16, Cox is the channel capacitance per unit area of ​​the sixteenth transistor M16, W / L is the aspect ratio of the sixteenth transistor M16, and Vth16 is the threshold voltage of the sixteenth transistor M16. In this embodiment, the light-emitting module 30 may include one or more of OLED, Micro-LED, and Mini-LED.

[0099] Simultaneously, the sweep signal SWEEP gradually changes from high level SWEEP-H to low level SWEEP-L. Due to the coupling effect of the second capacitor C2, the gate potential of the sixth transistor M6 changes synchronously. When the sweep signal SWEEP decreases to make the gate potential VG1 of the sixth transistor M6 satisfy VG1-VDD=Vth6, the sixth transistor M6 turns on. The first power supply voltage VDD is transmitted to the gate of the fifteenth transistor M15 through the thirteenth transistor M13, the sixth transistor M6, the fourteenth transistor M14, and the filter module 40, controlling the fifteenth transistor M15 to turn off. The third capacitor C3 is used to maintain the gate potential of the fifteenth transistor M15. Therefore, the first terminal of the sixteenth transistor M16 is disconnected from the first power line L1, the drive current is zero, the light-emitting module 30 is turned off, and the light-emitting time is controlled.

[0100] The specific working process of the filtering module 40 can be referred to the relevant description in any of the above embodiments, and will not be repeated here.

[0101] In practical applications, the twentieth transistor M20 and the tenth transistor M10 can be turned on simultaneously according to actual needs without affecting the operation of the pixel circuit.

[0102] Optionally, embodiments of the present invention also provide a display device, which includes the pixel circuit provided in embodiments of the present invention. Figure 11 This is a schematic diagram of a display device provided in an embodiment of the present invention. The display device can be a tablet, mobile phone, watch, wearable device, as well as other display-related electronic products such as automotive displays, camera displays, televisions, and computer screens. Since this display device includes the pixel circuits provided in any embodiment of the present invention, it also possesses the beneficial effects described in any embodiment of the present invention.

[0103] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0104] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A pixel circuit, characterized in that, include: The light emission timing control module, current control module, light emission module, and filtering module are included. The output terminal of the light emission time control module is connected to the input terminal of the filter module, and the output terminal of the filter module is connected to the control terminal of the current control module. The light emission time control module is used to control the potential of the control terminal of the current control module according to the first data signal and the frequency sweep signal, so as to control the light emission time of the light emission module. The filter module is used to filter out interference signals in the output signal of the output terminal of the light emission time control module. The current control module and the light-emitting module are connected between the first power line and the second power line. The current control module is used to drive the light-emitting module to emit light according to the voltage of its control terminal and input terminal. The filtering module includes a first switching unit and a second switching unit. The input terminals of the first switching unit and the second switching unit are connected to serve as the input terminals of the filtering module, and the output terminals of the first switching unit and the second switching unit are connected to serve as the output terminals of the filtering module. The first switching unit and the second switching unit are alternately turned on. The first switching unit includes a first transistor and a third transistor, the second switching unit includes a second transistor and a fourth transistor, and the filtering module further includes a fifth transistor; The first terminal of the first transistor is connected to the output terminal of the light emission timing control module; the second terminal of the first transistor is connected to the first terminal of the fourth transistor; the second terminal of the fourth transistor is connected to the control terminal of the current control module; the first terminal of the second transistor is connected to the output terminal of the light emission timing control module; the second terminal of the second transistor is connected to the first terminal of the third transistor; the second terminal of the third transistor is connected to the control terminal of the current control module. The first terminal of the fifth transistor is connected to the second terminal of the first transistor, the second terminal of the fifth transistor is connected to the first terminal of the third transistor, and the gate of the fifth transistor is connected to the first voltage control signal line; the fifth transistor is turned on during the light-emitting phase and turned off during the non-light-emitting phase.

2. The pixel circuit according to claim 1, characterized in that, The first switching unit includes a first transistor, and the second switching unit includes a second transistor; The gate of the first transistor is connected to the first clock signal line, the first terminal of the first transistor is connected to the output terminal of the light emission timing control module, and the second terminal of the first transistor is connected to the control terminal of the current control module; the gate of the second transistor is connected to the second clock signal line, the first terminal of the second transistor is connected to the output terminal of the light emission timing control module, and the second terminal of the second transistor is connected to the control terminal of the current control module.

3. The pixel circuit according to claim 2, characterized in that... The first clock signal transmitted on the first clock signal line and the second clock signal transmitted on the second clock signal line are complementary signals.

4. The pixel circuit according to claim 1, characterized in that, The gates of the first transistor and the third transistor are both connected to the first clock signal line, and the gates of the second transistor and the fourth transistor are both connected to the second clock signal line.

5. The pixel circuit according to claim 4, characterized in that, The first clock signal transmitted on the first clock signal line and the second clock signal transmitted on the second clock signal line are complementary signals.

6. The pixel circuit according to claim 1, characterized in that, The light emission timing control module includes a first driving unit, a coupling unit, a first reset unit, and a first voltage writing unit; The first voltage writing unit is used to transmit a fixed voltage to the control terminal of the first driving unit. The coupling unit is used to couple the first data signal and the sweep frequency signal to the control terminal of the first driving unit. The first driving unit is connected between the first power line and the input terminal of the filter module. The first terminal of the first reset unit is connected to the first initialization signal line. The second terminal of the first reset unit is connected to the input terminal of the filter module. The first reset unit is used to reset the voltage at the control terminal of the current control module.

7. The pixel circuit according to claim 6, characterized in that, The light emission timing control module further includes a first light emission control unit. The first end of the first light emission control unit is connected to the second end of the first driving unit. The first end of the first driving unit is connected to the voltage transmitted on the first power line. The second end of the first light emission control unit is connected to the input end of the filter module as the output end of the light emission timing control module.

8. The pixel circuit according to claim 7, characterized in that, The light emission time control module further includes a first compensation unit and a second voltage writing unit. The first compensation unit is connected between the second end of the first driving unit and the control end, and the second voltage writing unit is connected between the first power line and the first end of the first driving unit.

9. The pixel circuit according to claim 8, characterized in that, The first end of the first voltage writing unit is connected to the first initialization signal line, and the second end of the first voltage writing unit is connected to the control end of the first driving unit.

10. The pixel circuit according to claim 9, characterized in that, The first driving unit includes a sixth transistor, the first reset unit includes a seventh transistor, the first voltage writing unit includes an eighth transistor, the coupling unit includes a ninth transistor, a tenth transistor, a first capacitor and a second capacitor, the first compensation unit includes an eleventh transistor, the second voltage writing unit includes a twelfth transistor and a thirteenth transistor, and the first light-emitting control unit includes a fourteenth transistor. The gate of the ninth transistor is connected to the first scan line, the first terminal of the ninth transistor is connected to the first data line, and the second terminal of the ninth transistor is connected to the gate of the sixth transistor through the first capacitor; the gate of the tenth transistor is connected to the first light emission control signal line, the first terminal of the tenth transistor is connected to the sweep frequency signal line, and the second terminal of the tenth transistor is connected to the gate of the sixth transistor through the second capacitor; the gate of the seventh transistor is connected to the reset signal line, the first terminal of the seventh transistor is connected to the first initialization signal line, and the second terminal of the seventh transistor is connected to the input terminal of the filter module; the gate of the eighth transistor is connected to the second scan line, the first terminal of the eighth transistor is connected to the first initialization signal line, and the second terminal of the eighth transistor is connected to the gate of the sixth transistor; The gates of the eleventh transistor and the twelfth transistor are both connected to the first scan line. The first terminal of the eleventh transistor is connected to the second terminal of the sixth transistor, and the second terminal of the eleventh transistor is connected to the gate of the sixth transistor. The first terminal of the twelfth transistor is connected to the first power line, and the second terminal of the twelfth transistor is connected to the first terminal of the sixth transistor. The gate of the thirteenth transistor is connected to the first light emission control signal line, the first terminal of the thirteenth transistor is connected to the first power line, and the second terminal of the thirteenth transistor is connected to the first terminal of the sixth transistor. The gate of the fourteenth transistor is connected to the first light-emitting control signal line, the first terminal of the fourteenth transistor is connected to the second terminal of the sixth transistor, and the second terminal of the fourteenth transistor is connected to the input terminal of the filter module.

11. The pixel circuit according to claim 1, characterized in that, The current control module includes a second light-emitting control unit and a first storage unit. The control terminal of the second light-emitting control unit is connected to the output terminal of the filter module as the control terminal of the current control module. The first storage unit is connected to the control terminal of the second light-emitting control unit. The current control module further includes a second driving unit, a third voltage writing unit, a second storage unit, and a third light-emitting control unit. The first end of the second light-emitting control unit is connected to the first power line, the second end of the second light-emitting control unit is connected to the first end of the second driving unit, and the second end of the second driving unit is connected to the light-emitting module through the third light-emitting control unit. The third voltage writing unit is used to write the second data signal transmitted on the second data line to the control terminal of the second driving unit, and the second storage unit is connected to the control terminal of the second driving unit.

12. The pixel circuit according to claim 11, characterized in that, The current control module further includes an initialization unit, which is connected between the second initialization signal line and the control terminal of the second drive unit.

13. The pixel circuit according to claim 12, characterized in that, The current control module further includes a second compensation unit, which is connected between the control terminal and the second terminal of the second drive unit.

14. The pixel circuit according to claim 13, characterized in that, The current control module further includes a second reset unit, which is connected between the second initialization signal line and the control terminal of the second light-emitting control unit.

15. The pixel circuit according to claim 14, characterized in that, The second light-emitting control unit includes a fifteenth transistor, the second driving unit includes a sixteenth transistor, the third voltage writing unit includes a seventeenth transistor, the initialization unit includes an eighteenth transistor, the second compensation unit includes a nineteenth transistor, the third light-emitting control unit includes a twentieth transistor, the first storage unit includes a third capacitor, the second storage unit includes a fourth capacitor, and the light-emitting module includes a light-emitting diode. The gate of the fifteenth transistor is connected to the output terminal of the filter module, the first terminal of the fifteenth transistor is connected to the first power line, the second terminal of the fifteenth transistor is connected to the first terminal of the sixteenth transistor, the second terminal of the sixteenth transistor is connected to the first terminal of the twentieth transistor, the second terminal of the twentieth transistor is connected to the first terminal of the light-emitting diode, the second terminal of the light-emitting diode is connected to the second power line, and the gate of the twentieth transistor is connected to the second light-emitting control signal line. The gates of the seventeenth transistor and the nineteenth transistor are both connected to the second scan line. The first terminal of the seventeenth transistor is connected to the second data line. The second terminal of the seventeenth transistor is connected to the first terminal of the sixteenth transistor. The first terminal of the nineteenth transistor is connected to the gate of the sixteenth transistor. The second terminal of the nineteenth transistor is connected to the second terminal of the sixteenth transistor. The gate of the eighteenth transistor is connected to the third scan line. The first terminal of the eighteenth transistor is connected to the second initialization signal line. The second terminal of the eighteenth transistor is connected to the gate of the sixteenth transistor. The first terminal of the third capacitor and the first terminal of the fourth capacitor are both connected to the first power line. The second terminal of the third capacitor is connected to the gate of the fifteenth transistor, and the second terminal of the fourth capacitor is connected to the gate of the sixteenth transistor.

16. A display device, characterized in that, Includes the pixel circuit as described in any one of claims 1-15.

Images