Memory array and interconnect structure, method of operation

Abstract

The application provides a storage array, an interconnection structure and an operating method. The storage array comprises a plurality of bit lines, two bit lines are arranged in a row, including a first bit line and a second bit line; a plurality of source lines, two source lines are arranged in a row, including a first source line and a second source line; a storage unit and a transistor located on each column and each row, each transistor has a first source / drain and a second source / drain; for any row of the storage array, there is a connection relationship as follows: one end of the odd column storage unit is connected with the first bit line, and the other end is connected with the second source line; the first source / drain of the odd column transistor is connected with the first source line; the second source / drain of the odd column transistor is connected with the second source line; one end of the even column storage unit is connected with the second bit line, and the other end is connected with the first source line; the first source / drain of the even column transistor is connected with the second source line; and the second source / drain of the even column transistor is connected with the first source line.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a memory array and its interconnection structure and operation method. Background Technology

[0002] Magnetoresistive random access memory (MRAM) is a type of memory whose storage cells use magnetic states to store information. A single MRAM can store non-volatile data and can be written to multiple times throughout its lifetime.

[0003] To achieve the transition between high and low resistance states in MRAM, a 1T1R structure is typically composed of memory cells and transistors. By changing the direction of the current in the transistors, the memory cells can be written to either a low-resistance state or a high-resistance state.

[0004] In traditional 1T1R-MRAM memory devices, the width of the transistor must be large enough to ensure power supply capability. Dual-finger transistor structure is a common way to achieve large power supply capability. However, the existing dual-finger 1T1R structure MRAM read / write circuit has the following technical defects: while providing large power supply capability, the transistor increases the unit area of ​​the transistor, thereby limiting the storage cell density of MRAM. Summary of the Invention

[0005] To address the aforementioned problems, this invention provides a memory array that, without altering the power supply capability of a single transistor, can significantly increase the array density of memory cells while maintaining the transistor's power supply capability unchanged.

[0006] On one hand, the present invention provides a storage array, comprising:

[0007] Multiple bit lines, with two bit lines set per row, including the first bit line and the second bit line;

[0008] Multiple source lines, with two source lines set in one row, including the first source line and the second source line;

[0009] Storage cells and transistors are located in each column and each row, with each transistor having a first source / drain and a second source / drain;

[0010] For any row of the storage array, the following connection relationship exists:

[0011] One end of the odd-numbered column storage cell is connected to the first bit line, and the other end is connected to the second source line;

[0012] The first source / drain of the odd-numbered array transistors is connected to the first source line;

[0013] The second source / drain of the odd-numbered column transistors is connected to the second source line;

[0014] One end of the even-numbered column storage unit is connected to the second bit line, and the other end is connected to the first source line;

[0015] The first source / drain of the even-numbered column transistors is connected to the second source line;

[0016] The second source / drain of the even-numbered column transistors is connected to the first source line.

[0017] Optionally, the memory array further includes multiple word lines, with the gates of each column of transistors connected to the corresponding word lines.

[0018] Optionally, the storage unit is any one of the following types of storage units: MRAM, PCRAM, RRAM, and FRAM.

[0019] On the other hand, the present invention provides an interconnection structure for a storage array, comprising:

[0020] Multiple active regions, each of which corresponds to a row of the memory array, are used to form the source / drain of transistors in a row;

[0021] Multiple word lines spanning each of the active regions, each word line corresponding to a column of the memory array, the multiple word lines separating each of the active regions;

[0022] The storage cells are located between multiple word lines. One end of the odd-numbered column storage cell is connected to the active area between the odd-numbered column word line and the next even-numbered column word line, and the other end of the even-numbered column storage cell is connected to the active area between the even-numbered column word line and the next odd-numbered column word line.

[0023] And, the first bit line, the second bit line, the first source line, and the second source line located in each of the aforementioned active regions,

[0024] The first bit line is connected to the other end of the odd-numbered column storage cell;

[0025] The second bit line is connected to the other end of the even-numbered column storage cell;

[0026] The first source line is connected to the active region between the even-numbered column word line and the odd-numbered column word line of the next column;

[0027] The second source line is connected to the active region between the odd-numbered column word line and the even-numbered column word line of the next column.

[0028] Optionally, the first bit line, the second bit line, the first source line, and the second source line are all located above each active region, arranged in parallel along the word line extension direction, and there is no overlapping area in the vertical direction.

[0029] Optionally, the first source line and the second source line are located in the edge region of each of the active regions;

[0030] Alternatively, the first source line and the second source line are located in the middle region of each of the active regions;

[0031] Alternatively, one of the first source line and the second source line may be located in the middle region of each active region, and the other may be located in the edge region of each active region.

[0032] Optionally, the storage unit is located above the active region;

[0033] The storage unit is located on the contact plug or in any layer of via.

[0034] Optionally, the first source line and the second source line comprise one or more layers of metal wires.

[0035] Optionally, the first bit line and the first source line are arranged vertically and overlap in the vertical direction; the second bit line and the second source line are arranged vertically and overlap in the vertical direction.

[0036] Optionally, the first bit line is located above the first source line, and the first bit line is led out above the shallow trench isolation between the active regions through staggered metal traces; the second bit line is located above the second source line, and the second bit line is led out above the shallow trench isolation between the active regions through staggered metal traces.

[0037] Alternatively, the first source line is located above the first bit line, and the first source line is led out above the shallow trench isolation between the active areas through interleaved metal traces. The second source line is located above the second bit line, and the second source line is led out above the shallow trench isolation between the active areas through interleaved metal traces.

[0038] Optionally, the storage cell is located above the active area, or is led out by a metal trace above the shallow trench isolation between the active areas;

[0039] The storage unit is located on the contact plug, or in any layer of via;

[0040] Odd-numbered and even-numbered columns of storage units may be located in the same plane or in different planes.

[0041] Optionally, the first source line and the second source line comprise one or more layers of metal wires.

[0042] On the other hand, the present invention provides a method for operating a storage array, the method comprising:

[0043] When performing read / write operations on an odd-numbered column of memory cells in any row, the word lines adjacent to the selected odd-numbered column of memory cells are turned on, the first bit line and the first source line are connected to the control potential, the transistors corresponding to the remaining word lines are turned off, and the second bit line and the second source line remain floating; in other rows, the bit lines and source lines are all connected to 0, negative voltage, or floating, and the word lines are connected to 0.

[0044] When performing read / write operations on even-numbered columns of memory cells in any row, the word lines adjacent to the selected even-numbered column of memory cells are turned on, the second bit line and the second source line are connected to the control potential, the transistors corresponding to the remaining word lines are turned off, and the first bit line and the first source line remain floating; in other rows, the bit lines and source lines are all connected to 0, negative voltage, or floating, and the word lines are connected to 0.

[0045] The present invention provides a memory array and its interconnection structure and operation method. A memory cell and its two adjacent transistors constitute a basic operation unit. That is, adjacent memory cells can reuse each other's transistors. By reusing transistors, the array density of memory cells can be greatly increased while keeping the power supply capability of transistors unchanged, thus solving the problem of low transistor density in existing arrays using dual-finger structures. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of the circuit structure of a storage array according to an embodiment of the present invention;

[0047] Figure 2 This is a schematic diagram of the basic operating unit of a storage array according to an embodiment of the present invention;

[0048] Figure 3 This is a partial elevation view of the interconnect structure of a storage array according to an embodiment of the present invention;

[0049] Figure 4 This is a partial cross-sectional view of the interconnect structure of a storage array according to an embodiment of the present invention;

[0050] Figure 5 This is a partial cross-sectional view of the interconnect structure of a storage array according to an embodiment of the present invention;

[0051] Figure 6 This is a partial cross-sectional view of the interconnect structure of a storage array according to an embodiment of the present invention;

[0052] Figure 7 This is a partial cross-sectional view of the interconnect structure of a storage array according to an embodiment of the present invention;

[0053] Figure 8 This is a partial elevation view of the interconnect structure of a storage array according to an embodiment of the present invention;

[0054] Figure 9 This is a partial cross-sectional view of the interconnect structure of a storage array according to an embodiment of the present invention;

[0055] Figure 10 This is a partial cross-sectional view of the interconnect structure of a storage array according to an embodiment of the present invention;

[0056] Figure 11 This is a partial cross-sectional view of the interconnect structure of a storage array according to an embodiment of the present invention;

[0057] Figure 12 This is a partial cross-sectional view of the interconnect structure of a storage array according to an embodiment of the present invention;

[0058] Figure 13 This is a schematic diagram of a write 0 operation in an odd-numbered column storage unit according to an embodiment of the present invention;

[0059] Figure 14 This is a schematic diagram of a write-1 operation in an odd-numbered column storage unit according to an embodiment of the present invention;

[0060] Figure 15 This is a schematic diagram of a write 0 operation in an even-numbered column storage unit according to an embodiment of the present invention;

[0061] Figure 16 This is a schematic diagram of a write 1 operation in an even-numbered column storage unit according to an embodiment of the present invention. Detailed Implementation

[0062] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0063] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0064] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0065] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0066] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0067] One embodiment of the present invention provides a storage array, such as Figure 1 As shown, the storage array includes:

[0068] Multiple bit lines, with two bit lines set per row, including the first bit line and the second bit line;

[0069] Multiple source lines, with two source lines set in one row, including the first source line and the second source line;

[0070] Storage cells and transistors are located in each column and each row, with each transistor having a first source / drain and a second source / drain;

[0071] Each row of the storage array has the same structure, and for any row of the storage array, the following connection relationship exists:

[0072] One end of the odd-numbered column storage cell is connected to the first source line, and the other end is connected to the second source line;

[0073] The first source / drain of the odd-numbered array transistors is connected to the first source line;

[0074] The second source / drain of the odd-numbered column transistors is connected to the second source line;

[0075] One end of the even-numbered column storage unit is connected to the second bit line, and the other end is connected to the first source line;

[0076] The first source / drain of the even-numbered column transistors is connected to the second source line;

[0077] The second source / drain of the even-numbered column transistors is connected to the first source line.

[0078] Furthermore, the memory array also includes multiple word lines, with the gates of each column of transistors connected to the corresponding word lines.

[0079] In this embodiment, the storage array is arranged in rows horizontally and columns vertically. The horizontal rows BL and SL are connected to the row decoder; the vertical rows WL are connected to the column decoder.

[0080] It should be noted that the storage array of the present invention can be applied to various types of memory, and the type of storage unit can be any type of storage unit among MRAM, PCRAM, RRAM and FRAM.

[0081] The memory array provided in this embodiment of the invention comprises an odd-numbered column of memory cells in each row, an odd-numbered column of transistors in the same column, and an even-numbered column of transistors in the next column, forming a basic operation unit. The even-numbered column of memory cells in each row, an even-numbered column of transistors in the same column, and an odd-numbered column of transistors in the next column, forming a basic operation unit. The two basic operation units further constitute the minimum repeating unit of the memory array.

[0082] For example, such as Figure 2 As shown, storage cell A1 and transistors M1 and M2 constitute basic operation unit A1.1. WL1, WL2, BLA1, and SLA1 correspond to basic operation unit A1.1 and control the read and write operations of basic operation unit A1.1.

[0083] Similarly, storage cell A2 and transistors M3 and M4 constitute basic operation unit A1.2, and WL3, WL4, BLA1, and SLA1 correspond to basic operation unit A1.2, controlling the read and write operations of basic operation unit A1.2.

[0084] Storage cell B1 and transistors M2 and M3 constitute basic operation unit B1.1. WL2, WL3, BLB1, and SLB1 correspond to basic operation unit B1.1 and control the read and write operations of basic operation unit B1.1.

[0085] Storage cell B2 and transistors M4 and M5 constitute basic operation unit B1.2. WL4, WL5, BLB1, and SLB1 correspond to basic operation unit B1.2 and control the read and write operations of basic operation unit B1.2.

[0086] Basic operation units A1.1 and B1.1 constitute the smallest repeating unit, and basic operation units A1.2 and B1.2 constitute the smallest repeating unit. By extending the structure of the smallest repeating unit, the entire storage array can be obtained.

[0087] Extending to other lines, each word line (WL) can span multiple lines. For any given line:

[0088] The first line is connected to the other end of the odd-numbered column storage unit, denoted as BLAn;

[0089] The second bit line is connected to the other end of the even-numbered column storage unit, denoted as BLBn;

[0090] The first source line is connected to the first source / drain of the odd-numbered column transistors and the second source / drain of the even-numbered column transistors, denoted as SLAn;

[0091] The second source line is connected to the second source / drain of the odd-numbered column transistors and the first source / drain of the even-numbered column transistors, denoted as SLBn.

[0092] Any memory cell in BLAn, together with two adjacent WLs and SLAn, forms a basic operation unit; any memory cell in BLBn, together with two adjacent WLs and SLBn, forms a basic operation unit.

[0093] The present invention provides a memory array in which a memory cell and its two adjacent transistors constitute a basic operating unit. In other words, adjacent memory cells can reuse each other's transistors. By reusing transistors, the array density of memory cells can be greatly increased while keeping the power supply capability of transistors unchanged, thus solving the problem of low transistor density in existing arrays using dual-finger structures.

[0094] On the other hand, one embodiment of the present invention provides an interconnect structure for a storage array, the interconnect structure comprising:

[0095] Multiple active regions, each corresponding to a row of the memory array, are used to form the source / drain of transistors in a row;

[0096] Multiple word lines span each active region, each word line corresponding to a column of the memory array, and multiple word lines separate each active region;

[0097] The storage cells are located between multiple word lines. One end of the odd-numbered column storage cell is connected to the active area between the odd-numbered column word line and the next even-numbered column word line, and the other end of the even-numbered column storage cell is connected to the active area between the even-numbered column word line and the next odd-numbered column word line.

[0098] And, the first source line, the second source line, the first source line, and the second source line located in each active region.

[0099] The first line is connected to the other end of the odd-numbered column storage unit;

[0100] The second bit line is connected to the other end of the even-numbered column storage unit;

[0101] The first source line connects to the active region between the even-numbered column word line and the odd-numbered column word line of the next column;

[0102] The second source line connects to the active region between the odd-numbered column word line and the even-numbered column word line of the next column.

[0103] The above interconnection structure can be implemented in various ways, as illustrated below.

[0104] Interconnection Structure 1:

[0105] Figure 3 This diagram shows a partial schematic of the interconnect structure of a storage array according to an embodiment of the present invention. The interconnect structure represents the interconnect structure between the first two smallest repeating units in the first row of the storage array, i.e. Figure 2 The interconnection structure between the basic operating units A1.1, B1.1, A1.2 and B1.2 selected in the storage array.

[0106] refer to Figure 3 In the first row of active areas (AA), multiple word lines separate the active areas. The active area between odd-numbered word lines and the next even-numbered word lines is shared by odd-numbered transistors and the next even-numbered transistors to form the second source / drain of the odd-numbered transistors and the first source / drain of the even-numbered transistors. The active area between even-numbered word lines and the next odd-numbered word lines is shared by even-numbered transistors and the next odd-numbered transistors to form the second source / drain of the even-numbered transistors and the first source / drain of the odd-numbered transistors.

[0107] On the active area separated by the same word line, there are both the CT (contact) corresponding to the memory cell and the CT corresponding to the source line. One end of the memory cell is connected to the active area through the corresponding via (Via) and CT, and is separated by vertical WL lines. The other end of the odd-numbered column memory cells is connected to form the first bit line BLA1, and the other end of the even-numbered column memory cells is connected to form the second bit line BLB1. The first source line SLA1 is connected to the active area between the even-numbered column word line and the next odd-numbered column word line, and the second source line SLB1 is connected to the active area between the odd-numbered column word line and the next even-numbered column word line.

[0108] Extending to other active regions, each word line can span multiple active regions, separated by shallow trench isolation (STI). For example, for any active region AAn:

[0109] The first line is connected to the other end of the odd-numbered column storage unit, denoted as BLAn;

[0110] The second bit line is connected to the other end of the even-numbered column storage unit, denoted as BLBn;

[0111] The first source line is connected to the active region between the even-numbered column word line and the next odd-numbered column word line via VIA and CT, and is denoted as SLAn;

[0112] The second source line is connected to the active region between the odd-numbered column word line and the even-numbered column word line of the next column via VIA and CT, and is denoted as SLBn.

[0113] Any memory cell in BLAn, together with two adjacent WLs and SLAn, forms a basic operation unit; any memory cell in BLBn, together with two adjacent WLs and SLBn, forms a basic operation unit.

[0114] In this interconnection structure, the first bit line, second bit line, first source line and second source line of each active area are all located above each active area, arranged in parallel along the extension direction of the word line, and there is no overlapping area in the vertical direction.

[0115] As one implementation method, Figure 4 It shows Figure 3 The diagram shows a cross-sectional view of any two adjacent active regions AAn-1 and AAn in the interconnect structure. (Reference) Figure 4 , Figure 4 (a) is a cross-sectional view of the storage cell in the 4th column along the WL extension direction. Figure 4 (b) is a cross-sectional view of the memory cell in the third column along the WL extension direction. On an active region, contacts (CTs, generally referring to the metal connection between the active region and metal layer M1) are staggered, with memory cells integrated in vias (Vias, generally referring to the metal connection between different metal layers; for example, the metal connection between metal layers M1 and M2 can be denoted as Via1, the metal connection between metal layers M2 and M3 as Via2, and so on). The memory cell can be located in Via1 or other Via layers. Metal connections on Vias with memory cells correspond to BLs, and metal connections on CTs without memory cells correspond to SLs. SLs are located in the edge region of AAs, and BLs are located in the middle region of AAs. SLs can consist of a single metal layer M1 / M2 or a combination of M1 and M2. In this embodiment, SLs are led out by metal lines from layer M1, and BLs are led out by metal lines from layer M2.

[0116] It should be noted that interconnect structure 1 can also be implemented in other ways. For example, the relative positions of the source lines and bit lines can be changed. The first source line and the second source line can be located at the edge region of each active region; or, the first source line and the second source line can be located in the middle region of each active region; or, one of the first source line and the second source line can be located in the middle region of each active region, and the other can be located at the edge region of each active region. For example, the position of the memory cell can also be changed. The memory cell is formed above the active regions separated by word lines in each active region. It can be located on a contact plug and connected to the active region through the contact plug corresponding to the memory cell, or it can be located in any layer of vias and connected to the active region through the vias corresponding to the memory cell and the contact plugs. For example, the first source line and the second source line can contain one or more layers of metal lines. BL and SL can be led out from the same layer of metal lines or from different layers of metal lines.

[0117] Figures 5 to 7 Several variations of interconnect structure 1 are presented.

[0118] As one implementation method, refer to Figure 5 , Figure 5 (a) is a cross-sectional view of the storage cell in the 4th column along the WL extension direction. Figure 5 (b) is a cross-sectional view of the memory cells in the third column along the WL extension direction. On an active region, CTs are staggered, with memory cells integrated in the Via. The CTs with memory cells and the metal interconnects on the Via correspond to BL, while the metal interconnects on the CTs without memory cells correspond to SL. Compared to... Figure 4 The difference is that BL is located in the edge region of AA, while SL is located in the middle region of AA.

[0119] As one implementation method, refer to Figure 6 , Figure 6 (a) is a cross-sectional view of the storage cell in the 4th column along the WL extension direction. Figure 6 (b) is a cross-sectional view of the memory cells in the third column along the WL extension direction. On an active region, staggered CTs extend from each other, where memory cells are integrated on the CTs. The metal interconnects on the CTs with memory cells and on the Via correspond to BL, while the metal interconnects on the CTs without memory cells correspond to SL. Compared to Figure 4 The difference lies in the location of the storage units.

[0120] As one implementation method, refer to Figure 7 , Figure 7 (a) is a cross-sectional view of the storage cell in the 4th column along the WL extension direction. Figure 7 (b) is a cross-sectional view of the storage cell in the third column along the WL extension direction. Compared to Figure 4 , Figure 7The positions of BL and SL were adjusted, as were the positions of the storage units.

[0121] The interconnect structure of the memory array provided in this embodiment of the invention has CTs corresponding to memory cells and source lines on active regions spaced apart in the same WL (Wide Line Layer). The bit lines and source lines in each row are divided into two groups based on odd and even columns, allowing for separate operation. This embodiment of the invention can increase the memory cell density in the BL (Browser Layer) direction while ensuring no reduction in power supply capability. It significantly reduces the area per unit memory cell while maintaining the same back-end metal interconnect process nodes, exhibiting strong compatibility.

[0122] Interconnection Structure 2:

[0123] Figure 8 This diagram shows a partial schematic of the interconnect structure of a storage array according to an embodiment of the present invention. The interconnect structure represents the interconnect structure between the first two smallest repeating units in the first row of the storage array, i.e. Figure 2 The interconnection structure between the basic operating units A1.1, B1.1, A1.2 and B1.2 selected in the storage array.

[0124] refer to Figure 8 In the active region of the first row, multiple word lines separate the active regions. The active region between the odd-numbered word lines and the even-numbered word lines of the following column is shared by the odd-numbered transistors and the even-numbered transistors of the following column, forming the second source / drain of the odd-numbered transistors and the first source / drain of the even-numbered transistors. The active region between the even-numbered word lines and the odd-numbered word lines of the following column is shared by the even-numbered transistors and the odd-numbered transistors of the following column, forming the second source / drain of the even-numbered transistors and the first source / drain of the odd-numbered transistors.

[0125] On the active area separated by the same word line, there are both the CT (contact) corresponding to the memory cell and the CT corresponding to the source line. One end of the memory cell is connected to the active area through the corresponding via (Via) and CT, and is separated by vertical WL lines. The other end of the odd-numbered column memory cells is connected to form the first bit line BLA1, and the other end of the even-numbered column memory cells is connected to form the second bit line BLB1. The first source line SLA1 is connected to the active area between the even-numbered column word line and the next odd-numbered column word line, and the second source line SLB1 is connected to the active area between the odd-numbered column word line and the next even-numbered column word line.

[0126] In this interconnection structure, the first bit line and the first source line of each active region are arranged vertically, with overlapping areas in the vertical direction; the second bit line and the second source line are arranged vertically, with overlapping areas in the vertical direction.

[0127] As one implementation method, Figure 9 It shows Figure 8The diagram shows a cross-sectional view of any two adjacent active regions AAn-1 and AAn in the interconnect structure. (Reference) Figure 9 , Figure 9 (a) is a cross-sectional view of the storage cell in the 4th column along the WL extension direction. Figure 9 (b) is a cross-sectional view of the memory cell in the third column along the WL extension direction. The metal interconnects of the memory cells are staggered above the STI, and the memory cells are located in the Via above the STI; the metal traces leading from AA to STI can be any metal layer or the top or bottom electrode layer of the memory cell.

[0128] Specifically, on an active region, there are two rows of CTs. The odd-numbered CTs on the left side along the BL direction are directly connected to M1 and then vertically connected to V1; the even-numbered CTs on the right side along the BL direction are directly connected to M1 and then vertically connected to V1.

[0129] Correspondingly, the odd-numbered CTs along the BL direction on the right side are led out to the right onto the STI in layer M1; the even-numbered CTs along the BL direction on the left side are led out to the left onto the STI in layer M1; thus forming an alternating structure on the STI.

[0130] Subsequently, V1, which is vertically led out, is connected to M2 layer to form SL; M1, which is laterally led out to STI, is connected to V1 above STI, and connected to M2 on V1. M2 is connected upward to V2 and the memory cell, and the memory cell is connected upward to M3; M3 is laterally led out to AA above, forming two BL.

[0131] It should be noted that interconnect structure 2 can also be implemented in other ways. For example, the memory cell can be above AA, or it can be led out to above STI by a metal trace; the memory cell can be located on CT, or in any layer of via; odd-numbered and even-numbered memory cells do not need to be on the same plane, and the trace led out to above STI from above AA can be a metal layer, the top electrode of the memory cell, or the bottom electrode layer of the memory cell. For example, the first source line and the second source line can contain one or more layers of metal lines. BL and SL can be led out from the same layer of metal lines, or they can be led out from different layers of metal lines.

[0132] Figures 10 to 12 Several variations of interconnect structure 2 are presented.

[0133] As one implementation method, refer to Figure 10 , Figure 10 (a) is a cross-sectional view of the storage cell in the 4th column along the WL extension direction. Figure 10(b) is a cross-sectional view of the memory cell in the 3rd column along the WL extension direction. The metal interconnects of the memory cells are staggered on the STI, and the memory cells are located in the Via above the STI; even-numbered and odd-numbered columns of memory cells are not on the same plane; the metal traces extending from AA towards the STI can be any metal layer or the top or bottom electrode layer of the memory cell. Compared to Figure 9 The difference is that the corresponding storage units on the two BLs are located between M1 and M2 and between M2 and M3, respectively.

[0134] As one implementation method, refer to Figure 11 , Figure 11 (a) is a cross-sectional view of the storage cell in the 4th column along the WL extension direction. Figure 11 (b) is a cross-sectional view of the memory cell in the 3rd column along the WL extension direction. The memory cell is located in the CT or Via directly above AA (if located in Via, the memory cell is not led out to the STI with the trace); the metal traces of the memory cell are staggered on the STI; the metal traces leading from AA to STI can be any metal layer or the top or bottom electrode layer of the memory cell. Compared to Figure 9 The difference is that the storage unit is directly integrated on the CT and is not brought out to the STI.

[0135] As one implementation method, refer to Figure 12 , Figure 12 (a) is a cross-sectional view of the storage cell in the 4th column along the WL extension direction. Figure 12 (b) is a cross-sectional view of the memory cell in the 3rd column along the WL extension direction. The metal interconnects corresponding to SL are staggered on STI; the memory cell is located in CT or Via above AA. Compared to Figure 9 The difference is that the metal traces leading out to STI correspond to SL; therefore, the SL metal layer is ultimately above the BL metal layer.

[0136] The interconnect structure of the memory array provided in this embodiment of the invention utilizes shallow trench isolation between active regions to achieve metal interconnection. The traces connecting the memory cells are staggered on the STI between AA regions, or the metal traces corresponding to the source lines are staggered on the STI between AA regions, thereby reducing the size in the WL direction and achieving the purpose of increasing the array density.

[0137] It is understood that the interconnection structure 1 and interconnection structure 2 of the storage array provided in the embodiments of the present invention are applicable to the storage array provided in the foregoing embodiments and are a specific physical implementation of the storage array.

[0138] On the other hand, embodiments of the present invention provide an operation method for a storage array, applicable to the storage arrays provided in the foregoing embodiments, the operation method comprising:

[0139] When performing read / write operations on an odd-numbered column of memory cells in any row, the word lines adjacent to the selected odd-numbered column of memory cells are turned on, the first bit line and the first source line are connected to the control potential, the transistors corresponding to the remaining word lines are turned off, and the second bit line and the second source line remain floating; in other rows, the bit lines and source lines are all connected to 0, negative voltage, or floating, and the word lines are connected to 0.

[0140] When performing read / write operations on even-numbered columns of memory cells in any row, the word lines adjacent to the selected even-numbered column of memory cells are turned on, the second bit line and the second source line are connected to the control potential, the transistors corresponding to the remaining word lines are turned off, and the first bit line and the first source line remain floating; in other rows, the bit lines and source lines are all connected to 0, negative voltage, or floating, and the word lines are connected to 0.

[0141] Taking the odd-numbered column storage unit A2 as an example, the read and write operations will be explained.

[0142] Write 0 operation: such as Figure 13 As shown, BLA1 is connected to a high potential, SLA1 is connected to a low potential, the corresponding transistors WL3 and WL4 are turned on, BLB1 and SLB1 are floating, and the current flows from BLA1 through the memory cell A2 to SLA1. The remaining BL and SL are connected to 0 or negative voltage or floating, and the remaining WL are connected to 0.

[0143] Write 1 operation: such as Figure 14 As shown, BLA1 is connected to a low potential, SLA1 is connected to a high potential, the corresponding transistors WL3 and WL4 are turned on, BLB1 and SLB1 are floating, and the current flows from SLA1 through the memory cell A2 to BLA1. The remaining BL and SL are connected to 0 or negative voltage or floating, and the remaining WL are connected to 0.

[0144] Read operation: The specific operation circuit is the same as the write 0 operation circuit, which can be referred to. Figure 13 BLA1 is connected to a low potential, SLA1 is connected to a low potential, the corresponding transistors WL3 and WL4 are turned on, BLB1 and SLB1 are floating, and the current flows from BLA1 through the memory cell A2 to SLA1. The remaining BL and SL are connected to 0, negative voltage, or floating, and the remaining WL are connected to 0.

[0145] Taking even-numbered column storage unit B1 as an example, the read and write operations are explained.

[0146] Write 0 operation: such as Figure 15 As shown, BLB1 is connected to a high potential, SLB1 is connected to a low potential, the transistors corresponding to WL2 and WL3 are turned on, BLA1 and SLA1 are floating, and the current flows from BLB1 through the memory cell B1 to SLB1. The remaining BL and SL are connected to 0 or negative voltage or floating, and the remaining WL are connected to 0.

[0147] Write 1 operation: such as Figure 16 As shown, BLB1 is connected to a low potential, SLB1 is connected to a high potential, the transistors corresponding to WL2 and WL3 are turned on, BLA1 and SLA1 are floating, and the current flows from SLB1 through the memory cell B1 to BLB1. The remaining BL and SL are connected to 0 or negative voltage or floating, and the remaining WL are connected to 0.

[0148] Read operation: The specific operation circuit is the same as the write 0 operation circuit, which can be referred to. Figure 15 BLB1 is connected to a low potential, SLB1 is connected to a low potential, the corresponding transistors WL2 and WL3 are turned on, BLA1 and SLA1 are floating, and the current flows from BLB1 through the memory cell B1 to SLB1. The remaining BL and SL are connected to 0 or negative voltage or floating, and the remaining WL are connected to 0.

[0149] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A storage array, characterized in that, The storage array includes: Multiple bit lines, with two bit lines set per row, including the first bit line and the second bit line; Multiple source lines, with two source lines set in one row, including the first source line and the second source line; Storage cells and transistors are located in each column and each row, with each transistor having a source and a drain; For any row of the storage array, the following connection relationship exists: One end of the odd-numbered column storage cell is connected to the first bit line, and the other end is connected to the second source line; One end of the even-numbered column storage unit is connected to the second bit line, and the other end is connected to the first source line; The source of the odd-numbered transistor is connected to the first source line, the drain of the odd-numbered transistor is connected to the second source line, the source of the even-numbered transistor is connected to the second source line, and the drain of the even-numbered transistor is connected to the first source line; or, the drain of the odd-numbered transistor is connected to the first source line, the source of the odd-numbered transistor is connected to the second source line, the drain of the even-numbered transistor is connected to the second source line, and the source of the even-numbered transistor is connected to the first source line.

2. The storage array according to claim 1, characterized in that, The memory array further includes multiple word lines, with the gates of each column of transistors connected to the corresponding word lines.

3. The storage array according to claim 1, characterized in that, The storage unit is any one of the following types of storage units: MRAM, PCRAM, RRAM, and FRAM.

4. A storage array with an interconnect structure, characterized in that, The storage array includes: Multiple active regions, each of which corresponds to a row of the memory array, are used to form the source / drain of transistors in a row; Multiple word lines spanning each of the active regions, each word line corresponding to a column of the memory array, the multiple word lines separating each of the active regions; The storage cells are located between multiple word lines. One end of the odd-numbered column storage cell is connected to the active area between the odd-numbered column word line and the next even-numbered column word line, and one end of the even-numbered column storage cell is connected to the active area between the even-numbered column word line and the next odd-numbered column word line. And, the first bit line, the second bit line, the first source line, and the second source line located in each of the aforementioned active regions, The first bit line is connected to the other end of the odd-numbered column storage cell; The second bit line is connected to the other end of the even-numbered column storage cell; The first source line is connected to the active region between the even-numbered column word line and the odd-numbered column word line of the next column; The second source line is connected to the active region between the odd-numbered column word line and the even-numbered column word line of the next column.

5. The storage array with an interconnect structure according to claim 4, characterized in that, The first bit line, the second bit line, the first source line, and the second source line are all located above each active region, arranged in parallel along the word line extension direction, and there is no overlapping area in the vertical direction.

6. The storage array with an interconnect structure according to claim 5, characterized in that, The first source line and the second source line are located in the edge region of each of the active regions; Alternatively, the first source line and the second source line are located in the middle region of each of the active regions; Alternatively, one of the first source line and the second source line may be located in the middle region of each active region, and the other may be located in the edge region of each active region.

7. The storage array with an interconnect structure according to claim 5, characterized in that, The storage unit is located above the active area; The storage unit is located on the contact plug or in any layer of via.

8. The storage array with an interconnect structure according to claim 5, characterized in that, The first source line and the second source line comprise one or more layers of metal wires.

9. The storage array with an interconnect structure according to claim 4, characterized in that, The first bit line and the first source line are arranged vertically and overlap in the vertical direction; the second bit line and the second source line are arranged vertically and overlap in the vertical direction.

10. The storage array with an interconnect structure according to claim 9, characterized in that, The first bit line is located above the first source line, and is led out above the shallow trench isolation between the active regions via staggered metal traces. The second bit line is located above the second source line, and is led out above the shallow trench isolation between the active regions via staggered metal traces. Alternatively, the first source line is located above the first bit line, and the first source line is led out above the shallow trench isolation between the active areas through interleaved metal traces. The second source line is located above the second bit line, and the second source line is led out above the shallow trench isolation between the active areas through interleaved metal traces.

11. The storage array with an interconnect structure according to claim 9, characterized in that, The storage unit is located above the active area, or is led out by a metal trace above the shallow trench isolation between the active areas; The storage unit is located on the contact plug, or in any layer of via; Odd-numbered and even-numbered columns of storage units may be located in the same plane or in different planes.

12. The storage array with an interconnect structure according to claim 9, characterized in that, The first source line and the second source line comprise one or more layers of metal wires.

13. A method for operating a storage array, applicable to the storage array as described in claim 1, characterized in that, The method includes: When performing read / write operations on an odd-numbered column of memory cells in any row, the word lines adjacent to the selected odd-numbered column of memory cells are turned on, the first bit line and the first source line are connected to the control potential, the transistors corresponding to the remaining word lines are turned off, and the second bit line and the second source line remain floating; in other rows, the bit lines and source lines are all connected to 0, negative voltage, or floating, and the word lines are connected to 0. When performing read / write operations on even-numbered columns of memory cells in any row, the word lines adjacent to the selected even-numbered column of memory cells are turned on, the second bit line and the second source line are connected to the control potential, the transistors corresponding to the remaining word lines are turned off, and the first bit line and the first source line remain floating; in other rows, the bit lines and source lines are all connected to 0, negative voltage, or floating, and the word lines are connected to 0.

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