Voltage generation circuit and memory

Abstract

The embodiment of the present disclosure relates to the field of semiconductor circuit design, and provides a voltage generation circuit and a memory, wherein the voltage generation circuit comprises: a voltage output module configured to receive a reference voltage, generate a first output voltage and provide the first output voltage to a power supply node, and the power supply node is used to be connected with a load to supply power to the load; a voltage stabilizing module configured to receive the reference voltage, generate and output a control signal; and a compensation module configured to receive a power supply voltage, a flag signal and the control signal, turn on in response to the flag signal, and provide a second output voltage to the power supply node in response to a voltage value based on the control signal, so that the voltage of the power supply node is restored to the first output voltage, and the accuracy of the voltage generation circuit can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor circuit design, and in particular to a voltage generation circuit and a memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is widely used in modern electronic systems due to its high storage density and fast transfer speed. With the development of semiconductor technology, DRAM technology is becoming more and more advanced, and the integration of memory cells is becoming higher and higher; at the same time, various applications are placing increasingly higher demands on the performance, power consumption, and reliability of DRAM.

[0003] As the integration of memory cells becomes increasingly sophisticated, the control circuit corresponding to each memory cell needs to connect more components to achieve individual control of the memory cells. However, as the memory cells are turned on, the control circuit will generate voltage fluctuations, resulting in insufficient accuracy of the voltage supplied to the memory cells. Therefore, it is necessary to provide a voltage generation circuit to improve the accuracy of the voltage generation circuit. Summary of the Invention

[0004] This disclosure provides a voltage generation circuit and a memory, which can at least improve the accuracy of the voltage generation circuit.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a voltage generation circuit, including: a voltage output module configured to receive a reference voltage, generate a first output voltage, and provide the first output voltage to a power supply node, wherein the power supply node is configured to be connected to a load to supply power to the load; a voltage regulation module configured to receive the reference voltage, generate and output a control signal; and a compensation module configured to receive a power supply voltage, a flag signal, and the control signal, and to conduct in response to the flag signal and to provide a second output voltage to the power supply node based on the voltage value of the control signal, so that the voltage of the power supply node is restored to the first output voltage, wherein the flag signal indicates that the load is in operation.

[0006] In some embodiments, the compensation module includes: a switching unit for receiving the flag signal and outputting the power supply voltage based on the flag signal; and an adjustment unit connected to the switching unit for receiving the power supply voltage and the control signal to adjust the output amplitude of the compensation module based on the voltage value of the control signal.

[0007] In some embodiments, the switching unit includes: a first PMOS transistor, the gate of which receives the flag signal, and the source of which is connected to a power supply; the regulating unit includes: a first NMOS transistor, the gate of which receives the control signal, the drain of which is connected to the drain of the first PMOS transistor, and the source of which is connected to the power supply node to provide the second output voltage.

[0008] In some embodiments, the voltage regulator module includes: a first operational amplifier, the non-inverting input of the first operational amplifier receiving the reference voltage, and the output of the first operational amplifier outputting the control signal; a first resistor, one end of the first resistor being grounded, and the other end being connected to the inverting input of the first operational amplifier; a second PMOS transistor, the source of the second PMOS transistor being connected to the power supply voltage; a second NMOS transistor, the gate of the second NMOS transistor being connected to the output of the first operational amplifier, and the drain of the second NMOS transistor being connected to the drain of the second PMOS transistor; and a second resistor, one end of the second resistor being connected to the inverting input of the first operational amplifier, and the other end being connected to the source of the second NMOS transistor.

[0009] In some embodiments, the aspect ratio of the first NMOS channel is equal to that of the second NMOS channel.

[0010] In some embodiments, the voltage generation circuit further includes: a first voltage generation module, which receives the reference voltage and generates a driving voltage for driving the first operational amplifier.

[0011] In some embodiments, the driving voltage is greater than the sum of the voltage value corresponding to the control signal and the turn-on voltage of the second NMOS transistor.

[0012] In some embodiments, the system further includes a flag signal generation module configured to generate the flag signal based on an enable signal, the enable signal being used to control the operation of the load.

[0013] In some embodiments, the voltage output module includes: a second operational amplifier, the inverting input of which receives the reference voltage; a third resistor, one end of which is grounded and the other end of which is connected to the non-inverting input of the second operational amplifier; a third PMOS transistor, the gate of which is connected to the output of the second operational amplifier, the source of which is connected to the operating power supply, and the drain of which outputs the first output voltage; and a fourth resistor, one end of which is connected to the non-inverting input of the second operational amplifier and the other end of which is connected to the drain of the third PMOS transistor.

[0014] In some embodiments, the voltage of the operating power supply connected to the source of the third PMOS transistor is equal to the voltage of the drive voltage of the second operational amplifier.

[0015] In some embodiments, the system further includes a second voltage generation module, which is used to provide the reference voltage.

[0016] In some embodiments, the system further includes a capacitor, one end of which is connected to the output terminal of the voltage output module, and the other end is grounded.

[0017] According to some embodiments of this disclosure, another aspect of this disclosure also provides a memory, including: the voltage generation circuit described above; a load connected to the power supply node, the load operating in response to an enable signal.

[0018] In some embodiments, the number of loads is multiple, and different loads operate in response to different enable signals; the voltage generation circuit has multiple power supply nodes, and each power supply node is connected to a load; the voltage generation circuit includes multiple compensation modules, and each compensation module provides the second output voltage to a corresponding power supply node in response to a corresponding flag signal.

[0019] The technical solution provided by the embodiments of this disclosure has at least the following advantages: a first output voltage is provided to the power supply node through the voltage output module, thereby supplying power to the load; a control signal can be output through the voltage regulation module; the power supply voltage, the flag signal and the control signal are received through the compensation module, and the module is turned on in response to the flag signal, and a second output voltage is provided to the power supply node in response to the voltage value based on the control signal, so that the voltage of the power supply node is restored to the first output voltage, thereby improving the accuracy of the voltage generation circuit. Attached Figure Description

[0020] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the structure of a voltage generation circuit provided in one embodiment of the present disclosure;

[0022] Figure 2This is a schematic diagram of a voltage generation circuit provided in another embodiment of the present disclosure;

[0023] Figure 3 A schematic diagram of the specific structure of a voltage generation circuit provided in another embodiment of this disclosure;

[0024] Figure 4 A schematic diagram of the specific structure of a voltage output module provided in another embodiment of this disclosure;

[0025] Figure 5 This is a schematic diagram of the structure of a flag signal generation module provided in another embodiment of the present disclosure;

[0026] Figure 6 A signal fluctuation diagram is provided for another embodiment of this disclosure. Detailed Implementation

[0027] As can be seen from the background technology, reference Figure 1 , Figure 1 The circuit provided is a voltage generation circuit provided in the prior art. The voltage generation circuit provided in the prior art includes: a bandgap reference voltage generation module 100 and a reference voltage generation module 110 to provide a reference voltage; multiple voltage regulator circuit modules 120, and a load module 130 connected to each voltage regulator circuit module 120 in a one-to-one correspondence. The multiple voltage regulator circuit modules 120 include: an operational amplifier 140, the inverting input terminal of which receives the reference voltage; a fifth resistor 150, one end of which is grounded and the other end is connected to the non-inverting input terminal of the operational amplifier 140; a PMOS transistor 160, the gate of which is connected to the output terminal of the operational amplifier 140, and the source of which is connected to the operating power supply; and a sixth resistor 170, one end of which is connected to the non-inverting input terminal of the operational amplifier 140 and the other end of which is connected to the drain of the PMOS transistor 160. The voltage regulator circuit modules 120 can provide an output voltage to the load module 130, thereby controlling the conduction of the load module 130.

[0028] In summary, the bandgap reference voltage generation module 100 generates a bandgap reference voltage and outputs it to the reference voltage generation module 110. The reference voltage generation module 110 receives the generated bandgap reference voltage and outputs a reference voltage. The voltage regulation circuit module 120 receives the reference voltage and outputs the target output voltage to the load module 130.

[0029] However, when the load module 130 is turned on, the load module 130 consumes a portion of the output voltage, which reduces the output voltage provided by the connection node between the load module 130 and the voltage regulator module 120. This results in the voltage supplied to the load module 130 being lower than the preset value, which in turn may cause some components of the load module 130 to malfunction.

[0030] This disclosure provides a voltage generation circuit and a memory. The circuit receives a reference voltage through a voltage output module and provides a first output voltage to a power supply node, and supplies power to a load through the power supply node. The circuit outputs a control signal to a compensation module through a voltage regulation module, and the compensation module provides a second output voltage to the power supply node by receiving the power supply voltage, a flag signal, and a control signal, so that the voltage of the power supply node is restored to the first output voltage. This ensures that when the load is working, the voltage provided by the power supply node to the load is stable at the first output voltage, thereby improving the accuracy of the voltage generation circuit.

[0031] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0032] refer to Figures 2 to 6 ,in Figure 2 This is a schematic diagram of a circuit structure provided in an embodiment of the present disclosure. Figure 3 This is a schematic diagram illustrating the specific structure of a voltage regulator module, a compensation module, and a second voltage generation module provided in an embodiment of this disclosure. Figure 4 This is a schematic diagram of the specific structure of the voltage output module provided in an embodiment of this disclosure. Figure 5 This is a schematic diagram of the structure of the flag signal generation module provided in an embodiment of this disclosure. Figure 6 A signal fluctuation diagram and voltage generation circuit provided in this disclosure embodiment include:

[0033] The voltage output module 200 is configured to receive a reference voltage Vref, generate a first output voltage Vout1 and provide the first output voltage Vout1 to a power supply node, wherein the power supply node is used to connect to a load to supply power to the load.

[0034] The voltage regulator module 210 is configured to receive a reference voltage Vref and generate and output a control signal Vctrl.

[0035] The compensation module 220 is configured to receive a power supply voltage VPwr, a flag signal Reg, and a control signal Vctrl, and in response to the flag signal Reg being turned on, and in response to the voltage value of the control signal Vctrl, to provide a second output voltage Vout2 to the power supply node so that the voltage of the power supply node is restored to the first output voltage Vout1, wherein the flag signal Reg indicates that the load is in operation.

[0036] Specifically, when the load is in operation, it receives the first output voltage Vout1 from the voltage output module 200 and turns on. As the load turns on, the first output voltage Vout1 of the power supply node is consumed, causing the voltage value of the first output voltage Vout1 of the power supply node to drop. At the same time, the voltage regulator module 210 operates and receives the reference voltage Vref to provide a control signal Vctrl to the compensation module 220. The compensation module 220 receives the power supply voltage VPwr, the flag signal Reg, and the control signal Vctrl, and turns on in response to the flag signal Reg. It also generates and outputs the second output voltage Vout2 according to the voltage value of the control signal Vctrl. The power supply node receives the second output voltage Vout2 from the compensation module to compensate for the first output voltage Vout1 consumed by the load, so that the voltage provided by the power supply node to the load is stable at the first output voltage Vout1. This prevents the voltage signal received by the load from fluctuating due to its own turn-on, and also makes the voltage provided by the voltage generation circuit to the load stable at the first output voltage Vout1, thereby improving the accuracy of the voltage generation circuit.

[0037] It should be noted that in the above embodiments, the compensation module 220 responds to the flag signal being turned on. The flag signal Reg can be generated based on the enable signal En. In other embodiments, the compensation module 220 can also be set to be turned on directly based on the enable signal En.

[0038] In some embodiments, the compensation module 220 may include: a switching unit 221 for receiving a flag signal Reg and outputting a power supply voltage VPwr based on the flag signal Reg; and an adjustment unit 222 connected to the switching unit 221 for receiving the power supply voltage VPwr and a control signal Vctrl, and adjusting the output amplitude of the compensation module 220 based on the voltage value of the control signal Vctrl. The switching unit 221 can control whether the compensation module 220 is working. That is, when the load is working, the switching unit 221 receives the flag signal Reg and outputs the power supply voltage VPwr to the adjustment unit 222. The adjustment unit 222 can always be in a ready-to-turn state. When it receives the power supply voltage VPwr provided by the adjustment unit 222, it turns on and adjusts the output amplitude of the compensation module 220 according to the voltage value of the control signal Vctrl, thereby providing a second output voltage Vout2 to the power supply node, thus restoring the voltage value of the power supply node to the first output voltage Vout1, thereby improving the accuracy of the voltage value provided by the voltage generation circuit.

[0039] In some embodiments, the switching unit 221 may include: a first PMOS transistor 223, the gate of the first PMOS transistor 223 receiving a flag signal Reg, and the source of the first PMOS transistor 223 being connected to a power supply; the regulating unit 222 includes: a first NMOS transistor 224, the gate of the first NMOS transistor 224 receiving a control signal Vctrl, the drain of the first NMOS transistor 224 being connected to the drain of the first PMOS transistor 223, and the source of the first NMOS transistor 224 being connected to a power supply node to provide a second output voltage Vout2.

[0040] Understandably, the operating power supply can be used to provide the power supply voltage VPwr. The flag signal Reg can include two states, one of which is a high level state and the other is a low level state. When the flag signal Reg received by the gate of the first PMOS transistor 223 is in a low level state, the first PMOS transistor 223 is turned on and provides the power supply voltage VPwr to the drain of the first NMOS transistor 224. When the drain of the first NMOS transistor 224 receives the power supply voltage VPwr and the gate receives the control signal Vctrl, the first NMOS transistor 224 is turned on and provides the second output voltage Vout2 to the power supply node through the source, thereby restoring the voltage value of the power supply node to the first output voltage Vout1, which can improve the accuracy of the voltage value provided by the voltage generation circuit.

[0041] In some embodiments, the voltage generation circuit may include a plurality of compensation modules 220 and a plurality of power supply nodes, and each compensation module 220 is connected to a power supply node. The second output voltage Vout2 is provided to different loads 280 through the plurality of power supply nodes, so that each load 280 has a corresponding compensation module 220. The layout area of ​​the voltage generation circuit can be reduced by connecting the plurality of compensation modules 220 in parallel, and the voltage generation circuit has a faster response speed.

[0042] In some embodiments, the voltage regulator module 210 may include: a first operational amplifier 211, the non-inverting input terminal of the first operational amplifier 211 receiving a reference voltage Vref, and the output terminal of the first operational amplifier 211 outputting a control signal Vctrl; a first resistor 212, one end of the first resistor 212 being grounded, and the other end being connected to the inverting input terminal of the first operational amplifier 211; a second PMOS transistor 213, the source of the second PMOS transistor 213 being connected to the power supply voltage VPwr; a second NMOS transistor 214, the gate of the second NMOS transistor 214 being connected to the output terminal of the first operational amplifier 211, and the drain of the second NMOS transistor 214 being connected to the drain of the second PMOS transistor 213; and a second resistor 215, one end of the second resistor 215 being connected to the inverting input terminal of the first operational amplifier 211, and the other end being connected to the source of the second NMOS transistor 214.

[0043] Specifically, the voltage regulation principle of the voltage regulator module 210 is as follows: when the output voltage decreases, the voltage supplied to the inverting input terminal of the first operational amplifier 211 decreases due to the voltage division effect of the first resistor 212 and the second resistor 215. However, the reference voltage Vref connected to the non-inverting input terminal of the first operational amplifier 211 is stable. Therefore, the output voltage of the first operational amplifier 211 increases accordingly, the gate voltage of the second NMOS transistor 214 increases, and the output voltage of the voltage regulator module 210 increases accordingly, suppressing the decrease in output voltage and thus maintaining a stable output.

[0044] In this embodiment, the source of the second PMOS transistor 213 is connected to the power supply voltage VPwr, and the gate can be grounded. Therefore, the second PMOS transistor 213 is always on, and the power supply voltage VPwr is supplied from the drain of the second PMOS transistor 213 to the drain of the second NMOS transistor. The gate of the second NMOS transistor 214 is connected to the output terminal of the first operational amplifier 211. When a reference voltage Vref is supplied to the first operational amplifier 211, the second NMOS transistor 214 is turned on, and the entire voltage regulator module 210 starts to work.

[0045] It is understandable that the output voltage of the voltage regulator module 210 can be the third output voltage Vout3. The voltage value of the third output voltage Vout3 can be Vout3 = Vref * (R1 + R2) / R1, where Vref represents the voltage value of the reference voltage Vref, R1 represents the resistance value of the first resistor 212, R2 represents the resistance value of the second resistor 215, * represents multiplication in mathematics, and / represents division in mathematics.

[0046] The control signal Vctrl provided by the voltage regulator module 210 is connected to the gate of the second NMOS transistor 214. Therefore, the voltage value of the control signal Vctrl is Vctrl = Vout3 + Vth, where Vout3 represents the voltage value of the third output voltage that the voltage regulator module 210 can provide, and Vth represents the threshold voltage of the second NMOS transistor 214.

[0047] In some embodiments, the aspect ratio of the channel of the first NMOS transistor 224 is equal to that of the channel of the second NMOS transistor 214. This means that the threshold voltage of the first NMOS transistor 224 is equal to that of the second NMOS transistor 214. In other words, when the gate of the first NMOS transistor 224 receives the control signal Vctrl provided by the voltage regulator module 210, the voltage output from the source of the first NMOS transistor 224 is Vctrl minus the threshold voltage of the first NMOS transistor 224, which is equal to the threshold voltage of the third NMOS transistor 214. The voltage value of the output voltage Vout3 means that the voltage value of the second output voltage Vout2 is equal to the voltage value of the third output voltage Vout3. However, the voltage value of the third output voltage Vout3 is equal to the voltage value of the first output voltage Vout1. In other words, by controlling the width-to-length ratio of the channel of the first NMOS transistor 224 to be equal to the width-to-length ratio of the channel of the second NMOS transistor 214, the voltage value of the second output voltage Vout2 can be controlled to be equal to the voltage value of the first output voltage Vout1. This can improve the accuracy of the voltage generation circuit and make the voltage value provided by the voltage generation circuit to the power supply node stable at the first output voltage Vout1.

[0048] It should be noted that the statement that the width-to-length ratio of the first NMOS transistor 224 channel is equal to that of the second NMOS transistor 214 channel refers to an ideal equality. In reality, there may be a certain deviation between the width-to-length ratio of the first NMOS transistor 224 channel and the second NMOS transistor 214 channel. However, this bias voltage needs to be within a preset deviation range. That is to say, the voltage difference between the actual output voltage of the compensation module 220 and the ideal second output voltage Vout2 is within a preset range. In other words, the actual output voltage of the compensation module 220 can be slightly greater than or slightly less than the ideal second output voltage Vout2. When the actual output voltage of the compensation module 220 is significantly higher than the ideal second output voltage Vout2, the compensation module 220 may generate significant noise. When the actual output voltage of the compensation module 220 is significantly lower than the ideal second output voltage Vout2, the ability of the voltage of the stable power supply node to recover to the first output voltage Vout1 is poor, and the improvement effect is not good.

[0049] In some embodiments, the voltage generation circuit further includes a first voltage generation module 230, which receives a reference voltage Vref and generates a drive voltage Vhv for driving the first operational amplifier 211. The value of the drive voltage Vhv is greater than the sum of the voltage value corresponding to the control signal Vctrl and the threshold voltage of the NMOS transistor connected in series between the power supply terminal where the drive voltage is located and the output terminal of the first operational amplifier 211. By providing the above-mentioned drive voltage to the first operational amplifier 211 as a power supply voltage, it can be ensured that the first operational amplifier 211 can effectively receive the required control signal Vctrl. It is understood that when multiple MOS transistors are connected in series between the output terminal and the power supply terminal of the first operational amplifier, the voltage of the drive voltage Vhv should be greater than the sum of the voltage value corresponding to the control signal Vctrl and the threshold voltages corresponding to the multiple MOS transistors, that is, so that the maximum value of the output voltage of the first operational amplifier 211 is greater than the voltage value corresponding to the control signal Vctrl.

[0050] In some embodiments, the voltage generation circuit may further include a flag signal generation module 240, configured to generate a flag signal Reg based on an enable signal En, wherein the enable signal En is used to control the operation of the load 280. In this embodiment, the flag signal generation module 240 can convert the enable signal En into a corresponding flag signal Reg. For example, a first enable signal En1, a second enable signal En2, and a third enable signal En3 are provided to the flag signal generation module 240, and corresponding first flag signals Reg1, second flag signals Reg2, and third flag signals Reg3 can be generated by the flag signal generation module 240. Different enable signals En can be provided to different loads, and the flag signal Reg corresponding to the enable signal En can be provided to the compensation module 220 connected to the corresponding load 280. Thus, when the load 280 corresponding to the first enable signal En1 is turned on, the compensation module 220 receiving the first flag signal Reg1 starts to work to provide a second output voltage Vout2 to the load 280, thereby compensating for the voltage of the power supply node corresponding to the load 280.

[0051] In some embodiments, reference Figure 4The voltage output module 200 may include: a second operational amplifier 201, the inverting input of which receives a reference voltage Vref; a third resistor 202, one end of which is grounded and the other end is connected to the non-inverting input of the second operational amplifier 201; a third PMOS transistor 203, the gate of which is connected to the output of the second operational amplifier 201, the source of which is connected to the operating power supply, and the drain of which outputs a first output voltage Vout1; and a fourth resistor 204, one end of which is connected to the non-inverting input of the second operational amplifier 201 and the other end of which is connected to the drain of the third PMOS transistor 203.

[0052] It is understandable that the working principle of the voltage output module 200 is as follows: when the output voltage of the voltage output module 200 decreases, the voltage supplied to the non-inverting input terminal of the second operational amplifier 201 decreases due to the voltage division effect of the third resistor 202 and the fourth resistor 204. However, the reference voltage Vref connected to the inverting input terminal of the second operational amplifier 201 is stable. Therefore, the voltage at the output terminal of the second operational amplifier 201 decreases accordingly, the gate voltage of the third PMOS transistor 203 decreases, and the output voltage of the voltage output module 200 increases accordingly, suppressing the decrease in output voltage and thus maintaining a stable output.

[0053] In some embodiments, the voltage of the operating power supply connected to the source of the third PMOS transistor 203 is equal to the voltage of the driving voltage of the second operational amplifier 201. In other words, the source of the third PMOS transistor 203 and the second operational amplifier 201 can be connected to the same operating power supply, reducing the complexity caused by setting different power supplies.

[0054] In some embodiments, the specifications of the first operational amplifier 211 may also be the same as those of the second operational amplifier 201, thereby reducing the difference between the third output voltage Vout3 and the first output voltage Vout1, thereby reducing the difference between the second output voltage Vout2 generated based on the control signal Vctrl and the first output voltage Vout1, thereby restoring the voltage of the power supply node to the first output voltage Vout1.

[0055] In some embodiments, the voltage generation circuit may further include a second voltage generation module 250, which is used to provide a reference voltage Vref and can provide the reference voltage Vref to the voltage output module 200, the voltage regulator module 210 and the first voltage generation module 230.

[0056] In some embodiments, the second voltage generation module 250 may include a first voltage generation unit 251 and a second voltage generation unit 252. The first voltage generation unit 251 can generate a bandgap reference voltage Vbgr, and the second voltage generation unit 252 can receive the bandgap reference voltage Vbgr to generate a reference voltage Vref. In the memory, the bandgap reference voltage Vbgr is a stable voltage signal, and the magnitude of the voltage value is not affected by temperature. Therefore, the bandgap reference voltage Vbgr provided by the first voltage generation unit 251 is not affected by temperature, thereby generating a stable reference voltage Vref.

[0057] In some embodiments, the voltage generation circuit may further include a capacitor 260, one end of which is connected to the output terminal of the voltage output module 200, and the other end is grounded. By setting the capacitor 260, a filtering function can be implemented, thereby reducing the reliability of the voltage provided by the voltage generation circuit.

[0058] In some embodiments, the voltage generation circuit may further include a resistor 270, one end of which is connected to the output terminal of the voltage output module 200, and the other end is connected to the power supply node. By setting the resistor 270, the safety of the voltage generation circuit can be improved and the influence between different voltage nodes in the power network can be reduced.

[0059] refer to Figure 3 and Figure 6 ,in Figure 6 The signal fluctuation diagram for the voltage generation circuit is as follows: Specifically, a high-level power supply voltage VPwr is consistently provided to enable the voltage regulator module 210 and the flag signal generation module 240 to operate. An enable signal En is provided to the load 280 and the flag signal generation module 240. When the enable signal En is high, the load 280 is turned on, causing voltage fluctuations at the power supply node connected to the load 280. Simultaneously, when the enable signal En is high, the synchronous flag signal generation module 240 provides a flag signal Reg to the compensation module 220, enabling the compensation module 220 to operate and providing a second output voltage Vout2 to the power supply node to compensate for the voltage fluctuations. The voltage of the power node can be referenced from the voltage fluctuation diagram of the power supply node. When the enable signal is low, the power supply node receives the first output voltage Vout1 from the voltage output module 200, the voltage rises, the enable signal En becomes high, the load 280 is turned on, causing the voltage of the power supply node to be consumed and begin to drop. The compensation module 220 works to compensate the power supply node and slow down the voltage drop. When the enable signal En becomes low again, the load is turned off, the flag signal Reg goes low, the compensation module 220 is turned off, the power supply node receives the first output voltage Vout1 from the voltage output module 200, and the voltage rises.

[0060] Compared to the embodiments disclosed herein... Figure 1Compared with existing technologies, it has a smaller layout area, a smaller power tolerance range from the power supply voltage VPwr to the first output voltage Vout1, and consumes less power, with faster response speed and higher accuracy.

[0061] In this embodiment, the voltage output module 200 provides a first output voltage Vout1 to the power supply node. When the load causes the voltage of the power supply node to drop, the voltage regulator module 210 operates and receives a reference voltage Vref to provide a control signal Vctrl to the compensation module 220. The compensation module 220 receives the power supply voltage VPwr, the flag signal Reg, and the control signal Vctrl, and responds to the flag signal Reg by conducting. It also generates and outputs a second output voltage Vout2 to the power supply node based on the voltage value of the control signal Vctrl, thereby compensating for the first output voltage Vout1 consumed by the load at the power supply node. This stabilizes the voltage provided by the voltage generation circuit to the load at the first output voltage Vout1, thereby improving the accuracy of the voltage generation circuit.

[0062] It is worth mentioning that all units involved in this embodiment are logical units. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of this application, this embodiment does not introduce units that are not closely related to solving the technical problems proposed in this application; however, this does not mean that other units are absent in this embodiment.

[0063] It should be noted that the features disclosed in the power supply circuit provided in the above embodiments can be arbitrarily combined without conflict to obtain new power supply circuit embodiments.

[0064] Another embodiment of this disclosure also provides a memory, which may include the voltage generation circuit described above. The memory provided by the embodiments of this disclosure will be described below with reference to the accompanying drawings. It should be noted that the parts that are the same as or corresponding to the foregoing embodiments can be referred to the response description of the foregoing embodiments, and will not be repeated below.

[0065] refer to Figures 2 to 6 The memory provided in this embodiment includes: a voltage generation circuit as described above; a load 280 connected to a power supply node, and the load 280 operating in response to an enable signal En.

[0066] In this embodiment, the voltage output module 200 provides a first output voltage Vout1 to the power supply node. When the load 280 operates, causing the voltage of the power supply node to drop, the voltage regulator module 210 operates and receives the reference voltage Vref to provide a control signal Vctrl to the compensation module 220. The compensation module 220 receives the power supply voltage VPwr, the flag signal Reg, and the control signal Vctrl, and responds to the flag signal Reg by conducting. It also generates and outputs a second output voltage Vout2 to the power supply node based on the voltage value of the control signal Vctrl, thereby compensating for the first output voltage Vout1 consumed by the load 280 at the power supply node. This stabilizes the voltage provided by the voltage generation circuit to the load 280 at the first output voltage Vout1, thereby improving the accuracy of the voltage generation circuit.

[0067] In some embodiments, there are multiple loads 280, and different loads 280 operate in response to different enable signals En; the voltage generation circuit has multiple power supply nodes, and each power supply node is connected to a load 280; the voltage generation circuit includes multiple compensation modules 220, and each compensation module 220 provides a second output voltage Vout2 to a corresponding power supply node in response to a corresponding flag signal Reg. Taking three loads 280 as an example, the three loads 280 can be divided into a first load, a second load, and a third load. The first load, the second load, and the third load are connected to different power supply nodes, and each power supply node is connected to a different compensation module 220. The different compensation modules 220 provide the second output voltage Vout2 to the different loads respectively, so that each load 280 has a corresponding compensation module 220 for compensation.

[0068] In some embodiments, multiple loads 280 can be turned on simultaneously, and corresponding multiple compensation modules 220 are also turned on simultaneously; in other embodiments, multiple loads 280 can be turned on selectively, and correspondingly, the compensation module 220 connected to the turned load is turned on.

[0069] In summary, the working principle of the memory is as follows: When the load 280 is in the working state, the load 280 will consume part of the first output voltage Vout1 provided by the voltage output module 200 to the power supply node, which will cause the voltage of the power supply node to drop. When the load 280 is in the working state, the compensation module 220 receives the flag signal Reg and generates the second output voltage Vout2 based on the control signal Vctrl, and provides the second output voltage Vout2 to the power supply node, thereby compensating for the first output voltage Vout1 consumed by the load 280, so that the voltage of the power supply node is restored, thereby ensuring the stability and accuracy of the voltage provided by the voltage generation circuit to the power supply node.

[0070] refer to Figure 6The signal fluctuation diagram shown illustrates the situation when an enable signal En is provided to load 280, i.e. Figure 6 When the enable signal En is high, the load 280 starts working. At the moment the load 280 starts working, it consumes part of the voltage of the power supply node, causing the voltage of the power supply node to drop. At the same time as providing the enable signal En to the load 280, the enable signal En is simultaneously provided to the flag signal generation module 240. The flag signal generation module 240 generates a flag signal Reg and provides the flag signal Reg to the compensation module 220. Upon receiving the flag signal Reg, the compensation module 220 starts working, thereby outputting a second output voltage Vout2 to compensate the power supply node. This reduces the voltage drop of the power supply node and improves the accuracy of the voltage generation circuit. When the load 280 stops working, that is, when the enable signal En changes from high to low, the voltage of the power supply node is no longer consumed, the compensation module 220 no longer receives the flag signal Reg, the compensation module stops working, and the voltage of the power supply node receives the first output voltage Vout1 provided by the voltage output module 200 and rises.

[0071] In some embodiments, Figure 6 The signal fluctuation diagram shown can represent the enable signal En received by a certain load 280 within a certain period of time, and the flag signal Reg received by the compensation module 220 connected to the corresponding load 280. In other words, the load 280 is turned on once at regular intervals within a certain period of time. In other embodiments, Figure 6 The signal fluctuation diagram shown can also be the signal fluctuation diagram of the entire memory. That is, when one of the loads 280 in the memory is turned on, the loads 280 in the memory receive the enable signal En in sequence and turn on in response to the enable signal En. When one of the loads 280 in the memory is turned on, the other loads 280 are all in the off state.

[0072] It should be noted that memory can be a storage cell or device based on semiconductor devices or components. For example, a memory device can be volatile memory, such as Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate Synchronous Dynamic Random Access Memory (LPDDR SDRAM), Graphics Double Data Rate Synchronous Dynamic Random Access Memory (GDDR SDRAM), Double Data Rate Type Dual Synchronous Dynamic Random Access Memory (DDR2 SDRAM), Double Data Rate Type Triple Synchronous Dynamic Random Access Memory (DDR3 SDRAM), Double Data Rate Type Fourth Generation Synchronous Dynamic Random Access Memory (DDR4 SDRAM), Thyristor Random Access Memory (TRAM), etc.; or it can be non-volatile memory, such as Phase Change Random Access Memory (PRAM), Magnetic Random Access Memory (MRAM), Resistive Random Access Memory (RRAM), etc.

[0073] This embodiment of the present disclosure provides power through the voltage generation circuit provided in the above embodiment to provide a more stable first output voltage Vout1 to the load 280, and the first output voltage Vout1 is more accurate, thereby improving the response speed and accuracy of the memory.

[0074] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A voltage generation circuit, characterized in that, include: A voltage output module is configured to receive a reference voltage, generate a first output voltage, and provide the first output voltage to a power supply node, wherein the power supply node is configured to connect to a load to supply power to the load. The voltage regulator module is configured to receive the reference voltage, generate and output a control signal; The compensation module is configured to receive a power supply voltage, a flag signal, and the control signal, and in response to the flag signal being turned on, and in response to the voltage value of the control signal being used to provide a second output voltage to the power supply node so that the voltage of the power supply node is restored to the first output voltage, wherein the flag signal indicates that the load is in operation.

2. The voltage generation circuit according to claim 1, characterized in that, The compensation module includes: A switching unit is used to receive the flag signal and output the power supply voltage based on the flag signal; An adjustment unit, connected to the switching unit, is used to receive the power supply voltage and the control signal, and to adjust the output amplitude of the compensation module based on the voltage value of the control signal.

3. The voltage generation circuit according to claim 2, characterized in that, The switching unit includes: a first PMOS transistor, the gate of which receives the flag signal, and the source of which is connected to the operating power supply; The adjustment unit includes: a first NMOS transistor, the gate of which receives the control signal, the drain of which is connected to the drain of a first PMOS transistor, and the source of which is connected to the power supply node to provide the second output voltage.

4. The voltage generation circuit according to claim 3, characterized in that, The voltage regulator module includes: A first operational amplifier, wherein the non-inverting input terminal of the first operational amplifier receives the reference voltage, and the output terminal of the first operational amplifier outputs the control signal; The first resistor has one end grounded and the other end connected to the inverting input terminal of the first operational amplifier; The source of the second PMOS transistor is connected to the power supply voltage; The second NMOS transistor has its gate connected to the output terminal of the first operational amplifier, and its drain connected to the drain of the second PMOS transistor. The second resistor has one end connected to the inverting input of the first operational amplifier and the other end connected to the source of the second NMOS transistor.

5. The voltage generation circuit according to claim 4, characterized in that, The aspect ratio of the first NMOS channel is equal to that of the second NMOS channel.

6. The voltage generation circuit according to claim 4, characterized in that, The voltage generation circuit further includes: a first voltage generation module, which receives the reference voltage and generates a driving voltage for driving the first operational amplifier.

7. The voltage generation circuit according to claim 6, characterized in that, The driving voltage is greater than the sum of the voltage value corresponding to the control signal and the turn-on voltage of the second NMOS transistor.

8. The voltage generation circuit according to claim 1, characterized in that, Also includes: The flag signal generation module is configured to generate the flag signal based on an enable signal, the enable signal being used to control the operation of the load.

9. The voltage generation circuit according to claim 1, characterized in that, The voltage output module includes: A second operational amplifier, wherein the inverting input of the second operational amplifier receives the reference voltage; The third resistor has one end grounded and the other end connected to the non-inverting input terminal of the second operational amplifier; the third PMOS transistor has its gate connected to the output terminal of the second operational amplifier, its source connected to the operating power supply, and its drain outputting the first output voltage. The fourth resistor has one end connected to the non-inverting input of the second operational amplifier and the other end connected to the drain of the third PMOS transistor.

10. The voltage generation circuit according to claim 9, characterized in that, The voltage of the operating power supply connected to the source of the third PMOS transistor is equal to the voltage of the drive voltage of the second operational amplifier.

11. The voltage generation circuit according to claim 1, characterized in that, Also includes: A second voltage generation module is used to provide the reference voltage.

12. The voltage generation circuit according to claim 1, characterized in that, Also includes: A capacitor, one end of which is connected to the output terminal of the voltage output module, and the other end is grounded.

13. A memory, characterized in that, The voltage generation circuit as described in any one of claims 1-12; A load, which is connected to the power supply node, operates in response to an enable signal.

14. The memory according to claim 13, characterized in that, The number of loads is multiple, and different loads operate in response to different enable signals; The voltage generation circuit has multiple power supply nodes, and each power supply node is connected to a load. The voltage generation circuit includes a plurality of the compensation modules, and each of the compensation modules provides the second output voltage to the corresponding power supply node in response to the corresponding flag signal.

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