A ufs storage device supporting single power supply and a control method thereof

Abstract

The application provides a single-channel power supply supported UFS storage device and a control method thereof, the device comprising a controller chip and a flash memory chip, the controller chip being connected to a single-channel external power supply, the controller chip being internally provided with a step-down circuit, a step-up circuit, a low-voltage module, an ultra-low-voltage module and a physical layer interface, the step-down circuit being provided with an input power supply PAD and an output power supply PAD, so that the power supply voltage of the single-channel external power supply is stepped down to a first voltage value, and used for supplying power to all modules in the UFS storage device with the power supply voltage being the first voltage value; the step-up circuit being provided with an input power supply PAD and an output power supply PAD, so that the power supply voltage of the single-channel external power supply is stepped up to a second voltage value, and used for supplying power to all modules in the UFS storage device with the power supply voltage being the second voltage value. The application only uses one channel of external power supply to supply power to the UFS storage device, and the power supply voltage requirements of all modules in the device can be met.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, specifically to a UFS storage device that supports single-channel power supply and a control method for using the device. Background Technology

[0002] UFS (Universal Flash Memory) is a flash memory system defined by JEDEC (Joint Electronic Equipment Committee) for high-bandwidth and low-power mobile storage applications. The JEDEC protocol standard for UFS defines its electrical interface and the characteristics of the memory device. Over the past decade, advancements in semiconductor manufacturing processes have significantly increased wafer density, improving device performance and reliability. Consequently, the capacity of flash memory chips, the power supply voltage of flash memory devices, and interface speeds are constantly evolving, and the UFS flash memory standard is continuously being updated.

[0003] like Figure 1 As shown, Figure 1 This is the modular structure of a UFS memory device, where the controller and flash memory chips are packaged within the same module. The controller communicates with the UFS host outside the module via a physical layer interface and manages the power supply and communication of the flash memory chips inside the module through controller input / output. The UFS protocol standard specifies that the external power supply for the module is VCC, VCCQ, and VCCQ2. VCC is used to power the storage core of the flash memory chips, with a typical voltage of 3.3V (UFS 2 standard) or 2.5V (UFS 3 standard). VCCQ is used for the ultra-low voltage module of the controller and can also be used for the physical layer interface and input / output power supply, with a typical voltage of 1.2V. VCCQ2 is used for the low voltage module of the physical layer interface and the controller, with a typical voltage of 1.8V. The UFS protocol standard does not define the power supply voltage VCCIO for the controller input / output module and the flash memory input / output module; it depends on the interface voltage requirements of the flash memory chips, and the controller needs to adapt to the flash memory chips and provide appropriate voltage values. Generally speaking, small-capacity, low-speed flash memory chips manufactured using older processes support 1.8V VCCIO, while large-capacity, high-speed flash memory chips manufactured using newer processes support 1.2V VCCIO.

[0004] Therefore, the existing technology has the following problems:

[0005] I. From the perspective of the power requirements of the internal controller of the UFS storage device, two external power supplies, VCCQ and VCCQ2, are required:

[0006] (1) It is difficult to unify the operating voltage of each module in the controller chip. For example, analog circuit designs that require high voltage swing need to operate at 1.8V, which is difficult to design under a 1.2V power supply; while high-speed mixed-signal interface designs need to operate under a 1.2V power supply to achieve the required performance.

[0007] (2) The input / output interface voltage of flash memory chips varies with the manufacturing process, and the power supply scheme of storage devices needs to take into account the compatibility of different flash memory chips.

[0008] (3) The operating voltage of the same module in the controller will vary with the semiconductor manufacturing process. For example, the operating voltage of the physical layer interface of a controller using planar technology is 1.8V; the operating voltage of the physical layer interface of a controller using FinFET technology is 1.2V.

[0009] Second, from the perspective of product hardware design using UFS storage devices, reducing the number of power supplies is one of the design goals. This not only directly reduces the cost of the PMU (Power Management Unit) but also provides greater flexibility for PCB board design. Ample layout and routing space is also a very critical factor in high-speed PCB design. Summary of the Invention

[0010] In order to overcome the shortcomings of the prior art, the present invention aims to provide a UFS storage device that supports single-channel power supply and its control method. The device and method are used to solve the problems of high cost, difficulty in unifying operating voltage, poor adaptability, poor stability, low flexibility and insufficient wiring space in the prior art, so as to achieve the goal of using only one external power supply to power the UFS storage device and meet the power supply voltage requirements of each module in the device.

[0011] To solve the above problems, the technical solution adopted by the present invention is as follows:

[0012] A UFS storage device supporting single-channel power supply includes: a controller chip and a flash memory chip. The input / output terminals of the controller chip are connected to the input / output terminals of the flash memory chip. The flash memory chip is connected to a VCC power supply. The controller chip is connected to a single external power supply. The controller chip has a built-in buck circuit, a boost circuit, a low-voltage module, an ultra-low-voltage module, and a physical layer interface. The buck circuit has an input power PAD and an output power PAD, which reduces the power supply voltage of the single external power supply to a first voltage value to power all modules in the UFS storage device with a power supply voltage of the first voltage value. The boost circuit has an input power PAD and an output power PAD, which boosts the power supply voltage of the single external power supply to a second voltage value to power all modules in the UFS storage device with a power supply voltage of the second voltage value.

[0013] A further option is that the low-voltage module is used to operate at a fixed second voltage value to meet the circuit requirements of high voltage swing, and the ultra-low voltage module is used to operate at a fixed first voltage value to meet the design requirements of high-speed mixed signals.

[0014] Therefore, compared with the prior art, the present invention has the following beneficial effects:

[0015] 1. This invention adds a step-down circuit to the controller chip to step down the higher voltage VCCQ2 to a lower voltage, thereby achieving the purpose of supplying power to all modules in the storage device with a specified power supply voltage without the need for an external VCCQ.

[0016] 2. Add a boost circuit inside the controller chip to boost the lower voltage VCCQ to a higher voltage, thereby achieving the purpose of powering all modules in the storage device with a specified power supply voltage without the need for an external VCCQ2.

[0017] 3. For UFS storage devices, wire bonding is an optional packaging solution, which allows for selection of the operating voltage of each module in the storage device controller.

[0018] A control method for a UFS storage device supporting single-channel power supply, the method being applied to power control of the aforementioned UFS storage device supporting single-channel power supply, the method comprising the following steps:

[0019] When only the first external power supply is provided to the UFS storage device, the physical layer interface power supply voltage in the controller chip is the first voltage value, and its input and output voltage VCCIO is the first voltage value. The input power supply PAD of the buck circuit is connected to the first external power supply, and the output power supply PAD of the buck circuit is connected to the power supply PAD of the physical layer interface, the power supply PAD of the ultra-low voltage module, and the power supply PAD of voltage VCCIO, respectively. The boost circuit does not work, and its input power supply PAD and output power supply PAD are disconnected, maintaining the NC state. The low voltage module power supply PAD is connected to the first external power supply.

[0020] When only a second external power supply is provided to the UFS storage device, the physical layer interface power supply voltage inside the controller chip is the first voltage value, and its input and output terminal voltage VCCIO is the first voltage value. The input power supply PAD of the boost circuit is connected to the second external power supply, and the output power supply PAD of the boost circuit is connected to the power supply PAD of the low-voltage module. The buck circuit does not work, and its input power supply PAD and output power supply PAD are disconnected, maintaining the NC state. The power supply PAD of the physical layer interface, the power supply PAD of the ultra-low voltage module, and the power supply PAD of voltage VCCIO are connected to the second external power supply.

[0021] The power supply voltage provided by the first external power source is greater than the power supply voltage provided by the second external power source.

[0022] A further solution is that when only the first external power supply is provided to the UFS storage device, the physical layer interface power supply voltage in the controller chip is the second voltage value, and its input / output terminal voltage VCCIO is the second voltage value. The input power supply PAD of the buck circuit is connected to the first external power supply, and the output power supply PAD of the buck circuit is connected to the power supply PAD of the ultra-low voltage module. The boost circuit does not work, and its input power supply PAD and output power supply PAD are disconnected, maintaining the NC state. The power supply PAD of the low voltage module, the power supply PAD of the physical layer interface, and the power supply PAD of voltage VCCIO are connected to the first external power supply.

[0023] A further solution is that when only the first external power supply is provided to the UFS storage device, the physical layer interface power supply voltage in the controller chip is the first voltage value, and its input / output voltage VCCIO is the second voltage value. The input power supply PAD of the buck circuit is connected to the first external power supply, and the output power supply PAD of the buck circuit is connected to the power supply PAD of the ultra-low voltage module and the power supply PAD of the physical layer interface respectively. The boost circuit does not work, and its input power supply PAD and output power supply PAD are disconnected, maintaining the NC state. The power supply PAD of the low voltage module and the power supply PAD of voltage VCCIO are connected to the first external power supply.

[0024] A further solution is that when only the first external power supply is provided to the UFS storage device, the physical layer interface power supply voltage in the controller chip is the second voltage value, and its input / output terminal voltage VCCIO is the first voltage value. The input power supply PAD of the buck circuit is connected to the first external power supply, and the output power supply PAD of the buck circuit is connected to the power supply PAD of the ultra-low voltage module and the power supply PAD of voltage VCCIO, respectively. The boost circuit does not work, and its input power supply PAD and output power supply PAD are disconnected, maintaining the NC state. The power supply PAD of the low voltage module and the power supply PAD of the physical layer interface are connected to the first external power supply.

[0025] A further solution is to connect the input power supply PAD of the UFS storage device to the second external power supply when only a second external power supply is provided. The power supply voltage of the physical layer interface inside the controller chip is the second voltage value, and the input and output voltage VCCIO is the second voltage value. The input power supply PAD of the boost circuit is connected to the second external power supply, and the output power supply PAD of the boost circuit is connected to the power supply PAD of the low-voltage module, the power supply PAD of the physical layer interface, and the power supply PAD of voltage VCCIO, respectively. The buck circuit does not work, and its input power supply PAD and output power supply PAD are disconnected, maintaining the NC state. The power supply PAD of the ultra-low voltage module is connected to the second external power supply.

[0026] A further solution is that when only a second external power supply is provided to the UFS storage device, the physical layer interface power supply voltage inside the controller chip is the first voltage value, and its input / output terminal voltage VCCIO is the second voltage value. The input power supply PAD of the boost circuit is connected to the second external power supply, and the output power supply PAD of the boost circuit is connected to the power supply PAD of the low-voltage module and the power supply PAD of voltage VCCIO. The buck circuit does not work, and its input power supply PAD and output power supply PAD are disconnected, maintaining the NC state. The power supply PAD of the ultra-low voltage module and the power supply PAD of the physical layer interface are connected to the second external power supply.

[0027] A further solution is that when only a second external power supply is provided to the UFS storage device, the physical layer interface power supply voltage inside the controller chip is the second voltage value, and its input / output terminal voltage VCCIO is the first voltage value. The input power supply PAD of the boost circuit is connected to the second external power supply, and the output power supply PAD of the boost circuit is connected to the power supply PAD of the low-voltage module and the power supply PAD of the physical layer interface. The buck circuit does not work, and its input power supply PAD and output power supply PAD are disconnected, maintaining the NC state. The power supply PAD of the ultra-low voltage module and the power supply PAD of voltage VCCIO are connected to the second external power supply.

[0028] A further proposed solution is that the power supplied by the first external power source is a second voltage value, and the power supplied by the second external power source is a first voltage value.

[0029] Therefore, compared with the prior art, the present invention has the following beneficial effects:

[0030] 1. This invention reduces the number of external power supplies for UFS storage devices from two to one, allowing the storage device controller to support hardware power solutions for products with a single power supply VCCQ or a single power supply VCCQ2. This directly reduces the cost of the PMU (Power Management Unit) chip and provides more layout and routing space for PCB board design, resulting in better performance for high-speed PCB design.

[0031] 2. This invention allows for variations in the operating voltage of individual modules within the UFS storage device controller, and the same controller chip design can be manufactured on multiple semiconductor manufacturing process platforms, significantly improving the speed of product performance upgrades.

[0032] 3. The same controller chip can adapt to the input / output voltage VCCIO of different flash memory chips, and has better flash memory chip compatibility.

[0033] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0034] Figure 1This is a schematic diagram of an existing UFS storage device.

[0035] Figure 2 This is a first schematic diagram of an embodiment of a UFS storage device that supports single-channel power supply according to the present invention, which only provides a first external power supply.

[0036] Figure 3 This is a second schematic diagram of an embodiment of a UFS storage device that supports single-channel power supply according to the present invention, which only provides a first external power supply.

[0037] Figure 4 This is a third schematic diagram of an embodiment of the UFS storage device that supports single-channel power supply according to the present invention, in which only a first external power supply is provided.

[0038] Figure 5 This is a fourth schematic diagram of an embodiment of the UFS storage device that supports single-channel power supply according to the present invention, in which only a first external power supply is provided.

[0039] Figure 6 This is a first schematic diagram of an embodiment of the UFS storage device that supports single-channel power supply according to the present invention, which only provides a second external power supply.

[0040] Figure 7 This is a second schematic diagram of an embodiment of the UFS storage device that supports single-channel power supply according to the present invention, which only provides a second external power supply.

[0041] Figure 8 This is a third schematic diagram of an embodiment of the UFS storage device that supports single-channel power supply according to the present invention, in which only a second external power supply is provided.

[0042] Figure 9 This is a fourth schematic diagram of an embodiment of the UFS storage device that supports single-channel power supply according to the present invention, in which only a second external power supply is provided. Detailed Implementation

[0043] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0044] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0045] An example of a UFS storage device supporting single-channel power supply:

[0046] See Figure 1 The present invention provides a UFS storage device supporting single-channel power supply, comprising:

[0047] The controller chip 10 and flash memory chip 20 are connected to each other. The input / output terminals of the controller chip 10 and the flash memory chip 20 are connected to the VCC power supply. The controller chip 10 is connected to a single external power supply. The controller chip 10 has a built-in buck circuit 1, a boost circuit 2, a low-voltage module 3, an ultra-low-voltage module 4, and a physical layer interface 5. The buck circuit 1 has an input power PAD and an output power PAD, which reduces the power supply voltage of the single external power supply to a first voltage value, which is used to power all modules in the UFS storage device with the first voltage value. The boost circuit 2 has an input power PAD and an output power PAD, which boosts the power supply voltage of the single external power supply to a second voltage value, which is used to power all modules in the UFS storage device with the second voltage value.

[0048] Among them, the low-voltage module 3 is used to operate at the second voltage value to meet the circuit requirements of high voltage swing, and the ultra-low voltage module 4 is used to operate at the first voltage value to meet the design requirements of high-speed mixed signals.

[0049] In this embodiment, the first voltage value is 1.2V and the second voltage value is 1.8V. Of course, the first and second voltage values ​​in this embodiment include, but are not limited to, 1.2V and 1.8V, and can also be other power supply voltages that meet the requirements for powering UFS storage devices.

[0050] Specifically, this invention adds a buck circuit 1 (including an input power PAD and an output power PAD) and a boost circuit 2 (including an input power PAD and an output power PAD) to the controller chip 10, and selects the operating voltage of each module of the storage device controller through package bonding, such as... Figures 2 to 9 As shown, Figures 2 to 9 These are different packaging and wire bonding schemes. Among them, the low-voltage module 3 operates at 1.8V to meet the circuit requirements of high voltage swing, while the ultra-low-voltage module 4 operates at 1.2V to meet the design requirements of high-speed mixed signals.

[0051] Furthermore, in this embodiment, the external power supply voltage is variable depending on the product hardware design, the input / output voltage of the flash memory chip is variable depending on the chip capacity and speed, and the voltage of the physical layer interface 5 is variable depending on the semiconductor manufacturing process.

[0052] Therefore, this invention adds a step-down circuit 1 to the controller chip 10 to step down the 1.8V VCCQ2 to 1.2V, thereby achieving the purpose of supplying power to all modules in the storage device with a specified power supply voltage without the need for an external VCCQ; this invention also adds a boost circuit 2 to the controller chip 10 to boost the 1.2V VCCQ to 1.8V, thereby achieving the purpose of supplying power to all modules in the storage device with a specified power supply voltage without the need for an external VCCQ2; the packaging of the UFS storage device of this invention uses a wire bonding option, and the operating voltage of each module of the storage device controller is selected by the wire bonding of the packaging.

[0053] An embodiment of a control method for a UFS storage device supporting single-channel power supply:

[0054] A control method for a UFS storage device supporting single-channel power supply, the method being applied to power control of the aforementioned UFS storage device supporting single-channel power supply, the method comprising the following steps:

[0055] When only the first external power supply (such as VCCQ2 power supply) is provided to the UFS storage device, the power supply voltage of the physical layer interface 5 inside the controller chip 10 is the first voltage value, and its input and output terminal voltage VCCIO is the first voltage value. The input power supply PAD of the buck circuit 1 is connected to the first external power supply, and the output power supply PAD of the buck circuit 1 is connected to the power supply PAD of the physical layer interface 5, the power supply PAD of the ultra-low voltage module 4, and the power supply PAD of voltage VCCIO, respectively. The boost circuit 2 does not work, and its input power supply PAD and output power supply PAD are disconnected, maintaining the NC state. The power supply PAD of the low voltage module 3 is connected to the first external power supply.

[0056] When only a second external power supply (VCCQ power) is provided to the UFS storage device, the power supply voltage of the physical layer interface 5 inside the controller chip 10 is the first voltage value, and its input and output voltage VCCIO is the first voltage value. The input power supply PAD of the boost circuit 2 is connected to the second external power supply, and the output power supply PAD of the boost circuit 2 is connected to the power supply PAD of the low-voltage module 3. The buck circuit 1 does not work, and its input power supply PAD and output power supply PAD are disconnected, maintaining the NC state. The power supply PAD of the physical layer interface 5, the power supply PAD of the ultra-low voltage module 4, and the power supply PAD of voltage VCCIO are connected to the second external power supply.

[0057] The power supply voltage provided by the first external power source is greater than the power supply voltage provided by the second external power source.

[0058] The power supplied by the first external power source is the second voltage value, and the power supplied by the second external power source is the first voltage value.

[0059] Furthermore, such as Figure 2 As shown, when only VCCQ2 power is supplied externally to the UFS storage device, the power supply voltage of the physical layer interface 5 within the controller chip 10 is 1.2V, and the input / output voltage VCCIO is 1.2V. The input power PAD of the buck circuit 1 is wired to VCCQ2, and the output power PAD of the buck circuit 1 is wired to the power PAD of the physical layer interface 5, the power PAD of the ultra-low voltage module 4, and the power PAD of VCCIO, respectively. The boost circuit 2 does not work; its input and output power PADs are not wired, maintaining an NC (No connection) state. The power PAD of the low-voltage module 3 is connected to VCCQ2.

[0060] Furthermore, such as Figure 6 As shown, when only VCCQ power is supplied externally to the UFS storage device, the power supply voltage of the physical layer interface 5 within the controller chip 10 is 1.2V, and its input / output voltage VCCIO is 1.2V. The input power PAD of the boost circuit 2 is wired to VCCQ, and the output power PAD of the boost circuit 2 is wired to the power PAD of the low-voltage module 3. The buck circuit 1 is not working; its input and output power PADs are not wired, maintaining the NC state. The power PADs of the physical layer interface 5, the ultra-low voltage module 4, and VCCIO are connected to VCCQ.

[0061] In this embodiment, when only the first external power supply is provided to the UFS storage device, the power supply voltage of the physical layer interface 5 inside the controller chip 10 is the second voltage value, and its input and output terminal voltage VCCIO is the second voltage value. The input power supply PAD of the buck circuit 1 is connected to the first external power supply, and the output power supply PAD of the buck circuit 1 is connected to the power supply PAD of the ultra-low voltage module 4. The boost circuit 2 does not work, and its input power supply PAD and output power supply PAD are disconnected, maintaining the NC state. The power supply PAD of the low voltage module 3, the power supply PAD of the physical layer interface 5, and the power supply PAD of voltage VCCIO are connected to the first external power supply.

[0062] Furthermore, such as Figure 3 As shown, when only VCCQ2 power is supplied externally to the UFS storage device, the power supply voltage of the physical layer interface 5 within the controller chip 10 is 1.8V, and its input / output voltage VCCIO is 1.8V. The input power PAD of the buck circuit 1 is wired to VCCQ2, and the output power PAD of the buck circuit 1 is wired to the power PAD of the ultra-low voltage module 4. The boost circuit 2 is not working; its input and output power PADs are not wired, maintaining the NC state. The power PADs of the low-voltage module 3, the physical layer interface 5, and VCCIO are all connected to VCCQ2.

[0063] In this embodiment, when only the first external power supply is provided to the UFS storage device, the power supply voltage of the physical layer interface 5 inside the controller chip 10 is the first voltage value, and its input and output terminal voltage VCCIO is the second voltage value. The input power supply PAD of the buck circuit 1 is connected to the first external power supply, and the output power supply PAD of the buck circuit 1 is connected to the power supply PAD of the ultra-low voltage module 4 and the power supply PAD of the physical layer interface 5 respectively. The boost circuit 2 does not work, and its input power supply PAD and output power supply PAD are disconnected, maintaining the NC state. The power supply PAD of the low voltage module 3 and the power supply PAD of voltage VCCIO are connected to the first external power supply.

[0064] Furthermore, such as Figure 4 As shown, when only VCCQ2 power is supplied externally to the UFS storage device, the power supply voltage of the physical layer interface 5 within the controller chip 10 is 1.2V, and its input / output voltage VCCIO is 1.8V. The input power PAD of the buck circuit 1 is wired to VCCQ2, and the output power PAD of the buck circuit 1 is wired to the power PAD of the ultra-low voltage module 4 and the power PAD of the physical layer interface 5. The boost circuit 2 is not working; its input and output power PADs are not wired, maintaining the NC state. The power PAD of the low-voltage module 3 and the power PAD of VCCIO are connected to VCCQ2.

[0065] In this embodiment, when only the first external power supply is provided to the UFS storage device, the power supply voltage of the physical layer interface 5 inside the controller chip 10 is the second voltage value, and its input and output terminal voltage VCCIO is the first voltage value. The input power supply PAD of the buck circuit 1 is connected to the first external power supply, and the output power supply PAD of the buck circuit 1 is connected to the power supply PAD of the ultra-low voltage module 4 and the power supply PAD of voltage VCCIO, respectively. The boost circuit 2 does not work, and its input power supply PAD and output power supply PAD are disconnected, maintaining the NC state. The power supply PAD of the low voltage module 3 and the power supply PAD of the physical layer interface 5 are connected to the first external power supply.

[0066] Furthermore, such as Figure 5 As shown, when only VCCQ2 power is supplied externally to the UFS storage device, the power supply voltage of the physical layer interface 5 within the controller chip 10 is 1.8V, and its input / output voltage VCCIO is 1.2V. The input power PAD of the buck circuit 1 is wired to VCCQ2, and the output power PAD of the buck circuit 1 is wired to the power PAD of the ultra-low voltage module 4 and the power PAD of VCCIO. The boost circuit 2 is not working; its input and output power PADs are not wired, maintaining the NC state. The power PADs of the low-voltage module 3 and the physical layer interface 5 are connected to VCCQ2.

[0067] In this embodiment, when only a second external power supply is provided to the UFS storage device, the power supply voltage of the physical layer interface 5 inside the controller chip 10 is the second voltage value, and its input and output terminal voltage VCCIO is the second voltage value. The input power supply PAD of the boost circuit 2 is connected to the second external power supply, and the output power supply PAD of the boost circuit 2 is connected to the power supply PAD of the low-voltage module 3, the power supply PAD of the physical layer interface 5, and the power supply PAD of voltage VCCIO, respectively. The buck circuit 1 does not work, and its input power supply PAD and output power supply PAD are disconnected, maintaining the NC state. The power supply PAD of the ultra-low voltage module 4 is connected to the second external power supply.

[0068] Furthermore, such as Figure 7 As shown, when only VCCQ power is supplied externally to the UFS storage device, the power supply voltage of the physical layer interface 5 within the controller chip 10 is 1.8V, and its input / output voltage VCCIO is 1.8V. The input power PAD of the boost circuit 2 is wired to VCCQ, and the output power PAD of the boost circuit 2 is wired to the power PAD of the low-voltage module 3, the power PAD of the physical layer interface 5, and the power PAD of VCCIO. The buck circuit 1 is not working; its input and output power PADs are not wired, maintaining the NC state. The power PAD of the ultra-low voltage module 4 is connected to VCCQ.

[0069] In this embodiment, when only a second external power supply is provided to the UFS storage device, the power supply voltage of the physical layer interface 5 inside the controller chip 10 is the first voltage value, and its input and output terminal voltage VCCIO is the second voltage value. The input power supply PAD of the boost circuit 2 is connected to the second external power supply, and the output power supply PAD of the boost circuit 2 is connected to the power supply PAD of the low-voltage module 3 and the power supply PAD of voltage VCCIO. The buck circuit 1 does not work, and its input power supply PAD and output power supply PAD are disconnected, maintaining the NC state. The power supply PAD of the ultra-low voltage module 4 and the power supply PAD of the physical layer interface 5 are connected to the second external power supply.

[0070] Furthermore, such as Figure 8 As shown, when only VCCQ power is supplied externally to the UFS storage device, the power supply voltage of the physical layer interface 5 within the controller chip 10 is 1.2V, and its input / output voltage VCCIO is 1.8V. The input power PAD of the boost circuit 2 is wired to VCCQ, and the output power PAD of the boost circuit 2 is wired to the power PAD of the low-voltage module 3 and the power PAD of VCCIO. The buck circuit 1 is not working; its input and output power PADs are not wired, maintaining the NC state. The power PAD of the ultra-low voltage module 4 and the power PAD of the physical layer interface 5 are connected to VCCQ.

[0071] In this embodiment, when only a second external power supply is provided to the UFS storage device, the power supply voltage of the physical layer interface 5 inside the controller chip 10 is the second voltage value, and its input and output terminal voltage VCCIO is the first voltage value. The input power supply PAD of the boost circuit 2 is connected to the second external power supply, and the output power supply PAD of the boost circuit 2 is connected to the power supply PAD of the low-voltage module 3 and the power supply PAD of the physical layer interface 5. The buck circuit 1 does not work, and its input power supply PAD and output power supply PAD are disconnected, maintaining the NC state. The power supply PAD of the ultra-low voltage module 4 and the power supply PAD of voltage VCCIO are connected to the second external power supply.

[0072] like Figure 9 As shown, when only VCCQ power is supplied externally to the UFS storage device, the power supply voltage of the physical layer interface 5 within the controller chip 10 is 1.8V, and its input / output voltage VCCIO is 1.2V. The input power PAD of the boost circuit 2 is wired to VCCQ, and the output power PAD of the boost circuit 2 is wired to the power PAD of the low-voltage module 3 and the power PAD of the physical layer interface 5. The buck circuit 1 is not working; its input and output power PADs are not wired, maintaining the NC state. The power PADs of the ultra-low voltage module 4 and VCCIO are connected to VCCQ.

[0073] Therefore, this invention reduces the number of external power supplies for UFS storage devices from two to one, allowing the storage device controller to support hardware power solutions with a single power supply VCCQ or a single power supply VCCQ2. This directly reduces the cost of the PMU (Power Management Unit) and provides more layout and routing space for PCB design, resulting in better performance for high-speed PCB design. This invention also allows for variations in the operating voltage of individual modules within the UFS storage device controller, enabling the same controller chip 10 to be manufactured on multiple semiconductor manufacturing platforms, significantly improving the speed of product performance upgrades. Furthermore, the same controller chip 10 can adapt to the input / output voltages VCCIO of different flash memory chips, providing better flash memory chip compatibility.

[0074] The above embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of protection of the present invention. Any non-substantial changes and substitutions made by those skilled in the art based on the present invention shall fall within the scope of protection claimed by the present invention.

Claims

1. A UFS storage device supporting single-channel power supply, comprising a controller chip and a flash memory chip, wherein the input / output terminals of the controller chip are connected to the input / output terminals of the flash memory chip, and the flash memory chip is connected to a VCC power supply, characterized in that: The controller chip is connected to a single external power supply. The controller chip integrates a buck circuit, a boost circuit, a low-voltage module, an ultra-low-voltage module, and a physical layer interface. The buck circuit has an input power PAD and an output power PAD, which reduces the power supply voltage of the single external power supply to a first voltage value to power all modules within the UFS storage device that have a power supply voltage of the first voltage value. The boost circuit has an input power PAD and an output power PAD, which boosts the power supply voltage of the single external power supply to a second voltage value to power all modules within the UFS storage device that have a power supply voltage of the second voltage value. When only the first external power supply is provided to the UFS storage device, the physical layer interface power supply voltage in the controller chip is the first voltage value, and its input and output voltage VCCIO is the first voltage value. The input power supply PAD of the buck circuit is connected to the first external power supply, and the output power supply PAD of the buck circuit is connected to the power supply PAD of the physical layer interface, the power supply PAD of the ultra-low voltage module, and the power supply PAD of voltage VCCIO, respectively. The boost circuit does not work, and its input power supply PAD and output power supply PAD are disconnected, maintaining the NC state. The low voltage module power supply PAD is connected to the first external power supply. When only a second external power supply is provided to the UFS storage device, the physical layer interface power supply voltage in the controller chip is the first voltage value, and its input and output voltage VCCIO is the first voltage value. The input power supply PAD of the boost circuit is connected to the second external power supply, and the output power supply PAD of the boost circuit is connected to the power supply PAD of the low-voltage module. The buck circuit does not work, and its input power supply PAD and output power supply PAD are disconnected, maintaining the NC state. The power supply PAD of the physical layer interface, the power supply PAD of the ultra-low voltage module, and the power supply PAD of voltage VCCIO are connected to the second external power supply. The power supply voltage provided by the first external power source is greater than the power supply voltage provided by the second external power source.

2. The UFS storage device according to claim 1, characterized in that: The low-voltage module is used to operate at a fixed second voltage value to meet the circuit requirements of high voltage swing, and the ultra-low-voltage module is used to operate at a fixed first voltage value to meet the design requirements of high-speed mixed signals.

3. The UFS storage device according to claim 1, characterized in that: When only the first external power supply is provided to the UFS storage device, the physical layer interface power supply voltage inside the controller chip is the second voltage value, and its input and output terminal voltage VCCIO is the second voltage value. The input power supply PAD of the buck circuit is connected to the first external power supply, and the output power supply PAD of the buck circuit is connected to the power supply PAD of the ultra-low voltage module. The boost circuit does not work, and its input power supply PAD and output power supply PAD are disconnected, maintaining the NC state. The power supply PAD of the low voltage module, the power supply PAD of the physical layer interface, and the power supply PAD of voltage VCCIO are connected to the first external power supply.

4. The UFS storage device according to claim 1, characterized in that: When only the first external power supply is provided to the UFS storage device, the physical layer interface power supply voltage in the controller chip is the first voltage value, and its input / output terminal voltage VCCIO is the second voltage value. The input power supply PAD of the buck circuit is connected to the first external power supply, and the output power supply PAD of the buck circuit is connected to the power supply PAD of the ultra-low voltage module and the power supply PAD of the physical layer interface respectively. The boost circuit does not work, and its input power supply PAD and output power supply PAD are disconnected, maintaining the NC state. The power supply PAD of the low voltage module and the power supply PAD of voltage VCCIO are connected to the first external power supply.

5. The UFS storage device according to claim 1, characterized in that: When only the first external power supply is provided to the UFS storage device, the physical layer interface power supply voltage in the controller chip is the second voltage value, and its input / output terminal voltage VCCIO is the first voltage value. The input power supply PAD of the buck circuit is connected to the first external power supply, and the output power supply PAD of the buck circuit is connected to the power supply PAD of the ultra-low voltage module and the power supply PAD of voltage VCCIO respectively. The boost circuit does not work, and its input power supply PAD and output power supply PAD are disconnected, maintaining the NC state. The power supply PAD of the low voltage module and the power supply PAD of the physical layer interface are connected to the first external power supply.

6. The UFS storage device according to claim 1, characterized in that: When only a second external power supply is provided to the UFS storage device, the physical layer interface power supply voltage inside the controller chip is the second voltage value, and its input and output terminal voltage VCCIO is the second voltage value. Connect the input power supply PAD of the boost circuit to the second external power supply, and connect the output power supply PAD of the boost circuit to the power supply PAD of the low-voltage module, the power supply PAD of the physical layer interface, and the power supply PAD of voltage VCCIO respectively. The buck circuit does not work, and its input power supply PAD and output power supply PAD are disconnected, maintaining the NC state. Connect the power supply PAD of the ultra-low voltage module to the second external power supply.

7. The UFS storage device according to claim 1, characterized in that: When only a second external power supply is provided to the UFS storage device, the physical layer interface power supply voltage inside the controller chip is the first voltage value, and its input / output terminal voltage VCCIO is the second voltage value. The input power supply PAD of the boost circuit is connected to the second external power supply, and the output power supply PAD of the boost circuit is connected to the power supply PAD of the low-voltage module and the power supply PAD of voltage VCCIO. The buck circuit does not work, and its input power supply PAD and output power supply PAD are disconnected, maintaining the NC state. The power supply PAD of the ultra-low voltage module and the power supply PAD of the physical layer interface are connected to the second external power supply.

8. The UFS storage device according to claim 1, characterized in that: When only a second external power supply is provided to the UFS storage device, the physical layer interface power supply voltage inside the controller chip is the second voltage value, and its input / output terminal voltage VCCIO is the first voltage value. The input power supply PAD of the boost circuit is connected to the second external power supply, and the output power supply PAD of the boost circuit is connected to the power supply PAD of the low-voltage module and the power supply PAD of the physical layer interface. The buck circuit does not work, and its input power supply PAD and output power supply PAD are disconnected, maintaining the NC state. The power supply PAD of the ultra-low voltage module and the power supply PAD of voltage VCCIO are connected to the second external power supply.

9. The UFS storage device according to any one of claims 1 to 8, characterized in that: The first external power source provides a second voltage value, and the second external power source provides a first voltage value.

Images