Chip testing circuit and memory

Abstract

The application provides a chip test circuit and a memory, including: a sampling module samples a plurality of consecutive chip select signals based on a sampling clock, and data sampled based on an odd clock is referred to as odd data, and data sampled based on an even clock is referred to as even data; an operation module performs comparison operation based on the odd data and the even data to obtain an operation result; and an output module acquires the operation result in real time when an output clock is in a first state, and is configured to latch the current operation result, stop acquiring a new operation result, and output the latched operation result when the output clock is in a second state, the first state and the second state are opposite to each other, the period of the output clock is the length of a single chip select signal, and the rising edge of the output clock is aligned with the rising edge of the sampling clock of the chip select signal sampled first. The scheme can realize accurate and reliable chip select signal test.

Description

Technical Field

[0001] This application relates to memory technology, and more particularly to a chip test circuit and a memory. Background Technology

[0002] With the development of memory technology, memory has been widely used in many fields. For example, Dynamic Random Access Memory (DRAM) is widely used.

[0003] In practical applications, signal testing is typically required to ensure the normal operation of memory. For example, chip select (CS) signal pin timing margin is improved through CS training. Therefore, a solution is needed to implement CS testing. Summary of the Invention

[0004] Embodiments of this application provide a chip test circuit and a memory.

[0005] According to some embodiments, a first aspect of this application provides a chip test circuit, comprising: a sampling module for sampling a plurality of consecutive chip select signals based on a sampling clock, wherein the holding duration of each data bit of the chip select signal is equal to the period of the system clock, the sampling clock includes an odd clock and an even clock with opposite phases, the period of the odd clock and the even clock being equal to twice the period of the system clock, and the data sampled based on the odd clock is denoted as odd data, and the data sampled based on the even clock is denoted as even data; an arithmetic module connected to the sampling module for performing a comparison operation based on the odd data and the even data to obtain an operation result; and an output module connected to the arithmetic module for acquiring the operation result in real time when the output clock is in a first state, and for latching the current operation result and stopping the acquisition of new operation results and outputting the latched operation result when the output clock is in a second state, wherein the first state and the second state are inverses of each other, the period of the output clock is the length of a single chip select signal, and the rising edge of the output clock is aligned with the rising edge of the sampling clock that first sampled the chip select signal.

[0006] In some embodiments, each chip select signal includes four data bits.

[0007] In some embodiments, the arithmetic module includes: a first delay unit, a second delay unit, a first arithmetic unit, and a second arithmetic unit; the first delay unit, connected to the sampling module, is used to sequentially delay odd data at predetermined time intervals to obtain first delayed odd data, second delayed odd data, third delayed odd data, and fourth delayed odd data; the second delay unit, connected to the sampling module, is used to sequentially delay even data at time intervals to obtain first delayed even data, second delayed even data, third delayed even data, and fourth delayed even data; the input terminal of the first arithmetic unit is connected to the first delay unit and the second delay unit, and the first arithmetic unit is used for... The first arithmetic unit receives first delayed even data, second delayed odd data, third delayed even data, and fourth delayed odd data, and compares the first delayed even data and the second delayed odd data, as well as comparing the third delayed even data and the fourth delayed odd data; the output of the first arithmetic unit is connected to the output module; the input of the second arithmetic unit is connected to the first delay unit and the second delay unit, and the second arithmetic unit is used to receive first delayed odd data, second delayed even data, third delayed odd data, and fourth delayed even data, and compare the first delayed odd data and the second delayed even data, as well as comparing the third delayed odd data and the fourth delayed even data; the output of the second arithmetic unit is connected to the output module.

[0008] In some embodiments, the first arithmetic unit includes: a first NOT gate and a second NOT gate, a first NAND gate and a second NAND gate, and a first NOR gate; the input of the first NOT gate receives first delayed even data, and the output of the first NOT gate is connected to the first input of the first NAND gate; the second input of the first NAND gate receives second delayed odd data, and the output of the first NAND gate is connected to the first input of the first NOR gate; the input of the second NOT gate receives third delayed even data, and the output of the second NOT gate is connected to the first input of the second NAND gate; the second input of the second NAND gate receives fourth delayed odd data, and the output of the second NAND gate is connected to the second input of the first NOR gate; the output of the first NOR gate is connected to the output modulo gate. The block is connected; the second arithmetic unit includes: a third NOT gate and a fourth NOT gate, a third NAND gate and a fourth NAND gate, and a second NOR gate; the input of the third NOT gate receives first delayed odd data, and the output of the third NOT gate is connected to the first input of the third NAND gate; the second input of the third NAND gate receives second delayed even data, and the output of the third NAND gate is connected to the first input of the second NOR gate; the input of the fourth NOT gate receives third delayed odd data, and the output of the fourth NOT gate is connected to the first input of the fourth NAND gate; the second input of the fourth NAND gate receives fourth delayed even data, and the output of the fourth NAND gate is connected to the second input of the second NOR gate; the output of the second NOR gate is connected to the output module.

[0009] In some embodiments, the first delay unit includes: a plurality of first delay sub-units connected in series; the input terminal of the first first delay sub-unit is connected to the sampling module for receiving first delayed odd data generated based on odd data; the input terminal of each first delay sub-unit is connected to the output terminal of the previous first delay sub-unit, and each first delay sub-unit is used to output the received data after a time interval; the second delay unit includes: a plurality of second delay sub-units connected in series; the input terminal of the first second delay sub-unit is connected to the sampling module for receiving first delayed even data generated based on even data; the input terminal of each second delay sub-unit is connected to the output terminal of the previous second delay sub-unit, and each second delay sub-unit is used to output the received data after a time interval.

[0010] In some embodiments, each first delay sub-unit includes a first flip-flop and a fifth NOT gate. The input of the first flip-flop serves as the input of the first delay sub-unit, and the output of the first flip-flop is connected to the input of the fifth NOT gate. The output of the fifth NOT gate serves as the output of the first delay sub-unit. The clock terminal of the odd-numbered first flip-flop is connected to the inverted signal of an odd clock, and the clock terminal of the even-numbered first flip-flop is connected to an odd clock. Each second delay sub-unit includes a second flip-flop and a sixth NOT gate. The input of the second flip-flop serves as the input of the second delay sub-unit, and the inverted output of the second flip-flop is connected to the input of the sixth NOT gate. The output of the sixth NOT gate serves as the output of the second delay sub-unit. The clock terminal of the odd-numbered second flip-flop is connected to the inverted signal of an even clock, and the clock terminal of the even-numbered second flip-flop is connected to an even clock.

[0011] In some embodiments, the arithmetic module further includes: a first enabling unit connected to the sampling module and the first delay unit, configured to, in response to an enabling signal, transmit the odd data sampled by the sampling module to the input terminal of the first delay unit and use it as first delayed odd data; and a second enabling unit connected to the sampling module and the second delay unit, configured to, in response to an enabling signal, transmit the even data sampled by the sampling module to the input terminal of the second delay unit and use it as first delayed even data.

[0012] In some embodiments, the output clock includes a first output clock and a second output clock with opposite phases; at the same time, either the first output clock or the second output clock is valid; wherein the validity of either output clock indicates that the sampling clock corresponding to that output clock samples the chip select signal first.

[0013] In some embodiments, the output module includes: a first output unit and a second output unit, the output terminals of the first output unit and the second output unit being connected; the input terminal of the first output unit is connected to the first arithmetic unit, and is configured to, in response to the first output clock being valid, acquire the calculation result output by the first arithmetic unit in real time when the first output clock is in a first state; and, when the first output clock is in a second state, latch the current calculation result and stop acquiring new calculation results and output the latched calculation result; the input terminal of the second output unit is connected to the second arithmetic unit, and is configured to, in response to the second output clock being valid, acquire the calculation result output by the second arithmetic unit in real time when the second output clock is in a first state; and, when the second output clock is in a second state, latch the current calculation result and stop acquiring new calculation results and output the latched calculation result.

[0014] In some embodiments, the first output unit includes: a first transmission unit, a first latch unit, and a second transmission unit; wherein, the first transmission unit is connected to the first arithmetic unit and is configured to transmit the inverted signal of the operation result of the first arithmetic unit to the first latch unit when the first output clock is in a first state, and to stop transmission when the first output clock is in a second state; the first latch unit is configured to transmit the inverted signal of the operation result to the second transmission unit when the first output clock is in the first state, and to latch the current operation result when the first output clock is in the second state; the second transmission unit is connected to the first latch unit and is configured to stop output when the first output clock is in the first state, and to output the operation result latched by the first latch unit when the first output clock is in the second state. The calculation result is calculated; the second output unit includes: a third transmission unit, a second latch unit, and a fourth transmission unit; wherein, the third transmission unit is connected to the second arithmetic unit and is used to transmit the inverted signal of the calculation result of the second arithmetic unit to the second latch unit when the second output clock is in the first state, and to stop transmission when the second output clock is in the second state; the second latch unit is used to transmit the inverted signal of the calculation result to the fourth transmission unit when the second output clock is in the first state, and to latch the current calculation result when the second output clock is in the second state; the fourth transmission unit is connected to the second latch unit and is used to stop output when the second output clock is in the first state, and to output the calculation result latched by the second latch unit when the second output clock is in the second state.

[0015] In some embodiments, the first transmission unit includes a first inverter, a first switch, and a second switch; one end of the first switch is connected to a power supply signal, the other end of the first switch is connected to the power supply terminal of the first inverter, and the control terminal of the first switch is connected to a first output clock; the input terminal of the first inverter is connected to a first arithmetic unit, and the ground terminal of the first inverter is connected to one end of the second switch; the other end of the second switch is grounded, and the control terminal of the second switch is connected to the inverted signal of the first output clock; the first latch unit includes a ninth NOT gate and a first tri-state NOT gate; the input terminal of the ninth NOT gate is connected to the output terminal of the first inverter and the output terminal of the first tri-state NOT gate. The output of the ninth NOT gate is connected to the input of the first tri-state NOT gate; the control terminal of the first tri-state NOT gate is connected to the first output clock; the second transmission unit includes a second inverter, a third switch, and a fourth switch; one end of the third switch is connected to the power supply signal, the other end of the third switch is connected to the power supply terminal of the second inverter, and the control terminal of the third switch is connected to the inverted signal of the first output clock; the input of the second inverter is connected to the output of the ninth NOT gate, the output of the second inverter is used to output the calculation result, the ground terminal of the second inverter is connected to one end of the fourth switch; the other end of the fourth switch is grounded, and the control terminal of the fourth switch is connected to the first output clock.

[0016] In some embodiments, the third transmission unit includes a third inverter, a fifth switch, and a sixth switch; one end of the fifth switch is connected to a power supply signal, the other end of the fifth switch is connected to the power supply terminal of the third inverter, and the control terminal of the fifth switch is connected to a second output clock; the input terminal of the third inverter is connected to a second arithmetic unit, and the ground terminal of the third inverter is connected to one end of the sixth switch; the other end of the sixth switch is grounded, and the control terminal of the sixth switch is connected to the inverted signal of the second output clock; the second latch unit includes a tenth NOT gate and a second tri-state NOT gate; the input terminal of the tenth NOT gate is connected to the output terminal of the third inverter and the output terminal of the second tri-state NOT gate. The output of the tenth NOT gate is connected to the input of the second tri-state NOT gate; the control terminal of the second tri-state NOT gate is connected to the second output clock; the fourth transmission unit includes a fourth inverter, a seventh switch, and an eighth switch; one end of the seventh switch is connected to the power supply signal, the other end of the seventh switch is connected to the power supply terminal of the fourth inverter, and the control terminal of the seventh switch is connected to the inverted signal of the second output clock; the input of the fourth inverter is connected to the output of the tenth NOT gate, the output of the fourth inverter is used to output the calculation result, the ground terminal of the fourth inverter is connected to one end of the eighth switch; the other end of the eighth switch is grounded, and the control terminal of the eighth switch is connected to the second output clock.

[0017] In some embodiments, the time interval is one system clock cycle.

[0018] According to some embodiments, a second aspect of this application provides a memory including: a chip test circuit as described above.

[0019] In the chip test circuit and memory provided in this application embodiment, the sampling module samples multiple consecutive chip select signals based on odd and even clocks to obtain odd and even data. The calculation module performs comparison calculations based on the odd and even data to obtain the calculation result. The output module outputs the calculation result in response to the output clock. Based on the calculation result, it is possible to detect whether the chip select signal is normal. Through the above scheme, the acquisition, calculation, and output of the calculation result of each data bit in the chip select signal are realized based on odd and even clocks with a clock period twice the system clock period. This ensures accurate and reliable sampling while obtaining and outputting the calculation result based on the complete chip select signal, thus achieving accurate and reliable chip select signal testing. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of the embodiments of this application.

[0021] Figure 1 This is an example diagram of the architecture of a memory according to an embodiment of this application;

[0022] Figure 2 This is a structural example diagram of a storage cell shown in one embodiment of this application;

[0023] Figure 3 The storage topology is shown in the example.

[0024] Figure 4 A structural example diagram of a chip test circuit provided in one embodiment;

[0025] Figure 5 and Figure 6 This is a timing example diagram for sampling;

[0026] Figure 7 A structural example diagram of a computing module provided in one embodiment;

[0027] Figure 8 and Figure 9 A time-series example diagram of a data sequence;

[0028] Figure 10 Structural example diagrams of the first and second arithmetic units provided in one embodiment;

[0029] Figure 11 and Figure 12 Here are example diagrams of the structure of the first and second delay units;

[0030] Figure 13 A structural example diagram of a computing module provided in one embodiment;

[0031] Figure 14A structural example diagram of an output module provided in one embodiment;

[0032] Figure 15 This is a structural example diagram of the first output unit and the second output unit.

[0033] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0034] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0035] The terms "comprising" and "having" in this application are used to indicate an open-ended inclusion, meaning that additional elements / components / etc. may exist besides those listed. The terms "first" and "second," etc., are used only as markings or distinctions and are not intended to limit the order or quantity of the objects. Furthermore, the different elements and areas in the accompanying drawings are only schematic and are therefore not limited to the dimensions or distances shown in the drawings.

[0036] The technical solution will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0037] Figure 1 This is an example diagram of the memory architecture shown in one embodiment of this application, such as... Figure 1 As shown, taking DRAM as an example, it includes data input / output buffers, row decoders, column decoders, sense amplifiers, and a memory array. The memory array mainly consists of word lines, bit lines, and memory cells. Word lines in the memory array extend along the row direction, and bit lines extend along the column direction. The intersection of word lines and bit lines is the memory cell of the memory array.

[0038] Each storage unit is used to store one bit of data. For example... Figure 2 As shown, Figure 2This is a structural example diagram of a memory cell according to an embodiment of this application. The memory cell mainly consists of a transistor M and a capacitor C. The capacitor is used to store data, and the transistor is used to turn off or on depending on the word line state.

[0039] Access to a memory cell can be achieved by controlling rows and columns. Taking a read scenario as an example: when data needs to be read from a memory cell, the word line of the row containing that memory cell is selected using a row decoder. Correspondingly, transistor M in the diagram turns on, and the state of capacitor C can be detected by sensing and amplifying the bit line signal. For example, if the data stored in the memory cell is 1, then after transistor M turns on, 1 will be read from the bit line of the memory cell, and vice versa. Furthermore, taking a write scenario as an example: when data needs to be written to a memory cell, such as writing 1, the word line of the row containing that memory cell is selected using a row decoder. The corresponding transistor M in the diagram turns on, and by setting the logic level of the bit line to 1, capacitor C is charged, thus writing 1 to the memory cell. Conversely, to write 0, the logic level of the bit line is set to 0, causing capacitor C to discharge, thus writing 0 to the memory cell.

[0040] In practical applications, multiple memory chips are typically used to increase storage capacity. For example, Figure 3 This diagram illustrates a storage topology. It should be noted that this is merely an example; various chip topologies exist in related technologies, including but not limited to dual-T architectures and Fly-By topologies, and no limitation is made here. Referring to the example, when accessing a specific memory cell is required, the memory chip containing that cell must first be selected—this is called chip selection. For instance, when the chip select signal for a memory chip is latched high, all commands are ignored, meaning the chip is not selected; conversely, if it is low, the chip is selected and commands can be executed. Then, the corresponding memory cell is selected from the selected chips based on its address information, thereby enabling access to that memory cell, such as for data storage or retrieval. It is evident that the chip select signal affects whether the desired memory cell can be successfully addressed.

[0041] Therefore, relevant standards specify content related to chip select signal testing. As an example, during the test, a sample signal is sent to the memory. The memory performs calculations based on the sampled chip select signal to obtain the result. If the result matches the standard result, it indicates that the memory can receive the chip select signal normally, and the CS test passes; otherwise, it indicates that the memory cannot correctly receive the chip select signal. For example, Table 1 below shows an example chip select test sample signal and the corresponding standard result:

[0042] Table 1

[0043] 1 0 0 0 0 0 1 0 0 1 0 1 0 1 1 0 1 0 1 0 1 1 1 1

[0044] In this diagram, Sample0 to Sample3 represent the data bits of the test samples, output is the corresponding standard result, and output_B is the inverted result of the standard result. For example, Sample0 to Sample3 in the first row represent a set of test samples with the value 0000. Assuming the memory can correctly receive the chip select signal, the result of the operation based on the data bits of the chip select signal received by the memory should be 1. If the test sample is 0101, the corresponding standard result is 0; if the test sample is 1011, the corresponding standard result is 1; and if the test sample is 1111, the corresponding standard result is 1. In related technologies, the chip select signal is acquired once per system clock cycle.

[0045] Taking Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) as an example, the DDR5 standard specifies a Chip Select Testing Mode (CSTM) to provide an independent mode for CS testing. Once in CSTM mode, the DRAM samples the received CS signal on the rising edge of the clock. Specifically, the Multi Purpose Command (MPC) can be used to enter and exit CSTM mode. Considering that different memories support different operating frequencies—for example, the maximum frequency of DDR4 is no more than 3200 MHz—the sampling period can ensure reliable sampling. DDR5, however, has a maximum frequency of 6400 MHz, twice that of DDR4. It is clear that DDR5's speed and frequency are significantly higher than DDR4, thus placing higher demands on the reliability of CS testing.

[0046] Some aspects of the embodiments of this application relate to the above considerations. The following describes the solutions with reference to some embodiments of this application.

[0047] Example 1

[0048] Figure 4 A structural example diagram of a chip test circuit provided in one embodiment is shown below. Figure 4 As shown, the chip test circuit includes:

[0049] The sampling module 11 is used to sample multiple consecutive chip select signals based on a sampling clock. The holding time of each data bit of the chip select signal is equal to the period of the system clock. The sampling clock includes odd clock and even clock with opposite phases. The period of the odd clock and even clock is equal to twice the period of the system clock. The data sampled based on the odd clock is called odd data, and the data sampled based on the even clock is called even data.

[0050] The calculation module 12, connected to the sampling module 11, is used to perform comparison calculations based on odd and even data to obtain the calculation results;

[0051] The output module 13 is connected to the arithmetic module 12. It is used to acquire the arithmetic result in real time when the output clock is in the first state, and to latch the current arithmetic result and stop acquiring new arithmetic results and output the latched arithmetic result when the output clock is in the second state. The first state and the second state are inverses of each other. The period of the output clock is the length of a single chip select signal. The rising edge of the output clock is aligned with the rising edge of the sampling clock that first samples the chip select signal.

[0052] In practical applications, the chip test circuit provided in this embodiment can be used in various memories. For example, it can be applied to, but is not limited to, Double Data Rate Synchronous Dynamic Random Access Memory (DDR). Each chip select signal includes at least one data bit. In one example, considering a memory scenario, each chip select signal includes four data bits.

[0053] Taking DDR5 as an example, and illustrating with a practical scenario: When CS testing is required, CSTM mode can be initiated. Considering the high speed of DDR5, to ensure sampling reliability, this embodiment uses odd and even clocks for sampling, and the corresponding sampled signals are called odd data and even data, respectively. The odd and even clocks have opposite phases and their periods are twice the system clock period. Therefore, this provides a sufficient sampling window for the chip select signal, avoiding sampling errors and failures, and ensuring the accuracy of the CS test.

[0054] As an example, the chip select signal can be sampled at the rising edges of odd and even clocks. It should be noted that "odd data" and "even data" here are merely names for the data acquired in response to odd and even clocks, and do not limit the specific content of the sampled data or its parity attribute in the chip select signal. For example, odd data sampled in response to an odd clock might be data located in the odd-numbered bits of the chip select signal; for instance, in an eight-bit data set D0-D7, D0, D2, D4, etc., are data located in the odd-numbered bits. Alternatively, odd data could also be data located in the even-numbered bits, such as D1, D3, D5, etc. Similarly, "even data" could refer to data in the even-numbered bits of the chip select signal; in short, the names here do not limit the specific data bits.

[0055] Combination Figure 5 and Figure 6 Example: Figure 5 and Figure 6 This is a timing example diagram for sampling. CS is the chip select signal, CLK is the system clock, CLK_E is the even clock, and CLK_O is the odd clock. Odd data obtained from sampling based on the odd clock is ODD, and even data obtained from sampling based on the even clock is EVEN. The diagram also shows two scenarios: one where the chip select signal D0 is sampled first in response to the odd clock, and the other where it is sampled first in response to the even clock. Subsequently, based on the sampled odd and even data, a complete continuous chip select signal (D0~D7 in the example) is obtained for chip select test calculations. The chip select test calculation is used to perform a predetermined algorithm operation based on the test sample. The result is used to determine whether the actual sampled signal and the test sample are consistent. If they are consistent, it indicates that the chip select signal is functioning normally. As an example, the calculation result is obtained by performing a comparison operation. It should be noted that this is only an example; in practical applications, other calculation methods can also be combined to perform calculations on the test sample.

[0056] In one example Figure 7 A structural example diagram of a computing module provided in one embodiment is shown below. Figure 7 As shown, the arithmetic module 12 includes: a first delay unit 21, a second delay unit 22, a first arithmetic unit 23, and a second arithmetic unit 24;

[0057] The first delay unit 21 is connected to the sampling module 11 and is used to output the odd data ODD sequentially at predetermined time intervals to obtain the first delayed odd data ODD1, the second delayed odd data ODD2, the third delayed odd data ODD3 and the fourth delayed odd data ODD4.

[0058] The second delay unit 22 is connected to the sampling module 11 and is used to output the even data EVEN sequentially according to the time interval to obtain the first delayed even data EVEN1, the second delayed even data EVEN2, the third delayed even data EVEN3 and the fourth delayed even data EVEN4.

[0059] The input terminal of the first arithmetic unit 23 is connected to the first delay unit 21 and the second delay unit 22. The first arithmetic unit 23 is used to receive the first delayed even data EVEN1, the second delayed odd data ODD2, the third delayed even data EVEN3 and the fourth delayed odd data ODD4, and compare the first delayed even data EVEN1 and the second delayed odd data ODD2, as well as compare the third delayed even data EVEN3 and the fourth delayed odd data ODD4. The output terminal of the first arithmetic unit 23 is connected to the output module 13.

[0060] The input terminal of the second arithmetic unit 24 is connected to the first delay unit 21 and the second delay unit 22. The second arithmetic unit 24 is used to receive the first delayed odd data ODD1, the second delayed even data EVEN2, the third delayed odd data ODD3 and the fourth delayed even data EVEN4, and compare the first delayed odd data ODD1 and the second delayed even data EVEN2, as well as compare the third delayed odd data ODD3 and the fourth delayed even data EVEN4. The output terminal of the second arithmetic unit 24 is connected to the output module 13.

[0061] In one example, the time interval is one system clock cycle. Combined Figure 8 and Figure 9 Example: Figure 8 and Figure 9 This is a timing example diagram of the data sequence. The data sequence is generated by the first and second delay units based on the sampled odd and even data. For example, the data sequence includes ODD1~ODD4 output by the first delay unit and EVEN1~EVEN4 output by the second delay unit. Specifically, since this embodiment uses odd and even clocks to sample the chip select signal, before performing the chip select test operation, it is necessary to integrate the sampled odd and even data to generate two complete chip select signals D0~D3 and D4~D7. In this example, the first and second arithmetic units correspond to the two cases mentioned above, combined with... Figure 8 For example, when the sampling module samples the chip select signal D0 in response to an odd clock, the first arithmetic unit receives the first delayed even data EVEN1, the second delayed odd data ODD2, the third delayed even data EVEN3, and the fourth delayed odd data ODD4, which can form a complete chip select signal before the end of the period corresponding to each chip select signal (for example, the period corresponding to chip select signals D0 to D3 in the figure is four system clock cycles). Figure 8As shown, after the rising edge of the system clock corresponding to data bit D3, the EVEN1, ODD2, EVEN3 and ODD4 received by the first arithmetic unit form a complete chip select signal D3 to D0.

[0062] like Figure 8 For example, in the case where the chip select signal D0 is sampled first in response to an odd clock, the first delayed even data EVEN1, the second delayed odd data ODD2, the third delayed even data EVEN3, and the fourth delayed odd data ODD4 can form two complete chip select signals, D3~D0 and D7~D4, respectively, in two specific time periods. Similarly, as... Figure 9 As shown, in the case where the chip select signal D0 is sampled first in response to an even clock, two complete chip select signals, D3~D0 and D7~D4, can be formed from the first delayed odd data ODD1, the second delayed even data EVEN2, the third delayed odd data ODD3, and the fourth delayed even data EVEN4, within two specific time periods. These specific time periods are determined based on time intervals. Referring to the example in the figure, after the last data bit of the chip select signal (e.g., D3) is sampled, and before the sampling of the next chip select signal begins, such as before D4 is sampled, a complete chip select signal can be formed based on the delayed odd and delayed even data in both cases. It should be noted that the sampling clock corresponding to D3 or D4 may be different in different cases. Figure 8 As shown, D3 is sampled in response to the rising edge of the even clock CLK_E, and D4 is sampled in response to the rising edge of the odd clock CLK_O. Figure 9 In this example, D3 is sampled in response to the rising edge of the odd clock CLK_O, and D4 is sampled in response to the rising edge of the even clock CLK_E. This depends on which sampling clock samples the chip select signal first, so the timing at which a data bit is sampled in this example does not restrict the type of sampling clock.

[0063] Specifically, the first and second arithmetic units compare the received signals to obtain the calculation result, which is then output to the output module. In some examples, the first and second arithmetic units can perform calculations in real time; in this embodiment, there is no need to set up a dedicated control signal to control the operation of the arithmetic units. As an example, combined with... Figure 8 and Figure 9 As shown, in reality, the ODD1~ODD4 and EVEN~EVEN4 signals are updated in response to each rising edge of the system clock. Correspondingly, the first and second arithmetic units perform calculations in real time and output the updated results. However, combined with... Figure 8 For example, in reality, only half a system clock cycle before the end of the cycle corresponding to a chip select signal (e.g., D0~D3), for example, Figure 8After the rising edge of the system clock corresponding to D3, the data sequences corresponding to odd data (ODD2 and ODD4) and the data sequences corresponding to even data (EVEN1 and EVEN3) form a complete chip select signal D0 to D3, until the next chip select signal D4 to D7 begins sampling.

[0064] Based on the above characteristics, in this embodiment, the period of the output clock is the length of a single chip select signal, and the rising edge of the output clock is aligned with the rising edge of the sampling clock that first samples the chip select signal. Combined with... Figure 8 and Figure 9 Where CLK_2_O is the output clock response when the chip select signal is sampled first by an odd clock, and CLK_2_E is the output clock response when the chip select signal is sampled first by an even clock. The output clock has a first state and a second state. As an example, the first state of the output clock in the figure is a low level state, and the second state of the output clock is a high level state. Figure 9 As an example, Figure 9 This illustrates the case where, in response to the even clock first sampling the chip select signal, the rising edge of the output clock CLK_2_E is aligned with the rising edge of the even clock CLK_E, and the period of the output clock CLK_2_E is the length of a single chip select signal, i.e., four system clock cycles. Figure 9 As shown, after the first rising edge, the output clock CLK_2_E is in the second state. In response to the output clock being in the second state, the output module stops acquiring new calculation results. That is to say, even if the calculation unit outputs the calculation result at this time, the output module does not acquire the result at this time.

[0065] Based on the foregoing, at the beginning of sampling, the first delayed odd data ODD1, the second delayed even data EVEN2, the third delayed odd data ODD3, and the fourth delayed even data EVEN4 do not form a complete chip select signal. Therefore, in this example, in response to the output clock being in the second state, the output module stops acquiring the current calculation result. Afterwards, the output clock flips to the first state, i.e., a low-level state. At this time, the output module acquires the calculation result output by the arithmetic module in real time. However, as mentioned above, the signals received by the arithmetic module still do not form a complete chip select signal. Therefore, the output module only acquires the calculation result but does not output it. This continues until the next rising edge of the output clock arrives (i.e., before the next chip select signal D4~D7 begins sampling), specifically, before the last data bit D3 of the chip select signal is sampled. Figure 9After the rising edge of the system clock corresponding to D3, ODD1, EVEN2, ODD3, and EVEN4 form a complete chip select signal D3-D0. Therefore, when the next rising edge of the output clock arrives, the operation result latched by the output module is precisely the operation result obtained based on the complete chip select signals D3-D0. Thus, in response to the output clock returning to the second state, the output module outputs the currently latched operation result and stops acquiring operation results. This process continues, outputting the operation result based on each complete chip select signal, thereby ensuring sampling accuracy while maintaining timely and accurate output of operation results based on odd and even clocks.

[0066] Specifically, the first and second arithmetic units are used to perform chip select test operations. In one example, Figure 10 Structural example diagrams of the first and second arithmetic units provided in one embodiment, such as... Figure 10 As shown, the first arithmetic unit 23 includes: a first NOT gate 231 and a second NOT gate 232, a first NAND gate 233 and a second NAND gate 234, and a first NOR gate 235; the input of the first NOT gate 231 receives the first delayed even data EVEN1, and the output of the first NOT gate 231 is connected to the first input of the first NAND gate 233; the second input of the first NAND gate 233 receives the second delayed odd data ODD2, and the output of the first NAND gate 233 is connected to the first input of the first NOR gate 235; the input of the second NOT gate 232 receives the third delayed even data EVEN3, and the output of the second NOT gate 232 is connected to the first input of the second NAND gate 234; the second input of the second NAND gate 234 receives the fourth delayed odd data ODD4, and the output of the second NAND gate 234 is connected to the second input of the first NOR gate 235; the output of the first NOR gate 235 is connected to the output module 13. The second arithmetic unit 24 includes: a third NOT gate 241 and a fourth NOT gate 242, a third NAND gate 243 and a fourth NAND gate 244, and a second NOR gate 245; the input of the third NOT gate 241 receives the first delayed odd data ODD1, and the output of the third NOT gate 241 is connected to the first input of the third NAND gate 243; the second input of the third NAND gate 243 receives the second delayed even data EVEN2, and the output of the third NAND gate 243 is connected to the first input of the second NOR gate 245; the input of the fourth NOT gate 242 receives the third delayed odd data ODD3, and the output of the fourth NOT gate 242 is connected to the first input of the fourth NAND gate 244; the second input of the fourth NAND gate 244 receives the fourth delayed even data EVEN4, and the output of the fourth NAND gate 244 is connected to the second input of the second NOR gate 245; the output of the second NOR gate 245 is connected to the output module 13.

[0067] In practical applications, the content represented by the calculation result output by the arithmetic module can be set in conjunction with the input-output relationship of the output module. For example, assuming the input signal and output signal of the output module have the same level, the arithmetic module (the first arithmetic unit and the second arithmetic unit in this example) can be designed according to the standard result output based on the test sample. As another example, assuming the input signal and output signal of the output module have opposite levels, the arithmetic module can be designed according to the inverted result of the standard result output based on the test sample; there are no restrictions on this. Specifically, in practical applications, the calculation result output by the output module is compared with the standard result (output in Table 1) to obtain the CS test result. This example uses the calculation result output by the arithmetic module as the inverted result of the standard result in the CS test for illustration.

[0068] In this example, with test samples Sample0 to Sample3 set to 1010, the corresponding standard result is 0, and the inverted result is 1. That is, when test samples Sample0 to Sample3 are 1010, if the chip select signal is received normally, either the first or second arithmetic unit should output 1. The sampled chip select signals D0 to D3 correspond one-to-one with the test samples Sample0 to Sample3. Taking the second arithmetic unit as an example: assuming the sampled D0 to D3 are 1010, then in the diagram, EVEN4 is 1, ODD3 is 0, EVEN2 is 1, and ODD1 is 0. Correspondingly, ODD1 outputs 1 through the first NOT gate, and EVEN2, which sums to 1, is input to the first NAND gate for NAND operation. The first NAND gate outputs 0 to the first NOR gate. Similarly, ODD3 outputs 1 through the second NOT gate, and EVEN4, which sums to 1, is input to the second NAND gate for NAND operation. The second NAND gate outputs 0 to the first NOR gate. Consequently, the first NOR gate outputs 1 when both inputs are 0. It can be seen that the result output by the second arithmetic unit is consistent with the inverted result of the standard result, meaning the final output result of the output module will be consistent with the standard result, thus the chip select test is normal. Assuming the sampled D0 to D3 are not 1010, for example, if any data bit changes, the first or second NAND gate will output 1 accordingly. If any NAND gate outputs 1, the first NOR gate will output 0, which is inconsistent with the inverted result of the standard result. Based on the above, an arithmetic result characterizing whether the chip select test is normal can be output.

[0069] In this example, the first and second arithmetic units are implemented using conventional devices such as NOT gates, NAND gates, and NOR gates, thereby effectively simplifying the circuit structure and reducing costs while ensuring accurate and reliable chip select testing.

[0070] Specifically, in order to integrate the sampled odd and even data to obtain a complete chip select signal, in one example, the arithmetic module obtains multiple data sequences by delaying the odd and even data at intervals, and uses these multiple data sequences to combine into a complete chip select signal for a specific time period for arithmetic.

[0071] As an example, Figure 11 Structural example diagrams of the first delay unit and the second delay unit provided in one embodiment, such as... Figure 11 As shown, the first delay unit 21 includes: a plurality of first delay sub-units 211 connected in series; the input terminal of the first first delay sub-unit 211 is connected to the sampling module 11 for receiving first delayed odd data ODD1 generated based on odd data ODD; the input terminal of each first delay sub-unit 211 is connected to the output terminal of the previous first delay sub-unit 211, and each first delay sub-unit 211 is used to output the received data after a time interval; the second delay unit 22 includes: a plurality of second delay sub-units 221 connected in series; the input terminal of the first second delay sub-unit 221 is connected to the sampling module 11 for receiving first delayed even data EVEN1 generated based on even data EVEN; the input terminal of each second delay sub-unit 221 is connected to the output terminal of the previous second delay sub-unit 221, and each second delay sub-unit 221 is used to output the received data after a time interval.

[0072] The number of first and second delay sub-units can be determined based on the length of the chip select signal; for example, there can be one or more. As an example, if the chip select signal is four data bits long, then there are three first and three second delay sub-units. Specifically, the input of the first delay sub-unit outputs a first delayed odd data ODD1 generated based on odd data ODD, and the outputs of each first delay sub-unit output ODD2, ODD3, and ODD4, respectively. Similarly, the input of the first second delay sub-unit outputs a first delayed even data EVEN1 generated based on even data EVEN, and the outputs of each second delay sub-unit output EVEN2, EVEN3, and EVEN4, respectively.

[0073] As an example, the time interval between adjacent delayed odd data is one system clock cycle, and the time interval between adjacent delayed even data is also one system clock cycle. Specifically, the odd and even clocks are out of phase and their periods are twice the system clock cycle. Therefore, the corresponding delayed odd and even data (e.g., between ODD1 and EVEN1, or between ODD2 and EVEN2) also differ by one system clock cycle. Combining the aforementioned example, based on the data sequences generated by the delay units, a complete chip select signal can be constructed during the period from the sampling of the last data bit of the chip select signal to the sampling of the next chip select signal. This signal is used for chip select test calculations, and the corresponding output module outputs the calculation results within this period, thereby achieving accurate output of the chip select test results.

[0074] In one example Figure 12 Structural example diagrams of the first delay unit and the second delay unit provided in one embodiment, such as... Figure 12 As shown, each first delay sub-unit 211 includes a first flip-flop 31 and a fifth NOT gate 32. The input terminal of the first flip-flop 31 serves as the input terminal of the first delay sub-unit 211, and the output terminal of the first flip-flop 31 is connected to the input terminal of the fifth NOT gate 32. The output terminal of the fifth NOT gate 32 serves as the output terminal of the first delay sub-unit 211. The clock terminal of the odd-numbered first flip-flop 31 is connected to the inverted signal CLK_OB of the odd clock, and the clock terminal of the even-numbered first flip-flop 31 is connected to the odd clock CLK_O. Each second delay sub-unit 221 includes a second flip-flop 33 and a sixth NOT gate 34. The input terminal of the second flip-flop 33 serves as the input terminal of the second delay sub-unit 221, and the inverted output terminal of the second flip-flop 33 is connected to the input terminal of the sixth NOT gate 34. The output terminal of the sixth NOT gate 34 serves as the output terminal of the second delay sub-unit 221. The clock terminal of the odd-numbered second flip-flop 33 is connected to the inverted signal CLK_EB of the even clock, and the clock terminal of the even-numbered second flip-flop 33 is connected to the even clock CLK_E.

[0075] In this example, a delay sub-unit is constructed using flip-flops and NOT gates to generate a data sequence with a certain time interval, thereby enabling the calculation and accurate output of subsequent chip select test results. Furthermore, the use of conventional components simplifies the circuit structure and reduces costs. Additionally, the combination of flip-flop output inversion and NOT gate inversion processing provides a driving function, improving the accuracy of the generated signal.

[0076] In practical applications, considering that DDR5 specifies a dedicated Chip Select Test Mode (CSTM), in one example, an enable unit can be set to control entering or exiting this mode for better suitability for memory scenarios. As an example, Figure 13 A structural example diagram of a computing module provided in one embodiment is shown below. Figure 13 As shown, the arithmetic module 12 further includes: a first enable unit 25, connected to the sampling module 11 and the first delay unit 21, for transmitting the odd data ODD sampled by the sampling module 11 to the input terminal of the first delay unit 21 in response to the enable signal CSTM_EN and serving as the first delayed odd data ODD1; and a second enable unit 26, connected to the sampling module 11 and the second delay unit 22, for transmitting the even data EVEN sampled by the sampling module 11 to the input terminal of the second delay unit 22 in response to the enable signal CSTM_EN and serving as the first delayed even data EVEN1.

[0077] In one example, such as Figure 13 As shown, both the first enable unit 25 and the second enable unit 26 can be constructed using NAND gates and NOT gates. One input of the NAND gate receives the enable signal, and the other input receives either odd or even data. The output of the NAND gate is connected to the input of the NOT gate, and the output of the NOT gate is connected to either the first delay unit or the second delay unit. Taking the first enable unit 25 as an example, the enable signal is active high. That is, when the enable signal is high, the chip select test mode is entered. The output of the NAND gate depends on the other input, i.e., whether the odd data ODD is 1 or 0. Combined with the NOT gate, a second inversion operation is performed to transmit the odd data ODD to the input of the first delay unit as the first delayed odd data ODD1.

[0078] By setting a first enable unit and a second enable unit, it is possible to conveniently and timely control the start or stop of the generation of delayed odd data and delayed even data, which is suitable for mode control in memory scenarios.

[0079] In summary, the output module acquires and outputs the computation result only after the data sequence received by the computation module constitutes complete chip select data. Considering the two scenarios mentioned above, to achieve the output of computation results under different conditions, in one example, the output clock includes a first output clock CLK_2_O and a second output clock CLK_2_E with opposite phases. Furthermore, at any given time, either the first output clock CLK_2_O or the second output clock CLK_2_E is valid; the validity of either output clock indicates that the sampling clock corresponding to that output clock sampled the chip select signal first.

[0080] Specifically, the first output clock CLK_2_O corresponds to the odd clock CLK_O, and the second output clock CLK_2_E corresponds to the even clock CLK_E. Each rising edge of the output clock corresponds to the rising edge of the corresponding sampling clock. As an example, a single chip select signal includes four data bits; correspondingly, the period of the output clock is the same as the length of a single chip select signal, which is four system clock cycles, or twice the sampling clock. In one example, the corresponding output clock can be generated based on the sampling clock using a frequency divider circuit DIV.

[0081] In one example Figure 14 A structural example diagram of the output module provided in one embodiment is shown below. Figure 14 As shown, the output module 13 includes: a first output unit 131 and a second output unit 132, and the output terminals of the first output unit 131 and the second output unit 132 are connected.

[0082] The input terminal of the first output unit 131 is connected to the first arithmetic unit 23. It is used to respond to the first output clock CLK_2_O being valid, and when the first output clock CLK_2_O is in the first state, to acquire the calculation result output by the first arithmetic unit 23 in real time; and when the first output clock CLK_2_O is in the second state, to latch the current calculation result and stop acquiring new calculation results and output the latched calculation result.

[0083] The input terminal of the second output unit 132 is connected to the second arithmetic unit 24. It is used to respond to the second output clock CLK_2_E being valid, and when the second output clock CLK_2_E is in the first state, to acquire the calculation result output by the second arithmetic unit 24 in real time; and when the second output clock CLK_2_E is in the second state, to latch the current calculation result and stop acquiring new calculation results and output the latched calculation result.

[0084] Specifically, the first output unit corresponds to the first arithmetic unit, and the second output unit corresponds to the second arithmetic unit. The working principle of a single output unit is similar to the aforementioned principle. For example, taking the first output unit as an example, at the beginning of sampling, in response to the first output clock CLK_2_O being in the second state (high level state), the first output unit stops acquiring the calculation result of the first arithmetic unit. Afterwards, the first output clock CLK_2_O flips to the first state (low level state), at which time the first output unit acquires the calculation result output by the first arithmetic unit in real time, but does not output it. Until the next rising edge of the first output clock CLK_2_O arrives, ODD1, EVEN2, ODD3, and EVEN4 have formed a complete chip select signal D3~D0. Therefore, the calculation result of the first arithmetic unit latched at this time is based on the complete chip select signal D3~D0. Therefore, in response to the first output clock CLK_2_O being in the second state again, the output module outputs the currently latched calculation result and stops acquiring new calculation results, thus ensuring sampling accuracy while outputting the calculation result in a timely and accurate manner.

[0085] It should be noted that at any given time, only one of the first and second output clock signals is valid. Therefore, at any given time, only the calculation result obtained from the complete chip select signal, either from the first or second arithmetic unit, will be output. Specifically, in the first scenario, where the chip select signal is sampled first with an odd clock, the first output clock is valid, the first output unit operates normally, and the second output unit does not output. In the second scenario, where the chip select signal is sampled first with an even clock, the second output clock is valid, the second output unit operates normally, and the first output unit does not output. This eliminates the need for selection circuits for the first and second output units, simplifying the circuit structure and avoiding data conflict.

[0086] In one example, such as Figure 14 As shown, the first output unit 131 includes: a first transmission unit 41, a first latch unit 42, and a second transmission unit 43; wherein, the first transmission unit 41 is connected to the first arithmetic unit 23, and is used to transmit the inverted signal of the operation result of the first arithmetic unit 23 to the first latch unit 42 when the first output clock CLK_2_O is in the first state, and to stop transmission when the first output clock CLK_2_O is in the second state; the first latch unit 42 is used to transmit the inverted signal of the operation result to the second transmission unit 43 when the first output clock CLK_2_O is in the first state, and to latch the current operation result when the first output clock CLK_2_O is in the second state; the second transmission unit 43 is connected to the first latch unit 42, and is used to stop output when the first output clock CLK_2_O is in the first state, and to output the operation result latched by the first latch unit 41 when the first output clock CLK_2_O is in the second state. The second output unit 132 includes a third transmission unit 44, a second latch unit 45, and a fourth transmission unit 46. The third transmission unit 44 is connected to the second arithmetic unit 24 and is used to transmit the inverted signal of the calculation result of the second arithmetic unit 24 to the second latch unit 45 when the second output clock CLK_2_E is in the first state, and to stop transmission when the second output clock CLK_2_E is in the second state. The second latch unit 45 is used to transmit the inverted signal of the calculation result to the fourth transmission unit 46 when the second output clock CLK_2_E is in the first state, and to latch the current calculation result when the second output clock CLK_2_E is in the second state. The fourth transmission unit 46 is connected to the second latch unit 45 and is used to stop output when the second output clock CLK_2_E is in the first state, and to output the calculation result latched by the second latch unit 45 when the second output clock CLK_2_E is in the second state.

[0087] Regarding the structures in the output unit, in one example... Figure 15 A structural example diagram of the first output unit provided in one embodiment is shown below. Figure 15 As shown, the first transmission unit 41 includes a first inverter 411, a first switch 412, and a second switch 413; one end of the first switch 412 is connected to the power supply signal, the other end of the first switch 412 is connected to the power supply terminal of the first inverter 411, and the control terminal of the first switch 412 is connected to the first output clock CLK_2_0; the input terminal of the first inverter 412 is connected to the first arithmetic unit 23, and the ground terminal of the first inverter 412 is connected to one end of the second switch 413; the other end of the second switch 413 is grounded, and the control terminal of the second switch 413 is connected to the inverted signal CLK_2_OB of the first output clock; the first latch unit 42 includes a ninth NOT gate 421 and a first tri-state NOT gate 422; the input terminal of the ninth NOT gate 421 is connected to the output terminal of the first inverter 412 and the output terminal of the first tri-state NOT gate 422, and the ninth NOT gate... The output of inverter 421 is connected to the input of the first tri-state NOT gate 422; the control terminal of the first tri-state NOT gate 422 is connected to the first output clock CLK_2_O; the second transmission unit 43 includes a second inverter 431, a third switch 432, and a fourth switch 433; one end of the third switch 432 is connected to the power supply signal, the other end of the third switch 432 is connected to the power supply terminal of the second inverter 431, and the control terminal of the third switch 432 is connected to the inverted signal CLK_2_OB of the first output clock; the input of the second inverter 431 is connected to the output of the ninth NOT gate 421, the output of the second inverter 431 is used to output the calculation result, the ground terminal of the second inverter 431 is connected to one end of the fourth switch 433; the other end of the fourth switch 433 is grounded, and the control terminal of the fourth switch 433 is connected to the first output clock CLK_2_O.

[0088] As an example, the first switch 412 and the third switch 432 are both PMOS transistors, while the second switch 413 and the fourth switch 433 are both NMOS transistors. Referring to the example: when the first output clock CLK_2_O is high, both the first switch 412 and the second switch 413 are open, the first inverter 412 does not work, and therefore the first output unit stops acquiring the calculation result; simultaneously, the first tri-state NOT gate 422 works normally, forming a latch structure with the ninth NOT gate 421, and performs a latching function; both the third switch 432 and the fourth switch 433 are on, the second inverter 431 works normally, and the latched calculation result is output. When the first output clock CLK_2_O is low, both the first switch 412 and the second switch 413 are turned on, and the first inverter 412 outputs the inverted signal of the calculation result. At this time, the first tri-state NOT gate 422 does not work, so only the ninth NOT gate 421 forms the signal transmission path and outputs the calculation result. At this time, both the third switch 432 and the fourth switch 433 are turned off, so the second inverter 431 does not output. This process continues until the first output clock CLK_2_O is high again, and the aforementioned principle is repeated to realize that the first output unit outputs the calculation result obtained based on the complete chip select signal.

[0089] In this example, the chip select test result is output using a first output unit constructed from conventional components, which effectively simplifies the circuit structure and reduces costs.

[0090] In another example, Figure 15 A structural example diagram of the second output unit is also shown, still as follows. Figure 15As shown, the third transmission unit 44 includes a third inverter 441, a fifth switch 442, and a sixth switch 443; one end of the fifth switch 442 is connected to the power supply signal, and the other end of the fifth switch 442 is connected to the power supply terminal of the third inverter 441; the control terminal of the fifth switch 442 is connected to the second output clock CLK_2_E; the input terminal of the third inverter 441 is connected to the second arithmetic unit 24, and the ground terminal of the third inverter 441 is connected to one end of the sixth switch 443; the other end of the sixth switch 443 is grounded, and the control terminal of the sixth switch 443 is connected to the inverted signal CLK_2_EB of the second output clock; the second latch unit 45 includes a tenth NOT gate 451 and a second tri-state NOT gate 452; the input terminal of the tenth NOT gate 451 is connected to the output terminal of the third inverter 441 and the output terminal of the second tri-state NOT gate 452, and the tenth NOT gate... The output of inverter 451 is connected to the input of the second tri-state NOT gate 452; the control terminal of the second tri-state NOT gate 452 is connected to the second output clock CLK_2_E; the fourth transmission unit 46 includes a fourth inverter 461, a seventh switch 462, and an eighth switch 463; one end of the seventh switch 462 is connected to the power supply signal, and the other end of the seventh switch 462 is connected to the power supply terminal of the fourth inverter 461; the control terminal of the seventh switch 462 is connected to the inverted signal CLK_2_EB of the second output clock; the input of the fourth inverter 461 is connected to the output of the tenth NOT gate 451; the output of the fourth inverter 461 is used to output the calculation result; the ground terminal of the fourth inverter 461 is connected to one end of the eighth switch 463; the other end of the eighth switch 463 is grounded; the control terminal of the eighth switch 463 is connected to the second output clock CLK_2_E.

[0091] As an example, the fifth switch 442 and the seventh switch 462 are both PMOS transistors, while the sixth switch 443 and the eighth switch 463 are both NMOS transistors. Referring to the example: when the second output clock CLK_2_E is high, both the fifth switch 442 and the sixth switch 443 are open, the third inverter 441 is not working, and therefore the second output unit stops acquiring the calculation result; simultaneously, the second tri-state NOT gate 452 works normally, forming a latch structure with the tenth NOT gate 451, and performs a latching function; both the seventh switch 462 and the eighth switch 463 are on, the fourth inverter 461 works normally, and the latched calculation result is output. When the second output clock CLK_2_E is low, both the fifth switch 442 and the sixth switch 443 are turned on, and the third inverter 441 outputs the inverted signal of the calculation result. At this time, the second tri-state NOT gate 452 does not work, so only the tenth NOT gate 451 forms the signal transmission path and outputs the calculation result. At this time, both the seventh switch 462 and the eighth switch 463 are turned off, so the fourth inverter 461 does not output. This process continues until the second output clock CLK_2_E is high again, and the aforementioned principle is repeated to realize that the second output unit outputs the calculation result obtained based on the complete chip select signal.

[0092] In this example, the chip select test result is output through a second output unit composed of conventional components, which can effectively simplify the circuit structure and reduce costs.

[0093] It should be noted that the example diagrams in this embodiment are merely examples, and the aforementioned components can be implemented individually or in combination. This embodiment does not limit other possible implementation methods. Furthermore, in this embodiment, the calculation result output by the output module is used to compare with the standard result. The calculation module can be designed based on the input-output relationship of the output module. Specifically, the calculation module can be designed to output the standard result or the inverse of the standard result. The calculation result mentioned above can be determined according to the actual situation, and this embodiment does not limit the specific content of the calculation results output by each module.

[0094] In the chip test circuit provided in this embodiment, the sampling module samples multiple consecutive chip select signals based on odd and even clocks to obtain odd and even data. The calculation module performs comparison calculations based on the odd and even data to obtain the calculation result. The output module outputs the calculation result in response to the output clock. Based on the calculation result, it is possible to detect whether the chip select signal is normal. Through the above scheme, the acquisition, calculation, and output of the calculation result of each data bit in the chip select signal are realized based on odd and even clocks with a clock period twice the system clock period. This ensures accurate and reliable sampling while obtaining and outputting the calculation result based on the complete chip select signal, thus achieving accurate and reliable chip select signal testing.

[0095] Example 2

[0096] Embodiment 2 of this application provides a memory, which includes a chip test circuit as described in any of the foregoing examples.

[0097] As an example, when CS testing is required, the chip test circuit can be activated to enter CSTM mode. The chip test circuit uses odd and even clocks for sampling, obtaining odd and even data. The odd and even clocks are out of phase and their period is twice the system clock period, thus providing a sufficient sampling window for the chip select signal, avoiding sampling errors and failures, and ensuring the accuracy of the CS test. Based on the sampled odd and even data, a complete chip select signal is integrated for chip select test calculations, and the calculation result is obtained and output. The output calculation result is compared with a standard result to determine whether the chip select signal reception is normal.

[0098] In the memory provided in this embodiment, the sampling module of the chip test circuit samples multiple consecutive chip select signals based on odd and even clocks to obtain odd and even data. The arithmetic module performs comparison operations based on the odd and even data to obtain the operation result. The output module outputs the operation result in response to the output clock. Based on the operation result, it is possible to detect whether the chip select signal is normal. Through the above scheme, the acquisition, operation, and output of operation results of each data bit in the chip select signal are realized based on odd and even clocks with a clock period twice the system clock period. This ensures accurate and reliable sampling while obtaining and outputting the operation result based on the complete chip select signal, thus achieving accurate and reliable chip select signal testing.

[0099] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0100] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A chip testing circuit, characterized in that, include: A sampling module is used to sample multiple consecutive chip select signals based on a sampling clock. The holding time of each data bit of the chip select signal is equal to the period of the system clock. The sampling clock includes an odd clock and an even clock with opposite phases. The period of the odd clock and the even clock is equal to twice the period of the system clock. The data sampled based on the odd clock is denoted as odd data, and the data sampled based on the even clock is denoted as even data. A calculation module, connected to the sampling module, is used to perform a comparison calculation based on the odd data and the even data to obtain the calculation result; An output module, connected to the arithmetic module, is used to acquire the arithmetic result in real time when the output clock is in a first state, and to latch the current arithmetic result and stop acquiring new arithmetic results and output the latched arithmetic result when the output clock is in a second state. The first state and the second state are inverses of each other. The period of the output clock is the length of a single chip select signal, and the rising edge of the output clock is aligned with the rising edge of the sampling clock that first samples the chip select signal.

2. The circuit according to claim 1, characterized in that, Each chip select signal consists of four data bits.

3. The circuit according to claim 2, characterized in that, The computing module includes: a first delay unit, a second delay unit, a first computing unit, and a second computing unit; The first delay unit, connected to the sampling module, is used to sequentially delay the odd data according to a predetermined time interval to obtain the first delayed odd data, the second delayed odd data, the third delayed odd data, and the fourth delayed odd data. The second delay unit, connected to the sampling module, is used to sequentially delay the even data according to the time interval to output the first delayed even data, the second delayed even data, the third delayed even data, and the fourth delayed even data. The input terminal of the first arithmetic unit is connected to the first delay unit and the second delay unit. The first arithmetic unit is used to receive the first delayed even data, the second delayed odd data, the third delayed even data and the fourth delayed odd data, and to compare the first delayed even data and the second delayed odd data, as well as to compare the third delayed even data and the fourth delayed odd data. The output terminal of the first arithmetic unit is connected to the output module. The input terminal of the second arithmetic unit is connected to the first delay unit and the second delay unit. The second arithmetic unit is used to receive the first delayed odd data, the second delayed even data, the third delayed odd data and the fourth delayed even data, and compare the first delayed odd data and the second delayed even data, as well as compare the third delayed odd data and the fourth delayed even data. The output terminal of the second arithmetic unit is connected to the output module.

4. The circuit according to claim 3, characterized in that, The first arithmetic unit includes: a first NOT gate and a second NOT gate, a first NAND gate and a second NAND gate, and a first NOR gate; the input of the first NOT gate receives the first delayed even data, and the output of the first NOT gate is connected to the first input of the first NAND gate; the second input of the first NAND gate receives the second delayed odd data, and the output of the first NAND gate is connected to the first input of the first NOR gate; the input of the second NOT gate receives the third delayed even data, and the output of the second NOT gate is connected to the first input of the second NAND gate; the second input of the second NAND gate receives the fourth delayed odd data, and the output of the second NAND gate is connected to the second input of the first NOR gate; the output of the first NOR gate is connected to the output module. The second arithmetic unit includes: a third NOT gate and a fourth NOT gate, a third NAND gate and a fourth NAND gate, and a second NOR gate; the input of the third NOT gate receives the first delayed odd data, and the output of the third NOT gate is connected to the first input of the third NAND gate; the second input of the third NAND gate receives the second delayed even data, and the output of the third NAND gate is connected to the first input of the second NOR gate; the input of the fourth NOT gate receives the third delayed odd data, and the output of the fourth NOT gate is connected to the first input of the fourth NAND gate; the second input of the fourth NAND gate receives the fourth delayed even data, and the output of the fourth NAND gate is connected to the second input of the second NOR gate; the output of the second NOR gate is connected to the output module.

5. The circuit according to claim 3, characterized in that, The first delay unit includes: a plurality of first delay sub-units connected in series; the input terminal of the first first delay sub-unit is connected to the sampling module for receiving the first delayed odd data generated based on the odd data; the input terminal of each first delay sub-unit is connected to the output terminal of the previous first delay sub-unit, and each first delay sub-unit is used to output the received data after the time interval. The second delay unit includes: a plurality of second delay sub-units connected in series; the input terminal of the first second delay sub-unit is connected to the sampling module for receiving the first delayed even data generated based on the even data; the input terminal of each second delay sub-unit is connected to the output terminal of the previous second delay sub-unit, and each second delay sub-unit is used to output the received data after the time interval.

6. The circuit according to claim 5, characterized in that, Each of the first delay sub-units includes a first flip-flop and a fifth NOT gate. The input terminal of the first flip-flop serves as the input terminal of the first delay sub-unit, and the output terminal of the first flip-flop is connected to the input terminal of the fifth NOT gate. The output terminal of the fifth NOT gate serves as the output terminal of the first delay sub-unit. The clock terminal of the odd-numbered first flip-flop is connected to the inverted signal of the odd clock, and the clock terminal of the even-numbered first flip-flop is connected to the odd clock. Each second delay subunit includes a second flip-flop and a sixth NOT gate. The input terminal of the second flip-flop serves as the input terminal of the second delay subunit. The inverted output terminal of the second flip-flop is connected to the input terminal of the sixth NOT gate, and the output terminal of the sixth NOT gate serves as the output terminal of the second delay subunit. The clock terminal of the odd-numbered second flip-flop is connected to the inverted signal of the even-numbered clock, and the clock terminal of the even-numbered second flip-flop is connected to the even-numbered clock.

7. The circuit according to claim 3, characterized in that, The computing module also includes: A first enabling unit, connected to the sampling module and the first delay unit, is used to transmit the odd data sampled by the sampling module to the input terminal of the first delay unit in response to an enabling signal, and use it as the first delayed odd data. The second enabling unit, connected to the sampling module and the second delay unit, is used to transmit the even data sampled by the sampling module to the input of the second delay unit in response to the enabling signal, and use it as the first delayed even data.

8. The circuit according to claim 3, characterized in that, The output clock includes a first output clock and a second output clock with opposite phases; At the same time, either the first output clock or the second output clock is valid; The validity of any output clock indicates that the sampling clock corresponding to that output clock was the first to sample the chip select signal.

9. The circuit according to claim 8, characterized in that, The output module includes: a first output unit and a second output unit, wherein the output terminals of the first output unit and the second output unit are connected. The input terminal of the first output unit is connected to the first arithmetic unit, and is used to respond to the first output clock being valid, to acquire the calculation result output by the first arithmetic unit in real time when the first output clock is in a first state; and to latch the current calculation result and stop acquiring new calculation results and output the latched calculation result when the first output clock is in a second state. The input terminal of the second output unit is connected to the second arithmetic unit, and is used to, in response to the second output clock being valid, acquire the arithmetic result output by the second arithmetic unit in real time when the second output clock is in a first state; and, when the second output clock is in a second state, latch the current arithmetic result and stop acquiring new arithmetic results and output the latched arithmetic result.

10. The circuit according to claim 9, characterized in that, The first output unit includes: a first transmission unit, a first latch unit, and a second transmission unit; wherein, the first transmission unit is connected to the first arithmetic unit and is used to transmit the inverted signal of the operation result of the first arithmetic unit to the first latch unit when the first output clock is in a first state, and to stop transmission when the first output clock is in a second state; the first latch unit is used to transmit the inverted signal of the operation result to the second transmission unit when the first output clock is in the first state, and to latch the current operation result when the first output clock is in the second state; the second transmission unit is connected to the first latch unit and is used to stop output when the first output clock is in the first state, and to output the operation result latched by the first latch unit when the first output clock is in the second state; The second output unit includes a third transmission unit, a second latch unit, and a fourth transmission unit; wherein, the third transmission unit is connected to the second arithmetic unit and is used to transmit the inverted signal of the calculation result of the second arithmetic unit to the second latch unit when the second output clock is in a first state, and to stop transmission when the second output clock is in a second state; the second latch unit is used to transmit the inverted signal of the calculation result to the fourth transmission unit when the second output clock is in the first state, and to latch the current calculation result when the second output clock is in the second state; the fourth transmission unit is connected to the second latch unit and is used to stop output when the second output clock is in the first state, and to output the calculation result latched by the second latch unit when the second output clock is in the second state.

11. The circuit according to claim 10, characterized in that, The first transmission unit includes a first inverter, a first switch, and a second switch; one end of the first switch is connected to a power supply signal, the other end of the first switch is connected to the power supply terminal of the first inverter, and the control terminal of the first switch is connected to the first output clock; the input terminal of the first inverter is connected to the first arithmetic unit, the ground terminal of the first inverter is connected to one end of the second switch; the other end of the second switch is grounded, and the control terminal of the second switch is connected to the inverted signal of the first output clock; The first latch unit includes a ninth NOT gate and a first tri-state NOT gate; The input terminal of the ninth NOT gate is connected to the output terminal of the first inverter and the output terminal of the first tri-state NOT gate, and the output terminal of the ninth NOT gate is connected to the input terminal of the first tri-state NOT gate. The control terminal of the first tri-state NOT gate is connected to the first output clock. The second transmission unit includes a second inverter, a third switch, and a fourth switch; one end of the third switch is connected to a power supply signal, the other end of the third switch is connected to the power supply terminal of the second inverter, and the control terminal of the third switch is connected to the inverted signal of the first output clock; the input terminal of the second inverter is connected to the output terminal of the ninth NOT gate, the output terminal of the second inverter is used to output the calculation result, and the ground terminal of the second inverter is connected to one end of the fourth switch; the other end of the fourth switch is grounded, and the control terminal of the fourth switch is connected to the first output clock.

12. The circuit according to claim 11, characterized in that, The third transmission unit includes a third inverter, a fifth switch, and a sixth switch; one end of the fifth switch is connected to a power supply signal, the other end of the fifth switch is connected to the power supply terminal of the third inverter, and the control terminal of the fifth switch is connected to the second output clock; the input terminal of the third inverter is connected to the second arithmetic unit, and the ground terminal of the third inverter is connected to one end of the sixth switch; the other end of the sixth switch is grounded, and the control terminal of the sixth switch is connected to the inverted signal of the second output clock. The second latch unit includes a tenth NOT gate and a second tri-state NOT gate; The input terminal of the tenth NOT gate is connected to the output terminal of the third inverter and the output terminal of the second tri-state NOT gate, and the output terminal of the tenth NOT gate is connected to the input terminal of the second tri-state NOT gate. The control terminal of the second tri-state NOT gate is connected to the second output clock; The fourth transmission unit includes a fourth inverter, a seventh switch, and an eighth switch; one end of the seventh switch is connected to the power supply signal, the other end of the seventh switch is connected to the power supply terminal of the fourth inverter, and the control terminal of the seventh switch is connected to the inverted signal of the second output clock; the input terminal of the fourth inverter is connected to the output terminal of the tenth NOT gate, the output terminal of the fourth inverter is used to output the calculation result, the ground terminal of the fourth inverter is connected to one end of the eighth switch; the other end of the eighth switch is grounded, and the control terminal of the eighth switch is connected to the second output clock.

13. The circuit according to any one of claims 3-12, characterized in that, The time interval is one system clock cycle.

14. A memory, characterized in that, include: The chip test circuit as described in any one of claims 1-13.

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