Semiconductor structure and method of forming the same

Abstract

This disclosure provides a semiconductor structure and a method for forming the same, wherein the method includes: providing a substrate, wherein a first insulating layer is formed on the surface of the substrate, and a first initial spacer layer is located on the surface of the first insulating layer, spaced apart along a first direction and extending along a second direction, the first initial spacer layer including a first masking layer and a first anti-reflection layer located on the surface of the first masking layer; removing the first anti-reflection layer; multiplying the pattern of the first masking layer and transferring it to the first insulating layer to form a first pattern layer, the first pattern layer including at least first sidewall layers spaced apart along the first direction; forming a second pattern layer on the surface of the first pattern layer; the second pattern layer including at least second sidewall layers spaced apart along the first direction and extending along a third direction; and transferring the initial pattern defined by the second sidewall layer and the first sidewall layer to the substrate.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor structure manufacturing technology, photoresist and mask layers are usually used in combination with photolithography and etching processes to form the desired pattern. However, due to the limitations of photolithography, the desired pattern is easily deviated, which affects the yield of semiconductor structure fabrication.

[0003] Taking the manufacturing of Dynamic Random Access Memory (DRAM) as an example, in the process of forming the capacitors of DRAM, Self-Aligned Quadruple Patterning (SAQP) is usually used for pattern transfer. As the critical dimension (CD) of the pattern continues to shrink and the pattern density becomes larger and larger, the critical dimension of the sidewall pattern cannot be accurately controlled due to the etching load effect during the etching process. Furthermore, during the formation of the sidewall pattern, the bottom of the pattern is uneven due to the etching selectivity, which affects the subsequent pattern transfer and damages the final capacitor structure. For example, it results in poor uniformity of the final capacitor hole size and defects such as insufficient etching, etched hole bridging, and hole misalignment. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same.

[0005] In a first aspect, embodiments of this disclosure provide a method for forming a semiconductor structure, the method comprising: A substrate is provided, wherein a first insulating layer is formed on the surface of the substrate, and a first initial spacer layer is located on the surface of the first insulating layer, spaced apart along a first direction and extending along a second direction, the first initial spacer layer including a first masking layer and a first anti-reflective layer located on the surface of the first masking layer; Remove the first anti-reflective layer; The pattern of the first masking layer is multiplied and transferred to the first insulating layer to form a first pattern layer, the first pattern layer including at least first sidewall layers spaced apart along the first direction; A second pattern layer is formed on the surface of the first pattern layer; the second pattern layer includes at least two sidewall layers spaced apart along the first direction and extending along a third direction; the first direction, the second direction, and the third direction are any three directions in the plane where the substrate is located; The initial pattern defined by the second sidewall layer and the first sidewall layer is transferred to the substrate.

[0006] In some embodiments, the etching selectivity between the first antireflective layer and the substrate is 3 to 10 times that between the first insulating layer and the substrate.

[0007] In some embodiments, multiplying the pattern of the first masking layer and transferring it to the first insulating layer includes: A second initial covering layer is formed on the surface of the first masking layer and the surface of the first insulating layer; The second initial cover layer located on the top surface of the first masking layer and the surface of the first insulating layer is removed, and the second initial cover layer located on the sidewall of the first masking layer is retained to form the first sidewall layer.

[0008] In some embodiments, the first patterned layer further includes a first sacrificial layer; after forming the first sidewall layer, the method of forming the semiconductor structure further includes: The first sacrificial layer is formed in the gap between the first sidewall layers; The first sidewall layer is flush with the surface of the first sacrificial layer.

[0009] In some embodiments, the first initial spacer layer is formed by the following steps: A first initial mask layer and a second initial mask layer are sequentially formed on the surface of the first insulating layer; the first initial mask layer includes the first masking layer and the first anti-reflection layer; The second initial mask layer is etched to form a second initial spacer layer spaced apart along the first direction; A first covering layer is formed on the sidewall of the second initial spacer layer; The first initial mask layer is etched through the first cover layer to form the first initial spacer layer that is alternately arranged along the first direction.

[0010] In some embodiments, the second initial spacer layer is formed by the following steps: A first photoresist layer having a first preset pattern is formed on the surface of the second initial mask layer; wherein the first preset pattern includes a plurality of first sub-patterns arranged sequentially along the first direction and extending along the second direction, and the first sub-patterns expose a portion of the second initial mask layer; Remove the second initial mask layer exposed by the first sub-pattern to form the second initial spacer layer.

[0011] In some embodiments, the second pattern layer is formed by the following steps: A second insulating layer is formed on the surface of the first patterned layer, and a third initial spacer layer is formed on the surface of the second insulating layer, spaced apart along the first direction and extending along the third direction; the third initial spacer layer includes a third masking layer and a third anti-reflective layer on the surface of the third masking layer; Remove the third anti-reflective layer; wherein the etching selectivity between the third anti-reflective layer and the substrate is greater than the etching selectivity between the second insulating layer and the substrate; The pattern of the third masking layer is multiplied and transferred to the second insulating layer to form the second patterned layer.

[0012] In some embodiments, the etching selectivity between the third antireflective layer and the substrate is 3 to 10 times that between the second insulating layer and the substrate.

[0013] In some embodiments, multiplying the pattern of the third masking layer and transferring it to the second insulating layer includes: A fourth initial cover layer is formed on the surface of the third masking layer and the surface of the second insulating layer; The fourth initial cover layer located on the top surface of the third masking layer and the surface of the first insulating layer is removed, and the fourth initial cover layer located on the sidewall of the third masking layer is retained to form the second sidewall layer.

[0014] In some embodiments, the second patterned layer further includes a second sacrificial layer; after forming the second sidewall layer, the method for forming the semiconductor structure further includes: The second sacrificial layer is formed in the gap between the second sidewall layers; The second sidewall layer is flush with the bottom surface of the second sacrificial layer.

[0015] In some embodiments, the third initial spacer layer is formed by the following steps: A third initial mask layer and a fourth initial mask layer are sequentially formed on the surface of the second insulating layer; the third initial mask layer includes the third masking layer and the third anti-reflection layer; The fourth initial mask layer is etched to form a fourth initial spacer layer spaced apart along the first direction; A third covering layer is formed on the sidewall of the fourth initial spacer layer; The third initial mask layer is etched through the third capping layer to form the third initial spacer layer, which is alternately arranged along the first direction.

[0016] In some embodiments, the fourth initial spacer layer is formed by the following steps: A second photoresist layer with a second preset pattern is formed on the surface of the fourth initial mask layer; wherein, the second preset pattern includes a plurality of second sub-patterns arranged sequentially along the first direction and extending along the third direction, and the second sub-patterns expose a portion of the fourth initial mask layer; The fourth initial mask layer exposed by the second sub-pattern is removed to form the fourth initial spacer layer.

[0017] In some embodiments, the substrate includes an array region and a peripheral region, and after forming the second patterned layer, the method further includes: A third photoresist layer having a third preset pattern on the surface of the second pattern layer, wherein the third preset pattern includes a portion of the array region exposed away from the peripheral region; The initial pattern is transferred to the substrate corresponding to the array region exposed by the third preset pattern.

[0018] In some embodiments, after forming the first patterned layer and before forming the second patterned layer, the method for forming the semiconductor structure further includes: A dielectric layer is formed on the surface of the first patterned layer.

[0019] In some embodiments, the substrate includes a fourth mask layer; transferring an initial pattern defined by the second sidewall layer and the first sidewall layer into the substrate includes: Using the first sidewall layer and the second sidewall layer as masks, the initial pattern is transferred to the fourth mask layer to form a fourth mask layer with the initial pattern; the initial pattern includes multiple third sub-patterns.

[0020] In some embodiments, the substrate further includes a substrate, and the fourth mask layer is located on the surface of the substrate; after forming the fourth mask layer having the initial pattern, the method further includes: The exposed portion of the substrate of the third sub-pattern is removed to transfer the initial pattern into the substrate.

[0021] In some embodiments, the substrate further includes a stacked structure, the fourth mask layer being located on the surface of the stacked structure; after forming the fourth mask layer having the initial pattern, the method further includes: Remove the exposed portion of the stacked structure of the third sub-pattern to transfer the initial pattern into the stacked structure.

[0022] In some embodiments, the initial pattern includes a capacitor hole pattern.

[0023] In a second aspect, embodiments of this disclosure provide a semiconductor structure, which is formed by the semiconductor structure formation method described above, and the semiconductor structure includes: A substrate; the substrate includes an initial pattern; the initial pattern is defined by a first sidewall layer in a first pattern layer and a second sidewall layer in a second pattern layer; Wherein, the first pattern layer is located on the surface of the substrate, the first sidewall layers are spaced apart along the first direction and extend along the second direction; the second pattern layer is located on the surface of the first pattern layer, the second sidewall layers are spaced apart along the first direction and extend along the third direction; the first direction, the second direction and the third direction are any three directions in the plane where the substrate is located.

[0024] The semiconductor structure and its formation method provided in this disclosure have a first insulating layer formed on the surface of a substrate, and a first initial spacer layer located on the surface of the first insulating layer, spaced apart along a first direction and extending along a second direction. The first initial spacer layer includes a first masking layer and a first anti-reflection layer located on the surface of the first masking layer. During the formation of the first pattern layer, since the etching selectivity between the first anti-reflection layer and the substrate is greater than that between the first insulating layer and the substrate, the first insulating layer will not be damaged during the removal of the first anti-reflection layer. This prevents the pattern at the bottom of the first masking layer from having an uneven structure, reducing the etching load effect during the downward transfer of the first masking layer. As a result, the critical dimensions of the first sidewall layer can be easily controlled, without affecting subsequent pattern transfer, and thus without damaging the final semiconductor structure. Attached Figure Description

[0025] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0026] Figures 1a-1c This is a schematic diagram of the semiconductor structure formation process in related technologies; Figure 2 A schematic flowchart illustrating a semiconductor structure formation method provided in an embodiment of this disclosure; Figures 3a to 3l , Figures 4a-4p This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this disclosure. Detailed Implementation

[0027] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0028] In the following description, numerous details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0029] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0030] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0032] In related technologies, the SAQP process is typically used to transfer patterns and form capacitor holes in the formation process of capacitor transistors in dynamic random access memory. Figures 1a-1c This is a schematic diagram of the semiconductor structure formation process in related technologies, such as... Figure 1a As shown, the semiconductor structure in the related technology is divided into an array area (AA) and a peripheral area (PA). The semiconductor structure in the related technology includes a substrate (...). Figure 1a and Figure 1b (Not shown in the image) A mask layer 100 located on the surface of a substrate 10, a first pattern layer A located on the surface of the mask layer 100, and a second pattern layer B located on the surface of the first pattern layer A. The mask layer 100 includes a first hard mask layer 101, a second hard mask layer 102, and a third hard mask layer 103 stacked sequentially. The first pattern layer A includes a pattern layer along... Figure 1a The first sidewall layers 111 are spaced apart along the X-axis, and the second pattern layer B includes second sidewall layers 112 spaced apart along the X-axis. In related technologies, after forming the first pattern layer A and the second pattern layer B, the capacitor hole patterns defined by the first pattern layer A and the second pattern layer B are sequentially transferred downwards. For example, they are first transferred to the third hard mask layer 103, and then transferred to the second hard mask layer 102 through the etched third hard mask layer, forming the etched second hard mask layer 102a with capacitor holes 104 (e.g., ...). Figure 1b As shown in the figure, the material is then transferred to the first hard mask layer 101 and the substrate through the etched second hard mask layer 102a.

[0033] In related technologies, during the formation of the first sidewall layer and the second pattern layer, as the critical dimensions of the pattern continuously shrink and the pattern density increases, the critical dimensions of the first sidewall layer 111 and the second sidewall layer 112 cannot be accurately controlled due to the etching load effect during the etching process. Furthermore, due to the etching selectivity issue, the bottoms of the first pattern layer A and the second pattern layer B exhibit an uneven surface (e.g., ...). Figure 1a(As shown in the dashed box), which in turn affects subsequent pattern transfer and disrupts the final capacitor structure, for example, resulting in poor uniformity of the final capacitor aperture size (e.g., ...). Figure 1c Capacitor holes 104-1, 104-2, and 104-3 are shown in the image, and insufficient etching may occur (e.g.) Figure 1b (as shown in the dashed box), etched hole bridging and hole misalignment (such as...) Figure 1c (as shown in the image) and other defects.

[0034] Furthermore, due to the limitations of photolithography, pseudo-capacitor holes 103 are easily generated in the corners of the array region AA (such as...). Figure 1c As shown in the figure, this causes abnormal edge patterns in the array region AA, which in turn affects the performance and fabrication yield of the dynamic random access memory.

[0035] To address the aforementioned technical problems, this disclosure provides a novel method for forming a semiconductor structure, which can precisely control the critical dimensions of the sidewall pattern, ensuring that the bottom of the sidewall pattern is not uneven, thus not affecting the subsequent pattern transfer process and preventing damage to the final pattern. The semiconductor structure forming method provided by this disclosure can achieve good uniformity in the size of the final pattern, avoiding defects such as insufficient etching, bridging of etched holes, and misalignment of etched holes.

[0036] Before introducing the embodiments of this disclosure, let's define four directions that may be used in the following embodiments to describe the three-dimensional structure. The substrate may include a top surface on the front side and a bottom surface on the back side opposite the front side. Ignoring the flatness of the top and bottom surfaces, the direction intersecting (e.g., perpendicular) with the top and bottom surfaces of the substrate is defined as the fourth direction. In the direction of the top and bottom surfaces of the substrate (i.e., the plane in which the substrate lies), three intersecting directions are defined. For example, the extension direction of the first initial spacer layer can be defined as the second direction, and the extension direction of the second sidewall layer can be defined as the third direction. The second direction forms an acute or obtuse angle with the third direction. The first direction intersects with the second and third directions. The planar orientation of the substrate can be determined based on the first, second, and third directions. In the embodiments of this disclosure, the first direction is defined as the X-axis direction, the second direction as the Y1-axis direction, the third direction as the Y2-axis direction, and the fourth direction as the Z-axis direction.

[0037] This disclosure provides a method for forming a semiconductor structure. Figure 2 This is a schematic flowchart of a semiconductor structure formation method provided in an embodiment of the present disclosure, such as... Figure 2 As shown, the method for forming a semiconductor structure includes the following steps: Step S201: A substrate is provided, on the surface of which a first insulating layer is formed, and a first initial spacer layer is located on the surface of the first insulating layer, spaced apart along a first direction and extending along a second direction. The first initial spacer layer includes a first masking layer and a first anti-reflective layer located on the surface of the first masking layer.

[0038] In this embodiment, the substrate includes at least a substrate, which may include a silicon substrate, a germanium substrate, a silicon germanide substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc.; the substrate may also be a substrate comprising other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide, etc. In other embodiments, the substrate may also be an ion-doped substrate, such as a p-type doped substrate or an n-type doped substrate.

[0039] In some embodiments, the substrate may further include a stacked structure for forming capacitor vias in a semiconductor structure, the stacked structure including a bottom support layer, a bottom sacrificial layer, an intermediate support layer, a top sacrificial layer, and a top support layer.

[0040] In some embodiments, the substrate may further include a multilayer mask layer located on the surface of the substrate or the surface of the stacked structure, the multilayer mask layer being used to transfer a pattern to be transferred to the surface of the substrate or the stacked structure.

[0041] In this embodiment of the disclosure, the first insulating layer can be used as a mask layer, and the first insulating layer can be a spin-coated silicon anti-reflection coating (Si-ARC).

[0042] In this embodiment of the disclosure, the first initial spacer layer includes a first masking layer and a first anti-reflection layer located on the surface of the first masking layer. The first masking layer may be a spin-on hard mask (SOH), and the first anti-reflection layer may be a silicon oxide layer or a silicon oxynitride layer.

[0043] In some embodiments, the first initial spacer layers are spaced apart along a first direction and extend along a second direction, wherein the first direction and the second direction may form an acute angle or an obtuse angle.

[0044] Step S202: Remove the first anti-reflective layer.

[0045] In this embodiment of the disclosure, the first anti-reflection layer can be removed by wet etching technology, for example, by etching with strong acids such as concentrated sulfuric acid, hydrofluoric acid, or concentrated nitric acid.

[0046] In this embodiment of the present disclosure, the etching selectivity between the first antireflective layer and the substrate is greater than that between the first insulating layer and the substrate. For example, the etching selectivity between the first antireflective layer and the substrate is 3 to 10 times that between the first insulating layer and the substrate. Because the etching selectivity between the first antireflective layer and the substrate is greater than that between the first insulating layer and the substrate, the first insulating layer will not be damaged when the first antireflective layer is removed.

[0047] Step S203: The pattern of the first masking layer is multiplied and transferred to the first insulating layer to form a first pattern layer. The first pattern layer includes at least first sidewall layers arranged at intervals along a first direction.

[0048] In this embodiment of the disclosure, the pattern of the first masking layer can be multiplied by self-aligned double patterning (SADP) technology, and the multiplied pattern can be transferred to the first insulating layer to form the first sidewall layer.

[0049] In some embodiments, after forming the first sidewall layer, the method of forming the semiconductor structure further includes: forming a first sacrificial layer in the gap between the first sidewall layers; wherein the surface of the first sidewall layer is flush with the surface of the first sacrificial layer. The first sacrificial layer may be an SOH or a silicon oxynitride layer.

[0050] It should be noted that, in this embodiment of the present disclosure, the top and bottom surfaces of the first sidewall layer and the first sacrificial layer along the third direction are flush.

[0051] Step S204: A second pattern layer is formed on the surface of the first pattern layer; the second pattern layer includes at least a second sidewall layer that is spaced apart along a first direction and extends along a third direction.

[0052] In some embodiments, the second sidewall layers are spaced apart along the first direction and extend along the third direction, wherein the second direction and the third direction may form an acute angle or an obtuse angle, and the first direction and the second direction may form a right angle.

[0053] In this embodiment, a second patterned layer is formed on the surfaces of the first sidewall layer and the first sacrificial layer. The second patterned layer further includes a second sacrificial layer located between the second sidewall layers, wherein the surfaces of the second sidewall layers and the second sacrificial layer are flush, i.e., the top and bottom surfaces of the second sidewall layers and the second sacrificial layer are flush in the third direction. The second sacrificial layer may be an SOH or silicon oxynitride layer.

[0054] Step S205: Transfer the initial pattern defined by the second sidewall layer and the first sidewall layer to the substrate.

[0055] In this embodiment of the disclosure, the angle between the second direction and the third direction can be determined according to the layout design of the initial pattern. For example, the angle between the second direction and the third direction can be 20 degrees (°) to 90°, such as 20°, 40°, 70° or 90°.

[0056] In some embodiments, the initial pattern may be a capacitor hole pattern.

[0057] The semiconductor structure formation method provided in this disclosure includes forming a first insulating layer on the surface of a substrate and a first initial spacer layer located on the surface of the first insulating layer, spaced apart along a first direction and extending along a second direction. The first initial spacer layer includes a first masking layer and a first anti-reflective layer located on the surface of the first masking layer. During the formation of the first pattern layer, since the etching selectivity between the first anti-reflective layer and the substrate is greater than that between the first insulating layer and the substrate, the first insulating layer will not be damaged during the removal of the first anti-reflective layer. This prevents the pattern at the bottom of the first masking layer from having an uneven structure, reducing the etching load effect during the downward transfer of the first masking layer. As a result, the critical dimensions of the first sidewall layer can be easily controlled, without affecting subsequent pattern transfer, and thus without damaging the final semiconductor structure.

[0058] Figures 3a to 3l , Figure 4a Figures 4-4p are schematic diagrams of the semiconductor structure formation process provided in the embodiments of this disclosure. The following is a description of the process. Figures 3a to 3l , Figures 4a-4p The formation process of the semiconductor structure provided in the embodiments of this disclosure will be described in detail.

[0059] First, step S201 is performed, providing a substrate, on the surface of which a first insulating layer is formed, and a first initial spacer layer is located on the surface of the first insulating layer, spaced apart along a first direction and extending along a second direction. The first initial spacer layer includes a first masking layer and a first anti-reflective layer located on the surface of the first masking layer.

[0060] like Figure 3a As shown, the substrate includes a fourth mask layer 12 and a first insulating layer 13 located on the surface of the fourth mask layer 12. In this embodiment of the present disclosure, the fourth mask layer 12 includes a first hard mask layer 121, a second hard mask layer 122, and a third hard mask layer 123. The first hard mask layer 121 may be a polysilicon layer, the second hard mask layer 122 may be a silicon oxide layer, and the third hard mask layer 123 may be an amorphous carbon layer (ACL) or a polysilicon layer. The first insulating layer 13 may be a silicon nitride layer or a silicon oxynitride layer.

[0061] In some embodiments, the fourth mask layer 12 is used to transfer the initial pattern defined by the first sidewall layer and the second sidewall layer. Since the critical dimensions of the initial pattern shrink with each transfer during the transfer process, the initial pattern is transferred through the fourth mask layer 12, which has multiple hard mask layers, until the desired pattern size is reached. This allows for continuous miniaturization of the process node and improves the integration density of the semiconductor structure. Therefore, in this embodiment, the number of hard mask layers in the fourth mask layer 12 can be set according to actual needs. For example, the fourth mask layer 12 can also consist of one hard mask layer or five hard mask layers.

[0062] In this embodiment of the present disclosure, the first insulating layer 13 may be a spin-coated silicon-containing antireflective layer.

[0063] In this embodiment of the disclosure, please continue to refer to Figure 3a The substrate includes the array region AA and the peripheral region PA.

[0064] In some embodiments, the first initial spacer layer can be formed by the following steps: sequentially forming a first initial mask layer and a second initial mask layer on the surface of a substrate; the first initial mask layer includes a first masking layer and a first anti-reflection layer; etching the second initial mask layer to form second initial spacers spaced at intervals along a first direction; forming a first capping layer on the sidewall of the second initial spacer layer; etching the first initial mask layer through the first capping layer to form first initial spacers spaced alternately arranged along a first direction.

[0065] Please continue reading Figure 3a A first initial mask layer 14 and a second initial mask layer 15 are sequentially formed on the surface of the first insulating layer 13. The first initial mask layer 14 includes a first initial masking layer 141 and a first initial antireflective layer 142; the second initial mask layer 15 includes a second initial masking layer 151 and a second initial antireflective layer 152. The first initial masking layer 141 and the second initial masking layer 151 can be spin-coated hard mask layers or amorphous carbon layers (ACLs); the materials of the first initial antireflective layer 142 and the second initial antireflective layer 152 can both be silicon oxynitride. In this embodiment, the first initial mask layer and the second initial mask layer can be formed by any of the following suitable deposition processes: chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, or coating process.

[0066] In other embodiments, the first initial mask layer 14 may consist only of the first initial masking layer 141, and the second initial mask layer 15 may consist only of the second initial masking layer 151.

[0067] In some embodiments, etching a second initial mask layer to form a second initial spacer layer spaced apart along a first direction may include the following steps: forming a first photoresist layer having a first preset pattern on the surface of the second initial mask layer; wherein the first preset pattern includes a plurality of first sub-patterns arranged sequentially along a first direction and extending along a second direction, the first sub-patterns exposing a portion of the second initial mask layer; removing the second initial mask layer exposed by the first sub-patterns to form the second initial spacer layer.

[0068] Please continue reading Figure 3a and Figure 3b A first photoresist layer 16 with a first preset pattern is formed on the surface of the second initial mask layer 15; wherein, the first preset pattern includes a plurality of first sub-patterns E located in the array region AA and arranged sequentially along the X-axis direction, and the first sub-patterns E expose a portion of the second initial mask layer 15 (i.e., the second initial anti-reflection layer 152).

[0069] like Figure 3b and Figure 3c As shown, the second initial mask layer 15 is etched by the first photoresist layer 16 to remove the second initial mask layer 15 (including the second initial anti-reflection layer 152 and the second initial masking layer 151 located in the projection area of ​​the second initial anti-reflection layer 152 along the Z-axis) exposed by the first sub-pattern E, forming a second initial spacer layer 17. The second initial spacer layer 17 includes a second masking layer 171 and a second anti-reflection layer 172 located on the surface of the second masking layer 171.

[0070] In some embodiments, please continue to see Figure 3b and Figure 3c After forming the second initial spacer layer 17, the method for forming the semiconductor structure further includes removing the first photoresist layer 16 having a first preset pattern.

[0071] In some embodiments, the process of forming a first cover layer on the sidewall of the second initial spacer layer may include the following steps: forming a first initial cover layer on the surfaces of the second initial spacer layer and the first initial mask layer; removing the first initial cover layer located on the top surface of the second initial spacer layer and the surface of the first initial mask layer, and retaining the first initial cover layer located on the second initial spacer layer to form the first cover layer.

[0072] like Figure 3dAs shown, a first initial capping layer 18 is formed on the surfaces of the second initial spacer layer 17 and the first initial mask layer 14, wherein the first initial capping layer 18 covers the sidewalls and top surface of the second initial spacer layer 17 and the surface of the first initial mask layer 14. In this embodiment of the present disclosure, the first initial capping layer 18 can be formed using an atomic layer deposition process to improve the film quality of the first initial capping layer 18.

[0073] In this embodiment of the present disclosure, after the formation of the first initial capping layer 18, a dry etching process is used to simultaneously remove the first initial capping layer 18 from the top surface of the second initial spacer layer 17 and the surface of the first initial mask layer 14, while retaining the first initial capping layer 18 located on the sidewall of the second initial spacer layer 17. The retained first initial capping layer 18 constitutes the first capping layer 181 (e.g., ...). Figure 3e (As shown).

[0074] Please continue reading Figure 3d and Figure 3e After forming the first capping layer 181, the method for forming the semiconductor structure further includes removing the second initial spacer layer 17. In some embodiments, the second initial spacer layer 17 can be removed using a wet etching technique, for example, by etching with strong acids such as concentrated sulfuric acid, hydrofluoric acid, or concentrated nitric acid.

[0075] Please continue reading Figure 3e and Figure 3f The first initial mask layer 14 is etched by the first cover layer 181, that is, the portion of the first initial mask layer 14 exposed by the first cover layer 181 (including the first initial anti-reflection layer 142 and the first initial masking layer 141 located in the projection area of ​​the first initial anti-reflection layer 142 along the Z-axis direction) is removed to form the first initial spacer layer 19. The first initial spacer layer 19 includes the first masking layer 191 and the first anti-reflection layer 192 located on the surface of the first masking layer 191.

[0076] Next, step S202 is performed to remove the first anti-reflective layer.

[0077] like Figure 3f and Figure 3g As shown, the first anti-reflective layer 192 is removed using a wet etching technique. For example, the first anti-reflective layer 192 can be removed by etching with a diluted hydrofluoric acid solution (the volume ratio of water to hydrofluoric acid is 1:200).

[0078] In this embodiment of the disclosure, since the etching selectivity between the first antireflective layer 192 and the substrate is greater than that between the first insulating layer 13 and the substrate (for example, the etching selectivity between the first antireflective layer and the substrate is 3 to 10 times that between the first insulating layer and the substrate), the first insulating layer 13 will not be damaged when the first antireflective layer 192 is removed.

[0079] Next, step S203 is performed to multiply the pattern of the first masking layer and transfer it to the first insulating layer to form a first pattern layer. The first pattern layer includes at least first sidewall layers arranged at intervals along a first direction.

[0080] In some embodiments, step S203 may include the following steps: forming a second initial cover layer on the surface of the first masking layer and the surface of the first insulating layer; removing the second initial cover layer located on the top surface of the first masking layer and the surface of the first insulating layer, and retaining the second initial cover layer located on the sidewall of the first masking layer to form a first sidewall layer.

[0081] like Figure 3h As shown, a second initial capping layer 20 is formed on the surfaces of the first masking layer 191 and the first insulating layer 13; wherein the second initial capping layer 20 covers the sidewalls and top surface of the first masking layer 191 and the surface of the first insulating layer 13. In this embodiment of the present disclosure, the second initial capping layer 20 can be formed using an atomic layer deposition process to improve the film quality of the second initial capping layer 20.

[0082] like Figure 3h and Figure 3i As shown, a dry etching process is used to simultaneously remove the second initial cover layer 20 on the top surface of the first masking layer 191 and the surface of the first insulating layer 13, while retaining the second initial cover layer 20 located on the sidewall of the first masking layer 191; the first masking layer 191 is removed by a wet etching technique; the first insulating layer 13 is etched through the remaining second initial cover layer 20a to form a first sidewall layer 201, which includes the remaining second initial cover layer 20a and the etched first insulating layer 13a.

[0083] In some embodiments, after forming the first sidewall layer 201, the method of forming the semiconductor structure further includes forming a first sacrificial layer in the gap between the first sidewall layers 201.

[0084] In practice, a first initial sacrificial layer can be formed in the gap between the first sidewall layers, on the surface of the first sidewall layer, and on the surface of the gap between the first sidewall layers; the first initial sacrificial layer is etched back until the surface of the remaining second initial sacrificial layer 20a in the first sidewall layer is exposed, thus forming the first sacrificial layer.

[0085] like Figure 3j As shown, a first initial sacrificial layer 22 is formed in the gap between the first sidewall layer and the first masking layer, on the surface of the first sidewall layer, and on the surface of the gap between the first masking layers. The first sacrificial layer material is spin-coated to form the first initial sacrificial layer 22. The first sacrificial layer material can be SOH or other materials.

[0086] like Figure 3j and Figure 3k As shown, the first initial sacrificial layer 22 is etched back until the surface of the first sidewall layer 201 is exposed, and the remaining first initial sacrificial layer 22 located in the gaps between the first sidewall layers 201 constitutes the first sacrificial layer 23.

[0087] In this embodiment, the surfaces of the first sidewall layer 201 and the first sacrificial layer 22 are flush, that is, the top and bottom surfaces of the first sidewall layer 201 and the first sacrificial layer 22 along the Z-axis are flush, which makes the subsequent pattern transfer process more accurate.

[0088] The semiconductor structure formation method provided in this disclosure has a greater etching selectivity between the first antireflective layer and the substrate than between the first insulating layer and the substrate. Therefore, the first insulating layer will not be damaged during the removal of the first antireflective layer, so that the pattern at the bottom of the first masking layer will not have an uneven structure. This reduces the etching load effect during the downward transfer of the first masking layer. As a result, the critical dimensions of the first sidewall layer can be easily controlled, without affecting the subsequent pattern transfer, and thus without damaging the final semiconductor structure.

[0089] In this embodiment of the present disclosure, after the first sacrificial layer 23 is formed, the first pattern layer is also formed. Figure 3l This is a top view of the first pattern layer for ease of understanding. Figure 3k Only a limited number of the first sidewall layers are shown in the diagram, and Figure 3l The first sacrificial layer 23 in the first pattern layer 300 is not shown. For example... Figure 3l As shown, the first pattern layer 300 includes first sidewall layers 201 that are spaced apart along the X-axis and extend along the Y1-axis.

[0090] Next, step S204 is performed to form a second pattern layer on the surface of the first pattern layer; the second pattern layer includes at least a second sidewall layer that is spaced apart along a first direction and extends along a third direction.

[0091] In some embodiments, the second patterned layer is formed by the following steps: forming a second insulating layer on the surface of a first patterned layer, and a third initial spacer layer located on the surface of the second insulating layer, spaced apart along a first direction and extending along a third direction; the third initial spacer layer includes a third masking layer and a third anti-reflective layer located on the surface of the third masking layer; removing the third anti-reflective layer; wherein the etching selectivity between the third anti-reflective layer and the substrate is greater than the etching selectivity between the second insulating layer and the substrate; multiplying the pattern of the third masking layer and transferring it into the second insulating layer to form the second patterned layer.

[0092] In some embodiments, the third initial spacer layer can be formed by the following steps: forming a third initial mask layer and a fourth initial mask layer sequentially on the surface of the first pattern layer; the third initial mask layer includes a third masking layer and a third anti-reflection layer; etching the fourth initial mask layer to form fourth initial spacers spaced at intervals along a first direction; forming a third capping layer on the sidewall of the fourth initial spacer layer; etching the third initial mask layer through the third capping layer to form third initial spacers spaced alternately along the first direction.

[0093] In some embodiments, before forming the second patterned layer, the method for forming the semiconductor structure further includes forming a dielectric layer located above the first patterned layer 300.

[0094] like Figure 4a As shown, a dielectric layer 202 is formed on the surface of the first pattern layer 300. The material of the dielectric layer 202 can be silicon nitride or silicon oxynitride.

[0095] like Figure 4b As shown, a second insulating layer 24 is formed on the surface of the dielectric layer. The material of the second insulating layer 24 can be a spin-coated silicon-containing anti-reflective layer.

[0096] Please continue reading Figure 4b A third initial mask layer 25 and a fourth initial mask layer 26 are sequentially formed on the surface of the second insulating layer 24. The third initial mask layer 25 includes a third initial masking layer 251 and a third initial antireflective layer 252; the fourth initial mask layer 26 includes a fourth initial masking layer 261 and a fourth initial antireflective layer 262. The third initial masking layer 251 and the fourth initial masking layer 261 can be spin-coated hard mask layers or amorphous carbon layers; the materials of the third initial antireflective layer 252 and the fourth initial antireflective layer 262 can both be silicon oxynitride.

[0097] In this embodiment of the present disclosure, the first initial mask layer and the second initial mask layer can be formed by any suitable deposition process. In other embodiments, the third initial mask layer 25 may consist only of the third initial masking layer 251, and the fourth initial mask layer 26 may consist only of the fourth initial masking layer 261.

[0098] In some embodiments, the fourth initial spacer layer can be formed by the following steps: forming a second photoresist layer having a second preset pattern on the surface of the fourth initial mask layer; wherein the second preset pattern includes a plurality of second sub-patterns arranged sequentially along a first direction, the second sub-patterns exposing a portion of the fourth initial mask layer; the second sub-patterns extending along a third direction; removing the fourth initial mask layer exposed by the second sub-patterns to form the fourth initial spacer layer.

[0099] Please continue reading Figure 4b and Figure 4cA second photoresist layer 27 with a second preset pattern is formed on the surface of the fourth initial mask layer 26; wherein the second preset pattern includes a plurality of second sub-patterns F located in the array region AA and arranged sequentially along the X-axis direction and extending along the Y2-axis direction, and the second sub-patterns F expose a portion of the fourth initial mask layer 26.

[0100] like Figure 4c and Figure 4d As shown, the fourth initial mask layer 26 is etched by the second photoresist layer 27 to remove the fourth initial mask layer 26 (including the fourth initial anti-reflection layer 262 and the fourth initial masking layer 261 located in the projection area of ​​the fourth initial anti-reflection layer 262 along the Z-axis) exposed by the second sub-pattern F, forming the fourth initial spacer layer 28. The fourth initial spacer layer 28 includes the fourth masking layer 281 and the fourth anti-reflection layer 282 located on the surface of the fourth masking layer 281.

[0101] In some embodiments, please continue to see Figure 4c and Figure 4d After forming the fourth initial spacer layer 28, the method for forming the semiconductor structure further includes removing the second photoresist layer 27 having a second preset pattern.

[0102] In some embodiments, forming a third cover layer on the sidewall of the fourth initial spacer layer may include the following steps: forming a third initial cover layer on the surfaces of the fourth initial spacer layer and the third initial mask layer; removing the third initial cover layer located on the top surface of the fourth initial spacer layer and the surface of the third initial mask layer, and retaining the third initial cover layer located on the sidewall of the fourth initial spacer layer to form the third cover layer.

[0103] like Figure 4e As shown, a third initial capping layer 29 is formed on the surfaces of the fourth initial spacer layer 28 and the third initial mask layer 25, wherein the third initial capping layer 29 covers the sidewalls and top surface of the fourth initial spacer layer 28 and the surface of the third initial mask layer 25. In this embodiment, the third initial capping layer 29 can be formed using an atomic layer deposition process to improve the film quality of the third initial capping layer 29. The third initial capping layer 29 can be an oxide layer, such as a silicon oxide layer.

[0104] In this embodiment of the present disclosure, after the formation of the third initial capping layer 29, a dry etching process is used to simultaneously remove the third initial capping layer 29 from the top surface of the fourth initial spacer layer 28 and the surface of the third initial mask layer 25, retaining the third initial capping layer 29 located on the sidewall of the fourth initial spacer layer 28. The retained third initial capping layer 29 constitutes the third capping layer 291 (e.g., Figure 4f (As shown).

[0105] Please continue reading Figure 4e and Figure 4fAfter forming the third capping layer 291, the method for forming the semiconductor structure further includes removing the fourth initial spacer layer 28. In some embodiments, the fourth initial spacer layer 28 can be removed using a wet etching technique, for example, by etching with strong acids such as concentrated sulfuric acid, hydrofluoric acid, or concentrated nitric acid.

[0106] Please continue reading Figure 4f and Figure 4g The third initial mask layer 25 is etched through the third cover layer 291, that is, the portion of the third initial mask layer 25 exposed by the third cover layer 291 (including the third initial anti-reflection layer 252 and the third initial masking layer 251 located in the projection area of ​​the third initial anti-reflection layer 252 along the Z-axis) is removed to form the third initial spacer layer 30. The third initial spacer layer 30 includes the third masking layer 301 and the third anti-reflection layer 302 located on the surface of the third masking layer 301.

[0107] like Figure 4g and Figure 4h As shown, the third anti-reflective layer 302 is removed using a wet etching technique. For example, the third anti-reflective layer 302 can be removed by etching with a diluted hydrofluoric acid solution (the volume ratio of water to hydrofluoric acid is 1:200).

[0108] In this embodiment of the disclosure, since the etching selectivity between the third antireflective layer 302 and the substrate is greater than that between the second insulating layer 24 and the substrate (for example, the etching selectivity between the third antireflective layer 302 and the substrate is 3 to 10 times that between the second insulating layer 24 and the substrate), the second insulating layer 24 will not be damaged when the third antireflective layer 302 is removed.

[0109] In some embodiments, the pattern of the third masking layer is multiplied and transferred to the second insulating layer, comprising the following steps: forming a fourth initial cover layer on the surface of the third masking layer and the surface of the second insulating layer; removing the fourth initial cover layer located on the top surface of the third masking layer and the surface of the second insulating layer, and retaining the fourth initial cover layer located on the sidewall of the third masking layer to form a second sidewall layer.

[0110] like Figure 4i As shown, a fourth initial capping layer 31 is formed on the surfaces of the third masking layer 301 and the second insulating layer 24; wherein the fourth initial capping layer 31 covers the sidewalls and top surface of the third masking layer 301 and the surface of the second insulating layer 24. In this embodiment of the present disclosure, the fourth initial capping layer 31 can be formed using an atomic layer deposition process to improve the film quality of the fourth initial capping layer 31.

[0111] like Figure 4i and Figure 4jAs shown, after forming the fourth initial capping layer 31, the method for forming the semiconductor structure further includes: using a dry etching process to simultaneously remove the fourth initial capping layer 31 from the top surface of the third masking layer 301 and the surface of the second insulating layer 24; removing the third masking layer 301 using a wet etching technique; and etching the second insulating layer 24 through the remaining fourth initial capping layer 31a to form a second sidewall layer 311, wherein the second sidewall layer 311 includes the remaining fourth initial capping layer 31a and the etched second insulating layer 24a.

[0112] In some embodiments, such as Figure 4k As shown, after forming the second sidewall layer 311, the method for forming the semiconductor structure further includes forming a second sacrificial layer 34 in the gap between the second sidewall layers 311.

[0113] It should be noted that in this disclosed embodiment, the formation process of the second sacrificial layer 34 is the same as the formation process of the first sacrificial layer 23, and will not be described again here.

[0114] Figure 4l This is a top view of the second pattern layer, for ease of understanding. Figure 4l Only a limited number of second sidewall layers are shown in the diagram, and Figure 4l The second sacrificial layer 34 in the second pattern layer 400 is not shown. For example... Figure 4k As shown, the second pattern layer 400 includes second sidewall layers 311 that are spaced apart along the X-axis and extend along the Y2-axis.

[0115] The semiconductor structure formation method provided in this disclosure has a greater etching selectivity between the third antireflection layer and the substrate than between the second insulating layer and the substrate. Therefore, the second insulating layer is not damaged during the removal of the third antireflection layer, so that the pattern at the bottom of the third masking layer does not have an uneven structure. This reduces the etching load effect during the downward transfer of the third masking layer. As a result, the critical dimensions of the second sidewall layer can be easily controlled, without affecting the subsequent pattern transfer, and thus without damaging the final semiconductor structure.

[0116] In some embodiments, after forming the second patterned layer, the method for forming the semiconductor structure further includes: forming a third photoresist layer having a third preset pattern on the surface of the second patterned layer, wherein the third preset pattern includes a portion of the array region exposed away from the peripheral region.

[0117] like Figure 4l and Figure 4mAs shown, a third photoresist layer 36 with a third preset pattern is formed on the surface of the second pattern layer 400, wherein the third preset pattern includes a third sub-pattern. In this embodiment, the second sacrificial layer 34, the dielectric layer 202 located within the Z-axis projection region of the second sacrificial layer 34, and the first sacrificial layer 23 in the first pattern layer 300 are etched away from the exposed second pattern layer 400 by the third photoresist layer 36 with the third preset pattern, thereby forming a third photoresist layer 36 with the third preset pattern. Figure 4n The initial pattern H is defined by the first sidewall layer 201 and the second sidewall layer 311.

[0118] Finally, step S205 is performed to transfer the initial pattern defined by the second sidewall layer and the first sidewall layer into the substrate.

[0119] Combination Figure 3a , Figure 4o and Figure 4p As shown, the substrate includes a fourth mask layer 12, which includes a first hard mask layer 121, a second hard mask layer 122, and a third hard mask layer 123. In implementation, firstly, the initial pattern H is transferred to the third hard mask layer within the fourth mask layer. Secondly, the second hard mask layer 122 is etched through the third hard mask layer 123 containing the initial pattern H to transfer the initial pattern H to the second hard mask layer 122. Finally, the first hard mask layer 121 is etched through the second hard mask layer containing the initial pattern H to transfer the initial pattern H to the first hard mask layer 121, forming a first hard mask layer 121a with the initial pattern H, thereby achieving the transfer of the initial pattern H to the substrate. It should be noted that, for ease of understanding, Figure 4p Only a portion of the initial pattern H is shown.

[0120] In some embodiments, the initial pattern may be a capacitor hole pattern.

[0121] The semiconductor structure formation method provided in this disclosure has the following advantages: Since the etching selectivity between the first antireflective layer and the substrate is greater than that between the first insulating layer and the substrate, the first insulating layer is not damaged during the removal of the first antireflective layer, preventing uneven structures from appearing on the pattern at the bottom of the first masking layer and reducing the etching load effect during the downward transfer of the first masking layer. Furthermore, since the etching selectivity between the third antireflective layer and the substrate is greater than that between the second insulating layer and the substrate, the second insulating layer is not damaged during the removal of the third antireflective layer, preventing uneven structures from appearing on the pattern at the bottom of the third masking layer and reducing the etching load effect during the downward transfer of the third masking layer. Thus, the critical dimensions of the first and second sidewall layers can be easily controlled, without affecting subsequent pattern transfer, and consequently without damaging the final semiconductor structure.

[0122] In addition, the semiconductor structure formation method provided by the embodiments of this disclosure can achieve good uniformity of the final pattern size, and avoid defects such as insufficient etching, etch hole bridging, and etch hole misalignment, thereby improving the preparation yield of semiconductor structures.

[0123] In addition, this disclosure also provides a semiconductor structure, please refer to the following embodiments. Figures 4m to 4p The semiconductor structure includes: a substrate; the substrate includes an initial pattern H.

[0124] In this embodiment of the disclosure, please continue to refer to Figure 4m The substrate includes a fourth mask layer 12, which includes a first hard mask layer 121, a second hard mask layer 122, and a third hard mask layer 123.

[0125] In other embodiments, the substrate further includes a substrate and a stacked structure located on the surface of the substrate.

[0126] Please continue to refer to this. Figure 4m The initial pattern H is defined by the first sidewall layer 201 in the first pattern layer 300 and the second sidewall layer 311 in the second pattern layer 400. The first pattern layer 300 includes the first sidewall layer 201 and the first sacrificial layer 23, which are alternately arranged along the X-axis and extend along the Y1-axis (see Figure 3I).

[0127] Please continue to refer to this. Figure 4m The second pattern layer 400 is located on the surface of the first pattern layer 300. The second pattern layer 400 includes alternating patterns along the X-axis and along the Y2-axis (see reference). Figure 4l The second sidewall layer 311 and the second sacrificial layer 34 extend in the direction of )

[0128] In some embodiments, the initial pattern may be a capacitor hole pattern.

[0129] The semiconductor structure provided in this disclosure is similar to the semiconductor structure formation method in the above embodiments. For technical features not disclosed in detail in this disclosure, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0130] The semiconductor structure provided in this disclosure includes a substrate with an initial pattern, the initial pattern being defined by a first sidewall layer in a first patterning layer and a second sidewall layer in a second patterning layer. Since the semiconductor structure provided in this disclosure is formed using the above-described semiconductor structure formation method, the critical dimensions of the first and second sidewall layers in this disclosure are easily controlled, do not affect subsequent pattern transfer, and therefore do not damage the final semiconductor structure. Thus, the semiconductor structure in this disclosure has a high fabrication yield.

[0131] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the various components shown or discussed are coupled to each other or directly coupled.

[0132] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0133] The above are merely some embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, The method includes: A substrate is provided, wherein a first insulating layer is formed on the surface of the substrate, and a first initial spacer layer is located on the surface of the first insulating layer, spaced apart along a first direction and extending along a second direction, the first initial spacer layer including a first masking layer and a first anti-reflective layer located on the surface of the first masking layer; Remove the first anti-reflective layer; The pattern of the first masking layer is multiplied and transferred to the first insulating layer to form a first pattern layer, the first pattern layer including at least first sidewall layers spaced apart along the first direction; A second pattern layer is formed on the surface of the first pattern layer; the second pattern layer includes at least two sidewall layers spaced apart along the first direction and extending along a third direction; the first direction, the second direction, and the third direction are any three directions in the plane where the substrate is located; The initial pattern defined by the second sidewall layer and the first sidewall layer is transferred to the substrate.

2. The method according to claim 1, characterized in that, The etching selectivity between the first antireflective layer and the substrate is 3 to 10 times that between the first insulating layer and the substrate.

3. The method according to claim 2, characterized in that, Multiplying the pattern of the first masking layer and transferring it to the first insulating layer includes: A second initial covering layer is formed on the surface of the first masking layer and the surface of the first insulating layer; The second initial cover layer located on the top surface of the first masking layer and the surface of the first insulating layer is removed, and the second initial cover layer located on the sidewall of the first masking layer is retained to form the first sidewall layer.

4. The method according to claim 3, characterized in that, The first patterned layer further includes a first sacrificial layer; after forming the first sidewall layer, the method for forming the semiconductor structure further includes: The first sacrificial layer is formed in the gap between the first sidewall layers; The first sidewall layer is flush with the surface of the first sacrificial layer.

5. The method according to claim 4, characterized in that, The first initial spacer layer is formed by the following steps: A first initial mask layer and a second initial mask layer are sequentially formed on the surface of the first insulating layer; the first initial mask layer includes the first masking layer and the first anti-reflection layer; The second initial mask layer is etched to form a second initial spacer layer spaced apart along the first direction; A first covering layer is formed on the sidewall of the second initial spacer layer; The first initial mask layer is etched through the first cover layer to form the first initial spacer layer that is alternately arranged along the first direction.

6. The method according to claim 5, characterized in that, The second initial spacer layer is formed by the following steps: A first photoresist layer having a first preset pattern is formed on the surface of the second initial mask layer; wherein the first preset pattern includes a plurality of first sub-patterns arranged sequentially along the first direction and extending along the second direction, and the first sub-patterns expose a portion of the second initial mask layer; Remove the second initial mask layer exposed by the first sub-pattern to form the second initial spacer layer.

7. The method according to any one of claims 1 to 6, characterized in that, The second pattern layer is formed by the following steps: A second insulating layer is formed on the surface of the first patterned layer, and a third initial spacer layer is formed on the surface of the second insulating layer, spaced apart along the first direction and extending along the third direction; the third initial spacer layer includes a third masking layer and a third anti-reflective layer on the surface of the third masking layer; Remove the third anti-reflective layer; wherein the etching selectivity between the third anti-reflective layer and the substrate is greater than the etching selectivity between the second insulating layer and the substrate; The pattern of the third masking layer is multiplied and transferred to the second insulating layer to form the second pattern layer.

8. The method according to claim 7, characterized in that, The etching selectivity between the third antireflective layer and the substrate is 3 to 10 times that between the second insulating layer and the substrate.

9. The method according to claim 8, characterized in that, Multiplying the pattern of the third masking layer and transferring it to the second insulating layer includes: A fourth initial cover layer is formed on the surface of the third masking layer and the surface of the second insulating layer; The fourth initial cover layer located on the top surface of the third masking layer and the surface of the first insulating layer is removed, and the fourth initial cover layer located on the sidewall of the third masking layer is retained to form the second sidewall layer.

10. The method according to claim 9, characterized in that, The second patterned layer further includes a second sacrificial layer; after forming the second sidewall layer, the method for forming the semiconductor structure further includes: The second sacrificial layer is formed in the gap between the second sidewall layers; The second sidewall layer is flush with the bottom surface of the second sacrificial layer.

11. The method according to claim 10, characterized in that, The third initial spacer layer is formed by the following steps: A third initial mask layer and a fourth initial mask layer are sequentially formed on the surface of the second insulating layer; the third initial mask layer includes the third masking layer and the third anti-reflection layer; The fourth initial mask layer is etched to form a fourth initial spacer layer spaced apart along the first direction; A third covering layer is formed on the sidewall of the fourth initial spacer layer; The third initial mask layer is etched through the third capping layer to form the third initial spacer layer, which is alternately arranged along the first direction.

12. The method according to claim 11, characterized in that, The fourth initial spacer layer is formed by the following steps: A second photoresist layer with a second preset pattern is formed on the surface of the fourth initial mask layer; wherein, the second preset pattern includes a plurality of second sub-patterns arranged sequentially along the first direction and extending along the third direction, and the second sub-patterns expose a portion of the fourth initial mask layer; The fourth initial mask layer exposed by the second sub-pattern is removed to form the fourth initial spacer layer.

13. The method according to claim 12, characterized in that, The substrate includes an array region and a peripheral region. After forming the second pattern layer, the method further includes: A third photoresist layer having a third preset pattern on the surface of the second pattern layer, wherein the third preset pattern includes a portion of the array region exposed away from the peripheral region; The initial pattern is transferred to the substrate corresponding to the array region exposed by the third preset pattern.

14. The method according to claim 13, characterized in that, After forming the first patterned layer and before forming the second patterned layer, the method for forming the semiconductor structure further includes: A dielectric layer is formed on the surface of the first patterned layer.

15. The method according to claim 14, characterized in that, The substrate includes a fourth mask layer; transferring the initial pattern defined by the second sidewall layer and the first sidewall layer into the substrate includes: Using the first sidewall layer and the second sidewall layer as masks, the initial pattern is transferred to the fourth mask layer to form a fourth mask layer with the initial pattern; the initial pattern includes multiple third sub-patterns.

16. The method according to claim 15, characterized in that, The substrate further includes a substrate, and the fourth mask layer is located on the surface of the substrate; After forming the fourth mask layer having the initial pattern, the method further includes: The exposed portion of the substrate of the third sub-pattern is removed to transfer the initial pattern into the substrate.

17. The method according to claim 16, characterized in that, The substrate further includes a stacked structure, and the fourth mask layer is located on the surface of the stacked structure; After forming the fourth mask layer having the initial pattern, the method further includes: Remove the exposed portion of the stacked structure of the third sub-pattern to transfer the initial pattern into the stacked structure.

18. The method according to claim 17, characterized in that, The initial pattern includes a capacitor hole pattern.

19. A semiconductor structure, characterized in that, The semiconductor structure is formed by the semiconductor structure forming method according to any one of claims 1 to 18, wherein the semiconductor structure comprises: A substrate; the substrate includes an initial pattern; the initial pattern is defined by a first sidewall layer in a first pattern layer and a second sidewall layer in a second pattern layer; Wherein, the first pattern layer is located on the surface of the substrate, the first sidewall layers are spaced apart along the first direction and extend along the second direction; the second pattern layer is located on the surface of the first pattern layer, the second sidewall layers are spaced apart along the first direction and extend along the third direction; the first direction, the second direction and the third direction are any three directions in the plane where the substrate is located.

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