Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, a substrate is provided, the substrate has a fin on it; a dummy gate dielectric layer is formed on the top surface and sidewall of the fin; a dummy gate material layer is formed on the dummy gate dielectric layer; the dummy gate material layer is patterned to form a dummy gate layer; a first modification treatment is performed on the surface of the dummy gate layer to form a first modification layer; a second modification treatment is performed on the first modification layer to form a second modification layer. When the surface of the dummy gate layer is modified to form the second modification layer, the residue of the dummy gate material layer located at the corner formed by the dummy gate layer and the fin will also be modified to form the second modification layer. When the dummy gate layer is removed, the residue of the dummy gate material layer oxidized at the corner position is not easy to be removed. When the exposed dummy gate dielectric layer is removed, the consumption of the etching solution to the dummy gate dielectric layer located on the sidewall of the fin can be reduced, thereby reducing the risk of short circuit between the subsequently formed gate structure and the source / drain doping layer, and improving the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Technology

[0002] MOS (Metal-Oxide-Semiconductor) transistors are among the most important components in modern integrated circuits. The basic structure of a MOS transistor includes: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, the gate structure comprising: a gate dielectric layer on the surface of the semiconductor substrate and a gate electrode layer on the surface of the gate dielectric layer; and source / drain doped regions located in the semiconductor substrate on both sides of the gate structure.

[0003] With the development of semiconductor technology, the traditional planar MOS transistor has become less able to control the channel current, resulting in severe leakage current. Fin field-effect transistors (Fin FETs) are a new type of multi-gate device. They generally include fins protruding from the surface of a semiconductor substrate, a gate structure covering part of the top surface and sidewalls of the fins, and source / drain doped regions located in the fins on both sides of the gate structure.

[0004] However, existing technologies still present many problems in the process of forming fin field-effect transistors. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.

[0006] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate having fins extending along a first direction; forming a dummy gate dielectric layer on the top surface and sidewalls of the fins; forming a dummy gate material layer on the dummy gate dielectric layer; patterning the dummy gate material layer to form a dummy gate layer extending along a second direction, wherein the first direction is perpendicular to the second direction; performing a first modification treatment on the surface of the dummy gate layer to form a first modification layer; performing a second modification treatment on the first modification layer to form a second modification layer, wherein the etching rate of the dummy gate dielectric layer is greater than the etching rate of the second modification layer; after the second modification treatment, forming sidewalls on the sidewalls of the dummy gate layer; and after forming the sidewalls, forming source / drain doped layers within the fins on both sides of the dummy gate layer.

[0007] Optionally, the method for patterning the pseudo-gate material layer to form a pseudo-gate layer includes: forming a mask layer on the pseudo-gate material layer, etching the pseudo-gate material layer using the mask layer as a mask until the top surface of the pseudo-gate dielectric layer is exposed, thereby forming the pseudo-gate layer.

[0008] Optionally, the first modification process includes: a rapid thermal oxidation process; the process parameters of the rapid thermal oxidation process include: the oxidizing gas includes oxygen; the oxidation time is 5 seconds to 300 seconds; the oxidation temperature is 300 degrees Celsius to 1500 degrees Celsius; and the thickness of the first modified layer formed after oxidation is 5 angstroms to 20 angstroms.

[0009] Optionally, the second modification process includes a nitriding process; the nitriding process includes a decoupled plasma nitriding process.

[0010] Optionally, the first modification treatment process includes: a nitriding process; the nitriding process includes: a decoupled plasma nitriding process.

[0011] Optionally, the second modification process includes a rapid thermal oxidation process; the process parameters of the rapid thermal oxidation process include: the oxidizing gas includes oxygen; the oxidation time is 5 seconds to 300 seconds; the oxidation temperature is 300 degrees Celsius to 1500 degrees Celsius; and the thickness of the second modified layer formed after oxidation is 5 angstroms to 20 angstroms.

[0012] Optionally, the ratio of the etching rate of the pseudo-gate dielectric layer to the etching rate of the modified layer is 1.1:1 to 50:1.

[0013] Optionally, after forming the source / drain doped layers, the method further includes: forming a dielectric layer on the substrate, the dielectric layer covering the dummy gate layer and the sidewalls, and the dielectric layer exposing the top surfaces of the dummy gate layer and the sidewalls; removing the dummy gate layer and the exposed dummy gate dielectric layer; forming a gate opening within the dielectric layer; and forming a gate structure within the gate opening.

[0014] Optionally, the gate structure includes: a gate dielectric layer and a gate layer located on the gate dielectric layer.

[0015] Optionally, the material of the gate layer includes a metal; the metal includes tungsten, aluminum, copper, titanium, silver, gold, lead, or nickel.

[0016] Optionally, the material of the pseudo-gate layer includes polycrystalline silicon.

[0017] Optionally, the method of forming source / drain doped layers in the fins on both sides of the dummy gate layer includes: etching the fins using the sidewalls and the dummy gate layer as masks to form source / drain openings in the fins; and forming the source / drain doped layers in the source / drain openings.

[0018] Optionally, the method for forming the source / drain doped layer within the source / drain opening includes: forming an epitaxial layer within the source / drain opening using an epitaxial growth process; and during the epitaxial growth process, in-situ doping of source / drain ions into the epitaxial layer using an in-situ doping process to form the source / drain doped layer.

[0019] Optionally, the material of the pseudo-gate dielectric layer includes silicon oxide.

[0020] Optionally, the sidewall material includes silicon nitride.

[0021] Optionally, before forming the pseudo-gate dielectric layer, the method further includes: forming an isolation layer on the substrate, the isolation layer covering a portion of the sidewall surface of the fin, the top surface of the isolation layer being lower than the top surface of the fin.

[0022] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0023] In the semiconductor structure formation method of the present invention, during the first and second modification processes on the surface of the dummy gate layer, the residue of the dummy gate material layer located at the angle between the dummy gate layer and the fin is simultaneously modified to form a second modified layer, thereby increasing the etching selectivity between the dummy gate layer and the second modified layer. Subsequently, during the removal of the dummy gate layer, the oxidized residue of the dummy gate material layer at the angle is less easily removed, thus reducing the gap formed at the angle. Later, when removing the exposed dummy gate dielectric layer, the amount of etching solution flowing into the gap is reduced, thereby reducing the consumption of the dummy gate dielectric layer located on the sidewall of the fin by the etching solution, reducing the risk of exposing the source / drain doped layer, and further reducing the risk of short circuit between the subsequently formed gate structure and the source / drain doped layer, thereby improving the performance of the final semiconductor structure. Furthermore, the etching rate of the dummy gate dielectric layer is greater than the etching rate of the second modified layer. The second modified layer can increase the etching selectivity between the modified layer and the dummy gate dielectric layer. During the subsequent removal of the exposed dummy gate dielectric layer, the consumption of the second modified layer located on the sidewall of the fin can be reduced, thereby reducing the risk of exposing the source and drain doped layers. This reduces the risk of short circuit between the subsequently formed gate structure and the source and drain doped layers, thereby improving the performance of the final semiconductor structure. Attached Figure Description

[0024] Figures 1 to 3 This is a schematic diagram of the steps involved in forming a semiconductor structure.

[0025] Figures 4 to 17 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0026] As described in the background section, existing technologies still present numerous problems in the fabrication of fin field-effect transistors. These will be explained in detail below with reference to the accompanying drawings.

[0027] Figures 1 to 3 This is a schematic diagram of the steps involved in forming a semiconductor structure.

[0028] Please refer to Figure 1 and Figure 2 , Figure 2 yes Figure 1 A top view along line AA shows a substrate 100 having fins 101 extending along a first direction X; a dummy gate dielectric layer 102 is formed on the top surface and sidewalls of the fins 101; a dummy gate material layer (not shown) is formed on the dummy gate dielectric layer 102; the dummy gate material layer is patterned to form a dummy gate layer 103 extending along a second direction Y, the first direction X being perpendicular to the second direction Y; sidewalls 104 are formed on the sidewalls of the dummy gate layer 103; after forming the sidewalls 104, source / drain doped layers 105 are formed within the fins 101 on both sides of the dummy gate layer 103.

[0029] Please refer to Figure 3 , Figure 3 and Figure 2 With the view orientation consistent, a dielectric layer (not shown) is formed on the substrate 100, the dielectric layer covering the dummy gate layer 103 and the sidewall 104, and the dielectric layer 106 exposing the top surfaces of the dummy gate layer 103 and the sidewall 104; the dummy gate layer 103 and the exposed dummy gate dielectric layer 102 are removed, and a gate opening (not shown) is formed in the dielectric layer; a gate structure 106 is formed in the gate opening.

[0030] In this embodiment, because after the pseudo-gate material layer is patterned, residues of the pseudo-gate material layer (such as...) are easily found at the angle formed between the pseudo-gate layer 103 and the fin 101. Figure 2 (As shown in Part A). During the removal of the dummy gate layer 103, the residue of the dummy gate material layer at the included angle is also removed, resulting in a large gap at the included angle. During the removal of the exposed dummy gate dielectric layer 102, the etching solution flows into the gap, which consumes the dummy gate dielectric layer 102 located on the sidewall of the fin 101, exposing the source / drain doped layer 105. After the gate structure 106 is formed, it is easy to cause a short circuit between the gate structure 106 and the source / drain doped layer 105, thereby affecting the performance of the final semiconductor structure.

[0031] Based on this, the present invention provides a method for forming a semiconductor structure. During the first and second modification processes on the surface of the dummy gate layer, the residue of the dummy gate material layer located at the angle between the dummy gate layer and the fin is simultaneously modified to form a second modified layer, thereby increasing the etch selectivity between the dummy gate layer and the second modified layer. Subsequently, during the removal of the dummy gate layer, the oxidized residue of the dummy gate material layer at the angle is less easily removed, thus reducing the gap formed at the angle. Later, when removing the exposed dummy gate dielectric layer, the amount of etching solution flowing into the gap is reduced, thereby reducing the consumption of the dummy gate dielectric layer located on the fin sidewall by the etching solution, reducing the risk of exposing the source / drain doped layer, and further reducing the risk of short circuits between the subsequently formed gate structure and the source / drain doped layer, thereby improving the performance of the final semiconductor structure. Furthermore, the etching rate of the dummy gate dielectric layer is greater than the etching rate of the second modified layer. The second modified layer can increase the etching selectivity between the modified layer and the dummy gate dielectric layer. During the subsequent removal of the exposed dummy gate dielectric layer, the consumption of the second modified layer located on the sidewall of the fin can be reduced, thereby reducing the risk of exposing the source and drain doped layers. This reduces the risk of short circuit between the subsequently formed gate structure and the source and drain doped layers, thereby improving the performance of the final semiconductor structure.

[0032] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0033] Figures 4 to 17 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention.

[0034] Please refer to Figure 4 A substrate 200 is provided, wherein the substrate has fins 201 extending along a first direction X.

[0035] In this embodiment, the method for forming the substrate 200 and the fin 201 includes: providing an initial substrate (not shown); forming a patterned layer (not shown) on the initial substrate, the patterned layer exposing a portion of the top surface of the initial substrate; etching the initial substrate using the patterned layer as a mask to form the substrate 200 and the fin 201; and removing the patterned layer after forming the substrate 200 and the fin 201.

[0036] In this embodiment, the substrate 200 is made of silicon; in other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0037] In this embodiment, the fin 201 is made of silicon; in other embodiments, the fin may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium.

[0038] Please refer to Figure 5 An isolation layer 202 is formed on the substrate 200, the isolation layer 202 covers part of the sidewall surface of the fin 201, and the top surface of the isolation layer 202 is lower than the top surface of the fin 201.

[0039] In this embodiment, the method for forming the isolation layer 202 includes: forming an isolation material layer (not shown) on the substrate 200, the isolation material layer covering the sidewall of the fin 201; removing a portion of the isolation material layer to form the isolation layer 202, the top surface of the isolation layer 202 being lower than the top surface of the fin 201.

[0040] The insulating layer 202 is made of an insulating material, including silicon oxide, silicon nitride, or silicon oxynitride; in this embodiment, the insulating layer 202 is made of silicon oxide.

[0041] Please refer to Figure 6 A pseudo-gate dielectric layer 203 is formed on the top surface and sidewall of the fin 201.

[0042] In this embodiment, the pseudo-gate dielectric layer 203 is formed using an atomic layer deposition process; in other embodiments, the pseudo-gate dielectric layer can also be formed using an in-situ water vapor growth process.

[0043] In this embodiment, the pseudo-gate dielectric layer 203 is also formed on the top surface of the isolation layer 202.

[0044] In this embodiment, the material of the pseudo-gate dielectric layer 203 is silicon oxide.

[0045] Please refer to Figure 7 A pseudo-gate material layer 204 is formed on the pseudo-gate dielectric layer 203.

[0046] In this embodiment, the pseudo-gate material layer 204 is formed using a furnace tube growth process.

[0047] In this embodiment, the pseudo-gate material layer 204 is made of polycrystalline silicon.

[0048] Please refer to Figures 8 to 10 , Figure 9 yes Figure 8 Schematic diagram of the cross section along line BB. Figure 10 yes Figure 9A top view along the CC line shows that the pseudo-gate material layer 204 is patterned to form a pseudo-gate layer 205, which extends along the second direction Y, and the first direction X is perpendicular to the second direction Y.

[0049] In this embodiment, the method for patterning the pseudo gate material layer 204 to form the pseudo gate layer 205 includes: forming a mask layer 206 on the pseudo gate material layer 204, etching the pseudo gate material layer 204 with the mask layer 206 as a mask until the top surface of the pseudo gate dielectric layer 203 is exposed, thereby forming the pseudo gate layer 205.

[0050] In this embodiment, since the pseudo gate layer 205 is formed by patterning the pseudo gate material layer 204, and the material of the pseudo gate material layer 204 is polysilicon, the material of the pseudo gate layer 205 is also polysilicon.

[0051] It should be noted that, in this embodiment, after the pseudo-gate material layer 204 is patterned, a residue of the pseudo-gate material layer 204 will be generated at the angle between the pseudo-gate layer 205 and the fin 201.

[0052] Please refer to Figure 11 , Figure 11 and Figure 10 With the view direction consistent, the surface of the pseudo-gate layer 205 is subjected to a first modification treatment to form a first modified layer 207.

[0053] In this embodiment, after the pseudo gate layer 205 is formed, the mask layer 206 is not removed. When the surface of the pseudo gate layer 205 is subjected to the first modification treatment, since the mask layer 206 covers the top surface of the pseudo gate layer 205, the first modification layer 207 is only formed on the sidewall of the pseudo gate layer 205.

[0054] In this embodiment, the first modification treatment adopts a rapid thermal oxidation process; the process parameters of the rapid thermal oxidation process include: the oxidizing gas includes oxygen; the oxidation time is 5 seconds to 300 seconds; the oxidation temperature is 300 degrees Celsius to 1500 degrees Celsius; and the thickness of the first modified layer 207 formed after oxidation is 5 angstroms to 20 angstroms.

[0055] In this embodiment, since both the pseudo-gate material layer 204 and the pseudo-gate layer 205 are made of polycrystalline silicon, the material of the first modified layer 207 formed after the first modification treatment is silicon oxide.

[0056] Please refer to Figure 12The first modified layer 207 is subjected to a second modification treatment to form a second modified layer 208, wherein the etching rate of the pseudo gate dielectric layer 203 is greater than the etching rate of the second modified layer 208.

[0057] In this embodiment, during the first and second modification processes on the surface of the dummy gate layer 205, the residue of the dummy gate material layer 204 located at the angle formed by the dummy gate layer 205 and the fin 201 is simultaneously modified to form a second modified layer 208, thereby increasing the etching selectivity between the dummy gate layer 205 and the second modified layer 208. Subsequently, during the removal of the dummy gate layer 205, the oxidized residue of the dummy gate material layer 204 located at the angle is less easily removed, thus reducing the gap formed at the angle. Subsequently, when removing the exposed dummy gate dielectric layer 203, the amount of etching solution flowing into the gap is reduced, thereby reducing the consumption of the dummy gate dielectric layer 203 located on the sidewall of the fin 201 by the etching solution, reducing the risk of exposing the subsequently formed source / drain doped layers, and thus reducing the risk of short circuits between the subsequently formed gate structure and the source / drain doped layers, thereby improving the performance of the final semiconductor structure. Furthermore, the etching rate of the dummy gate dielectric layer 203 is greater than the etching rate of the second modified layer 208. The second modified layer 208 increases the etching selectivity with the dummy gate dielectric layer 203. During the subsequent removal of the exposed dummy gate dielectric layer 203, the consumption of the second modified layer 208 located on the sidewall of the fin 201 is reduced, decreasing the risk of exposing the source / drain doped layers. This, in turn, reduces the risk of short circuits between the subsequently formed gate structure and the source / drain doped layers, thereby improving the performance of the final semiconductor structure.

[0058] In this embodiment, the second modification treatment is carried out using a nitriding process; the nitriding process is carried out using a decoupled plasma nitriding process.

[0059] In this embodiment, the material of the second modified layer formed after nitriding is silicon oxynitride.

[0060] In this embodiment, the ratio of the etching rate of the pseudo-gate dielectric layer to the etching rate of the modified layer is 1.1:1 to 50:1.

[0061] In other embodiments, the first modification treatment process may also be a nitriding process; the nitriding process includes: decoupled plasma nitriding process; the second modification treatment process is a rapid thermal oxidation process; the process parameters of the rapid thermal oxidation process include: the oxidizing gas includes oxygen; the oxidation time is 5 seconds to 300 seconds; the oxidation temperature is 300 degrees Celsius to 1500 degrees Celsius; and the thickness of the second modified layer formed after oxidation is 5 angstroms to 20 angstroms.

[0062] Please refer to Figure 13 After the modification treatment, a sidewall 209 is formed on the sidewall of the pseudo-gate layer 205.

[0063] In this embodiment, the method for forming the sidewall 209 includes: forming a sidewall material layer (not shown) on the sidewall and top surface of the dummy gate layer 205, the sidewall and top surface of the fin 201, and the top surface of the isolation layer 202; and etching the sidewall material layer back until the top surface of the dummy gate layer 205 is exposed to form the sidewall 209.

[0064] In this embodiment, the sidewall material layer is formed using atomic layer deposition (ALD).

[0065] In this embodiment, the sidewall 209 is made of silicon nitride.

[0066] Please refer to Figure 14 After the sidewall 209 is formed, a source / drain doped layer 210 is formed in the fins 201 on both sides of the pseudo gate layer 205.

[0067] In this embodiment, the method of forming a source / drain doped layer 210 in the fins 201 on both sides of the dummy gate layer 205 includes: etching the fins 201 using the sidewalls 209 and the dummy gate layer 205 as masks, forming source / drain openings (not shown) in the fins 201; and forming the source / drain doped layer 210 in the source / drain openings.

[0068] In this embodiment, the method for forming the source / drain doped layer 210 within the source / drain opening includes: forming an epitaxial layer (not shown) within the source / drain opening using an epitaxial growth process; and during the epitaxial growth process, in-situ doping of source / drain ions into the epitaxial layer to form the source / drain doped layer 210.

[0069] In this embodiment, the source / drain ion is a P-type ion; in other embodiments, the source / drain ion may also be an N-type ion.

[0070] Please refer to Figure 15 A dielectric layer 211 is formed on the substrate 200, the dielectric layer 211 covering the dummy gate layer 205 and the sidewall 209, and the dielectric layer 211 exposing the top surfaces of the dummy gate layer 205 and the sidewall 209.

[0071] In this embodiment, the dielectric layer 211 is made of silicon oxide; in other embodiments, the dielectric layer may also be made of low-K dielectric material (low-K dielectric material refers to dielectric material with a relative permittivity of less than 3.9) or ultra-low-K dielectric material (ultra-low-K dielectric material refers to dielectric material with a relative permittivity of less than 2.5).

[0072] Please refer to Figure 16 Remove the dummy gate layer 205 and the exposed dummy gate dielectric layer 203, and form a gate opening 212 in the dielectric layer 211.

[0073] In this embodiment, the method for removing the dummy gate layer 205 and the exposed dummy gate dielectric layer 203 includes: removing the dummy gate layer 205 using a first etching process; and removing the exposed dummy gate dielectric layer 203 using a second etching process.

[0074] In this embodiment, the first etching process employs both dry etching and wet etching processes.

[0075] In this embodiment, the second etching process is a wet etching process.

[0076] Please refer to Figure 17 A gate structure 213 is formed within the gate opening 212.

[0077] In this embodiment, the gate structure 213 includes: a gate dielectric layer and a gate layer (not shown) located on the gate dielectric layer.

[0078] In this embodiment, the material of the gate dielectric layer includes a high-k dielectric material.

[0079] The gate layer is made of a metal, including tungsten, aluminum, copper, titanium, silver, gold, lead, or nickel. In this embodiment, the gate layer is made of tungsten.

[0080] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided having fins extending along a first direction; A pseudo-gate dielectric layer is formed on the top surface and sidewalls of the fin; A pseudo-gate material layer is formed on the pseudo-gate dielectric layer; The pseudo-gate material layer is patterned to form a pseudo-gate layer, which extends along a second direction, and the first direction is perpendicular to the second direction. The surface of the pseudo-gate layer is subjected to a first modification treatment to form a first modified layer; The first modified layer is subjected to a second modification treatment to form a second modified layer, wherein the etching rate of the pseudo gate dielectric layer is greater than the etching rate of the second modified layer; After the second modification treatment, a sidewall is formed on the sidewall of the pseudo-gate layer; After the sidewalls are formed, source / drain doped layers are formed within the fins on both sides of the pseudo-gate layer.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for patterning the pseudo-gate material layer to form a pseudo-gate layer includes: forming a mask layer on the pseudo-gate material layer, etching the pseudo-gate material layer using the mask layer as a mask until the top surface of the pseudo-gate dielectric layer is exposed, thereby forming the pseudo-gate layer.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first modification process includes a rapid thermal oxidation process; the process parameters of the rapid thermal oxidation process include: the oxidizing gas includes oxygen; the oxidation time is 5 seconds to 300 seconds; the oxidation temperature is 300 degrees Celsius to 1500 degrees Celsius; and the thickness of the first modified layer formed after oxidation is 5 angstroms to 20 angstroms.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The second modification process includes a nitriding process; the nitriding process includes a decoupled plasma nitriding process.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first modification treatment process includes: a nitriding process; the nitriding process includes: a decoupled plasma nitriding process.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The second modification process includes a rapid thermal oxidation process; the process parameters of the rapid thermal oxidation process include: the oxidizing gas includes oxygen; the oxidation time is 5 seconds to 300 seconds; the oxidation temperature is 300 degrees Celsius to 1500 degrees Celsius; and the thickness of the second modified layer formed after oxidation is 5 angstroms to 20 angstroms.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The ratio of the etching rate of the pseudo-gate dielectric layer to the etching rate of the modified layer is 1.1:1 to 50:

1.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, After forming the source / drain doped layers, the method further includes: forming a dielectric layer on the substrate, the dielectric layer covering the dummy gate layer and the sidewalls, and the dielectric layer exposing the top surfaces of the dummy gate layer and the sidewalls; removing the dummy gate layer and the exposed dummy gate dielectric layer; forming a gate opening within the dielectric layer; and forming a gate structure within the gate opening.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The gate structure includes: a gate dielectric layer and a gate layer located on the gate dielectric layer.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The gate layer is made of a metal; the metal includes tungsten, aluminum, copper, titanium, silver, gold, lead, or nickel.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the pseudo-gate layer includes polycrystalline silicon.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method of forming a source / drain doped layer in the fins on both sides of the dummy gate layer includes: etching the fins using the sidewalls and the dummy gate layer as a mask to form source / drain openings in the fins; and forming the source / drain doped layer in the source / drain openings.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The method for forming the source / drain doped layer within the source / drain opening includes: forming an epitaxial layer within the source / drain opening using an epitaxial growth process; and, during the epitaxial growth process, in-situ doping of source / drain ions into the epitaxial layer to form the source / drain doped layer.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the pseudo-gate dielectric layer includes silicon oxide.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the sidewall includes silicon nitride.

16. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before forming the pseudo-gate dielectric layer, the method further includes: forming an isolation layer on the substrate, the isolation layer covering a portion of the sidewall surface of the fin, the top surface of the isolation layer being lower than the top surface of the fin.

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