Semiconductor structure and method of forming the same

Abstract

The application provides a semiconductor structure and a forming method thereof. The forming method comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a top metal layer and a passivation layer on the semiconductor substrate and part of the top metal layer; arranging a soldering material on part of the top metal layer, and the surface of the soldering material is higher than the top surface of the passivation layer; forming a sealing layer on the top metal layer between the soldering material and the passivation layer, and the top surface of the sealing layer is flush with the top surface of the passivation layer; and performing a reflow soldering treatment on the soldering material to form a spherical soldering bump. The technical scheme has simple forming process and is easy to operate, and can save process cost.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] Flip chip is a commonly used packaging method that offers many advantages over traditional wire bonding, such as superior electrical and thermal performance and reduced package size. Flip chip manufacturing involves depositing tin-lead balls on an I / O pad, then flipping the chip and heating it to bond the molten tin-lead balls to a ceramic substrate. This technology replaces conventional wire bonding and is gradually becoming the mainstream packaging method, currently primarily used in high-clock-frequency CPUs, GPUs (Graphics Processor Units), and Chipsets.

[0003] Currently, most flip chips are manufactured in packaging plants, and the flip-chip process is relatively complex and costly, so the flip chip process needs to be improved. Summary of the Invention

[0004] The technical problem to be solved by this application is to provide a semiconductor structure and a method for forming the same, which can form spherical welding bumps, and the forming process is simple, easy to operate, and can save process costs.

[0005] To address the aforementioned technical problems, this application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, wherein the semiconductor substrate includes a top metal layer and a passivation layer located on the semiconductor substrate and a portion of the top metal layer; disposing a welding material on a portion of the top metal layer, wherein the surface of the welding material is higher than the top surface of the passivation layer; forming a sealing layer with a surface flush with the top surface of the passivation layer on the top metal layer between the welding material and the passivation layer; and performing a reflow soldering process on the welding material to form spherical welding bumps.

[0006] In some embodiments of this application, the welding material comprises several discrete welding material blocks.

[0007] In some embodiments of this application, a method for setting welding material on a portion of the top metal layer includes: setting a positioning plate on the passivation layer, wherein the positioning plate includes a channel for defining the position of the welding material; setting the welding material on a portion of the top metal layer through the channel; and removing the positioning plate.

[0008] In some embodiments of this application, the channel is a continuous channel, and the channel and the top metal layer extend in the same direction.

[0009] In some embodiments of this application, the channel includes a plurality of sub-channels spaced apart along the extension direction of the top metal layer.

[0010] In some embodiments of this application, the method for forming the sealing layer includes: forming a sealing material layer on the surface of the passivation layer, the top metal layer, and the welding material; removing the sealing material layer above the surface of the passivation layer to form the sealing layer.

[0011] In some embodiments of this application, a dry etching process is used to etch the sealing material layer and stop on the passivation layer to remove the sealing material layer above the surface of the passivation layer.

[0012] In some embodiments of this application, the width of the welding material is 1 / 2 to 2 / 3 of the width of the top metal layer.

[0013] In some embodiments of this application, the thickness of the top metal layer is 1.75 μm to 4.15 μm, and the height of the spherical welding bumps is 5.25 μm to 12.45 μm.

[0014] In some embodiments of this application, the reflow soldering process is performed at a temperature of 100°C to 160°C for a duration of 90s to 120s.

[0015] In some embodiments of this application, the sealing layer and the top metal layer are made of the same material.

[0016] In some embodiments of this application, the materials of the sealing layer and the top metal layer include aluminum, and the welding material includes a Sn-Pb alloy.

[0017] This application also provides a semiconductor structure, comprising: a semiconductor substrate, wherein the semiconductor substrate includes a top metal layer and a passivation layer located on the semiconductor substrate and a portion of the top metal layer; a ball-shaped welding bump located on a portion of the top metal layer, wherein the surface of the ball-shaped welding bump is higher than the top surface of the passivation layer; and a sealing layer located on the top metal layer between the ball-shaped welding bump and the passivation layer, wherein the surface of the sealing layer is flush with the top surface of the passivation layer.

[0018] In some embodiments of this application, the thickness of the top metal layer is 1.75 μm to 4.15 μm, and the height of the spherical welding bumps is 5.25 μm to 12.45 μm.

[0019] In some embodiments of this application, the sealing layer and the top metal layer are made of the same material.

[0020] In some embodiments of this application, the materials of the sealing layer and the top metal layer include aluminum, and the material of the spherical weld bumps includes a Sn-Pb alloy.

[0021] Compared with the prior art, the semiconductor structure and its formation method of the present application have the following advantages:

[0022] By placing solder material on the top metal layer, and then forming a sealing layer with its surface flush with the top surface of the passivation layer on the top metal layer between the solder material and the passivation layer, and finally reflow soldering the solder material, spherical solder bumps can be formed. This process can be performed after the traditional wafer fabrication process is completed, without having to go through the packaging plant. Compared with the formation process currently used by packaging plants, the process steps are simpler and easier to operate, which can significantly reduce process costs. At the same time, the spherical solder bumps formed are of high quality, which can reduce yield loss in subsequent packaging processes.

[0023] Positioning the welding material via channels on the positioning plate not only facilitates operation but also improves the quality of spherical weld bumps. Furthermore, the quality of spherical weld bumps can be further improved by controlling the size of the welding material or the temperature and time during reflow soldering. Attached Figure Description

[0024] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:

[0025] Figure 1 This is a schematic diagram of the semiconductor structure formation method according to an embodiment of this application;

[0026] Figures 2 to 10 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of this application. Detailed Implementation

[0027] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0028] The technical solution of this application, after the traditional wafer fabrication process is completed, forms spherical solder bumps on the pad through a simple and easy-to-operate process method for subsequent flip chip packaging, thereby reducing the cost of the flip chip packaging process and achieving a high yield rate.

[0029] refer to Figure 1 This application provides a method for forming a semiconductor structure, including:

[0030] Step S1: Provide a semiconductor substrate, the semiconductor substrate including a top metal layer and a passivation layer located on the semiconductor substrate and a portion of the top metal layer;

[0031] Step S2: Apply welding material to a portion of the top metal layer, wherein the surface of the welding material is higher than the top surface of the passivation layer;

[0032] Step S3: Form a sealing layer on the top metal layer between the welding material and the passivation layer, with a surface flush with the top surface of the passivation layer;

[0033] Step S4: Perform reflow soldering on the welding material to form spherical welding bumps.

[0034] refer to Figure 2 The semiconductor substrate 100 is formed using conventional wafer fabrication processes; therefore, the structure of the semiconductor substrate 100 is not specifically limited, and it may also be referred to as a chip below. The top metal layer 200 on the semiconductor substrate 100 can be an I / O pad, and the material of the top metal layer 200 may include, for example, aluminum. The thickness of the top metal layer 200 can be 1.75 μm to 4.15 μm. The passivation layer 300 on the semiconductor substrate 100 and part of the top metal layer 200 serves as an electrical insulator. The material of the passivation layer 300 may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0035] refer to Figure 3 The method for setting the welding material may include: setting a positioning plate 400 on the passivation layer 300, the positioning plate 400 having channels 410 for defining the position of the welding material, the positioning plate 400 being a single plate with a plurality of channels 410 distributed thereon, which is placed on the passivation layer 300 during use. The positioning plate 400 may be made of metal, such as a steel plate. The size of the positioning plate 400 is determined according to the actual situation. If the positioning plate 400 is only used to make welding bumps for a single chip, then... Figure 3 The structure of the positioning plate 400 shown can achieve its function. If the positioning plate 400 is used to make solder bumps for multiple chips, then... Figure 3Based on the structure of the positioning plate 400 shown, it extends a certain width to the left and right sides, and each chip has a corresponding channel 410 above the top metal layer 200. Figure 4 The illustration shows a configuration where the positioning plate 400 has four channels 410. The thickness of the positioning plate 400 is determined based on actual conditions. In some embodiments, the sum of the thicknesses of the positioning plate 400 and the passivation layer 300 is not less than half the thickness of the welding material, which helps maintain the balance of the welding material.

[0036] Continue to refer to Figure 4 The channel 410 can be a continuous channel, and the extending direction of the channel 410 is the same as the extending direction of the top metal layer 200. (Reference) Figure 5 In some embodiments, the channel 410 may include a plurality of sub-channels 411, and the sub-channels 411 are spaced apart along the extension direction of the top metal layer 200. Compared with the continuous channel, the sub-channels 411 are more capable of precisely positioning the welding material.

[0037] refer to Figure 6 The welding material 510 is disposed on the top metal layer 200 through the channel 410. (Reference) Figure 7 The welding material 510 may include a plurality of discrete welding material blocks 511. Figure 7 This is merely an example of the relative positional relationship between the welding material 510 and the top metal layer 200, and does not limit their relative dimensions. When the channel 410 is Figure 4 When the channel 410 is a continuous channel as shown, the channel 410 can define the lateral position of the welding material 510 on the top metal layer 200, but the longitudinal position of the welding material block 511 on the top metal layer 200 cannot be directly defined. When the channel 410 includes, as shown, Figure 5 As shown, the channel 410, with its plurality of sub-channels 411, can define not only the lateral position of the welding material 510 on the top metal layer 200, but also the longitudinal position of the welding material block 511 on the top metal layer 200. The material of the welding material 510 may, for example, include a Sn-Pb alloy. After the welding material 510 is set, the positioning plate 400 can be removed.

[0038] The width of the welding material 510 needs to be within an appropriate range. If the width is too small, it will cause poor contact and prevent the application of electricity. If the width is too large, it will cause the spherical welding bumps formed during subsequent reflow soldering to extend beyond the top metal layer 200. In some embodiments, the width of the welding material 510 is 1 / 2 to 2 / 3 of the width of the top metal layer 200.

[0039] refer to Figure 8 The method for forming the sealing layer includes forming a sealing material layer 610 on the surfaces of the passivation layer 300, the top metal layer 200, and the welding material 510. The material of the sealing material layer 610 can be the same as the material of the top metal layer 200; for example, the material of the sealing material layer 610 may include aluminum. The sealing material layer 610 can be formed, for example, by conventional deposition processes such as chemical vapor deposition or physical vapor deposition.

[0040] refer to Figure 9 The sealing material layer 610 above the surface of the passivation layer 300 is removed to form the sealing layer 600. In some embodiments, the sealing material layer 610 may be etched using a dry etching process and stopped on the passivation layer 300 to remove the sealing material layer 610 above the surface of the passivation layer 300.

[0041] refer to Figure 10 The welding material 510 is reflow soldered to form spherical welding bumps 500. In some embodiments, the reflow soldering temperature can be 100℃~160℃, and the time can be 90s~120s. The top surface of the spherical welding bumps 500 needs to be higher than the top surface of the passivation layer 300. In some embodiments, the height of the spherical welding bumps 500 can be 5.25μm~12.45μm.

[0042] Continue to refer to Figure 10 This application also provides a semiconductor structure, including: a semiconductor substrate 100, the semiconductor substrate 100 including a top metal layer 200 and a passivation layer 300 located on the semiconductor substrate 100 and a portion of the top metal layer 200; ball-shaped welding bumps 500 located on a portion of the top metal layer 200, and the surface of the ball-shaped welding bumps 500 is higher than the top surface of the passivation layer 300; and a sealing layer 600 located on the top metal layer 200 between the ball-shaped welding bumps 500 and the passivation layer 300, and the surface of the sealing layer 600 is flush with the top surface of the passivation layer 300.

[0043] The semiconductor substrate 100 can be a chip formed using conventional wafer fabrication processes. The thickness of the top metal layer 200 can be 1.75 μm to 4.15 μm, and the height of the ball-shaped bonding bumps 500 can be 5.25 μm to 12.45 μm. The sealing layer 600 and the top metal layer 200 can be made of the same material, for example, aluminum. The ball-shaped bonding bumps 500 can be made of, for example, a Sn-Pb alloy. The passivation layer 300 can be made of, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0044] The specific number of the spherical welding bumps 500 is not required and can be designed according to actual needs. When the top metal layer 200 has multiple spherical welding bumps 500, they are distributed along the extension direction of the top metal layer 200.

[0045] The semiconductor structure and its formation method provided in this application embodiment can better form the spherical solder bumps required for packaging. Compared with the solder bump process of current packaging plants, the structure is simple and the process steps are easy to implement. The entire formation process can be completed in the wafer fab, eliminating the process of making spherical solder bumps in the packaging plant, improving packaging efficiency. At the same time, the formed spherical solder bumps have high quality, which can improve the yield of subsequent packaging.

[0046] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0047] It should be understood that the term "comprising" used in this embodiment, when used in this application document, indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or groups thereof.

[0048] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including a top metal layer and a passivation layer located on the semiconductor substrate and a portion of the top metal layer; A welding material is disposed on a portion of the top metal layer, and the surface of the welding material is higher than the top surface of the passivation layer; A sealing layer with a surface flush with the top surface of the passivation layer is formed on the top metal layer between the welding material and the passivation layer; The welding material is subjected to reflow soldering to form spherical welding bumps.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The welding material comprises several discrete welding material blocks.

3. The method for forming a semiconductor structure according to claim 1, characterized in that, A method for applying welding material to a portion of the top metal layer includes: A positioning plate is disposed on the passivation layer, and the positioning plate includes a channel for defining the position of the welding material; The welding material is placed on a portion of the top metal layer through the channel, and the positioning plate is removed.

4. The method for forming a semiconductor structure according to claim 3, characterized in that, The channel is a continuous channel, and the channel and the top metal layer extend in the same direction.

5. The method for forming a semiconductor structure according to claim 3, characterized in that, The channel includes a number of sub-channels spaced apart along the extension direction of the top metal layer.

6. The method for forming a semiconductor structure according to claim 1, characterized in that, The method for forming the sealing layer includes: A sealing material layer is formed on the surface of the passivation layer, the top metal layer, and the welding material; The sealing material layer above the surface of the passivation layer is removed to form the sealing layer.

7. The method for forming a semiconductor structure according to claim 6, characterized in that, The sealing material layer is etched using a dry etching process, and the etching stops on the passivation layer to remove the sealing material layer above the surface of the passivation layer.

8. The method for forming a semiconductor structure according to claim 1, characterized in that, The width of the welding material is 1 / 2 to 2 / 3 of the width of the top metal layer.

9. The method for forming a semiconductor structure according to claim 1, characterized in that, The thickness of the top metal layer is 1.75μm to 4.15μm, and the height of the spherical welding bumps is 5.25μm to 12.45μm.

10. The method for forming a semiconductor structure according to claim 1, characterized in that, The reflow soldering process is performed at a temperature of 100℃~160℃ for a time of 90s~120s.

11. The method for forming a semiconductor structure according to claim 1, characterized in that, The sealing layer and the top metal layer are made of the same material.

12. The method for forming a semiconductor structure according to claim 1, characterized in that, The sealing layer and the top metal layer are made of aluminum, and the welding material is a Sn-Pb alloy.

13. A semiconductor structure, characterized in that, include: A semiconductor substrate, wherein the semiconductor substrate includes a top metal layer and a passivation layer located on the semiconductor substrate and a portion of the top metal layer; A spherical welding bump is located on a portion of the top metal layer, and the surface of the spherical welding bump is higher than the top surface of the passivation layer; A sealing layer is located on the top metal layer between the spherical welding bump and the passivation layer, and the surface of the sealing layer is flush with the top surface of the passivation layer. The sealing layer and the top metal layer are made of the same material.

14. The semiconductor structure according to claim 13, characterized in that, The thickness of the top metal layer is 1.75μm to 4.15μm, and the height of the spherical welding bumps is 5.25μm to 12.45μm.

15. The semiconductor structure according to claim 13, characterized in that, The sealing layer and the top metal layer are made of aluminum, and the spherical weld bumps are made of Sn-Pb alloy.

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