A chip packaging structure manufacturing method and a chip packaging structure

Abstract

The application provides a chip packaging structure manufacturing method and a chip packaging structure, and relates to the technical field of chip packaging. The method comprises the following steps: providing a substrate; arranging a first positioning mark on the substrate; arranging a second positioning mark on the substrate based on the first positioning mark; adhering a chip assembly on the substrate based on the second positioning mark, wherein the chip assembly comprises at least one chip, and the chip comprises a pin; forming a plastic encapsulation layer covering the chip assembly on one side of the substrate; arranging an insulating layer on the side of the chip assembly opposite to the plastic encapsulation layer; and forming a redistribution layer on the side of the insulating layer away from the plastic encapsulation layer based on the second positioning mark. The application can greatly improve the alignment accuracy between the redistribution block and the pins of the chip, thereby greatly improving the precision of the chip packaging, and further improving the quality of the chip packaging structure.

Description

Technical Field

[0001] This application relates to the field of chip packaging technology, and more specifically, to a method for manufacturing a chip packaging structure and a chip packaging structure. Background Technology

[0002] A chip, also known as a microcircuit, microchip, or integrated circuit, is actually a general term for semiconductor electronic components. Chips can be classified in many ways; based on their signal processing capabilities, they can be divided into analog chips and digital chips. To protect the chip, it needs to be packaged, forming a chip package structure.

[0003] However, the alignment of the chip package in the related technologies is poor, which affects the quality of the chip package structure. Summary of the Invention

[0004] In order to overcome the technical problems mentioned in the above technical background, this application provides a method for manufacturing a chip packaging structure and a chip packaging structure.

[0005] This application provides a method for fabricating a chip packaging structure, the method comprising:

[0006] Provide a substrate;

[0007] A first positioning mark is provided on the substrate;

[0008] Based on the first positioning mark, a second positioning mark is provided on the substrate;

[0009] Based on the second positioning mark, a chip assembly is attached to the substrate, the chip assembly including at least one chip, the chip including pins;

[0010] A molding compound layer covering the chip assembly is formed on one side of the substrate;

[0011] An insulating layer is provided on one side of the chip assembly relative to the molding layer;

[0012] Based on the second positioning mark, a redistribution layer is formed on the side of the insulating layer away from the molding layer. The redistribution layer includes redistribution units that are electrically connected to the pins of the chip.

[0013] In one possible implementation, the step of setting a second positioning mark on the substrate based on the first positioning mark includes:

[0014] A metal layer is formed on one side of the substrate;

[0015] Photoresist is applied to the side of the metal layer away from the substrate, and the photoresist is exposed and developed to form a patterned photoresist.

[0016] Based on the patterned photoresist, the metal layer is etched to form a patterned metal block;

[0017] Based on the first positioning mark, a portion of the patterned metal block is removed, and the remaining portion of the patterned metal block forms a second positioning mark on the substrate.

[0018] In one possible implementation, after the step of etching the metal layer based on the patterned photoresist to form a patterned metal block, the method further includes:

[0019] Remove the photoresist;

[0020] A transparent protective layer covering the patterned metal block is coated on one side of the substrate;

[0021] The transparent protective layer is then polished.

[0022] In one possible implementation, prior to the step of attaching the chip assembly to the substrate based on the second positioning mark, the method further includes:

[0023] Based on the first positioning mark, check the first offset of the second positioning mark; if the first offset exceeds the preset offset, reset the second positioning mark or provide a new substrate.

[0024] In one possible implementation, prior to the step of forming an insulating layer on one side of the chip assembly opposite to the molding compound, the method further includes:

[0025] The molding layer, the chip assembly, and the second positioning mark are peeled off the substrate as a whole.

[0026] Based on the second positioning marker, the second offset of the chip assembly is detected.

[0027] In one possible implementation, the step of forming a redistribution layer on the side of the insulating layer away from the molding compound, based on the second positioning mark, includes:

[0028] Based on the second offset and the second positioning mark, a redistribution layer is formed on the side of the insulating layer away from the molding layer.

[0029] In one possible implementation, the step of forming a redistribution layer on the side of the insulating layer away from the molding compound, based on the second positioning mark, includes:

[0030] Multiple vias are formed on the insulating layer along a direction perpendicular to the insulating layer, and the vias correspond to the pins of the chip;

[0031] Based on the second positioning mark, a redistribution layer is formed on the side of the insulating layer away from the molding layer; the redistribution unit is electrically connected to the pins of the chip through the via.

[0032] In one possible implementation, the step of forming a molding layer covering the chip assembly on one side of the substrate includes:

[0033] A molding compound layer covering the chip assembly is formed on one side of the substrate, and the molding compound layer is polished.

[0034] In one possible implementation, after the step of forming a redistribution layer on the side of the insulating layer away from the molding compound layer based on the second positioning mark, the method further includes:

[0035] The encapsulation layer between the packaged chips is cut along a direction perpendicular to the substrate to separate the packaged chips from each other.

[0036] In one possible implementation, this application also provides a chip packaging structure, which is fabricated by the chip packaging structure fabrication method described in this application.

[0037] Compared with the prior art, this application has at least the following beneficial effects:

[0038] This application provides a method for manufacturing a chip packaging structure and a chip packaging structure. Based on a first positioning mark, a second positioning mark is set on the substrate. The chip components and the redistribution layer are both set based on the second positioning mark. Therefore, the alignment accuracy between the redistribution block and the chip pins can be greatly improved, thereby greatly improving the accuracy of chip packaging and thus improving the quality of the chip packaging structure. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 A top view schematic diagram illustrating the bonding of chip components on a substrate in the related art provided in this application is illustrated.

[0041] Figure 2 A top view schematic diagram illustrating the covering of a chip component by a molding compound in the related technologies provided in this application is illustrated.

[0042] Figure 3 A top view diagram illustrating the chip assembly after it has been peeled off the substrate in the related technology provided in this application is shown;

[0043] Figure 4 A top view schematic diagram illustrating the redistribution layer on a chip assembly is provided in the related technology of this application;

[0044] Figure 5 A top view schematic diagram of chip offset in the related technology provided in this application is illustrated;

[0045] Figure 6 A top view schematic diagram of rewiring layer offset in the related technology provided in this application is illustrated;

[0046] Figure 7 A cross-sectional schematic diagram of the chip package structure fabricated using the methods of related technologies provided in this application is illustrated.

[0047] Figure 8 A flowchart illustrating the fabrication method of the chip packaging structure provided in this application is shown.

[0048] Figure 9 A top view of the first positioning mark provided in this application is illustrated.

[0049] Figure 10 A top view of the second positioning mark provided in this application is illustrated.

[0050] Figure 11 A top view schematic diagram illustrating the bonding of a chip assembly to a substrate based on a second positioning mark provided in this application is illustrated.

[0051] Figure 12 A top view of the molding compound layer covering the chip assembly provided in this application is illustrated.

[0052] Figure 13 This application provides a top view diagram showing the chip assembly and the second positioning mark after being peeled off from the substrate.

[0053] Figure 14 The example provided in this application is a cross-sectional schematic diagram of the chip assembly and the second positioning mark after being peeled off from the substrate;

[0054] Figure 15 A cross-sectional schematic diagram of an insulating layer provided in this application is illustrated on the side of a chip assembly away from the molding compound.

[0055] Figure 16 A cross-sectional schematic diagram of a via in an insulating layer provided in this application is illustrated.

[0056] Figure 17A top view of the redistribution layer on the insulation provided in this application is illustrated.

[0057] Figure 18 A cross-sectional schematic diagram of a redistribution layer on insulation is provided in this application;

[0058] Figure 19 A schematic diagram illustrating the specific execution method of step S12 provided in this application is shown;

[0059] Figure 20 A cross-sectional schematic diagram of a metal layer formed on one side of a substrate is provided in this application;

[0060] Figure 21 A cross-sectional schematic diagram of a metal layer coated with photoresist on the side away from the substrate, as provided in this application, is illustrated.

[0061] Figure 22 A cross-sectional schematic diagram of etching a metal layer to form a patterned metal block is provided in this application;

[0062] Figure 23 This example illustrates a flowchart of a method following the step of etching a metal layer to form a patterned metal block, as provided in this application.

[0063] Figure 24 A cross-sectional schematic diagram illustrating the removal of photoresist from the side of a patterned metal block away from the substrate, as provided in this application, is illustrated.

[0064] Figure 25 A cross-sectional schematic diagram of a transparent protective layer covering a patterned metal block coated on one side of a substrate is provided in this application.

[0065] Figure 26 A top view of a patterned metal block provided in this application is illustrated.

[0066] Figure 27 A cross-sectional schematic diagram of a rewiring unit with solder balls provided in this application is illustrated.

[0067] Reference numerals: 1. Substrate; 2. Chip assembly; 21. Chip; 211. Pin; 3. Positioning mark; 4. Molding layer; 5. Redistribution layer; 51. Redistribution block; 6. Insulating layer; 61. Via; 7. First positioning mark; 8. Second positioning mark; 9. Metal layer; 91. Patterned metal block; 10. Patterned photoresist; 11. Transparent protective layer; 12. Solder ball. Detailed Implementation

[0068] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0069] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0070] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0071] In the description of this application, it should be noted that the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product is usually placed when in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or electronic component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0072] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.

[0073] The fabrication method of chip packaging structure in related technologies includes the following steps:

[0074] Please see Figure 1 Positioning marks 3 are set on substrate 1, and chip assembly 2 is attached to substrate 1 based on positioning marks 3. Chip assembly 2 includes chip 21, and chip 21 includes pins.

[0075] Please see Figure 2 A molding layer 4 covering the chip assembly 2 is disposed on the substrate 1.

[0076] Please see Figure 3 The chip assembly 2 and the molding layer 4 are peeled off from the substrate 1 as a whole.

[0077] Please see Figure 4An insulating layer is formed on the side of the chip assembly 2 opposite to the molding layer 4, and vias are formed on the insulating layer. Then, a redistribution layer 5 is formed on the side of the insulating layer away from the substrate 1. The redistribution layer 5 is electrically connected to the pins of the chip 21 through the vias to complete the fabrication of the chip 21 package structure.

[0078] However, since the chip assembly 2 is set based on the positioning mark 3 on the substrate 1, the via 61 on the insulating layer 6 and the redistribution layer 5 can only be set using the chip 21 as a marker. Therefore, the markers referenced for setting the chip assembly 2 and the redistribution layer 5 are different. Please see [link to relevant documentation]. Figures 5-7 If chip 21 is offset, and via 61 and redistribution layer 5 are set with the offset chip 21 as a marker, via 61 and redistribution layer 5 will also be offset. Therefore, via 61 on insulating layer 6 will be misaligned with pin 211 of chip 21, making it difficult for redistribution layer 5 to be electrically connected to pin 211 of chip 21 through via 61 on insulating layer 6, thus affecting the packaging accuracy of chip 21 and ultimately affecting the quality of chip 21 packaging structure.

[0079] To address the aforementioned technical problems, the inventor has innovatively designed the following technical solution, the specific implementation of which will be described in detail below with reference to the accompanying drawings.

[0080] Please see Figure 8 This application provides a method for fabricating a chip 21 package structure, the method comprising:

[0081] S10: Provide a substrate 1.

[0082] Substrate 1 can be a glass substrate 1, etc.

[0083] S11: A first positioning mark 7 is set on the substrate 1.

[0084] Please see Figure 9 The first positioning mark 7 can be set by drilling holes or laser drilling on the substrate 1. The first positioning mark 7 can be located at the top corner of the substrate 1.

[0085] S12: Based on the first positioning mark 7, a second positioning mark 8 is set on the substrate 1.

[0086] Please see Figure 10 Based on the first positioning mark 7, multiple second positioning marks 8 are set on the substrate 1. The second positioning marks 8 can also be set at the top corner of the substrate 1, and one second positioning mark 8 corresponds to one first positioning mark 7.

[0087] S13: Based on the second positioning mark 8, a chip assembly 2 is attached to the substrate 1. The chip assembly 2 includes at least one chip 21, and the chip 21 includes pins 211.

[0088] Please see Figure 11 Using the second positioning mark 8 as a reference, the chip assembly 2 is attached to the substrate 1. For example, an adhesive layer can be coated on the substrate 1, and then the chip assembly 2 can be attached to the substrate 1 through the adhesive layer. The chip assembly 2 may include multiple chips 21, and each chip 21 may include multiple pins 211, through which signals of the chip 21 can be transmitted.

[0089] S14: A molding layer 4 covering the chip assembly 2 is formed on one side of the substrate 1.

[0090] Please see Figure 12 A molding layer 4 is provided on one side of the substrate 1. The molding layer 4 covers the chip 21 and protects the chip 21. The molding layer 4 can be made of epoxy resin.

[0091] S15: An insulating layer 6 is provided on the side of the chip assembly 2 opposite to the molding layer 4.

[0092] Please see Figures 13-14 The molding layer 4, chip assembly 2, and second positioning mark 8 are peeled off from the substrate 1 as a whole.

[0093] Please see Figure 15 An insulating layer 6 is provided on the side of the chip assembly 2 opposite to the molding layer 4. The insulating layer 6 can protect and insulate the chip 21. The material of the insulating layer 6 can be polyimide.

[0094] S16: Based on the second positioning mark 8, a redistribution layer 5 is formed on the side of the insulating layer 6 away from the molding layer 4. The redistribution layer 5 includes redistribution units, which are electrically connected to the pins 211 of the chip 21.

[0095] Please see Figure 16 Along a direction perpendicular to the insulating layer 6, based on the second positioning mark 8, a plurality of vias 61 are formed on the insulating layer 6, and the vias 61 correspond to the pins 211 of the chip 21.

[0096] Please see Figures 17-18 Based on the second positioning mark 8, a redistribution layer 5 is formed on the side of the insulating layer 6 away from the molding layer 4; the redistribution unit is electrically connected to the pin 211 of the chip 21 through a via 61.

[0097] Since the chip assembly 2 is disposed on the substrate 1, the via 61 is formed on the insulating layer 6, and the redistribution layer 5 is disposed on the insulating layer 6, all are based on the second positioning mark 8. Therefore, the via 61 formed on the insulating layer 6 is more likely to correspond to the pin 211 of the chip 21, thereby making it easier to make the redistribution layer 5 and the pin 211 of the chip 21 electrically connected through the via 61.

[0098] Based on the above design, in this embodiment, a second positioning mark 8 is set on the substrate 1 based on the first positioning mark 7. The chip assembly 2 and the redistribution layer 5 are both set based on the second positioning mark 8. Therefore, the alignment accuracy between the redistribution block 51 and the pins 211 of the chip 21 can be greatly improved, thereby greatly improving the accuracy of the chip 21 packaging and thus improving the quality of the chip 21 packaging structure.

[0099] In one possible implementation, please refer to Figure 19 The step of setting a second positioning mark 8 on the substrate 1 based on the first positioning mark 7 includes:

[0100] S121: A metal layer 9 is formed on one side of the substrate 1.

[0101] Please see Figure 20 A metal layer 9 is sputtered on one side of the substrate 1. The metal layer 9 can be a single-layer structure of aluminum or a double-layer structure of titanium and copper. The thickness of the metal layer 9 can be 0.1μm-0.5μm, such as 0.1μm, 0.2μm, 0.3μm, 0.4μm or 0.5μm.

[0102] S122: Photoresist is coated on the side of the metal layer 9 away from the substrate 1, and the photoresist is exposed and developed to form patterned photoresist 10.

[0103] Please see Figure 21 Photoresist is applied to the side of the metal layer 9 away from the substrate 1. Then, the photoresist is exposed and developed according to the shape and position of the second positioning mark 8 to be formed, and finally the patterned photoresist 10 is formed.

[0104] S123: Based on the patterned photoresist 10, the metal layer 9 is etched to form a patterned metal block 91.

[0105] Please see Figure 22 Based on the patterned photoresist 10, the metal layer 9 is etched to finally form a patterned metal block 91.

[0106] S124: Based on the first positioning mark 7, a portion of the patterned metal block 91 is removed, and the remaining portion of the patterned metal block 91 forms a second positioning mark 8 on the substrate 1.

[0107] Please see again Figure 2 Based on the first positioning mark 7, some patterned metal blocks 91 are removed, and the remaining patterned metal blocks 91 are used as second positioning marks 8. For example, four patterned metal blocks 91 located at the top corner of the substrate 1 and corresponding to the first positioning mark 7 are used as four second positioning marks 8.

[0108] The above method makes it easier to prepare the second positioning mark 8.

[0109] In one possible implementation, please refer to Figure 23 After the step of etching the metal layer 9 based on the patterned photoresist 10 to form the patterned metal block 91, the method further includes:

[0110] S01: Remove photoresist.

[0111] Please see Figure 24 The photoresist on the side of the patterned metal block 91 away from the substrate 1 is removed.

[0112] S02: A transparent protective layer 11 covering the patterned metal block 91 is coated on one side of the substrate 1.

[0113] Please see Figure 25 A transparent protective layer 11 covering a patterned metal block 91 is coated on one side of the substrate 1, and the transparent protective layer 11 is cured. The transparent protective layer 11 can be made of polyimide.

[0114] Please see Figure 26 The orthographic projection shape of the patterned metal block 91 on the molding layer 4 can be a cross shape, etc., so that the center of the second positioning mark 8 can be detected more accurately, thereby improving the accuracy of using the second positioning mark 8 as a positioning reference.

[0115] S03: Grind the transparent protective layer 11.

[0116] Depending on actual needs, the transparent protective layer 11 can be ground to thin it, and the patterned metal block 91 can be ground into individual pieces that are separated from each other, which makes it easier to form the second positioning mark 8 in step S124.

[0117] By using the above method, a transparent protective layer 11 is provided on the second positioning mark 8, which can reduce the risk of oxidation of the second positioning mark 8 and scratches on the second positioning mark 8, and can protect the second positioning mark 8.

[0118] In one possible implementation, prior to the step of attaching the chip assembly 2 to the substrate 1 based on the second positioning mark 8, the method further includes: checking a first offset of the second positioning mark 8 based on the first positioning mark 7; if the first offset exceeds a preset offset, then resetting the second positioning mark 8, or providing a new substrate 1.

[0119] The preset offset is a pre-set offset. If the first offset is within the preset offset, it means that the setting of the second positioning mark 8 meets the requirements. If the first offset exceeds the preset offset, it means that the setting of the second positioning mark 8 does not meet the requirements.

[0120] The second positioning mark 8, set based on the first positioning mark 7, may have a large offset. Therefore, based on the first positioning mark 7, the first offset of the second positioning mark 8 is checked. If the first offset exceeds a preset offset, the second positioning mark 8 is reset on the substrate 1, or the second positioning mark 8 is discarded, a new substrate 1 is provided, and the second positioning mark 8 is reset on the substrate 1. In this way, before the chip assembly 2 is bonded to the substrate 1, it is possible to detect whether the second positioning mark 8 is offset beyond the specifications, and timely process control can be performed, thereby further improving the packaging accuracy of the chip 21.

[0121] In one possible implementation, prior to the step of setting the insulating layer 6 on the side of the chip assembly 2 opposite to the molding compound 4, the method further includes: detecting a second offset of the chip assembly 2 based on the second positioning mark 8.

[0122] Before the step of forming the insulating layer 6 on the side of the chip assembly 2 opposite to the molding compound 4, that is, before the step of forming the redistribution layer 5 on the side of the insulating layer 6 away from the molding compound 4, the second offset of the chip assembly 2 is detected again based on the second positioning mark 8. Then, based on the second offset, the redistribution layer 5 is formed on the side of the insulating layer 6 away from the molding compound 4. In this way, the redistribution layer 5 can be formed with the second offset as compensation, thereby enabling a more precise electrical connection between the redistribution layer 5 and the pins 211 of the chip 21 through the via 61.

[0123] In one possible implementation, the step of forming a molding compound 4 covering the chip assembly 2 on one side of the substrate 1 includes: forming a molding compound 4 covering the chip assembly 2 on one side of the substrate 1 and grinding the molding compound 4.

[0124] A grinding process can be selectively added according to different customer needs, which can reduce the thickness of the molding layer 4 and make the molding layer 4 flatter, thus making it easier to meet customer needs.

[0125] In one possible implementation, after forming the redistribution layer 5 on the side of the insulating layer 6 away from the molding compound layer 4 based on the second positioning mark 8, the method further includes: cutting the molding compound layer 4 between the packaged chips 21 along a direction perpendicular to the substrate 1, thereby separating each packaged chip 21 from the others. In this way, the packaged chip assembly 2 can be divided into independent chip 21 package structures according to customer needs.

[0126] In one possible implementation, please refer to Figure 27 Following the step of forming a redistribution layer 5 on the side of the insulating layer 6 away from the molding compound 4 based on the second positioning mark 8, the method further includes: placing solder balls 12 on the redistribution unit. The solder balls 12 facilitate the extraction of signals from the chip 21.

[0127] In summary, this application sets a second positioning mark 8 on the substrate 1 based on the first positioning mark 7. Both the chip assembly 2 and the redistribution layer 5 are set based on the second positioning mark 8. Therefore, the alignment accuracy between the redistribution block 51 and the pins 211 of the chip 21 can be greatly improved, thereby significantly improving the packaging accuracy of the chip 21 and ultimately enhancing the quality of the chip 21 packaging structure. Because the alignment accuracy of the chip 21 packaging structure is higher, the distance between the pins 211 of the chip 21 can be set to be smaller.

[0128] Based on the same inventive concept, this application also provides a chip packaging structure, which is fabricated using the chip packaging structure fabrication method described in this application. This chip packaging structure has higher alignment accuracy and better quality.

[0129] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a chip packaging structure, characterized in that, The method includes: Provide a substrate; A first positioning mark is provided on the substrate; Based on the first positioning mark, a second positioning mark is provided on the substrate; Based on the second positioning mark, a chip assembly is attached to the substrate, the chip assembly including at least one chip, the chip including pins; A molding compound layer covering the chip assembly is formed on one side of the substrate; An insulating layer is provided on one side of the chip assembly relative to the molding layer; Based on the second positioning mark, a redistribution layer is formed on the side of the insulating layer away from the molding layer. The redistribution layer includes redistribution units that are electrically connected to the pins of the chip.

2. The method for fabricating the chip packaging structure as described in claim 1, characterized in that, The step of setting a second positioning mark on the substrate based on the first positioning mark includes: A metal layer is formed on one side of the substrate; Photoresist is applied to the side of the metal layer away from the substrate, and the photoresist is exposed and developed to form a patterned photoresist. Based on the patterned photoresist, the metal layer is etched to form a patterned metal block; Based on the first positioning mark, a portion of the patterned metal block is removed, and the remaining portion of the patterned metal block forms a second positioning mark on the substrate.

3. The method for fabricating the chip packaging structure as described in claim 2, characterized in that, After the step of etching the metal layer based on the patterned photoresist to form a patterned metal block, the method further includes: Remove the photoresist; A transparent protective layer covering the patterned metal block is coated on one side of the substrate; The transparent protective layer is then polished.

4. The method for fabricating the chip packaging structure as described in claim 1, characterized in that, Prior to the step of attaching the chip assembly to the substrate based on the second positioning mark, the method further includes: Based on the first positioning mark, check the first offset of the second positioning mark; if the first offset exceeds the preset offset, reset the second positioning mark or provide a new substrate.

5. The method for fabricating the chip packaging structure as described in claim 1, characterized in that, Prior to the step of forming an insulating layer on one side of the chip assembly relative to the molding compound, the method further includes: The molding layer, the chip assembly, and the second positioning mark are peeled off the substrate as a whole. Based on the second positioning marker, the second offset of the chip assembly is detected.

6. The method for fabricating the chip packaging structure as described in claim 5, characterized in that, The step of forming a redistribution layer on the side of the insulating layer away from the molding layer based on the second positioning mark includes: Based on the second offset and the second positioning mark, a redistribution layer is formed on the side of the insulating layer away from the encapsulation layer.

7. The method for fabricating the chip packaging structure as described in claim 1, characterized in that, The step of forming a redistribution layer on the side of the insulating layer away from the molding layer based on the second positioning mark includes: Multiple vias are formed on the insulating layer along a direction perpendicular to the insulating layer, and the vias correspond to the pins of the chip; Based on the second positioning mark, a redistribution layer is formed on the side of the insulating layer away from the molding layer; the redistribution unit is electrically connected to the pins of the chip through the via.

8. The method for fabricating the chip packaging structure as described in claim 7, characterized in that, The step of forming a molding compound covering the chip assembly on one side of the substrate includes: A molding compound layer covering the chip assembly is formed on one side of the substrate, and the molding compound layer is polished.

9. The method for fabricating the chip packaging structure as described in claim 8, characterized in that, After the step of forming a redistribution layer on the side of the insulating layer away from the molding compound layer based on the second positioning mark, the method further includes: The encapsulation layer between the packaged chips is cut along a direction perpendicular to the substrate to separate the packaged chips from each other.

10. A chip packaging structure, characterized in that, The chip packaging structure is manufactured by the method for manufacturing the chip packaging structure according to any one of claims 1-9.

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