Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same. The method includes forming linear semiconductor patterns extending along a first direction and arranged in a second direction and a vertical direction on a semiconductor substrate, the linear semiconductor patterns being separated by first insulating layers, the linear semiconductor patterns including channel regions and drain regions connected to the channel regions; etching a portion of the first insulating layers on a side of the drain regions to form first openings; ion doping the drain regions exposed by the first openings to form ground doped regions in the drain regions, the ground doped regions being connected to the channel regions and having the same doping type as the channel regions; and filling the first openings with conductive material to form ground conductive plugs electrically connected to the ground doped regions and the semiconductor substrate. The channel regions can be grounded by forming the ground doped regions and the ground conductive plugs to prevent the generation of floating body effects.

Description

Technical Field

[0001] This disclosure relates to the field of memory, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers, consisting of many repeating memory cells. Each memory cell typically includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the transistor to turn on or off, thereby reading data information stored in the capacitor through the bit line, or writing data information into the capacitor for storage through the bit line.

[0003] To improve integration density, current 3D DRAM manufacturing processes typically employ multi-layered stacked lateral transistor structures. However, in these structures, the channel regions of the lateral transistors are floating, making it easy for charge to accumulate and causing a floating body effect. This floating body effect can lead to many adverse consequences, severely impacting device performance and even causing device failure. Summary of the Invention

[0004] This disclosure provides a method for forming a semiconductor structure, including:

[0005] Provide semiconductor substrates;

[0006] Linear semiconductor patterns extending along a first direction and arranged in an array in a second direction and a vertical direction are formed on the semiconductor substrate, and a first insulating layer is formed between the linear semiconductor patterns; the linear semiconductor patterns include a channel region and a drain region connected to the channel region; a portion of the first insulating layer on one side of the drain region is etched to form a first opening, the first opening exposing a first sidewall of a plurality of drain regions arranged in a vertical direction, and the bottom of the first opening exposing a portion of the surface of the semiconductor substrate;

[0007] The drain region exposed by the first opening is ion-doped to form a ground doped region in the drain region, the ground doped region being connected to the channel region and having the same doping type as the channel region;

[0008] The first opening is filled with conductive material to form a grounded conductive plug, which is electrically connected to the grounded doped region and the semiconductor substrate.

[0009] Some embodiments of this disclosure also provide a semiconductor structure, including:

[0010] Semiconductor substrate;

[0011] The semiconductor substrate has an alternating stacked structure of insulating layers and linear semiconductor patterned layers. Each linear semiconductor patterned layer includes a plurality of parallel linear semiconductor patterns extending along a first direction. Each linear semiconductor pattern includes a channel region and a ground doped region connected to the channel region. The ground doped region has the same doping type as the channel region.

[0012] A ground conductive plug is located between adjacent linear semiconductor patterns, the ground conductive plug extends vertically through the stacked structure and connects to the semiconductor substrate, and the ground conductive plug is connected to the ground doped region on one side in a second direction.

[0013] The semiconductor structure formation method in some of the foregoing embodiments of this disclosure enables the channel region to be grounded by forming a ground doped region and a ground conductive plug, thereby releasing the charge accumulated in the channel region through the ground doped region and the ground conductive plug, preventing the generation of the floating body effect, improving the performance of the device, and the ground doped region is formed in the drain region, and the ground conductive plug is formed in the first trench, which does not occupy additional area and can ensure the integration of the formed 3D DRAM device. Attached Figure Description

[0014] Figure 1-52 This is a schematic diagram of the formation process of a semiconductor structure in some embodiments of this disclosure. Detailed Implementation

[0015] The specific embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0016] This disclosure first provides a method for forming a semiconductor structure, and the method is described in detail below with reference to the accompanying drawings.

[0017] refer to Figures 1-4 ,in Figure 2 for Figure 1 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 3 for Figure 1 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 4 for Figure 1 A schematic diagram of the cross-sectional structure along the cutting line CC1 (it should be noted that, for better illustration, Figure 1The topmost sacrificial layer 202 is not shown; instead, a semiconductor layer 233 at the bottom of the topmost sacrificial layer 202 is shown directly. The method for forming the semiconductor structure includes: providing a semiconductor substrate 200; and forming a stacked structure 201 on the semiconductor substrate 200 in which the sacrificial layer 202 and the semiconductor layer 233 are alternately stacked in a vertical direction, wherein the vertical direction is perpendicular to the upper surface of the semiconductor substrate.

[0018] The semiconductor substrate 200 can be made of single-crystal silicon (Si), single-crystal germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other group III-V compounds. In this embodiment, the semiconductor substrate 200 is made of single-crystal silicon (Si).

[0019] The stacked structure 201 includes sacrificial layers 202 and semiconductor layers 233 alternately stacked in the vertical direction. The alternating stacking of the sacrificial layers 202 and semiconductor layers 233 in the vertical direction means that after forming a sacrificial layer 202, a semiconductor layer 233 is formed on the surface of the sacrificial layer 202, and then the steps of forming the sacrificial layer 202 and the semiconductor layer 233 on the sacrificial layer 202 are repeated sequentially. The number of sacrificial layers 202 and semiconductor layers 233 can be determined according to actual needs. In this embodiment, four sacrificial layers 202 and four semiconductor layers 233 are used as an example for illustration, and the bottom and top layers of the stacked structure 201 are both single sacrificial layers 202. In other embodiments, the number of sacrificial layers 202 and semiconductor layers 233 can be other numbers.

[0020] Semiconductor layer 233 is subsequently used to form a linear semiconductor pattern. Sacrificial layer 202 is removed as a sacrificial material in subsequent processes, or a portion of sacrificial layer 202 can be directly used as part of an insulating layer. The material of sacrificial layer 202 is different from that of semiconductor layer 233 so that when sacrificial layer 202 is removed subsequently, sacrificial layer 202 has a high etch selectivity (etch selectivity greater than 2:1) relative to semiconductor layer 233 (or linear semiconductor pattern), thereby ensuring that semiconductor layer 233 (or linear semiconductor pattern) is not etched or is etched in a small amount while sacrificial layer 202 is being removed.

[0021] In some embodiments, the semiconductor layer 233 is made of silicon or silicon germanium, and the sacrificial layer 202 is made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, amorphous silicon, amorphous carbon, polycrystalline silicon, or silicon germanium. In this embodiment, the semiconductor layer 233 is made of silicon, and the sacrificial layer 202 is made of silicon germanium. In other embodiments, the sacrificial layer 202 is made of silicon oxide, silicon hydroxide, silicon nitride, etc., and the semiconductor layer 233 is made of an oxide semiconductor, for example, In...x Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn z O、In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O、Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O, Al x Zn y Sn z O、Yb x Ga y Zn z O、In x Ga y O or a combination of the above materials.

[0022] In some embodiments, the semiconductor layer 233 is a doped semiconductor layer 233, meaning that the semiconductor layer 233 is pre-doped with impurity ions. The impurity ions can be N-type or P-type impurity ions. In some embodiments, the P-type impurity ions are one or more of boron, gallium, and indium, and the N-type impurity ions include one or more of phosphorus, arsenic, and antimony. In this embodiment, the impurity ions doped in the semiconductor layer 233 are P-type impurity ions. In other embodiments, the semiconductor layer 233 can also be an undoped semiconductor layer 233.

[0023] The sacrificial layer 202 and the semiconductor layer 233 are formed by deposition processes. The deposition processes include epitaxial processes.

[0024] refer to Figures 5-8 ,in Figure 6 for Figure 5 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 7 for Figure 5 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 8 for Figure 5A cross-sectional view along the cutting line CC1 shows the etched stacked structure 201 to form multiple first trenches 204 penetrating the stacked structure in the first and vertical directions. The remaining semiconductor layer extending along the first direction between adjacent first trenches 204 is a linear semiconductor pattern 203. The linear semiconductor patterns 203 extend along the first direction and are arranged in an array in the second and vertical directions. Each linear semiconductor pattern 203 includes a channel region 21 and a source region 23 and a drain region 22 located at both ends of the channel region 21 and connected to the channel region 21, respectively (see reference). Figure 5 and Figure 6 The first direction is perpendicular to the second direction and both are parallel to the upper surface of the semiconductor substrate 200.

[0025] Multiple first grooves 204 penetrate the stacked structure 201 vertically, the multiple first grooves 204 are parallel to each other, and the formed first grooves 204 extend along a first direction. In this disclosure, the direction of the cutting line AA1 is parallel to the first direction.

[0026] In some embodiments, during the formation of the first trench 204, the semiconductor substrate 200 is over-etched such that the bottom of the first trench 204 is located within the semiconductor substrate 200 (see reference). Figure 8 ).

[0027] In some embodiments, before etching the stacked structure 201, a patterned first mask layer (not shown in the figure) is formed on the surface of the stacked structure 201. The patterned first mask layer has a plurality of openings extending along a first direction, and the positions of the plurality of openings correspond to the positions of the plurality of first trenches to be formed. Using the patterned first mask layer as a mask, the stacked structure 201 is etched along the openings to form a plurality of parallel first trenches 204 extending along the first direction in the stacked structure. The patterned first mask layer is then removed.

[0028] In some embodiments, the etched stack structure 201 may employ an anisotropic dry etching process, such as anisotropic plasma etching.

[0029] Semiconductor layer 233 of each layer (reference) Figures 1-4 After being etched, multiple linear semiconductor patterns 203 extending along the first direction and parallel to each other are formed. The multiple linear semiconductor patterns 203 in each layer constitute a linear semiconductor pattern layer.

[0030] Each linear semiconductor pattern 203 includes a channel region 21 and a source region 23 and a drain region 22 located at both ends of the channel region 21 and connected to the channel region 21, respectively (see reference). Figure 5 and Figure 6The channel region 21 subsequently serves as the channel region of the lateral transistor, the source region 23 is subsequently used to form the source region of the lateral transistor, a portion of the drain region 22 is used to form the drain region of the lateral transistor, and another portion of the drain region 22 is used to form a grounded doped region connected to the channel region 21.

[0031] refer to Figures 9-12 ,in Figure 10 for Figure 9 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 11 for Figure 9 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 12 for Figure 9 A cross-sectional view along the cutting line CC1 shows a first insulating layer 206 forming in the first trench 204, filling the first trench completely.

[0032] The first insulating layer 206 is used for electrical isolation between devices formed subsequently.

[0033] In some embodiments, the material of the first insulating layer 206 may be one or more selected from silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), or BPSG (boron-phosphorus-doped silicon dioxide), and low dielectric constant (K less than 2.5). In this embodiment, the material of the first insulating layer 206 is silicon oxide, and the process for forming the first insulating layer 206 is chemical vapor deposition.

[0034] In some embodiments, when the sacrificial layer 202 is made of a non-insulating material (e.g., when the sacrificial layer material is germanium-silicon), before forming the first insulating layer 206, the sacrificial layer between adjacent drain regions 22 is removed along the first trench 204 to form a first cavity. The removal of the sacrificial layer between adjacent drain regions 22 can be performed using a wet etching process. In some embodiments, before removing the sacrificial layer between adjacent drain regions 22, other areas outside the drain regions can be covered by a mask layer (e.g., a photoresist mask layer or other suitable mask layer); thus forming a first insulating layer 206 that fills the first cavity and the first trench.

[0035] In some other embodiments, when the sacrificial layer 202 is made of an insulating material (such as silicon oxide or silicon nitride), the sacrificial layer between adjacent drain regions 22 may not be removed before forming the first insulating layer 206, and the sacrificial layer between adjacent drain regions 22 may be directly incorporated as part of the first insulating layer. Alternatively, before forming the first insulating layer 206, the sacrificial layer between adjacent drain regions 22 may be removed along the first trench 204 to form a first cavity; then, the first insulating layer 206 is formed, filling the first cavity and the first trench.

[0036] In some embodiments, reference Figures 13-16 ,in Figure 14 for Figure 13 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 15 for Figure 13 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 16 for Figure 13 A cross-sectional view along the cutting line CC1 shows that a portion of the first insulating layer 206 and a portion of the sacrificial layer 202 are removed to form multiple support structures 207 extending in the vertical and second directions. The support structures fill the spaces between the linear semiconductor patterns 203. The material of the support structures 207 is different from the material of the first insulating layer 206 and the sacrificial layer 202.

[0037] The support structure 207 is used in subsequent processes to support the linear semiconductor pattern 203 and prevent the linear semiconductor pattern 203 from deforming due to suspension.

[0038] In one embodiment, there are at least two support structures 207, which are located at opposite ends of the channel region 21. The material of the support structure 207 is different from that of the first insulating layer 206 and the sacrificial layer 202, which results in a very low etching rate of the support structure 207 during subsequent etching of the first insulating layer 206 and the sacrificial layer 202, thus ensuring the integrity of the support structure 207.

[0039] In some embodiments, the material of the support structure 207 may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or silicon carbonitride. In this embodiment, the material of the support structure 207 is silicon nitride.

[0040] In some embodiments, before forming the support structure 207, it is necessary to etch the sacrificial layer 202 and the first insulating layer 206, form at least two openings extending in a second direction in the sacrificial layer 202 and the first insulating layer 206, and form the support structure 207 that fills the openings.

[0041] The second direction is located at a certain angle to the first direction. In this embodiment, the second direction is perpendicular to the first direction, or the angle between the second direction and the first direction is 90°.

[0042] In one embodiment, reference Figures 17-20 ,in Figure 18 for Figure 17 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 19 for Figure 17 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 20 for Figure 17A cross-sectional view along the cutting line CC1 shows that the first insulating layer 206 in the middle portion of the first trench 204 between adjacent drain regions 22 is etched away to form a second opening 208 extending in the first direction in the first insulating layer 206 in the first trench 204. The bottom of the second opening 208 exposes a portion of the surface of the semiconductor substrate 200.

[0043] The second opening 208 is subsequently used to form an isolation layer, which is used for electrical isolation. Bit lines and grounding conductive plugs are formed on both sides of the isolation layer, respectively. The second opening 208 is formed using an anisotropic dry etching process. Before etching the first insulating layer 206, a patterned mask layer is formed on the surface of the stacked structure. Using the patterned mask layer as a mask, the middle portion of the first insulating layer 206 in the first trench 204 between adjacent drain regions 22 is etched, forming the second opening 208 extending along the first direction in the first insulating layer 206 in the first trench 204.

[0044] In some embodiments, the size of the second opening 208 is 10%-20% of the size of the first trench 204. This ensures the electrical isolation performance of the isolation layer subsequently formed in the second opening 208 while exposing sufficient space on both sides of the isolation layer to form bit lines and grounding conductive plugs, respectively. The size of the second opening 208 is the vertical distance between the two side walls of the second opening 208 along the second direction, and the size of the first trench 204 is the vertical distance between the two side walls of the first trench 204 along the second direction.

[0045] In some embodiments, reference Figures 21-24 ,in Figure 22 for Figure 21 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 23 for Figure 21 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 24 for Figure 21 A cross-sectional view along the cutting line CC1 shows an isolation layer 209 that fills the second opening.

[0046] The material of the insulating layer 209 is different from that of the first insulating layer 206. The material of the insulating layer 209 can be silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or silicon carbonitride. In this embodiment, the material of the insulating layer 209 is silicon nitride.

[0047] In one embodiment, reference Figures 25-28 ,in Figure 26 for Figure 25 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 27 for Figure 25 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 28 for Figure 25A cross-sectional view along the cutting line CC1 shows the removal of the sacrificial layer and the first insulating layer between adjacent channel regions 21. A second cavity is formed at the location where the sacrificial layer was removed. The second cavity is connected to the first trench, making the channel region 21 suspended. A word line dielectric layer (not shown in the figure) is formed on the surface of the channel region. Metal word lines 210 extending in the second direction are formed on the word line dielectric layer of each channel region.

[0048] In this embodiment, the channel region 21 is pre-doped with P-type impurity ions, and the channel region 21 is directly used as the channel region of the lateral transistor. In other embodiments, the channel region is doped with impurity ions before forming the word line dielectric layer, and the channel region of the lateral transistor is formed in the channel region 21.

[0049] In this embodiment, the metal word lines are horizontal word lines (the horizontal word lines are set horizontally and parallel to the surface of the semiconductor substrate 200). The channel regions 21 of multiple linear semiconductor patterns in each layer correspond to a metal word line 210. The metal word lines 210 of adjacent layers are discrete or separate.

[0050] In this embodiment, the metal word lines 210 are a surrounding gate structure, and each metal word line 210 surrounds the surface of multiple channel regions 21 arranged along the second direction in a certain layer.

[0051] In other embodiments, the metal word lines can be a double-gate structure, with the double gates in each metal word line located on the upper and lower surfaces of multiple channel regions arranged along a second direction in a certain layer.

[0052] In one embodiment, the material of the word line dielectric layer can be silicon oxide or a high-k (K greater than 2.5) dielectric material, and the material of the metal word line can be one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, and Wsi.

[0053] In other embodiments, the formed metal word lines are vertical word lines (vertical word lines are arranged vertically and perpendicular to the surface of the semiconductor substrate 200), each metal word line surrounds the word line dielectric layer on the surface of multiple channel regions 21 in the vertical direction, or is located on the surface of the word line dielectric layer on the surface of multiple channel regions 21 in the vertical direction, and two adjacent metal word lines are discrete or separate.

[0054] In some embodiments, after the metal letter line 210 is formed, the remaining first trench and second cavity are filled with the second insulating layer 211 (see reference). Figure 26 and Figure 27 ).

[0055] In this embodiment, the word line dielectric layer and the metallic word line 210 are formed before the subsequently formed bit line and ground wire plugs. In other embodiments, the word line dielectric layer and the metallic word line 210 are formed after the bit line and ground wire plugs are formed.

[0056] refer to Figures 29-32 ,in Figure 39 for Figure 29 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 31 for Figure 29 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 32 for Figure 29 A cross-sectional view along the cutting line CC1 shows that a portion of the first insulating layer 206 on the other side of the isolation layer 209 (the other side being the side of the isolation layer 209 that does not contact the bit line subsequently formed) is etched away to form a third opening 212. The side of the third opening 212 exposes the second side of multiple drain regions 22 in the vertical direction.

[0057] Each drain region includes a first side and a second side along the second direction.

[0058] The third opening 212 is subsequently used to form a bit line, and the third opening 212 is also used as a window for doping the drain region to form the drain region.

[0059] refer to Figures 33-36 ,in Figure 34 for Figure 33 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 35 for Figure 33 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 36 for Figure 33 A cross-sectional view along the cutting line CC1 shows that multiple drain regions 22 exposed in the vertical direction of the third opening 212 are doped to form a drain region 213 in the drain region 22. The drain region 213 is adjacent to the subsequently formed ground doped region, and the doping type of the drain region 213 is opposite to that of the ground doped region and the channel region 21.

[0060] Along the third opening 212, an ion implantation process is performed on the drain region 22 exposed by the third opening 212 to form a drain region 213. The drain region 213 is only formed in a part of the drain region 22 (the part near the third opening 212). The other part of the drain region 22 is subsequently used to form a ground doped region.

[0061] The impurity ions doped in the drain region 213 can be N-type or P-type impurity ions. In some embodiments, the P-type impurity ions are one or more of boron, gallium, and indium, and the N-type impurity ions include one or more of phosphorus, arsenic, and antimony. In this embodiment, the impurity ions doped in the semiconductor layer 233 are N-type impurity ions.

[0062] refer to Figures 37-40 ,in Figure 38 for Figure 37 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 39 for Figure 37 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 40 for Figure 37 A cross-sectional view along the cutting line CC1 shows that a bit line 214 is formed in the third opening, filling the third opening, and the bit line 214 is connected to multiple drain areas 213.

[0063] Each bit line 214 is connected to multiple drain regions 213 exposed in the third opening. The bit line 214 is made of metal, which can be one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, and Wsi.

[0064] In this embodiment, bit line 214 is formed in the first trench and connected to the side of drain region 213 (the side of drain region is a surface parallel to the first direction). In other embodiments, bit line can be formed at the end of drain region 213 or in drain region 213 by forming a through hole through drain region 213 and filling the through hole with conductive material.

[0065] In other embodiments, when the formed metal word lines are vertical word lines (vertical word lines are vertically arranged and perpendicular to the surface of the semiconductor substrate 200), each metal word line surrounds the word line dielectric layer on the surface of multiple channel regions 21 in the vertical direction, or is located on the surface of the word line dielectric layer on the surface of multiple channel regions 21 in the vertical direction, and two adjacent metal word lines are discrete or separate, the formed bit lines can be multiple horizontal bit lines (horizontal bit lines are horizontally arranged and parallel to the surface of the semiconductor substrate 200). The multiple horizontal bit lines are discrete, each horizontal bit line connects multiple drain regions in a certain layer together, and the horizontal bit lines are not connected to the subsequently formed ground doped regions.

[0066] refer to Figures 41-44 ,in Figure 42 for Figure 41 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 43 for Figure 41 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 44 for Figure 41 A cross-sectional view along the cutting line CC1 shows that a portion of the first insulating layer 206 in the first trench on one side of the drain region 22 is etched, and a first opening 215 is formed in the first insulating layer 206. The side of the first opening 215 exposes one side wall of a plurality of drain regions 22 in the vertical direction, and the bottom of the first opening 215 exposes a portion of the surface of the semiconductor substrate.

[0067] In this embodiment, a portion of the first insulating layer on one side of the isolation layer 209 is etched away to form a first opening 215. A grounding conductive plug is subsequently formed in the first opening 215, and the first opening serves as a window for ion implantation when forming the ground doped region. The first opening 215 and the aforementioned third opening are located on opposite sides of the isolation layer 209, and therefore the grounding conductive plug formed in the first opening 215 and the bit line formed in the third opening are also located on opposite sides of the isolation layer 209.

[0068] refer to Figures 45-48 ,in Figure 46 for Figure 45 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 47 for Figure 45 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 48 for Figure 45 A cross-sectional view along the cutting line CC1 shows that the drain region 22 exposed by the first opening 215 is ion-doped to form a ground doped region 216 in the drain region 22. The ground doped region 216 is connected to the channel region 21 and has the same doping type as the channel region 21.

[0069] Along the first opening 215, an ion implantation process is performed on the drain region 22 exposed by the first opening 215 to form a ground doped region 216. The ground doped region 216 is only formed in a part of the drain region 22 (the part near the first opening 215), and the ground doped region 216 is located on one side of the drain region 213.

[0070] The impurity ions doped in the ground doping region 216 can be N-type or P-type impurity ions. In some embodiments, the P-type impurity ions are one or more of boron, gallium, and indium, and the N-type impurity ions include one or more of phosphorus, arsenic, and antimony. In this embodiment, the impurity ions doped in the ground doping region 216 are P-type impurity ions.

[0071] In this embodiment, the ground doped region 216 is connected to the channel region 21 and has the same doping type as the channel region 21, making the ground doped region 216 and the channel region 21 conductive. After the ground conductive plug is formed in the first opening, the ground conductive plug and the ground doped region 216 are connected and conductive. Therefore, by forming the ground doped region 216 and the ground conductive plug, the channel region 21 can be grounded, thereby releasing the charge accumulated in the channel region 21 through the ground doped region 216 and the ground conductive plug, preventing the generation of the floating body effect, improving the performance of the device. Furthermore, the ground doped region 216 is formed in the drain region, and the ground conductive plug is formed in the first trench, which does not occupy additional area and can ensure the integration of the formed DRAM device.

[0072] refer to Figures 49-52 ,in Figure 50 for Figure 49 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 51 for Figure 49 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 52 for Figure 49 A cross-sectional view along the cutting line CC1 shows that the first opening is filled with conductive material to form a grounding conductive plug 217, which is connected to the grounding doped region 216 and the semiconductor substrate 200.

[0073] The grounding conductive plug 217 is made of metal or doped polycrystalline silicon. The metal can be one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, and Wsi.

[0074] The semiconductor substrate has a ground terminal. The upper end of the ground conductive plug 217 is connected to the ground doped region 216, and the lower end of the ground conductive plug 217 is connected to the ground terminal on the semiconductor substrate 200. Therefore, in this disclosure, by forming the ground doped region 216 and the ground conductive plug 217, the channel region 21 can be grounded, thereby releasing the charge accumulated in the channel region 21 through the ground doped region 216 and the ground conductive plug 217, preventing the generation of the floating body effect, improving the performance of the device. Furthermore, the ground doped region 216 is formed in the drain region 22, and the ground conductive plug 217 is formed in the first trench 204, which does not occupy additional area and can ensure the integration of the formed 3D DRAM device.

[0075] In this embodiment, the grounding conductive plug 217 and the bit line 214 are both formed in the first trench. The grounding conductive plug 217 and the bit line 214 are isolated by the isolation layer 209. The grounding conductive plug 217 and the bit line 214 do not occupy additional area, which is beneficial to improving the integration of the device.

[0076] In this embodiment, the grounding conductive plug 217 is formed after the bit line 214. In other embodiments, the grounding conductive plug 217 may be formed before the bit line 214.

[0077] In one embodiment, the method further includes: doping the source region 23 to form a source region (not shown in the figure), wherein the doping type of the source region is the same as that of the drain region; removing the sacrificial layer and the isolation layer between the source regions, and forming a capacitor (not shown in the figure) connected to the source region in the region where the sacrificial layer and the isolation layer are removed.

[0078] This disclosure also provides a semiconductor structure in some embodiments, see reference. Figures 49-52 ,in Figure 50 for Figure 49 A schematic diagram of the cross-sectional structure along the cutting line AA1. Figure 51 for Figure 49 A schematic diagram of the cross-sectional structure along the cutting line BB1. Figure 52 for Figure 49 A cross-sectional structural diagram along the cutting line CC1, including:

[0079] Semiconductor substrate 200;

[0080] The stacked structure consists of an insulating layer (206 / 211) and a linear semiconductor pattern layer alternately stacked on a semiconductor substrate 200. Each linear semiconductor pattern layer includes a plurality of parallel linear semiconductor patterns 203 extending along a first direction. The linear semiconductor pattern 203 includes a channel region and a ground doped region 216 connected to the channel region. The ground doped region 216 has the same doping type as the channel region.

[0081] A ground conductive plug 217 is located between adjacent linear semiconductor patterns 203. The ground conductive plug 217 penetrates the stacked structure in the vertical direction and is connected to the semiconductor substrate 200. The ground conductive plug 217 is connected to the ground doped region 216 on one side in the second direction.

[0082] In some embodiments, the system further includes: a linear semiconductor pattern 203 including a drain region 213 connected to a channel region, the drain region 213 being located on one side of a ground doped region 216, and the doping type of the drain region 213 being opposite to the doping type of the ground doped region 216 and the channel region; an isolation layer 209 located on the side of the ground conductive plug 217 away from the side contacting the ground doped region 216; and a bit line 214 located on the side of the isolation layer 209 in a second direction away from the ground conductive plug 217, the bit line 214 penetrating the stacked structure vertically and being connected to a plurality of drain regions 213. In some embodiments, the isolation layer 209 is made of a different material than the insulating layer (206).

[0083] In some embodiments, the size of the isolation layer 209 is 10%-20% of the size of the first trench 204.

[0084] In some embodiments, the method further includes: forming a word line dielectric layer (not shown) on the surface of the channel region; a metal word line 210 extending in a second direction on the word line dielectric layer of the channel region of each layer; and filling the area between adjacent metal word lines 210 with an insulating layer.

[0085] In some embodiments, the metal word lines 210 are a surrounding gate structure, with each metal word line 210 surrounding the surface of a plurality of channel regions arranged in a second direction in a certain layer.

[0086] In some embodiments, the metal word lines are double-layer gate structures, and the double-layer gates in each metal word line are respectively located on the upper and lower surfaces of a plurality of channel regions arranged along the second direction in a certain layer.

[0087] In some embodiments, the invention further includes a plurality of support structures 207 extending in a second direction on the surface of the linear semiconductor pattern 203 in the plurality of insulating layers and the top layer, wherein the material of the support structures 207 is different from that of the insulating layers.

[0088] In some embodiments, the grounding conductive plug 217 is made of metal or doped polycrystalline silicon.

[0089] In some embodiments, the system further includes: a source region (not shown) located in the source region 23, the doping type of the source region being the same as that of the drain region; and a capacitor (not shown) connected to the source region.

[0090] It should be noted that the limitations or descriptions of the same or similar parts in some embodiments of the aforementioned semiconductor structure and some embodiments of the aforementioned semiconductor structure forming method will not be repeated here. For details, please refer to the limitations or descriptions of the corresponding parts in some embodiments of the aforementioned semiconductor structure forming method.

[0091] Although this disclosure has been presented above with reference to preferred embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make possible changes and modifications to the technical solutions of this disclosure by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this disclosure. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this disclosure without departing from the content of the technical solutions of this disclosure shall fall within the protection scope of the technical solutions of this disclosure.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide semiconductor substrates; Linear semiconductor patterns extending along a first direction and arranged in an array in a second direction and a vertical direction are formed on the semiconductor substrate, and a first insulating layer is formed between the linear semiconductor patterns; the linear semiconductor patterns include a channel region and a drain region connected to the channel region; a portion of the first insulating layer on one side of the drain region is etched to form a first opening, the first opening exposing a first sidewall of a plurality of drain regions arranged in a vertical direction, and the bottom of the first opening exposing a portion of the surface of the semiconductor substrate; The drain region exposed by the first opening is ion-doped to form a ground doped region in the drain region, the ground doped region being connected to the channel region and having the same doping type as the channel region; The first opening is filled with conductive material to form a grounded conductive plug, which is electrically connected to the grounded doped region and the semiconductor substrate.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, Forming a linear semiconductor pattern on the semiconductor substrate, extending along a first direction and arranged in an array along a second and vertical direction, includes: A stacked structure in which sacrificial layers and semiconductor layers are alternately stacked in the vertical direction is formed on the semiconductor substrate; The stacked structure is etched to form a plurality of first trenches penetrating the stacked structure in the first direction and the vertical direction. The remaining semiconductor layer between adjacent first trenches is a linear semiconductor pattern. The vertical direction is perpendicular to the upper surface of the semiconductor substrate. The first direction is perpendicular to the second direction and is parallel to the upper surface of the semiconductor substrate. The first insulating layer is filled between the linear semiconductor patterns.

3. The method for forming a semiconductor structure according to claim 2, characterized in that, Before forming the first opening, the method further includes: etching away a first insulating layer in the middle portion of a first trench between adjacent drain regions to form a second opening extending in a first direction in the first insulating layer in the first trench, the bottom of the second opening exposing a portion of the surface of the semiconductor substrate; and forming an isolation layer that fills the second opening.

4. The method for forming a semiconductor structure according to claim 3, characterized in that, The etching of a portion of the first insulating layer on one side of the drain region includes: A portion of the first insulating layer on one side of the isolation layer is etched away to form the first opening.

5. The method for forming a semiconductor structure according to claim 3, characterized in that, The method further includes: etching away a portion of the first insulating layer on the other side of the isolation layer to form a third opening, the third opening exposing the second sidewalls of a plurality of drain regions arranged in a vertical direction; doping the plurality of drain regions exposed in the vertical direction along the third opening to form drain regions in the drain regions, the drain regions being adjacent to the ground doped region, and the doping type of the drain regions being opposite to the doping type of the ground doped region and the channel region; and forming a bit line filling the third opening in the third opening, the bit line being connected to the plurality of drain regions.

6. The method for forming a semiconductor structure according to claim 4, characterized in that, The method further includes: removing the sacrificial layer and the first insulating layer between adjacent channel regions; forming a second cavity at the location where the sacrificial layer is removed, the second cavity communicating with the first trench to suspend the channel region; forming a word line dielectric layer on the surface of the channel region; forming a metal word line extending in a second direction on the word line dielectric layer of each channel region; and filling the remaining first trench and second cavity with a second insulating layer.

7. The method for forming a semiconductor structure according to claim 6, characterized in that, The metal letter lines are a surrounding grid structure, with each metal letter line surrounding the surface of multiple channel regions arranged in the second direction on the same layer.

8. The method for forming a semiconductor structure according to claim 6, characterized in that, The metal word lines are double-layer gate structures, and the double-layer gates in each metal word line are located on the upper and lower surfaces of multiple channel regions arranged along the second direction in the same layer.

9. The method for forming a semiconductor structure according to claim 2, characterized in that, The method further includes: removing a portion of the first insulating layer and a portion of the sacrificial layer to form a plurality of support structures extending along the vertical direction and the second direction, the support structures filling the spaces between the linear semiconductor patterns, the material of the support structures being different from the material of the first insulating layer and the sacrificial layer.

10. The method for forming a semiconductor structure according to claim 2, characterized in that, Before filling the first insulating layer between the linear semiconductor patterns, the method further includes: removing a sacrificial layer between adjacent drain regions along the first trench to form a first cavity; the first insulating layer further fills the first cavity.

11. The method for forming a semiconductor structure according to claim 5, characterized in that, The linear semiconductor pattern also includes a source region connected to the channel region; The source region and the drain region are located at opposite ends of the channel region, and the method further includes: doping the source region to form a source region in the source region, wherein the doping type of the source region is the same as the doping type of the drain region; Remove the sacrificial layer and isolation layer between the source regions, and form a capacitor electrically connected to the source region in the region where the sacrificial layer and isolation layer are removed.

12. A semiconductor structure, characterized in that, include: Semiconductor substrate; The semiconductor substrate has an alternating stacked structure of insulating layers and linear semiconductor patterned layers. Each linear semiconductor patterned layer includes a plurality of parallel linear semiconductor patterns extending along a first direction. Each linear semiconductor pattern includes a channel region and a ground doped region connected to the channel region. The ground doped region has the same doping type as the channel region. A ground conductive plug is located between adjacent linear semiconductor patterns, the ground conductive plug extends vertically through the stacked structure and connects to the semiconductor substrate, and the ground conductive plug is connected to the ground doped region on one side in a second direction.

13. The semiconductor structure according to claim 12, characterized in that, Also includes: The linear semiconductor pattern also includes a drain region connected to the channel region; and an isolation layer located on the side of the ground conductive plug away from the contact with the ground doped region. A bit line located on the side of the isolation layer away from the ground conductive plug in the second direction, the bit line penetrating the stack structure in the vertical direction and the bit line connecting to the plurality of the drain areas.

14. The semiconductor structure according to claim 13, characterized in that, The materials of the isolation layer and the insulation layer are different.

15. The semiconductor structure according to claim 13, characterized in that, Also includes: Word line dielectric layer located on the surface of the channel region; Metal word lines extending in the second direction on the word line dielectric layer located in the channel region of each layer; The area between adjacent metal letter lines is filled with an insulating layer.

16. The semiconductor structure according to claim 15, characterized in that, The metal letter lines are a surrounding grid structure, with each metal letter line surrounding the surface of a plurality of channel regions arranged along a second direction in a certain layer.

17. The semiconductor structure according to claim 15, characterized in that, The metal word lines are double-layer gate structures, and the double-layer gates in each metal word line are located on the upper and lower surfaces of multiple channel regions arranged along the second direction in a certain layer.

18. The semiconductor structure according to claim 15, characterized in that, Multiple support structures extending in a second direction are located on the surface of the insulating layer and the top layer of the linear semiconductor pattern, the material of the support structures being different from that of the insulating layer.

19. The semiconductor structure according to claim 12, characterized in that, The grounding conductive plug is made of metal or doped polycrystalline silicon.

20. The semiconductor structure according to claim 13, characterized in that, The linear semiconductor pattern further includes a source region connected to the channel region; the source region and the drain region are located at opposite ends of the channel region, and the pattern also includes: a source region located in the source region, wherein the doping type of the source region is the same as that of the drain region; and a capacitor connected to the source region.

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