Semiconductor structure and method of forming the same

Abstract

A structure of a semiconductor and a method of forming the same, the method comprising: forming a first channel stack structure on a protrusion in a first region, the first channel stack structure comprising one or more longitudinally stacked first channel stacks, each first channel stack comprising a first sacrificial layer and a first channel layer on the first sacrificial layer; forming a second channel stack structure on a protrusion in a second region, the second channel stack structure comprising one or more longitudinally stacked second channel stacks, each second channel stack comprising a second sacrificial layer and a second channel layer on the second sacrificial layer, and the second sacrificial layer having a different thickness than the first sacrificial layer; removing the first sacrificial layer and the second sacrificial layer; and forming a device gate structure across the first channel layer and the second channel layer on top of the substrate. The process window of the device gate structure formed in the first region and the process window of the device gate structure formed in the second region both meet process requirements.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor transistors are evolving towards higher device density and higher integration, and semiconductor process nodes are continuously shrinking in accordance with Moore's Law. Transistors, as the most basic semiconductor material, are currently widely used. Therefore, as the device density and integration of semiconductor transistors increase, the channel length of transistors must be continuously shortened to adapt to the shrinking process nodes.

[0003] To better adapt to the requirement of proportionally shrinking transistor dimensions, semiconductor manufacturing processes have gradually transitioned from planar transistors to more efficient three-dimensional transistors, such as FinFETs and Gate-all-around (GAA) transistors. GAA transistors include vertical and horizontal types. In a GAA transistor, the gate surrounds the channel region from all sides. Compared to planar transistors, GAA transistors offer stronger control over the channel and better suppress short-channel effects.

[0004] However, the performance of the fully enclosed gate structure still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to further improve the performance of the semiconductor structure.

[0006] To address the aforementioned problems, the present invention provides a semiconductor structure comprising: a substrate, the substrate including a first region and a second region, the substrate including a substrate and protrusions respectively protruding from the substrates of the first region and the second region; an isolation layer located on the substrate exposed by the protrusions, and the isolation layer covering the sidewalls of the protrusions; a first channel structure layer suspended on top of the protrusions in the first region, the first channel structure layer including one or more spaced-apart first channel layers along the normal direction of the substrate surface; and a second channel structure layer suspended on top of the protrusions in the second region, the second channel structure layer including... One or more spaced second channel layers, wherein the longitudinal distance between adjacent second channel layers is different from the longitudinal distance between adjacent first channel layers; a dielectric wall located on the substrate between the first and second channel structure layers, and the dielectric wall covering the sidewalls of the first and second channel structure layers; a device gate structure located on top of the substrate and spanning the first and second channel layers, wherein in a first region, the device gate structure surrounds and covers a portion of the top, a portion of the sidewalls, and a portion of the bottom of the first channel layer, and in a second region, the device gate structure surrounds and covers a portion of the top, a portion of the sidewalls, and a portion of the bottom of the second channel layer.

[0007] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: forming a substrate, the substrate including a first region and a second region, the substrate including a substrate and protrusions respectively protruding from the substrate in the first region and the second region; forming a first channel stack structure on the protrusion in the first region, the first channel stack structure including one or more vertically stacked first channel stacks, each first channel stack including a first sacrificial layer and a first channel layer on the first sacrificial layer; forming a second channel stack structure on the protrusion in the second region, the second channel stack structure including one or more vertically stacked second channel stacks, each second channel stack including a second sacrificial layer and a second channel layer on the second sacrificial layer, and the thickness of the second sacrificial layer being different from the thickness of the first sacrificial layer; removing the first sacrificial layer and the second sacrificial layer; after removing the first sacrificial layer and the second sacrificial layer, forming a device gate structure spanning the first channel layer and the second channel layer on top of the substrate, wherein in the first region, the device gate structure surrounds a portion of the top, a portion of the sidewalls and a portion of the bottom of the first channel layer, and in the second region, the device gate structure surrounds a portion of the top, a portion of the sidewalls and a portion of the bottom of the second channel layer.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] This invention provides a method for forming a semiconductor structure, comprising forming a first channel stack structure on a protrusion in a first region, the first channel stack structure including one or more vertically stacked first channel stacks, each first channel stack including a first sacrificial layer and a first channel layer on the first sacrificial layer, and forming a second channel stack structure on a protrusion in a second region, the second channel stack structure including one or more vertically stacked second channel stacks, each second channel stack including a second sacrificial layer and a second channel layer on the second sacrificial layer, wherein the thickness of the second sacrificial layer is different from the thickness of the first sacrificial layer. Accordingly, after the first and second sacrificial layers are subsequently removed, the vertical distance between adjacent second channel layers is different from the vertical distance between adjacent first channel layers. During the subsequent formation of the device gate structure, because the vertical distance between adjacent second channel layers is different from the vertical distance between adjacent first channel layers, the process window for forming the device gate structure in the first region and the process window for forming the device gate structure in the second region can both meet the process requirements. Thus, the device gate structure surrounding and covering the top, sidewalls, and bottom of the first and second channel layers all meet the process requirements, thereby improving the performance of the semiconductor structure. Attached Figure Description

[0010] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0011] Figure 5 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0012] Figures 6 to 19 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0013] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of a semiconductor structure needs further improvement, using a specific semiconductor structure formation method as an example.

[0014] Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0015] refer to Figure 1A substrate 12 is provided, the substrate 12 includes a first region 10A and a second region 10B, the substrate 12 includes a substrate 11 and protrusions 10 protruding from the substrate 11 in the first region 10A and the second region 10B respectively, one or more longitudinally stacked channel stacks 15 are formed above the protrusions 10, each channel stack 15 includes a sacrificial layer 13 and a channel layer 14 located on the sacrificial layer 13, an isolation layer 16 is formed on the substrate 11 exposed by the channel stack 15, and the isolation layer 16 covers the sidewalls of the protrusions 10.

[0016] refer to Figure 2 A dielectric wall 17 is formed between the channel stack 15 in the first region 10A and the channel stack 15 in the second region 10B, and the dielectric wall 17 covers the sidewall of the channel stack 15.

[0017] refer to Figure 3 Remove the sacrificial layer 13 in the first region 10A and the sacrificial layer 13 in the second region 10B.

[0018] refer to Figure 4 After removing the sacrificial layer 13 in the first region 10A and the second region 10B, a gate dielectric layer 18 is formed on the top of the substrate 11 in the first region 10A and the second region 10B, surrounding a portion of the top, a portion of the sidewalls, and a portion of the bottom of the channel layer 14; a work function layer 19 is formed surrounding the gate dielectric layer 18 covering the first region 10A and the second region 10B, respectively, with different thicknesses of the work function layer 19 in the first region 10A and the second region 10B; a gate electrode layer 20 is formed surrounding the work function layer 19 covering the first region 10A and the second region 10B, respectively. The gate dielectric layer 18, the work function layer 19, and the gate electrode layer 20 constitute the device gate structure 21.

[0019] The first region 10A is used to form an NMOS transistor, and the second region 10B of the device region is used to form a PMOS transistor, wherein the threshold voltage of the NMOS transistor is less than the threshold voltage of the PMOS transistor.

[0020] The thickness of the work function layer 19 is used to adjust the threshold voltage of the transistor. Since the threshold voltage of the NMOS transistor is less than that of the PMOS transistor, the thickness of the work function layer 19 in the NMOS transistor is less than that in the PMOS transistor.

[0021] Research has revealed that, because the longitudinal distance between adjacent channel layers 14 in the first region 10A is the same as that in the second region 10B, during the formation of the work function layer 19 surrounding and covering the gate dielectric layer 18 of the first region 10A and the second region 10B respectively, if the longitudinal distance between adjacent channel layers 14 in the first region 10A meets the process size requirements (i.e., the longitudinal distance between adjacent channel layers 14 in the first region 10A meets the process window for forming the work function layer 19 in the first region 10A), then the longitudinal distance between adjacent channel layers 14 in the second region 10B is too small. This means the longitudinal distance between adjacent channel layers 14 in the second region 10B makes the process window for forming the work function layer 19 in the second region 10B too small. Consequently, this increases the process difficulty of forming the work function layer 19 in the second region 10B, resulting in poor filling quality of the work function layer 19 in the second region 10B. Consequently, the performance of the device gate structure 21 located in the second region 10B is poor, thus affecting the performance of the semiconductor structure.

[0022] To address the technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: forming a substrate, the substrate including a first region and a second region, the substrate including a substrate and protrusions respectively protruding from the substrate in the first region and the second region; forming a first channel stack structure on the protrusions in the first region, the first channel stack structure including one or more vertically stacked first channel stacks, each first channel stack including a first sacrificial layer and a first channel layer on the first sacrificial layer; forming a second channel stack structure on the protrusions in the second region, the second channel stack structure including one or more vertically stacked second channel stacks, each second channel stack including a second sacrificial layer and a second channel layer on the second sacrificial layer, and the thickness of the second sacrificial layer being different from the thickness of the first sacrificial layer; removing the first sacrificial layer and the second sacrificial layer; after removing the first sacrificial layer and the second sacrificial layer, forming a device gate structure spanning the first channel layer and the second channel layer on top of the substrate, wherein in the first region, the device gate structure surrounds and covers a portion of the top, a portion of the sidewalls, and a portion of the bottom of the first channel layer, and in the second region, the device gate structure surrounds and covers a portion of the top, a portion of the sidewalls, and a portion of the bottom of the second channel layer.

[0023] In this embodiment of the invention, the thickness of the second sacrificial layer is different from that of the first sacrificial layer. Correspondingly, after the first and second sacrificial layers are subsequently removed, the longitudinal distance between adjacent second channel layers is different from that between adjacent first channel layers. During the subsequent formation of the device gate structure, because the longitudinal distance between adjacent second channel layers is different from that between adjacent first channel layers, the process window for forming the device gate structure in the first region and the process window for forming the device gate structure in the second region can both meet the process requirements. This ensures that the device gate structure surrounding and covering the top, sidewalls, and bottom of the first and second channel layers all meet the process requirements, thereby improving the performance of the semiconductor structure.

[0024] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0025] Figure 5 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0026] The semiconductor structure includes: a substrate 202, which includes a first region 200A and a second region 200B, and includes a substrate 2021 and protrusions 2022 respectively protruding from the substrate 2021 of the first region 200A and the second region 200B; an isolation layer 218 located on the substrate 2021 exposed by the protrusions 2022, and the isolation layer 218 covering the sidewalls of the protrusions 2022; a first channel structure layer 212 suspended on top of the protrusions 2022 of the first region 200A, along the normal direction of the surface of the substrate 2021, the first channel structure layer 212 including one or more spaced-apart first channel layers 2122; and a second channel structure layer 215 suspended on top of the protrusions 2022 of the second region 200B, along the normal direction of the surface of the substrate 2021. 15 includes one or more spaced second channel layers 2152, and the longitudinal distance between adjacent second channel layers 2152 is different from the longitudinal distance between adjacent first channel layers 2122; dielectric wall 220 is located on substrate 2021 between first channel structure layer 212 and second channel structure layer 215, and dielectric wall 220 covers the sidewalls of first channel structure layer 212 and second channel structure layer 215; device gate structure 228 is located on top of substrate 2021 and spans first channel layer 2122 and second channel layer 2152. In first region 200A, device gate structure 228 surrounds and covers a portion of the top, a portion of the sidewalls and a portion of the bottom of first channel layer 2122. In second region 200B, device gate structure 228 surrounds and covers a portion of the top, a portion of the sidewalls and a portion of the bottom of second channel layer 2152.

[0027] It should be noted that by setting the longitudinal distance between adjacent second channel layers 2152 to be different from the longitudinal distance between adjacent first channel layers 2122, the process window for forming the device gate structure 228 in the first region 200A and the process window for forming the device gate structure 228 in the second region 200B can both meet the process requirements. This ensures that the device gate structure 228 surrounding and covering the top, sidewalls, and bottom of the first channel layer 2122 and the second channel layer 2152 all meet the process requirements, thereby improving the performance of the semiconductor structure.

[0028] In this embodiment, the substrate 202 has a three-dimensional structure, including a substrate 2021 and a protrusion 2022 protruding from the substrate 2021.

[0029] In this embodiment, the substrate 2021 is a silicon substrate 2021, and the protrusion 2022 is made of the same material as the substrate 2021, which is silicon.

[0030] In this embodiment, the first region 200A is used to form a first-type transistor, and the second region 200B is used to form a second-type transistor. The first-type transistor and the second-type transistor have different threshold voltages and different channel conductivity types. In other embodiments, the first region is used to form a first-type transistor, the second region is used to form a second-type transistor, and the first-type transistor and the second-type transistor have different threshold voltages or different channel conductivity types.

[0031] As an example, the first type of transistor is an NMOS transistor and the second type of transistor is a PMOS transistor; in other embodiments, the first type of transistor is a PMOS transistor and the second type of transistor is an NMOS transistor.

[0032] It should be noted that the thickness of the work function layer 222 is used to adjust the threshold voltage of the transistor. The threshold voltages of the first type transistor and the second type transistor are different. Accordingly, the thickness of the work function layer 222 of the first type transistor is different from that of the second type transistor.

[0033] In this embodiment, the first channel structure layer 212 is used to provide a conductive channel for the first type of transistor.

[0034] In this embodiment, the material of the first channel layer 2122 includes one or more of silicon, silicon germanide, germanium, and group III-V semiconductor materials. The material of the first channel layer 2122 is determined based on the performance of the first type transistor.

[0035] In this embodiment, there are three first channel layers 2122. In other embodiments, the number of first channel layers 2122 may be other numbers.

[0036] In this embodiment, the top of the first channel structure layer 212 and the top of the second channel structure layer 215 are flush with each other. Specifically, the flushness of the top of the first channel structure layer 212 and the top of the second channel structure layer 215 improves the flatness of the top surfaces of the first channel structure layer 212 and the second channel structure layer 215. Correspondingly, the flatness of the top surface of the device gate structure 228 spanning the first channel layer 2122 and the second channel layer 2152 is also relatively high, thereby improving the performance of the semiconductor structure.

[0037] Specifically, the longitudinal distance between adjacent second channel layers 2152 is different from the longitudinal distance between adjacent first channel layers 2122. In the process of forming the device gate structure 228, the process window for forming the device gate structure 228 in the first region 200A and the process window for forming the device gate structure 228 in the second region 200B can both meet the process requirements. This ensures that the device gate structure 228 surrounding and covering the top, sidewalls and bottom of the first channel layer 2122 and the second channel layer 2152 all meet the process requirements, thereby improving the performance of the semiconductor structure.

[0038] In this embodiment, the second channel structure layer 215 is used to provide a conductive channel for the second type of transistor.

[0039] In this embodiment, the material of the second channel layer 2152 includes one or more of silicon, silicon germanide, germanium, and group III-V semiconductor materials. The material of the second channel layer 2152 is determined according to the performance of the type II transistor.

[0040] In this embodiment, there are two second channel layers 2152. In other embodiments, the number of second channel layers 2152 may be other numbers.

[0041] It should be noted that the difference between the longitudinal distance between adjacent second channel layers 2152 and the longitudinal distance between adjacent first channel layers 2122 should not be too large or too small. If the difference is too large, it can easily lead to an increase in the overall height of the semiconductor structure, resulting in an excessively large space occupied by the semiconductor structure. If the difference is too small, while the longitudinal distance between adjacent first channel layers 2122 may meet the process size requirements, the longitudinal distance between adjacent second channel layers 2152 may be too small. Consequently, in the process of forming the device gate structure 228, the process window for forming the device gate structure 228 in the second region 200B may be too small, increasing the difficulty of forming the device gate structure 228 and thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the difference between the longitudinal distance between adjacent second channel layers 2152 and the longitudinal distance between adjacent first channel layers 2122 is in the range of 1 nanometer to 10 nanometers.

[0042] Specifically, the dielectric wall 220 is used to electrically isolate the first region 200A and the second region 200B.

[0043] In this embodiment, the dielectric wall 220 is made of one or more of silicon oxide, silicon nitride, and silicon oxynitride. Specifically, silicon oxide, silicon nitride, and silicon oxynitride are all dielectric materials and have good electrical isolation properties.

[0044] Specifically, the isolation layer 218 is used for electrical isolation of adjacent devices.

[0045] Therefore, the material of the isolation layer 218 is a dielectric material, which may include silicon oxide, silicon nitride, or silicon oxynitride. As an example, the material of the isolation layer 218 is silicon oxide.

[0046] Specifically, when the device is in operation, the device gate structure 228 is used to control the opening or closing of the conductive channels of the first type transistor in the first region 200A and the second type transistor in the second region 200B.

[0047] In this embodiment, the device gate structure 228 includes: a gate dielectric layer 221, which surrounds and covers a portion of the top, a portion of the sidewalls, and a portion of the bottom of the first channel layer 2122, and a portion of the top, a portion of the sidewalls, and a portion of the bottom of the second channel layer 2152; a work function layer 222, which surrounds and covers the gate dielectric layer 221 covering the first region 200A and the second region 200B, and the thicknesses of the work function layer 222 in the first region 200A and the second region 200B are different; and a gate electrode layer 223, which surrounds and covers the work function layer 222 covering the first region 200A and the second region 200B.

[0048] In this embodiment, the material of the gate dielectric layer 221 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0049] Specifically, the gate dielectric layer 221 includes a gate oxide layer that conformally covers a portion of the top, a portion of the sidewalls, and a portion of the bottom of the first channel layer 2122 and the second channel layer 2152, and a high-k gate dielectric layer 221 that conformally covers the gate oxide layer. The high-k gate dielectric layer is made of a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide.

[0050] The work function layer 222 is used to adjust the threshold voltage of the first type transistor and the second type transistor. Since the threshold voltage of the first type transistor and the threshold voltage of the second type transistor are different, the thickness of the work function layer 222 in the first region 200A and the second region 200B is different.

[0051] In this embodiment, the material of the work function layer 222 includes one or more of TiN, TaN, TaSiN, TiAl, TiSiN, TaSiN, and TiAlC. The specific material of the work function layer 222 is determined based on the performance of the first-type transistor and the second-type transistor.

[0052] The gate electrode layer 223 is used for electrical connection with external structures.

[0053] The gate electrode layer 223 is made of one or more of Pt, Ti, Ag, W, Al, Cu, Ni, and Au. As an example, the gate electrode layer 223 is made of W.

[0054] Figures 6 to 19 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0055] refer to Figures 6 to 13A substrate 102 is formed, comprising a first region 100A and a second region 100B. The substrate 102 includes a substrate 1021 and protrusions 1022 respectively protruding from the substrate 1021 in the first region 100A and the second region 100B. A first channel stack structure 113 is formed on the protrusions 1022 in the first region 100A. The first channel stack structure 113 includes one or more longitudinally stacked first channel stacks 112, each first channel stack 112 including a first sacrificial... The first sacrificial layer 1121 and the first channel layer 1122 located on the first sacrificial layer 1121; forming a second channel stack structure 116 on the protrusion 1022 of the second region 100B, the second channel stack structure 116 including one or more longitudinally stacked second channel stacks 115, each second channel stack 115 including a second sacrificial layer 1151 and a second channel layer 1152 located on the second sacrificial layer 1151, and the thickness of the second sacrificial layer 1151 is different from the thickness of the first sacrificial layer 1121.

[0056] The substrate 102 is used to provide a process platform for subsequent process manufacturing.

[0057] It should be noted that, in this embodiment, before patterning the first channel material stack 100 and the second channel material stack 111, the substrate 102 is a planar substrate 102. Specifically, the planar substrate 102 is used as the material for subsequently patterning to form the substrate 1021 and the protrusions 1022 on the substrate 1021.

[0058] In this embodiment, the first region 100A is used to form a first-type transistor, and the second region 100B is used to form a second-type transistor. The first-type transistor and the second-type transistor have different threshold voltages and different channel conductivity types. In other embodiments, the first region is used to form a first-type transistor, and the second region is used to form a second-type transistor. The first-type transistor and the second-type transistor have different threshold voltages or different channel conductivity types. As an example, the first-type transistor is an NMOS transistor, and the second-type transistor is a PMOS transistor; in other embodiments, the first-type transistor is a PMOS transistor, and the second-type transistor is an NMOS transistor.

[0059] It should be noted that the thickness of the work function layer is used to adjust the threshold voltage of the transistor. The threshold voltages of the first type transistor and the second type transistor are different, and correspondingly, the thickness of the work function layer of the first type transistor is different from that of the second type transistor.

[0060] Reference Figures 6 to 13 The steps for forming the first channel stacked structure 113 and the second channel stacked structure 116 are described in detail.

[0061] refer to Figure 6 A first channel material laminate structure 100 is formed on a substrate 102 in the first region 100A;

[0062] Specifically, the first channel material stack 100 is used as the material for forming the first channel stack 113.

[0063] In this embodiment, the first channel material stack structure 100 includes one or more longitudinally stacked first channel material stacks 101, each first channel material stack 101 including a first sacrificial material layer 1011 and a first channel material layer 1012 located on the first sacrificial material layer 1011.

[0064] In this embodiment, the material of the first sacrificial material layer 1011 includes silicon and germanium; the material of the first channel material layer 1012 includes silicon, silicon germanide, germanium, or group III-V semiconductor materials, and there is an etching selectivity between the first sacrificial material layer 1011 and the first channel material layer 1012.

[0065] In this embodiment, during the step of forming the first channel material stack structure 100 on the substrate 102 of the first region 100A, the first channel material stack structure 100 is also formed on the substrate 102 of the second region 100B. Specifically, the first channel material stack structure 100 is formed on the substrate 102 of the second region 100B to provide space for the subsequent formation of the second channel material stack structure 111.

[0066] In this embodiment, the number of first sacrificial material layers 1011 and first channel material layers 1012 are the same.

[0067] refer to Figures 7 to 13 ,in, Figure 9 It is a top view. Figure 10 yes Figure 9 Cross-sectional views along the AA and BB directions. Figure 11 yes Figure 9 Cross-sectional views along the AA and BB directions. Figure 13 yes Figure 9 After forming the first channel material laminate structure 100 in the cross-sectional view along the AA and BB directions, a second channel material laminate structure 111 is formed on the substrate 102 of the second region 100B.

[0068] Specifically, the second channel material stack structure 111 is used as the material for forming the second channel stack structure 116.

[0069] In this embodiment, the second channel material stack structure 111 includes one or more longitudinally stacked second channel material stacks 110, each second channel material stack 110 including a second sacrificial material layer 1101 and a second channel material layer 1102 located on the second sacrificial material layer 1101.

[0070] In this embodiment, the material of the second sacrificial material layer 1101 includes silicon and germanium; the material of the second channel material layer 1102 includes silicon, silicon germanide, germanium, or group III-V semiconductor materials, and there is an etch selectivity between the second sacrificial material layer 1101 and the second channel material layer 1102.

[0071] In this embodiment, the number of the second sacrificial material layer 1101 and the second channel material layer 1102 are the same.

[0072] In this embodiment, the step of forming a second channel material laminate structure 111 on the substrate 102 of the second region 100B includes: forming a trench 107 in the second region 100B that penetrates the first channel material laminate structure 100; and forming the second channel material laminate structure 111 in the trench 107.

[0073] Specifically, the trench 107 provides space for forming the second channel material laminate structure 111. In this embodiment, the extension direction of the trench 107 is the same as the extension direction of the first channel material laminate structure 100.

[0074] In this embodiment, the step of forming the trench 107 includes: forming a mask layer 106 on top of the first channel material stack structure 100, the mask layer 106 having a mask opening (not shown) located in the second region 100B, the mask opening being located on top of the first channel material stack structure 100 in the second region 100B; using the mask layer 106 as a mask, removing the first channel material stack structure 100 in the second region 100B along the mask opening, and forming a trench 107 penetrating the first channel material stack structure 100 on top of the substrate 102 in the second region 100B.

[0075] In this embodiment, the process of removing the first channel material stack structure 100 of the second region 100B along the mask opening includes a dry etching process. Specifically, the dry etching process includes anisotropic dry etching. Anisotropic dry etching has the characteristics of anisotropic etching, that is, the longitudinal etching rate is greater than the transverse etching rate. It can ensure the morphological quality of the trench 107 sidewalls while removing the first channel material stack structure 100 of the second region 100B, providing a good process foundation for subsequent processes.

[0076] In this embodiment, the process of forming the second channel material stack structure 111 in the trench 107 includes an epitaxial process. Specifically, the epitaxial process has the characteristics of fast growth rate and high morphology quality. During the formation of the second channel material stack structure 111 using the epitaxial process, the second channel material stack structure 111 can completely fill the trench 107, reducing the probability of voids forming at the interface between the second channel material stack structure 111 and the first channel material stack structure 100, thereby improving the performance of the semiconductor structure.

[0077] In this embodiment, it should be noted that after forming the trench 107, the process also includes removing the mask layer.

[0078] Specifically, the process of removing the mask layer includes an ashing process.

[0079] refer to Figures 10 to 11 After the trench 107 is formed and before the second channel material laminate structure 111 is formed, the method further includes forming a barrier layer 109 on the sidewall of the trench 107.

[0080] Specifically, during the formation of the second channel material stack 111, the barrier layer 109 reduces the probability of the material forming the second channel material stack 111 coming into contact with the material of the first channel material stack 100. Correspondingly, it also reduces the probability of atoms in the material of the second channel material stack 111 diffusing with atoms in the material of the first channel material stack 100, thereby improving the carrier mobility in the subsequently formed first channel layer 1122 and second channel layer 1152, and thus improving the performance of the semiconductor structure.

[0081] In this embodiment, the step of forming the barrier layer 109 includes: forming a barrier material layer 108 on the sidewall and bottom of the trench 107 and on the top of the first channel material laminate structure 100; removing the barrier material layer 108 at the bottom of the trench 107 and the top of the first channel material laminate structure 100, and the remaining barrier material layer 108 located on the sidewall of the trench 107 as the barrier layer 109.

[0082] In this embodiment, the process of forming a barrier material layer 108 on the sidewalls and bottom of the trench 107 and on the top of the first channel material stack structure 100 includes an atomic layer deposition (ALD) process. The ALD process involves multiple ALD cycles, which helps improve the thickness uniformity of the barrier material layer 108. Furthermore, the ALD process has good step coverage, enabling the barrier material layer 108 to cover the sidewalls and bottom of the trench 107 and the top of the first channel material stack structure 100.

[0083] In this embodiment, the barrier layer 109 is made of one or more of silicon nitride, silicon oxide, and silicon carbide. Specifically, the silicon nitride, silicon oxide, and silicon carbide materials prevent atoms in the second channel material stack 111 from diffusing with atoms in the first channel material stack 100. Simultaneously, in the subsequent process of forming the second channel material stack 111, the silicon nitride, silicon oxide, and silicon carbide materials provide a better growth environment for the formation of the second channel material stack 111, improving the formation quality of the second channel material stack 111 and thus improving the performance of the semiconductor structure.

[0084] It should be noted that the thickness of the barrier layer 109 should not be too large or too small. If the thickness of the barrier layer 109 is too large, it will increase the difficulty of removing the barrier layer 109 in the subsequent process, reduce the process efficiency, and also make it easy for the barrier layer 109 to occupy too much space in the second channel material stack structure 111, causing the process dimensions of the second channel material stack structure 111 to fail to meet the process requirements, thereby affecting the performance of the semiconductor structure. If the thickness of the barrier layer 109 is too small, it will easily lead to a decrease in the effectiveness of the barrier layer 109 in preventing the atoms in the second channel material stack structure 111 from diffusing with the atoms in the first channel material stack structure 100, thus affecting the carrier mobility in the subsequently formed first channel layer 1122 and second channel layer 1152. Therefore, in this embodiment, the thickness of the barrier layer 109 is 8 nanometers to 8.5 nanometers.

[0085] refer to Figure 7 It should also be noted that, in this embodiment, before forming the trench 107, a protective layer 103 is formed on the top of the first channel material laminate structure 100.

[0086] Specifically, during the formation of the second channel material stack structure 111, the protective layer 103 is used to protect the top of the first channel material stack structure 100, reducing the risk of the material of the second channel material stack structure 111 growing on the top of the first channel material stack structure 100.

[0087] In this embodiment, the process for forming the protective layer 103 includes chemical vapor deposition.

[0088] It should be noted that, in this embodiment, during the formation of the trench 107, the trench 107 also penetrates the protective layer 103 at the top of the first channel material laminate structure 100. Specifically, the trench 107 penetrates the protective layer 103 at the top of the first channel material laminate structure 100, which facilitates the subsequent formation of the second channel material laminate structure 111 in the trench 107.

[0089] In this embodiment, the material of the protective layer 103 includes one or more of silicon nitride, silicon oxide, and silicon carbide. Silicon nitride, silicon oxide, and silicon carbide are all dielectric materials. During the subsequent formation of the second channel material stack structure 111, the material forming the second channel material stack structure 111 is less likely to come into contact with the first channel material stack structure 100, thereby protecting the top of the first channel material stack structure 100.

[0090] It should be noted that the thickness of the protective layer 103 should not be too large or too small. If the thickness of the protective layer 103 is too large, it will increase the difficulty of removing the protective layer 103 in the subsequent process and reduce the process efficiency. If the thickness of the protective layer 103 is too small, the protective effect of the protective layer 103 on the top of the first channel material stack 100 will decrease during the subsequent formation of the second channel material stack 111, thereby affecting the performance of the first channel material stack 100. Therefore, in this embodiment, the thickness of the protective layer 103 is 450 angstroms to 500 angstroms.

[0091] refer to Figures 13 to 14 The first channel material stack structure 100 and the second channel material stack structure 111 are graphically represented. The first channel material stack structure 100 is graphically represented as the first channel stack structure 113, and the second channel material stack structure 111 is graphically represented as the second channel stack structure 116.

[0092] It should be noted that the first channel stack structure 113 and the second channel stack structure 116 provide the process basis for the subsequent formation of the suspended first channel layer 1122 and the second channel layer 1152.

[0093] It should also be noted that the thickness of the second sacrificial layer 1151 is different from that of the first sacrificial layer 1121. Accordingly, after the first sacrificial layer 1121 and the second sacrificial layer 1151 are subsequently removed, the longitudinal distance between adjacent second channel layers 1152 is different from the longitudinal distance between adjacent first channel layers 1122. During the subsequent formation of the device gate structure, because the longitudinal distance between adjacent second channel layers 1152 is different from that between adjacent first channel layers 1122, the process window for forming the device gate structure in the first region 100A and the process window for forming the device gate structure in the second region 100B can both meet the process requirements. This allows the device gate structure surrounding and covering the top, sidewalls, and bottom of the first channel layer 1122 and the second channel layer 1152 to meet the process requirements, thereby improving the performance of the semiconductor structure.

[0094] As an example, as mentioned above, the first type of transistor is an NMOS transistor, and the second type of transistor is a PMOS transistor. The threshold voltage of the NMOS transistor is less than that of the PMOS transistor, that is, the thickness of the second sacrificial layer 1151 is greater than that of the first sacrificial layer 1121.

[0095] In this embodiment, the number of first channel stacks 112 is three. In other embodiments, the number of first channel stacks may be other numbers.

[0096] In this embodiment, the first channel layer 1122 in the first region 100A is used to provide a conductive channel for the first type of transistor, and the first sacrificial layer 1121 is used to support the first channel layer 1122. After the first sacrificial layer 1121 in the first region 100A is subsequently removed, the first channel layer 1122 can be suspended with gaps. The first sacrificial layer 1121 in the first region 100A also occupies space for the subsequent formation of the gate dielectric layer, work function layer, and gate electrode layer. In this embodiment, the number of first sacrificial layers 1121 and first channel layers 1122 is the same.

[0097] In this embodiment, there are two second channel stacks 115. In other embodiments, the number of second channel stacks may be other numbers.

[0098] In this embodiment, the second channel layer 1152 in the second region 100B is used to provide a conductive channel for the second type of transistor, and the second sacrificial layer 1151 is used to support the second channel layer 1152. After the second sacrificial layer 1151 in the second region 100B is subsequently removed, the second channel layer 1152 can be suspended with spacing. The second sacrificial layer 1151 in the second region 100B also occupies space for the subsequent formation of the gate dielectric layer, work function layer, and gate electrode layer. In this embodiment, the number of second sacrificial layers 1151 and second channel layers 1152 is the same.

[0099] It should be noted that the thickness difference between the second sacrificial layer 1151 and the first sacrificial layer 1121 should not be too large or too small. If the thickness difference is too large, it will easily lead to an increase in the overall height of the semiconductor structure, resulting in an excessively large space occupied by the semiconductor structure. If the thickness difference is too small, while the thickness of the first sacrificial layer 1121 meets the process dimension requirements, the thickness of the second sacrificial layer 1151 will be too small, meaning the longitudinal distance between adjacent second channel layers 1152 will be too small. Consequently, the process window for forming the device gate structure in the second region 100B will be too small, increasing the difficulty of forming the device gate structure and affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness difference between the second sacrificial layer 1151 and the first sacrificial layer 1121 is in the range of 1 nanometer to 10 nanometers.

[0100] In this embodiment, in the step of graphically representing the first channel material stack structure 100 and the second channel material stack structure 111, the barrier layer 109 is removed.

[0101] Specifically, in the same step, the first channel material stack structure 100 and the second channel material stack structure 111 are graphically represented, and the barrier layer 109 is removed, which reduces the number of process steps, lowers the process cost, and improves the process efficiency.

[0102] It should be noted that before graphically representing the first channel material stack 100 and the second channel material stack 111, the protective layer 103 is removed.

[0103] Specifically, the protective layer 103 is removed to expose the first channel material stack structure 100 and the second channel material stack structure 111, which facilitates the subsequent graphical representation of the first channel material stack structure 100 and the second channel material stack structure 111.

[0104] In this embodiment, forming the substrate 1021 and the protrusion 1022 includes: during the process of patterning the first channel material stack structure 100 and the second channel material stack structure 111, the substrate 102 is also patterned, the unpatterned remaining substrate 102 is retained as the substrate 1021, and the portion protruding on the remaining substrate 102 is retained as the protrusion 1022.

[0105] Specifically, during the process of patterning the first channel material stack 100 and the second channel material stack 111, a substrate 1021 and a protrusion 1022 are formed, which reduces the number of process steps, lowers the process cost, and improves the process efficiency.

[0106] In this embodiment, the substrate 102 has a three-dimensional structure, and the substrate 102 includes a substrate 1021 and a protrusion 1022 protruding from the substrate 1021.

[0107] In this embodiment, the substrate 1021 is a silicon substrate 1021, and the protrusion 1022 is made of the same material as the substrate 1021, which is silicon.

[0108] Accordingly, in this embodiment, the first channel stack structure 113 and the second channel stack structure 116 are formed on the protrusion 1022.

[0109] refer to Figure 15 After the formation of the first channel stack structure 113 and the second channel stack structure 116, and before the formation of the dielectric wall, the method further includes: forming an isolation layer 118 on the substrate 1021 exposed by the first channel stack structure 113 and the second channel stack structure 116, the isolation layer 118 covering the sidewall of the protrusion 1022.

[0110] Specifically, the isolation layer 118 is used for electrical isolation of adjacent devices.

[0111] Therefore, the material of the isolation layer 118 is a dielectric material, which may include silicon oxide, silicon nitride, or silicon oxynitride. As an example, the material of the isolation layer 118 is silicon oxide.

[0112] refer to Figures 16 to 17 A dielectric wall 120 is formed between the first channel stack 113 and the second channel stack 116, and the dielectric wall 120 covers the sidewalls of the first channel structure layer and the second channel structure layer.

[0113] Specifically, the dielectric wall 120 is used to electrically isolate the first region 100A and the second region 100B.

[0114] In this embodiment, the step of forming the dielectric wall 120 includes: forming a dielectric material layer 119 that conformally covers the first channel stack structure 113, the second channel stack structure 116, and the top of the substrate 102, wherein the dielectric material layers 119 on the opposite sidewalls of the first channel stack structure 113 and the second channel stack structure 116 are in contact; removing the dielectric material layers 119 on the top of the substrate 102, the top of the first channel stack structure 113, the top of the second channel stack structure 116, and the sidewalls of the first channel stack structure 113 and the second channel stack structure 116, and the remaining dielectric material layer 119 between the first channel stack structure 113 and the second channel stack structure 116 serves as the dielectric wall 120.

[0115] In this embodiment, the process of removing the dielectric material layer 119 from the top of the substrate 102, the top of the first channel stack 113, the top of the second channel stack 116, the sidewalls of the first channel stack 113, and the sidewalls of the second channel stack 116 includes a dry etching process.

[0116] In this embodiment, the dielectric wall 120 is made of one or more of silicon oxide, silicon nitride, and silicon oxynitride. Specifically, silicon oxide, silicon nitride, and silicon oxynitride are all dielectric materials and have good electrical isolation properties.

[0117] refer to Figure 18 Remove the first sacrificial layer 1121 and the second sacrificial layer 1151.

[0118] It should be noted that removing the first sacrificial layer 1121 and the second sacrificial layer 1151 exposes a portion of the top, a portion of the sidewalls, and a portion of the bottom of the first channel layer 1122 and the second channel layer 1152, providing space for the subsequent formation of the device gate structure.

[0119] In this embodiment, a wet etching process is used to remove the first sacrificial layer 1121 and the second sacrificial layer 1151.

[0120] Specifically, the first channel layer 1122 and the second channel layer 1152 are both made of silicon, and the first sacrificial layer 1121 and the second sacrificial layer 1151 are both made of germanium silicon. Therefore, when the first sacrificial layer 1121 and the second sacrificial layer 1151 are removed by HCl vapor, the etching rate of the wet etching process on the first sacrificial layer 1121 and the second sacrificial layer 1151 is much greater than the etching rate on the first channel layer 1122 and the second channel layer 1152.

[0121] refer to Figure 19 After removing the first sacrificial layer 1121 and the second sacrificial layer 1151, a device gate structure 128 is formed on the top of the substrate 1021, spanning the first channel layer 1122 and the second channel layer 1152. In the first region 100A, the device gate structure 128 surrounds and covers a portion of the top, a portion of the sidewalls, and a portion of the bottom of the first channel layer 1122. In the second region 100B, the device gate structure 128 surrounds and covers a portion of the top, a portion of the sidewalls, and a portion of the bottom of the second channel layer 1152.

[0122] Specifically, when the device is in operation, the device gate structure 128 is used to control the opening or closing of the conductive channels of the first type transistor in the first region 100A and the second type transistor in the second region 100B.

[0123] In this embodiment, the step of forming the device gate structure 128 includes: forming a gate dielectric layer 121 that respectively surrounds the top, sidewalls and bottom of a portion of the first channel layer 1122 and the top, sidewalls and bottom of a portion of the second channel layer 1152; forming a work function layer 122 that respectively surrounds the gate dielectric layer 121 covering the first region 100A and the second region 100B, wherein the thicknesses of the work function layer 122 in the first region 100A and the second region 100B are different; and forming a gate electrode layer 123 that respectively surrounds the work function layer 122 covering the first region 100A and the second region 100B.

[0124] In this embodiment, the material of the gate dielectric layer 121 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0125] Specifically, the gate dielectric layer 121 includes a gate oxide layer that conformally covers a portion of the top, a portion of the sidewalls, and a portion of the bottom of the first channel layer 1122 and the second channel layer 1152, and a high-k gate dielectric layer 121 that conformally covers the gate oxide layer. The high-k gate dielectric layer is made of a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide.

[0126] The work function layer 122 is used to adjust the threshold voltage of the first type transistor and the second type transistor. Since the threshold voltage of the first type transistor and the threshold voltage of the second type transistor are different, the thickness of the work function layer 122 in the first region 100A and the second region 100B is different.

[0127] In this embodiment, the material of the work function layer 122 includes one or more of TiN, TaN, TaSiN, TiAl, TiSiN, TaSiN, and TiAlC. The specific material of the work function layer 122 is determined based on the performance of the first-type transistor and the second-type transistor.

[0128] The gate electrode layer 123 is used for subsequent electrical connection with an external structure. The material of the gate electrode layer 123 includes one or more of Pt, Ti, Ag, W, Al, Cu, Ni, and Au. As an example, the material of the gate electrode layer 123 is W.

[0129] In this embodiment, the process of forming the gate electrode layer 123 that surrounds the work function layer 122 covering the first region 100A and the second region 100B respectively includes a chemical vapor deposition process.

[0130] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, the substrate including a first region and a second region, the substrate including a substrate and protrusions respectively protruding from the first region and the second region on the substrate; An isolation layer is located on the substrate exposed by the protrusion, and the isolation layer covers the sidewall of the protrusion; A first channel structure layer is suspended on top of the protrusion in the first region. Along the normal direction of the substrate surface, the first channel structure layer includes one or more spaced-apart first channel layers. The second channel structure layer is suspended on top of the protrusion in the second region. Along the normal direction of the substrate surface, the second channel structure layer includes one or more spaced second channel layers, and the longitudinal distance between adjacent second channel layers is different from the longitudinal distance between adjacent first channel layers. A dielectric wall is located on a substrate between the first channel structure layer and the second channel structure layer, and the dielectric wall covers the sidewalls of the first channel structure layer and the second channel structure layer. A device gate structure is located on top of the substrate and spans the first and second channel layers. In the first region, the device gate structure surrounds and covers a portion of the top, a portion of the sidewalls, and a portion of the bottom of the first channel layer. In the second region, the device gate structure surrounds and covers a portion of the top, a portion of the sidewalls, and a portion of the bottom of the second channel layer.

2. The semiconductor structure as described in claim 1, characterized in that, The top of the first channel structure layer and the top of the second channel structure layer are flush with each other.

3. The semiconductor structure as described in claim 1, characterized in that, The difference between the longitudinal distance between adjacent second channel layers and the longitudinal distance between adjacent first channel layers ranges from 1 nanometer to 10 nanometers.

4. The semiconductor structure as described in claim 1, characterized in that, The dielectric wall is made of one or more of silicon oxide, silicon nitride, and silicon oxynitride.

5. The semiconductor structure as described in claim 1, characterized in that, The device gate structure includes: a gate dielectric layer that surrounds and covers the top, sidewalls and bottom of a portion of the first channel layer, and the top, sidewalls and bottom of a portion of the second channel layer, respectively; The work function layers surround and cover the gate dielectric layers of the first and second regions, respectively, and the thicknesses of the work function layers in the first and second regions are different. Gate electrode layers surround the work function layers covering the first and second regions, respectively.

6. The semiconductor structure as described in claim 5, characterized in that, The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3; The material of the work function layer includes one or more of TiN, TaN, TiAl, TiSiN, TaSiN, and TiAlC; The material of the gate electrode layer includes one or more of Pt, Ti, Ag, W, Al, Cu, Ni, and Au.

7. The semiconductor structure as described in claim 1, characterized in that, The material of the first channel layer includes one or more of silicon, silicon germanide, germanium, and group III-V semiconductor materials; The material of the second channel layer includes one or more of silicon, silicon germanide, germanium, and group III-V semiconductor materials.

8. The semiconductor structure as described in claim 1, characterized in that, The first region is used to form a first type transistor, and the second region is used to form a second type transistor. The first type transistor and the second type transistor have different threshold voltages, and / or the first type transistor and the second type transistor have different channel conductivity types.

9. A method for forming a semiconductor structure, characterized in that, include: A substrate is formed, the substrate including a first region and a second region, the substrate including a substrate and protrusions respectively protruding from the first region and the second region on the substrate; A first channel stack structure is formed on the protrusion in the first region. The first channel stack structure includes one or more longitudinally stacked first channel stacks. Each first channel stack includes a first sacrificial layer and a first channel layer located on the first sacrificial layer. A second channel stack structure is formed on the protrusion in the second region. The second channel stack structure includes one or more longitudinally stacked second channel stacks. Each second channel stack includes a second sacrificial layer and a second channel layer on the second sacrificial layer. The thickness of the second sacrificial layer is different from the thickness of the first sacrificial layer. Remove the first and second sacrificial layers; After removing the first sacrificial layer and the second sacrificial layer, a device gate structure is formed on top of the substrate, spanning the first channel layer and the second channel layer. In the first region, the device gate structure surrounds and covers a portion of the top, a portion of the sidewalls, and a portion of the bottom of the first channel layer. In the second region, the device gate structure surrounds and covers a portion of the top, a portion of the sidewalls, and a portion of the bottom of the second channel layer.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The steps of forming the first channel stack structure and the second channel stack structure include: forming a first channel material stack structure on a substrate in the first region; forming a second channel material stack structure on a substrate in the second region after forming the first channel material stack structure; and graphically representing the first channel material stack structure and the second channel material stack structure, wherein the first channel material stack structure is graphically represented as the first channel stack structure, and the second channel material stack structure is graphically represented as the second channel stack structure.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, Before graphically representing the first channel material stack structure and the second channel material stack structure, the substrate is a planar substrate; Forming the substrate and the protrusion includes: during the process of patterning the first channel material stack structure and the second channel material stack structure, the substrate is also patterned, the remaining unpatterned substrate is retained as the substrate, and the portion protruding on the remaining substrate is retained as the protrusion.

12. The method for forming a semiconductor structure as described in claim 10, characterized in that, In the step of forming a first channel material stack structure on the substrate of the first region, the first channel material stack structure is also formed on the substrate of the second region; The step of forming a second channel material laminate structure on a substrate in the second region includes: forming a trench in the second region that penetrates the first channel material laminate structure; A second channel material stack structure is formed in the groove.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The process of forming a second channel material stack structure in the trench includes an epitaxial process.

14. The method for forming a semiconductor structure as described in claim 12 or 13, characterized in that, After the trench is formed and before the second trench material laminate structure is formed, the method further includes: forming a barrier layer on the sidewall of the trench; The step of graphically representing the first channel material stack structure and the second channel material stack structure also includes removing the barrier layer.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The barrier layer is made of one or more of silicon nitride, silicon oxide, and silicon carbide.

16. The method for forming a semiconductor structure as described in claim 14, characterized in that, The thickness of the barrier layer is 8 nanometers to 8.5 nanometers.

17. The method for forming a semiconductor structure as described in claim 14, characterized in that, The step of forming the barrier layer includes: forming a barrier material layer on the sidewalls and bottom of the trench and on top of the first trench material laminate structure; removing the barrier material layer at the bottom of the trench and the top of the first trench material laminate structure, and using the remaining barrier material layer on the sidewalls of the trench as the barrier layer.

18. The method for forming a semiconductor structure as described in claim 12 or 13, characterized in that, Before forming the trench, the method further includes: forming a protective layer on top of the first trench material laminate structure; During the formation of the trench, the trench also penetrates the protective layer at the top of the first channel material laminate structure.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, The protective layer is made of one or more of silicon nitride, silicon oxide, and silicon carbide.

20. The method for forming a semiconductor structure as described in claim 18, characterized in that, The thickness of the protective layer is 450 to 500 angstroms.

21. The method for forming a semiconductor structure as described in claim 9, characterized in that, After forming the first channel stack structure and the second channel stack structure, and before removing the first sacrificial layer and the second sacrificial layer, the method further includes: forming a dielectric wall between the first channel stack structure and the second channel stack structure, the dielectric wall covering the sidewalls of the first channel structure layer and the second channel structure layer.

22. The method for forming a semiconductor structure as described in claim 9, characterized in that, The thickness difference between the second sacrificial layer and the first sacrificial layer ranges from 6 nanometers to 8 nanometers.

23. The method for forming a semiconductor structure as described in claim 9, characterized in that, The step of forming the gate structure of the device includes: forming a gate dielectric layer that surrounds and covers the top, sidewalls and bottom of the first channel layer portion, and the top, sidewalls and bottom of the second channel layer portion, respectively; A work function layer is formed that surrounds and covers the gate dielectric layer of the first region and the second region, respectively, and the thickness of the work function layer of the first region and the second region is different. Gate electrode layers are formed that surround the work function layers covering the first and second regions, respectively.

24. The method for forming a semiconductor structure as described in claim 9, characterized in that, The first region is used to form a first type transistor, and the second region is used to form a second type transistor. The first type transistor and the second type transistor have different threshold voltages, and / or the first type transistor and the second type transistor have different channel conductivity types.

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