Embedded trace substrate assemblies and related microelectronic device assemblies, electronic systems, and processes

Abstract

This application relates to embedded trace substrate assemblies and related microelectronic device assemblies, electronic systems, and processes. An embedded trace substrate assembly includes an accumulated laminate material having an upper surface on a die side and a board side. A solder resist material on the die side defines a bonding line segment, wherein bonding pads include a first lateral width, and top first and second plating materials are on the bonding pads. The top second plating material has a top surface above the upper surface of the accumulated laminate material. The bonding line segment includes a row of the bonding pads, the top first plating material, and the top second plating material, and the solder resist material extends from a portion of the upper surface and recedes from the bonding pads.

Description

[0001] Priority Claim

[0002] This application claims the filing date benefit of U.S. Patent Application Serial No. 17 / 930,021, filed on September 6, 2022, entitled "Embedded trace substrate assemblies, and associated microelectronic device assemblies, electronic systems, and processes". Technical Field

[0003] In various embodiments, this disclosure generally relates to the field of integrated circuit device substrates, including the design and fabrication of embedded trace substrates. More specifically, this disclosure relates to bonding finger structures in embedded trace substrates. Background Technology

[0004] Integrated circuit devices can be mounted on through-hole boards. Through-hole boards can be used to mount microelectronic devices, which in turn are used to mount the through-hole boards onto larger structures such as printed circuit boards. Due to miniaturization challenges in fabricating integrated circuits on semiconductor wafers and coupling diced integrated circuits to through-hole boards, improvements to through-hole boards are desired. Summary of the Invention

[0005] In some embodiments, an embedded trace substrate assembly includes a cumulative laminate, a solder resist, a bonding pad, a first top plating, a second top plating, and a wire bonding segment. The cumulative laminate includes a die side including an upper surface and a board side opposite the die side. The solder resist is on the upper surface of the die side of the cumulative laminate. The bonding pad is exposed through the cumulative laminate at the die side and has a first lateral width. The first top plating is on the bonding pad. The first top plating includes a top surface substantially coplanar with the upper surface of the cumulative laminate. The second top plating is on the first top plating and has a second lateral width less than the first lateral width. The first top plating includes a top surface overlying the upper surface of the die side of the cumulative laminate. The wire bonding segment includes a row of the bonding pads, the first top plating, and the second top plating. The solder resist extends from a portion of the upper surface of the die side of the cumulative laminate and is recessed from the bonding pads.

[0006] In an additional embodiment, a microelectronic device assembly includes a microelectronic device and bonding wires wire-bonded to an embedded trace substrate assembly. The embedded trace substrate assembly includes an accumulated laminate, a solder resist, bonding pads, a first top plating material, a second top plating material, and a wire bonding segment. The accumulated laminate includes a board side and a die side opposite the board side, including an upper surface. The solder resist is located on the upper surface of the die side. The bonding pads are exposed on the die side through the accumulated laminate and have a first lateral width. The first top plating material is on the bonding pads and includes a top surface substantially coplanar with the upper surface of the die side of the accumulated laminate. The second top plating material is on the first top plating material and has a second lateral width less than the first lateral width. The first top plating material is contained on a top surface above the upper surface of the die side of the accumulated laminate. The wire bonding segment includes a row of bonding pads, the first top plating material, and the second top plating material. The solder resist material is only present on the periphery adjacent to the wire bonding section. The bonding line couples the microelectronic device to the top second plating material.

[0007] In another embodiment, a process for forming an embedded trace substrate assembly includes patterning a masking material on an upper surface of an accumulated laminate and on bonding pads to form a patterned masking material overlapping a portion of the bonding pads, the bonding pads having a first lateral width. A first top plating material is formed on the bonding pads to a height equal to the upper surface of the accumulated laminate. A second top plating material is formed on the first top plating material. The second top plating material is at least partially above the upper surface of the accumulated laminate and has a second lateral width smaller than the first lateral width of the bonding pads. The patterned masking material is removed. A top solder mask is formed on the upper surface to define wire bonding segments. The top solder mask is only peripherally adjacent to the wire bonding segments.

[0008] In yet another embodiment, an electronic system includes: an input device; an output device; a processor device operatively coupled to the input device and the output device; a memory device operatively coupled to the processor device; and an embedded trace substrate assembly. The embedded trace substrate assembly includes an accumulated laminate material, a solder resist material, bonding pads, a first top plating material, a second top plating material, and a wire bonding segment. The accumulated laminate material includes a die side having an upper surface and a board side opposite to the die side. The solder resist material is on the upper surface of the die side of the accumulated laminate material. The bonding pads are exposed at the die side through the accumulated laminate material and each has a first lateral width. The second top plating material is on the first top plating material and has a second lateral width smaller than the first lateral width of each of the bonding pads. The first top plating material has a top surface vertically overlying the upper surface of the die side of the accumulated laminate material. The wire bonding segment includes rows of bonding pads, the first top plating material, and the second top plating material. The solder resist material extends from a portion of the upper surface and retracts from the bonding finger pad. The solder resist material is only present on the periphery adjacent to the wire bonding section. Attached Figure Description

[0009] Figures 1A to 1G This is a simplified longitudinal cross-sectional view of the embedded trace substrate assembly according to embodiments of the present disclosure at different processing stages of the process for forming an integrated circuit device.

[0010] Figures 2A to 2F According to embodiments of this disclosure Figure 1G Simplified longitudinal cross-sectional views of the obtained published embedded trace substrate assembly at different processing stages of the process for forming integrated circuit devices.

[0011] Figure 2Fi From Figure 2F Segment insertion in Figure 2Fi Detailed enlarged images obtained.

[0012] Figure 2G This is a detailed enlarged view of an embedded trace substrate assembly according to an embodiment of the present disclosure.

[0013] Figure 3 This is a simplified longitudinal cross-section of an embedded trace substrate assembly according to an embodiment of the present disclosure.

[0014] Figure 4 This is a simplified perspective view of a microelectronic device package including an embedded trace substrate assembly according to embodiments of the present disclosure.

[0015] Figure 5This is a simplified longitudinal cross-sectional view of an embedded trace substrate assembly including wire bonding sections and flip chip sections according to an embodiment of the present disclosure.

[0016] Figure 6 This is a block diagram of an electronic system according to an embodiment of the present disclosure.

[0017] Figure 7 and 8 yes Figures 1A to 2G A simplified process flow diagram of the method embodiment described herein. Detailed Implementation

[0018] During the miniaturization trend of substrate assemblies for microelectronic devices, the problem of sufficiently reducing the spacing of bond lines (L / S) without bridging between adjacent bond lines is addressed. Similarly, with the miniaturization of substrate assemblies, the problem of unsatisfactory wire bond pin values ​​is addressed by the disclosed recessed bond finger pads and the bump-coated material on the recessed bond fingers, which provides useful mechanical tensile strength prior to wire bond failure.

[0019] The following description provides specific details, such as material composition, shape, and size, to provide an exhaustive description of embodiments of this disclosure. However, those skilled in the art will understand that embodiments of this disclosure can be practiced without these specific details. In fact, embodiments of this disclosure can be practiced in conjunction with conventional microelectronic device packaging substrate manufacturing techniques used in industry. Furthermore, the description provided below does not form a complete process flow for manufacturing microelectronic device packaging substrates (e.g., memory device packaging substrates, integrated circuit device packaging substrates, and die-deposited integrated circuit device packaging substrates). The structures described below do not form a complete microelectronic device packaging substrate. However, those process actions and structures are useful for understanding embodiments of this disclosure and will be described in detail below. Additional actions to form a complete microelectronic device packaging substrate from the structure can be performed using conventional manufacturing techniques.

[0020] The drawings presented herein are for illustrative purposes only and do not represent actual drawings of any particular material, component, structure, device, or system. Variations in the shapes depicted in the drawings are expected due to, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes or areas illustrated, but rather include shape deviations due to, for example, manufacturing processes. For instance, an area illustrated or described as box-shaped may have rough and / or non-linear characteristics, and an area illustrated or described as circular may contain some rough and / or linear characteristics. Furthermore, illustrated acute angles may be rounded, and vice versa. Therefore, the areas illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of the areas and do not limit the scope of the claims of this invention. The drawings are not necessarily drawn to scale. Additionally, common elements between figures may retain the same numerical symbols.

[0021] As used herein, the term "package substrate" refers to a printed circuit board used to mount microelectronic devices (e.g., memory dies or processor dies), and the package substrate may be mounted on a larger printed circuit board, such as a motherboard. The package substrate may be an embedded trace substrate assembly, wherein the main portion of the electrical connection structure is located below the top organic surface of the package substrate. The embedded trace substrate assembly may be a substrate used to assemble a decomposed die integrated circuit system.

[0022] As used herein, “memory device” means and includes, but is not limited to, microelectronic devices that exhibit memory functionality but are not limited to memory functionality. In other words, by way of non-limiting example only, the term “memory device” includes not only conventional memory (e.g., conventional volatile memory, such as conventional dynamic random access memory (DRAM); conventional non-volatile memory, such as conventional NAND memory), but also application-specific integrated circuits (ASICs) (e.g., system-on-a-chip (SoC)), microelectronic devices combining logic and memory, and graphics processing units (GPUs) incorporating memory.

[0023] As used herein, the terms “integrated circuit” or “integrated circuit device” may refer to “microelectronic device” or “nanoelectronic device,” each of which may be associated with a critical size demonstrated by testing. The term “integrated circuit” includes (but is not limited to) memory devices and other devices (e.g., semiconductor devices) that may or may not be incorporated into memory. The term “integrated circuit” may include (but is not limited to) logic devices. The term “integrated circuit” may include (but is not limited to) processor devices, such as a central processing unit (CPU) or a graphics processing unit (GPU). The term “integrated circuit” may include (but is not limited to) radio frequency (RF) devices. Furthermore, an “integrated circuit” device may incorporate memory and other functions, such as (for example) a so-called “system-on-a-chip (SoC)” that includes a processor and memory, or an integrated circuit device that includes logic and memory. Furthermore, an “integrated circuit” device may incorporate memory and other functions, such as (for example) a so-called “disassembled die device,” in which dissimilar integrated circuit components are associated to produce higher functionality, such as the functionality of a SoC, including processor-only, memory-only, processor and memory, or integrated circuit devices that include logic and memory. The decomposed die device may be a system-in-package (SiP) assembly comprising at least one logic processor, at least one graphics processor, at least one memory device (e.g., a 3D NAND memory device), at least one radio frequency device, at least one analog device (e.g., a capacitor, inductor, resistor, balun), and at least two of these SiP devices, and may be assembled and connected to at least one embedded multi-die interconnect bridge (EMIB) device, and at least two of said devices may be coupled with through-silicon via (TSV) technology.

[0024] As used herein, the term “configured” refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device in a predetermined manner to facilitate the operation of one or more of the structure and device.

[0025] As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” refer to the principal plane of the reference structure and are not necessarily defined by the Earth’s gravitational field. A “horizontal” or “lateral” direction is a direction substantially parallel to the principal plane of the structure, while a “vertical” or “longitudinal” direction is a direction substantially perpendicular to the principal plane of the structure. The principal plane of the structure is defined by the surfaces of the structure having a relatively larger area than the other surfaces of the structure. Referring to the figures, a “horizontal” or “lateral” direction may be perpendicular to the indicated “Z” axis and parallel to the indicated “X” axis and / or parallel to the indicated “Y” axis; and a “vertical” or “longitudinal” direction may be parallel to the indicated “Z” axis, perpendicular to the indicated “X” axis, and perpendicular to the indicated “Y” axis. Furthermore, as used herein, in a CMOS device, the gate width direction may be represented by the “W” axis, where the Y-axis is replaced by the W axis to indicate the direction of the gate width.

[0026] As used herein, features described as “adjacent” to each other (e.g., areas, structures, devices) mean and include the features of one (or more) disclosed individuals that are most closely (e.g., closest) to each other. Additional features (e.g., additional areas, additional structures, additional devices) of one (or more) disclosed individuals that do not match “adjacent” features may be positioned between “adjacent” features. In other words, “adjacent” features may be positioned adjacent to each other such that no other features intervene between “adjacent” features; or “adjacent” features may be positioned non-adjacent to each other such that at least one feature of an individual other than the individual associated with at least one “adjacent” feature is positioned between “adjacent” features. Thus, features described as “vertically adjacent” to each other mean and include the features of one (or more) disclosed individuals that are most closely (e.g., vertically closest) to each other. Furthermore, features described as “horizontally adjacent” to each other mean and include the features of one (or more) disclosed individuals that are most closely (e.g., horizontally closest) to each other.

[0027] As used herein, for ease of description, spatially relative terms (e.g., “below,” “under,” “down,” “bottom,” “above,” “top,” “front,” “back,” “left,” “right,” and the like) may be used to describe the relationship of one element or feature to another element(s), as illustrated in the figures. Unless otherwise specified, spatially relative terms are intended to cover not only the orientation depicted in the figures but also different orientations of the material. For example, if the material in the figures were reversed, an element described as being “below,” “under,” “below,” or “on the bottom” of other elements or features would be oriented “above” or “on the top” of other elements or features. Therefore, those skilled in the art will understand that the term “below” can encompass both above and below orientations, depending on the context in which the term is used. Material may be oriented in other ways (e.g., rotated 90 degrees, reversed, flipped) and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0028] As used herein, the singular forms “a” and “the” are intended to also include the plural forms, unless the context clearly indicates otherwise.

[0029] As used in this document, “and / or” includes any and all combinations of one or more of the associated columns.

[0030] As used in this article, the phrase “coupled to” refers to structures being operationally connected to each other, such as by a direct ohmic connection or by an indirect connection (e.g., by another structure).

[0031] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and includes, as understood by one of ordinary skill in the art, the degree to which a given parameter, property, or condition is satisfied within a certain range of variation (e.g., within acceptable tolerances). For example, depending on the specific parameter, property, or condition that is substantially satisfied, it may be satisfied at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100%.

[0032] As used herein, “about” or “approximate” with respect to a particular parameter includes the degree of variation of the value within acceptable tolerances for the particular parameter, as understood by one of ordinary skill in the art. For example, “about” or “approximate” with respect to a value may include additional values ​​within the range of 90.0% to 110.0% of the value, such as within the range of 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0033] As used herein, “conductive material” means and includes conductive materials, such as one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), alloys (e.g., Co-based) Alloys, Fe-based alloys, Ni-based alloys, Fe and Ni-based alloys, Co and Ni-based alloys, Fe and Co-based alloys, Co, Ni and Fe-based alloys, Al-based alloys, Cu-based alloys, Magnesium (Mg)-based alloys, Ti-based alloys, steel, low-carbon steel, stainless steel), conductive metallic materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides), and conductive doped semiconductor materials (e.g., conductive doped polycrystalline silicon, conductive doped germanium (Ge), conductive doped silicon-germanium (SiGe)). Furthermore, "conductive structure" means and includes structures formed from conductive materials and containing conductive materials.

[0034] As used herein, “insulating material” means and includes electrically insulating materials, such as one or more of the following: at least one dielectric oxide material (such as one or more of the following: silicon oxide (SiO2)). x Phosphorus silicate glass, borosilicate glass, borosilicate-phosphorus silicate glass, fluorosilicate glass, alumina (AlO) x ), hafnium oxide (HfO) x ), niobium oxide (NbO) x Titanium oxide (TiO) x Zirconium oxide (ZrO) x ), tantalum oxide (TaO) x ) and magnesium oxide (MgO) x ()), at least one dielectric nitride material (e.g., silicon nitride (SiN) y ()), and at least one dielectric oxide nitride material (e.g., silicon oxynitride (SiO) x N y and at least one dielectric carbon nitride material (e.g., silicon carbon nitride (SiO2)). x C z N y This article contains the chemical formula of one or more of "x", "y" and "z" (e.g., SiO2). x AlO x HfO x NbO x TiO x SiN y SiO x N ySiO x C z N y An insulating material represents a material containing, for each atom of another element (e.g., Si, Al, Hf, Nb, Ti), an average ratio of "x" atoms of one element, "y" atoms of another element, and "z" atoms of an additional element (if present). Because a chemical formula represents relative atomic ratios rather than absolute chemical structures, an insulating material may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x," "y," and "z" (if present) may be integers or non-integers. As used herein, the term "non-stoichiometric compound" means and includes chemical compounds composed of elements that cannot be expressed by a well-defined ratio of natural numbers and violate the law of definite proportions. Additionally, "insulating structure" means and includes structures formed from and containing insulating materials.

[0035] As used herein, the term "homogeneous" means that the relative amounts of elements contained in a feature (e.g., material, structure) remain constant across all different parts of the feature (e.g., different horizontal parts, different vertical parts). Conversely, as used herein, the term "heterogeneous" means that the relative amounts of elements contained in a feature (e.g., material, structure) vary across all different parts of the feature. If a feature is heterogeneous, then the amounts of one or more elements contained in the feature may vary gradually (e.g., abruptly) or continuously (e.g., gradually, such as linearly or parabolically) across all different parts of the feature. A feature may, for example, be formed by and contain a stack of at least two different materials.

[0036] As used herein, the term "semiconductor substrate" means a structure comprising semiconducting materials, including (but not limited to) bulk semiconducting materials such as semiconducting wafers (alone or in a combination of other materials) and layers or feature structures of semiconducting materials (alone or in a combination of other materials). The term "substrate" refers to any support structure comprising (but not limited to) the aforementioned semiconductor substrate. In some applications, a substrate may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit manufacturing. Such materials may include one or more of, for example, refractory metals, barrier materials, diffusion materials, insulating materials, etc.

[0037] Unless the context otherwise indicates, the materials described herein can be formed by any suitable technique including (but not limited to) spin coating, blanket coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), physical vapor deposition (PVD) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, the technique used for depositing or growing the material may be selected by a person skilled in the art. Additionally, unless the context otherwise indicates, the removal of the materials described herein can be accomplished by any suitable technique including (but not limited to) etching (e.g., dry etching, wet etching, vapor etching), ion milling, planarization (e.g., chemical mechanical planarization (CMP)), or other known methods.

[0038] Figures 1A to 1G This is a simplified longitudinal cross-sectional view of the embedded trace substrate assembly according to embodiments of the present disclosure at different processing stages of the process for forming an integrated circuit device. Figures 2A to 2F According to embodiments of this disclosure Figure 1G Simplified longitudinal cross-sectional views of the published embedded trace substrate assembly at different processing stages of the process for forming an integrated circuit device. The embedded trace substrate (ETS) assembly may include traces integrated with a printed circuit board structure, for example, having a main portion of electrical connection on or beneath the surface of the organic material of the printed circuit board (PWB). "Trace" generally means an electrical contact structure, an in-board electrical connection structure, a lead of a wire bonding pad structure, and other conductive structures that may have exposed portions for electrical contact or extend between other contact structures under solder resist. "Main portion" of the electrical connection may mean that the majority of the electrical connection is on or beneath the surface of the organic material of the printed circuit board. The ETS printed circuit board may have a die side and a board side (e.g., Figure 2AThe ETS printed circuit board (PCB) includes a die side 132 and a board side 134. The die side of the PCB may have electrical connections for connecting to active integrated circuit devices, such as microelectronic devices, including processor devices, memory devices, RF devices, and motion-sensitive devices. The die side may also include solder bump pads for mounting flip-chip microelectronic devices, such as processors, RF devices, memory devices, and other microelectronic devices. The die side may also have electrical connections for connecting to passive devices, such as capacitors, inductors, resistors, baluns, RFID devices, and other devices coupled to the integrated circuit devices on the die side. The die side of the ETS PCB may include an array of electrical contacts, such as bonding fingers for wire bonding, having a main portion of the bonding fingers on or below the surface of the organic material of the PWB structure. The die side of the ETS PCB may include via contacts for communication between the die side and the board side. An ETS printed circuit board on the die side may include "top traces" for die-side electrical connectivity for inter-chip-side connections between chip-side devices. The ETS printed circuit board may be a package substrate having electrical connections on a board side opposite the die side for coupling to a larger board, such as a motherboard printed circuit board. These board-side electrical connections may include an array of electrical bumps, such as a solder bump array including an array of electrical bump pads (e.g., solder bump pads). An ETS printed circuit board on the board side may include "bottom traces" for board-side electrical connectivity for inter-board-side connections between board-side structures. The ETS printed circuit board may also include solder bump pads on the board side for electrical connectivity. Hereinafter, electrical connections on the die side may be referred to as a "top structure" or a first-side structure, and electrical connections on the board side may be referred to as a "board side" or a second-side structure.

[0039] refer to Figure 1A The embedded trace substrate assembly precursor 99 includes a carrier wafer 102, a first conductive temporary layer 104, and a second conductive temporary layer 106 opposite to the first conductive temporary layer 104. The carrier wafer 102, the first conductive temporary layer 104, and the second conductive temporary layer 106 are useful for dual-sided manufacturing embodiments of the ETS printed circuit board. In this embodiment, the first conductive temporary layer 104 and the second conductive temporary layer 106 are electronic-grade copper.

[0040] refer to Figure 1B Constructed in the embedded trace substrate assembly precursor 99 ( Figure 1AThe embedded trace substrate assembly 100 illustrates a processing stage in which a first masking material 108 is patterned on each of a first conductive temporary layer 104 and a second conductive temporary layer 106, and a plating process is performed to include the formation of conductive structures, such as traces 110 (also referred to as top traces 110A), via contacts 112, and bonding pads 114 for wire bonding interconnects. The plating material for traces 110, via contacts 112, and bonding pads 114 may include electronic-grade copper (Cu). In an embodiment, plating is performed using the first conductive temporary layer 104 and the second conductive temporary layer 106 as cathodes, and electronic-grade copper is electroplated onto the embedded trace substrate assembly 100. Other conductive materials can be used to form traces 110, via contacts 112, and bonding pads 114, such as silver (Ag), copper-silver alloys, gold (Au), gold-silver alloys, copper-silver-gold alloys, aluminum (Al), and other conductive materials.

[0041] refer to Figure 1C The embedded trace substrate assembly 100 has had the first shielding material 108 stripped off. Figure 1B This leaves traces 110, via contacts 112, and engagement pads 114 on the first conductive temporary layer 104 and the second conductive temporary layer 106. In an embodiment, the first shielding material 108 ( Figure 1B It is removed by a dry stripping process that substantially exposes both the first conductive temporary layer 104 and the second conductive temporary layer 106, as well as the trace 110, the via contact 112 and the engagement finger pad 114.

[0042] refer to Figure 1D The embedded trace substrate assembly 100 is covered with a cumulative laminate material 116, such as a prepreg material useful for printed circuit boards used for mounting microelectronic devices. The process may include spin-coating the prepreg precursor material and then curing and planarizing the cumulative laminate material 116 as needed. The prepreg precursor material may be assembled in a stage where it is useful to composite the cumulative laminate material 116. In an embodiment, a metal seed material 118 is formed on the cumulative laminate material 116, wherein the metal seed material 118 may be a copper material useful for plating a second layer of traces and pads on the embedded trace substrate assembly 100. In an embodiment, the metal seed material 118 is electronic-grade copper, which is substantially homogeneous copper, wherein the material of the trace 110, the via contact 112, and the bonding pad 114 is electronic-grade copper. In an embodiment, the metal seed material 118 is a non-metallic conductive material, such as a graphene seed material.

[0043] refer to Figure 1EThe embedded trace substrate assembly 100 has been processed to expose the path contacts 112 at the upper surface 120 of the path contacts by opening a path 122 through the accumulated laminate material 116 and the metal seed material 118. The path 122 may have non-orthogonal sidewalls that expose the upper surface 120 of the path contacts 112, wherein the non-orthogonal sidewalls have been formed with characteristics of a laser drilling process.

[0044] refer to Figure 1F The embedded trace substrate assembly 100 has been treated with a second masking material 124 patterned over the accumulated laminate material 116 and the metal seed material 118. The second masking material 124 may be a photoresist material spin-coated and patterned over the accumulated laminate material 116 and the metal seed material 118. After patterning the second masking material 124, a second plating process is performed to form a bottom array bonding pad 126, such as an electrical bump array pad 126. The second plating process also forms bottom traces 128 and bottom via pads 130, wherein the bottom array bonding pads 126 and the bottom traces 128 are above the surface of the accumulated laminate material 116 and above and on the metal seed material 118, and wherein the bottom via pads 130 contact via contacts 112. The bottom via pads 130 may also be referred to as through-substrate fill vias 130, wherein the through-substrate fill vias 130 are connected from the board side 134 (e.g., through contact with via contacts 112 on the die side 132). Figure 2A ) Connect to the die side 132 (e.g.) Figure 2A ). Figure 1F The term "bottom" refers to the discrete embedded trace substrate assembly (e.g. Figure 2A The embedded trace substrate assembly 200 is used for reference to the lower, bottom, or plate side connection.

[0045] refer to Figure 1G The embedded trace substrate assembly 100 has had the second shielding material 124 stripped off. Figure 1F This leaves the bottom array bonding pads 126, bottom traces 128, and bottom via pads 130. In an embodiment, an etching process is performed to individually cut the metal seed material 118 (e.g., between the bottom array bonding pads 126, bottom traces 128, and bottom via pads 130) between them. Figure 2A The portion for which the metal seed material 118 is used to cut a plurality of bottom array bonding pads 126, bottom traces 128 and bottom passage pads 130 can be processed in a subsequent processing stage (e.g. Figure 2A Implemented in ).

[0046] Figure 2A yes Figure 1GThe image depicts a portion of the embedded trace substrate assembly 100 after subsequent processing for forming the embedded trace substrate assembly 200 (also referred to herein as "released embedded trace substrate assembly 200"). The embedded trace substrate assembly 200 represents the accumulation to the second conductive temporary layer 106 (…). Figures 1A to 1G The structure on the substrate is described, and the embedded trace substrate assembly 200 is depicted having a die side 132 and a plate side 134. In the following, the die side 132 may also be referred to as the first side 132, and the plate side 134 may also be referred to as the second side 134. Furthermore, the die side 132 may be referred to as the top side 132 or upper side 132, and the plate side 134 may be referred to as the bottom side 134 or lower side 134. Processes have been completed to remove the carrier wafer 102, for example, by a thermal release process. Figure 1G ) and the second conductive temporary layer 106 ( Figure 1G ) to carry the carrier chip 102 ( Figure 1G ) and the second conductive temporary layer 106 ( Figure 1G Separation is then performed, followed by an etching process to remove the second conductive temporary layer 106. Figure 1G In an embodiment, the second conductive temporary layer 106 is used to remove the temporary layer. Figure 1G The etching process resulted in the top trace 110, top pass contact 112, and engagement finger pad 114 being etched. Figures 1A to 1G Several structural recesses are provided, namely a recessed top trace 110A, a recessed top access contact 112A, and a recessed engagement finger pad 114A (hereinafter referred to as top trace 110A, top access contact 112A, and engagement finger pad 114A). Etching for forming the top trace 110A, top access contact 112A, and engagement finger pad 114A produces a recess depth 136, which is a measurement between the upper surface 138 of the accumulated laminate material 116 and the exposed layer of the top trace 110A, top access contact 112A, and engagement finger pad 114A. In embodiments, the recess depth 136 ranges from about 2 micrometers (μm) to about 6 μm.

[0047] Still referencing Figure 2A Metal seed material 118 ( Figure 1D to 1G The metal seed material 118 between several structures of the bottom array bonding pad 126, bottom trace 128, and bottom via pad 130 has been removed by processing (e.g., directional etching). Figure 1D to 1G The exposed portion of the material is cut to form a metal seed material 118A.

[0048] refer to Figure 2BA process has been completed to form a third masking material 140 on each of the die side 132 and board side 134 of the embedded trace substrate assembly 200. The process includes patterning the third masking material 140 on the die side 132 to expose the bonding pads 114A, and the masking material intrusion distance 142 (also referred to as the top plating material backlash distance 142) from the lateral boundary of the bonding pads 114A to the lateral boundary of the exposed bonding pads 114A, rather than all of the third masking material 140. In embodiments, the third masking material 140 is formed using a dry film adhesion process employing any useful known technique, followed by patterning and material removal to expose some of the bonding pads 114A, resulting in the masking material intrusion distance 142. Other materials can be used to form the third masking material 140, such as photoresist materials that can be spin-coated, cured, and patterned to form the masking material intrusion distance 142. In the embodiments, the shielding material intrusion distance 142 is in the range of about 1 μm to about 4 μm.

[0049] refer to Figure 2C The process has been completed to form a top first plating material 144 onto a plurality of bonding finger pads 114A. In an embodiment, the top first plating material 144 is a nickel-containing material, such as electronic-grade nickel. The top first plating material 144 may fill the bonding finger pads 114A to a depth substantially the same as the recess depth 136, such that the recess depth 136 is substantially filled by the top first plating material 144 and the top first plating material 144 does not protrude above the upper surface 138 of the cumulative laminate material 116, and such that the top first plating material 144 fills the bonding finger pads 114A up to the upper surface 138 of the cumulative laminate material 116 on the die side 132. In other words, the top first plating material 144 has a top surface 145 that is substantially coplanar with the upper surface 138 of the cumulative laminate material 116 on the die side 132.

[0050] Still referencing Figure 2CThe process has also been completed to form a second top plating material 146 onto the first top plating material 144. The second top plating material 146 may be electronic-grade gold (Au). The second top plating material 146 may be electronic-grade silver (Ag). The second top plating material 146 may be an electronic-grade gold-silver alloy. The second top plating material 146 is formed onto the first top plating material 144 such that the second top plating material 146 has a bump height 148 above the prepreg (BHP) portion of the accumulated laminate material 116, wherein the bump height 148 extends above the upper surface 138 of the accumulated laminate material 116, and the bump height 148 is in the range of about 0.5 μm to about 1.3 μm. Therefore, the second top plating material 146 is higher than the bonding finger pad 114A, resulting in excellent wire bonding pin pull strength. Furthermore, the lower and less useful wire-joint pin values ​​are eliminated by extending the bump height 148 above the upper surface 138. In an embodiment, electroless plating is performed without external electric attraction to form at least one of the top first plating material 144 and the top second plating material 146. When the top second plating material 146 may have a bump height 148 measured above the upper surface 138, the embedded engagement finger pad 114A has a vertical (Z-direction) thickness 147 in the range of about 8 μm to about 16 μm. The ratio of the BHP height 148 to the engagement finger height 147 may have a relative height ratio in the range of about 0.03:1 to about 0.08:1. The bump height 148 is vertically above the upper surface 138 of the accumulated laminate material 116.

[0051] refer to Figure 2D The process to remove the third shielding material 140 has been completed. Figure 2C ), so that the first plating material 144 and the second plating material 146 on the top are coated with a coating material on the top. Figure 2C The approximate intrusion distance 142 achieved during deposition by the third shielding material 140 may now be referred to as the top plating material back-off distance 142, wherein the top plating material back-off distance 142 is similarly measured from the lateral boundary of the bonding finger pad 114A to at least the lateral boundary of the top second plating material 146. The top plating material back-off distance 142 may range from about 1 μm to about 4 μm. The top second plating material 146 is laterally (in the X direction) backed from the corner formed at the upper surface 138 in the cumulative laminate material 116 by a distance ranging from about 1 μm to about 4 μm.

[0052] refer to Figure 2E The process has been completed to form a top solder resist 150 and a patterned bottom solder resist 152. Processing can be performed to use the same material for both the top solder resist 150 and the bottom solder resist 152. The top solder resist 150 has been further processed by patterning to form a solder resist lateral backlash 154 (approximately...). Figure 2E The first top joint finger joint pad 114A1 on the left and approximately in Figure 2E (The following description refers to the subsequent top bonding pad 114A2 on the right side of the center), wherein the solder mask lateral retraction distance 154 may be greater than the top plating material retraction distance 142. When the top trace 110A can only be connected on the die side, the top solder mask material 150 may cover and protect the top trace 110A.

[0053] like Figure 2E As shown, the wire bonding sections 170 of a plurality of bonding pads 114A have an open field, wherein there is no top solder mask 150 within the wire bonding section 170. In other words, the bonding pads 114A having a top first plating material 144 and a top second plating material 146 within the bonding line section 170 have a solder mask 150 structure only at the outermost periphery of the wire bonding section 170. Therefore, the attachment bonding line 166 (e.g., Figure 3 Furthermore, it does not bridge the bonding line material between adjacent bonding pads 114A at the top second plating material 146. In an embodiment, the solder mask backing distance 154 is in the range of about 4 μm to about 10 μm.

[0054] Still referencing Figure 2E The main portions of the bonding finger pad 114A and the top first coating material 144 are substantially below the upper surface 138 of the organic material of the cumulative laminate 116. Although the top second coating material 146 extends above the prepreg material of the cumulative laminate 116, the main portions of the bonding finger pad 114A, the top first coating material 144, and the top second coating material 146 are generally substantially below the upper surface 138 of the organic material of the cumulative laminate 116.

[0055] Continue to refer to Figure 2E The bottom solder mask 152 is also formed to expose the bottom array bonding pads 126 and bottom via pads 130 to achieve useful array coupling to the main printed circuit board (not shown) (e.g., to the motherboard), wherein electrical bumps (not shown) couple the main printed circuit board (not shown) to the embedded trace substrate assembly 200 at the bottom array bonding pads 126 and bottom via pads 130. The lateral (X-direction) spacing between two adjacent bottom array bonding pads 126 may range from about 300 μm to about 400 μm. When the bottom trace 128 can only perform board-side in-circuit connections, the bottom solder mask 152 may cover and protect the bottom trace 128.

[0056] refer to Figure 2FThe embedded trace substrate assembly 200 has been further processed to form a bottom first plating material 156 onto a plurality of bottom array bonding pads 126 and bottom via pads 130 (illustrating one case). In an embodiment, the bottom first plating material 156 is a nickel-containing material, such as electronic-grade nickel. The bottom first plating material 156 may fill the bottom array bonding pads 126 and the bottom via pads 130 to vertically (Z-direction) fill at least some areas laterally adjacent to the bottom solder mask 152.

[0057] Still referencing Figure 2F The process has been completed to form a second bottom plating material 158 onto the first bottom plating material 156. The second bottom plating material 158 can be electronic-grade gold (Au). The second bottom plating material 158 can be electronic-grade silver (Ag). The second bottom plating material 158 can be an electronic-grade gold-silver alloy. The second bottom plating material 158 is formed onto the first bottom plating material 156 such that the second bottom plating material 158 is located at or below the vertical limit of the bottom solder mask 152 at the board side 134 (positive Z direction). When... Figure 2F When the process is completed as described in the description, the embedded trace substrate assembly 200 may be referred to as the embedded trace microelectronic device packaging substrate assembly 200.

[0058] Figure 2Fi From Figure 2F An enlarged illustration of the obtained segment 2Fi. Figure 2F Following the treatment described herein, an organic surface protectant (OSP) material 160 is formed on the laterally exposed portions of the bonding finger pad 114A, and on the laterally exposed portions of the top first plating material 144 and the top second plating material 146. The OSP material 160 may be a flux-type protective material that protects the exposed metal material at least until, for example, wire bonding to the top second plating material 146. The use of the OSP material 160 promotes protective maintenance of each of the top plating material retraction distance 142 and the solder resist lateral retraction distance 154, which would otherwise expose conductive material during the treatment.

[0059] The bonding pad 114A may have a first width 241, which is partially defined as recessed (in the X direction) from and below the exposed upper surface 138 of the accumulated laminate 116 (in the Z direction). The top second metal material 146 has a second width 243, which is partially defined by the difference between the first width 241 and twice the recess distance 142 of the top plating material. The second width 243 is smaller than the first width 241, and the second width 243 can be measured substantially centered on the first width 241 within the processing parameters for forming the top second plating material 246, within the processing registration parameters.

[0060] Figure 2G It is an embedded trace substrate assembly 201 (e.g.) Figure 2F An enlarged illustration of the embedded trace substrate assembly 200 depicted in the figure, wherein the bonding finger pad 114A is exposed by the adjacent presence of the top solder mask 150. Unlike Figure 2F (and Figure 3 The open-line bonding section 170 described herein, with bonding pads 114A positioned on both sides (in the illustrated X direction and also the Y direction) at die side 132, wherein the top solder mask 150 is adjacent on both sides when viewed in, for example, an XZ cross section. The illustrated bonding pads 114A of the embedded trace substrate assembly 201 may have a first width 241, which is partially defined as recessed (in the X direction) from and below the exposed upper surface 138 of the accumulated laminate 116 (in the Z direction). The top second metal material 146 has a second width 243, which is partially defined by the difference between the first width 241 and twice the lateral recess distance 142 of the top plating material. The second width 243 is smaller than the first width 241. The third width 255 portion is defined by the second width 243 plus twice the sum of the solder resist retraction distance 154 generated by the top solder resist material 150, which is adjacent to and retracts from each of the engagement finger pad 114A, the top first plating material 144, and the top second plating material 146. The third width 255 is greater than the second width 243, and the second width 243 can be measured substantially centered on the third width 255 within the processing registration parameters that form the solder resist lateral retraction distance 154 around the top second plating material 246.

[0061] Figure 3 It is possible from Figure 2FThe image shows a simplified longitudinal cross-sectional view of the embedded trace substrate assembly 300, which is derived from and extends from the embedded trace substrate assembly 200, after wire bonding is completed according to several embodiments. The embedded trace substrate assembly 300 may be referred to as a microelectronic device packaging substrate assembly 300. A bonding wire 162 is attached over a bonding finger pad 114A, wherein the bonding wire 162 includes a bonding finger attachment portion 164 that physically and metallurgically contacts the top second plating material 146. The bonding wire may be a metallic material, such as a lead-based solder material. The bonding wire may be a metallic material, such as a silver-based solder material. The bonding wire may be a metallic material, such as Au wire, Ag wire, Au-Ag combination, Cu, Cu-Pd, and any alloy or combination of materials of wire bonding materials. The bonding wire 162 also has an elongated wire portion 166 exposed from the bonding finger attachment portion 164. In an embodiment, the metallurgical bond between the top second plating material 146 and the bonding finger attachment portion 164 allows for a useful wire bond pin value, such as a minimum of about 1.8 gf, which is the mechanical tensile strength (also referred to as the wire bond pin value), prior to a wire bond failure in which the bonding line 162 is otherwise pulled away from the top second plating material 146. The bonding finger attachment portion 164 of the bonding line 162 may have a lateral width (X direction) less than or equal to the lateral width (X direction) of the top second plating material 146. Furthermore, in an embodiment, the bonding finger attachment portion 164 of the bonding line 162 may have a lateral width (X direction) that does not extend to any portion of the accumulated laminate 116 that touches the exposed upper surface 138 containing the accumulated laminate 116. Thus, the wire spacing (L / S) distance 168, measured between the centers of adjacent top wire bond finger pads 114A, is maintained to resist wire bond short circuits that could otherwise occur due to metallurgical bridging between two adjacent bonding lines 162. The L / S distance 168 may range from about 10 μm to about 60 μm. In some embodiments, the L / S distance 168 may range from about 10 μm to about 60 μm. In some embodiments, the L / S distance 168 may range from about 10 μm to about 50 μm. In some embodiments, the L / S distance 168 may range from about 10 μm to about 40 μm. In some embodiments, the L / S distance 168 may range from about 10 μm to about 30 μm. In some embodiments, the L / S distance 168 may range from about 10 μm to about 20 μm. In some embodiments, the L / S distance is in the range from about 30 μm to about 50 μm. The bonding finger attachment portion 164 of the bonding line 162 has a lateral (X-direction) width that is at least 80% smaller than the line spacing 168 between adjacent bonding lines 162. The line spacing 368 between adjacent bottom array bonding pads 126 (including bottom pass pads 130) can be in the range of about 400 μm to about 800 μm.

[0062] Still referencing Figure 3 The wire bonding metallurgy between the bonding line 162 and the top second plating material 146 promotes a balance between adequate wetting during wire bonding to achieve a useful wire bonding pin value and a useful lateral limitation range of the bonding finger attachment portion 164 of the bonding line 162 so that the bonding finger attachment portion 164 of the bonding line 162 does not contact any of the accumulated laminate material 116 and does not bridge to adjacent bonding lines 162. The bonding line 162 can be extended from the embedded trace substrate assembly 300 to a portion of the top solder mask material 150 seated above the accumulated laminate material 116 to a microelectronic device (e.g., a wire-bonded DRAM device). Figure 4 The wire-bonded microelectronic memory device 476) is attached to an electronic device (e.g., a wire-bonded memory device), and the DRAM device (e.g., Figure 4 The wire-bonded microelectronic memory device 476) uses bonding wire 162 for wire bonding because bonding wire 162 is electrically and metallurgically bonded to the top second plating material 146, and none of the bonding finger attachment portions 164 contact the exposed upper surface 138, the top solder mask material 150, or adjacent bonding wire 162.

[0063] Figure 4 This is a simplified perspective view of a microelectronic device assembly 400 coupled to an embedded trace substrate assembly 401 according to several embodiments. Several microelectronic devices (including a first wire-bonded microelectronic memory device 476 and a subsequent wire-bonded microelectronic memory device 478) are wire-bonded to several of the presence of bonding pads 114A and 414A. The first bonding pad 114A may be arranged in a first bonding pad row 171A, and the subsequent bonding pad 414A may be arranged in a subsequent bonding pad row 171B. The listed bonding pads 114A may be similar to... Figure 3 The engagement finger pad 114A is generally positioned as described. In an embodiment, it can be positioned relative to... Figure 3 Some mating finger pads 414A were found, which are orthogonal to each other in the Y direction. Figure 3The line extends from the drawing plane in the diagram. The first top second plating material 146 and the subsequent top second plating material 446, having substantially the same structure, are coupled above the corresponding first bonding pad 114A and subsequent bonding pad 414A. A first bonding line 162 electrically couples a first wire-bonded microelectronic device 476 to the first top second plating material 146, and a subsequent bonding line 462 electrically couples a subsequent wire-bonded microelectronic memory device 478 to the subsequent top second plating material 446. The corresponding first wire-bonded microelectronic memory device 476 and subsequent wire-bonded microelectronic memory device 478 can be DRAM memory devices: wire-bonded first microelectronic memory device 476 and wire-bonded subsequent microelectronic memory device 478. More wire-bonded microelectronic devices than the illustrated corresponding first wire-bonded microelectronic memory devices 476 and subsequent wire-bonded microelectronic memory devices 478 can be stacked. In one embodiment, four (4) wire-bonded microelectronic devices are stacked, including a first wire-bonded microelectronic memory device 476 on solder mask 150 and two (2) wire-bonded microelectronic devices between the first wire-bonded microelectronic memory device 476 and subsequent wire-bonded microelectronic memory devices 478. Each of the four (4) stacked wire-bonded microelectronic devices may be coupled to a bonding pad, such as bonding pad 114A, in a corresponding first to fourth row. In another embodiment, eight (8) stacked wire-bonded microelectronic devices are stacked, including a first wire-bonded microelectronic memory device 476 on solder mask 150 and six (6) wire-bonded microelectronic memory devices between the first wire-bonded microelectronic memory device 476 and subsequent wire-bonded microelectronic memory devices 478. Each of the eight (8) stacked wire-bonded microelectronic devices may be coupled to a bonding pad, such as bonding pad 114A, in a corresponding first to fourth row.

[0064] Still referencing Figure 4Within the electrical bump array section 172 of the microelectronic device assembly 400, a stack of flip-chip microelectronic devices 480 and 482 is assembled over solder resist 150. In an embodiment, a single flip-chip microelectronic device 480 occupies the coverage area of ​​the electrical bump array section 172. The stack of flip-chip devices may include a first flip-chip microelectronic device 480 and subsequent flip-chip microelectronic devices 482. Electrical bump array bonding pads 444A may be structurally similar to bonding finger pads 114A and may be substantially linearly aligned with the first bonding finger pad row 171A and subsequent bonding finger pad rows 171B. Electrical bump array bonding pads 444A are illustrated with dashed lines because they are within the cumulative laminate 116 and are blocked by at least the first flip-chip microelectronic device 480. Electrical bump array bonding pad 444A may also be exposed at the exposed upper surface 138 within the electrical bump array section 172, similar to the first and subsequent bonding pads 114A and 414A within the wire bonding section 170. In this embodiment, the electrical bump array bonding pad 444A is not separated by the presence of solder resist 158 ​​(e.g., Figure 2Fi In this embodiment, the electrical bump array bonding pad 414A is separated by the presence of solder resist 158 ​​(e.g., Figure 2G (Still referencing) Figure 4 At least two flip-chip microelectronic devices 480 and 482 are stacked one on top of the solder resist 150, and the first flip-chip microelectronic device 480 is coupled to an electrical bump bonding pad 444A via an exposed upper surface 138 in an electrical bump array section 172 of an embedded trace substrate assembly 401. The illustrated electrical bump array bonding pad 444A is connected via electrical bumps (e.g., ...). Figure 5 Electrical bumps 174) are coupled to the first flip-chip microelectronic device 480, and a subsequent flip-chip microelectronic device 482 is coupled to the first flip-chip microelectronic device 480 via at least one through-silicon via (TSV) 484 within the first flip-chip microelectronic device 480. In one embodiment, four (4) flip-chip microelectronic devices are stacked, including the first flip-chip microelectronic device 480 above the electrical bump array bonding pad 444A and two (2) flip-chip microelectronic devices between the first flip-chip microelectronic device 480 and the subsequent flip-chip microelectronic device 482. In another embodiment, eight (8) stacked flip-chip microelectronic devices are stacked, including the first flip-chip microelectronic device 480 above the electrical bump array bonding pad 444A and six (6) flip-chip microelectronic devices between the first flip-chip microelectronic device 480 and the subsequent flip-chip microelectronic device 482.

[0065] Figure 5 This is a simplified longitudinal cross-sectional view of a portion of an embedded trace substrate assembly 500 according to an embodiment of the present disclosure. The embedded trace substrate assembly 500 may have, for example, features for wire bonding microelectronic devices (e.g., Figure 4 The wire bonding section 170 and the microelectronic device for flip-chip assembly (e.g.) Figure 4 The electrically bump array segment 172 of the embedded trace substrate assembly 500 may be referred to as a microelectronic device package embedded trace substrate (ETS) assembly 500. The electrically bump array segment 172 of the embedded trace substrate assembly 500 can be used to mount microelectronic devices, such as those for processor devices (e.g., processors). Figure 4 The first flip-chip microelectronic device 480, such as a central processing unit, graphics processing unit, radio frequency transceiver device, or other useful device electrically and metallurgically bonded to the top second plating material 446 within the electrical bump array segment 172. In an embodiment, the wire bonding segment 170 and the electrical bump array segment 172 are not adjacent to each other, as illustrated by discontinuity 173. Similar to Figure 3 and 4 The bonding wire 162 described herein is attached above the bonding finger pad 114A within the wire bonding section 170, wherein the bonding wire 162 includes a bonding finger attachment portion 164 that physically and metallurgically contacts the top second plating material 146. The bonding wire 162 also has an elongated wire portion 166 protruding from the bonding finger attachment portion 164. In an embodiment, the metallurgical bond between the top second plating material 146 and the bonding finger attachment portion 164 allows for a useful wire bonding pin value, which is the mechanical tensile strength, before a wire bonding failure occurs where the bonding wire 162 is pulled out of the top second plating material 146. Similar to the bonding wire 162, the electrical bump 174 is physically and metallurgically bonded to a top second plating material 546 that may also be formed as the top second plating material 146. In an embodiment, the electrical bump 174 is first bonded to a flip chip device (e.g., Figure 4 The first flip-chip microelectronic device 480 has an array of electrical bumps, and then the electrical bumps 174 are thermally bonded (TCB) to a top second plating material 546 within the electrical bump array segment 172. The electrical bumps 174 also enable physical and metallurgical bonding of the top second plating material 546 with useful line spacing and without any of the electrical bumps 174 contacting the top solder mask 150. In an embodiment, the solder mask 150 is not present within the inner lateral boundary of the electrical bump array segment 172, similar to how the solder mask 150 is not present within the inner lateral boundary of the wire bonding segment 170. In an embodiment, the first flip-chip microelectronic device (e.g., Figure 4 The first flip-chip microelectronic device 480 is mounted at the electrical bump 174 within the electrical bump array segment 172, and subsequent flip-chip microelectronic devices (e.g., Figure 4 The subsequent flip-chip microelectronic device 482 is mounted on top of the first flip-chip device, and the electrical and signal communication between the first microelectronic device 480 and the subsequent microelectronic device 482 is through a through-silicon via (TSV, e.g.) Figure 4TSV 484).

[0066] The embedded trace substrate assembly of this disclosure (e.g., the embedded trace substrate assembly 200 of this disclosure) Figure 2F ), 201( Figure 2G ), 300 Figure 3 ), 401 Figure 4 ) and 500 ( Figure 5 This may be included in embodiments of the electronic systems disclosed herein. For example, Figure 6 This is a block diagram of an electronic system 600 according to an embodiment of the present disclosure. This electronic system 600 may include, for example... Figure 4 The microelectronic device assembly 400 described herein may be wholly or partially included in the electronic system 600 as described and illustrated. The electronic system 600 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet computer (e.g., for example). or Tablet computers, e-book readers, or navigation devices, etc., in which embedded trace substrate assemblies 200 can be used. Figure 2F ), 201( Figure 2G ), 300 Figure 3 ), 401 Figure 4 ) and 500 ( Figure 5 An embodiment of the electronic system 600 is described. The electronic system 600 includes at least one memory device 620. The memory device 620 may include, for example, wire-bonded to the embedded trace substrate assembly 200 of this disclosure. Figure 2F ), 201( Figure 2G ), 300 Figure 3 ), 401 Figure 4 ) and 500 ( Figure 5 One or more microelectronic devices according to embodiments of the present disclosure. Electronic system 600 may further include at least one electronic signal processor device 610 (generally referred to as a “microprocessor”) as part of an integrated circuit. Electronic signal processor device 610 may include, for example, wire-bonded or flip-chip bonded to the embedded trace substrate assembly 200 of the present disclosure. Figure 2F ), 201( Figure 2G ), 300 Figure 3 ), 401 Figure 4 ) and 500 ( Figure 5 One or more of the various microelectronic devices in the embodiments of ) . Although Figure 6The memory device 620 and the electronic signal processor device 610 are depicted as two (2) separate devices, but in additional embodiments, a single (e.g., only one) memory / processor device having the functionality of both the memory device 620 and the electronic signal processor device 610 is included in the electronic system 600. In such embodiments, the memory / processor device may include, for example, wire bonding or flip-chip bonding to the embedded trace substrate assembly 200 of this disclosure (…). Figure 2F ), 201( Figure 2G ), 300 Figure 3 ), 401 Figure 4 ) and 500 ( Figure 5 The processor device 610 and memory device 620 may be part of a central processing unit, wherein the memory device 620 includes a wire-bonded memory device, which includes on-die DRAM cache memory. The processor device 610 and memory device 620 may be part of a die-deposited integrated circuit assembly 610 and 620, which may also be referred to as a die-deposited integrated circuit assembly, including at least one of the processor device 610 and memory device 620. In a die-deposited integrated circuit assembly of more than two devices, more than one of these devices is included, wherein one or more of the plurality of microelectronic devices are wire-bonded or flip-chip bonded to the embedded trace substrate assembly 200 of this disclosure. Figure 2F ), 201( Figure 2G ), 300 Figure 3 ), 401 Figure 4 ) and 500 ( Figure 5 Examples of the embodiments. Furthermore, the disassembled die assemblies 610 and 620 can be assembled using, for example, bridging materials in an embedded multi-interconnect bridge (EMIB), which may include at least one TSV interconnect in one of the dies coupled to the EMIB.

[0067] The electronic system 600 may further include one or more input devices 630 for users to input information into the electronic system 600, such as (for example) a mouse or other pointing device, a keyboard, a touchpad, buttons, or a control panel. The electronic system 600 may further include one or more output devices 640 for outputting information (e.g., visual or audio output) to the user, such as (for example) a monitor, display, printer, audio output jack, and / or speaker. In some embodiments, the input devices 630 and output devices 640 may constitute a single touchscreen device that can be used both to input information into the electronic system 600 and to output visual information to the user. The input devices 630 and output devices 640 may be electrically connected to one or more of the memory device 620 and the electronic signal processor device 610.

[0068] Examples of processing embedded trace substrate assemblies can be found by referring to Figure 7 and 8 Please provide an explanation. Figure 7 yes Figures 1A to 2G A simplified process flow diagram of the method embodiment illustrating the structure and apparatus described herein. (Source: [Original Source Name]) Figures 1A to 2G Reference figures are available in the following description of method embodiments. A method for forming an embedded trace substrate assembly is disclosed. At 710, the method includes forming a top trace 110, a via contact 112, and a top bonding pad 114 on a conductive temporary layer 104 above a carrier wafer 102. At 712, the method includes forming a via 122 through an accumulated laminate material 116, wherein the accumulated laminate material 116 covers the top trace 110 and the top bonding pad 114. At 714, the method includes forming a bottom array bonding pad 126, a bottom trace 128, and a bottom via pad 130 on a metal seed material 118 at a die side 132 of the accumulated laminate material 116, wherein forming the bottom via pad 130 further includes forming the bottom via pad 130 on the via contact 112. At 716, the method includes recessing the top trace, top access contact 112, and top engagement finger pad 114 below the upper surface 138 of the accumulated laminate material 116 at the die side 132. At 718, the method includes forming a top first plating material 144 on the top engagement finger pad 114A and further includes forming a top second plating material 146 on the top first plating material 144, wherein the top engagement finger pad 114A has a first lateral dimension, wherein each of the top first plating material 144 and the top second plating material 146 has a second lateral dimension smaller than the first lateral dimension, and wherein the top second plating material 146 extends above the upper surface 138 of the accumulated laminate material 116.

[0069] At 720, the method further includes patterning a top solder resist 150 on the die side 132 to define a line bonding section 170, wherein the top solder resist 150 is laterally recessed from at least one top second plating material 146, and wherein the patterned top solder resist 150 also covers the top trace 110. At 722, the method further includes: forming a bottom first plating material 156 on a bottom array bonding pad 126 and a bottom passage pad 130 at a board side 134 of the accumulated laminate material 116, wherein the board side 134 is opposite to the die side 132; and forming a bottom second plating material 158 on the bottom first plating material 156 at the board side 134, wherein the bottom array bonding pad 126 and the bottom passage pad 130 are separated by a patterned bottom solder resist 152, and wherein the patterned bottom solder resist 152 covers the bottom trace 128.

[0070] Figure 8 It is the attachment joint line 162 (e.g.) Figure 2Fi ,2G A simplified process flow diagram of method 3). At 810, the method includes attaching bonding line 162 over top bonding finger pad 114A and onto top second plating material 146, wherein top second plating material 146 extends over upper surface 138 of cumulative laminate material 116, and wherein top second plating material 146 has a lateral width smaller than top bonding finger pad 114A. At 808, the method may begin by attaching bonding line 162 when first removing organic surface protectant (OSP) material 160 or during in-line bonding when using OSP material 160 as a protective material.

[0071] The disclosed embodiments illustrate miniaturization techniques for substrate assemblies, wherein the problem of sufficiently reducing the bond line spacing (L / S) without bridging adjacent bond lines is addressed. Furthermore, with miniaturization of the substrate assembly, the problem of useful wire bond pin values ​​is solved, wherein useful mechanical tensile strength prior to wire bond failure is disclosed.

[0072] Therefore, an embedded trace substrate assembly is disclosed, comprising: an accumulated laminate material including: a die side having an upper surface; and a board side opposite to the die side; a solder resist material on the upper surface of the die side of the accumulated laminate material; a bonding pad exposed at the die side through the accumulated laminate material and having a first lateral width; a top first plating material on the bonding pad, the top first plating material including a top surface substantially coplanar with the upper surface of the accumulated laminate material; a top second plating material on the top first plating material and having a second lateral width less than the first lateral width, the top first plating material including a top surface covering the upper surface of the die side of the accumulated laminate material; and a wire bonding section including a row of the bonding pads, the top first plating material, and the top second plating material, the solder resist material extending from a portion of the upper surface of the die side of the accumulated laminate material and receding from the bonding pads.

[0073] Therefore, a microelectronic device assembly is also disclosed, comprising: a microelectronic device wire-bonded to an embedded trace substrate assembly, the embedded trace substrate assembly comprising: an accumulated laminate material including: a board side; and a die side opposite to the board side and including an upper surface; a solder resist material on the upper surface of the die side; a bonding pad exposed through the accumulated laminate material on the die side, the bonding pad having a first lateral width; and a top first plating material on the bonding pad and including the die side of the accumulated laminate material. The top surface of the wafer side is substantially coplanar; a second top plating material is on the first top plating material and has a second lateral width less than the first lateral width, the first top plating material being contained above the top surface of the wafer side of the accumulated laminate; a wire bonding section including the row of bonding pads, the first top plating material and the second top plating material, wherein the solder resist material is only adjacent to the wire bonding section peripherally; and a bonding line that couples the microelectronic device to the second top plating material.

[0074] Therefore, a process for forming an embedded trace substrate assembly is also disclosed, comprising: patterning a masking material on an upper surface of an accumulated laminate and on a bonding pad to form a patterned masking material overlapping a portion of the bonding pad, the bonding pad having a first lateral width; forming a first top plating material on the bonding pad to a height of the upper surface of the accumulated laminate; forming a second top plating material on the first top plating material, the second top plating material being at least partially above the upper surface of the accumulated laminate and having a second lateral width smaller than the first lateral width of the bonding pad; removing the patterned masking material; and forming a top solder resist on the upper surface to define a wire bonding segment, the top solder resist being adjacent only to the periphery of the wire bonding segment.

[0075] Therefore, an electronic system is also disclosed, comprising: an input device; an output device; a processor device operatively coupled to the input device and the output device; a memory device operatively coupled to the processor device; and an embedded trace substrate assembly comprising: an accumulated laminate material including: a die side having an upper surface; and a board side opposite to the die side; a solder resist material on the upper surface of the die side of the accumulated laminate material; bonding pads exposed through the accumulated laminate material at the die side and each having a first lateral width; and a top first plating material on the bonding pads and The material comprises: a top surface substantially coplanar with the upper surface of the die side of the accumulated laminate; a top second plating material on the top first plating material and having a second lateral width less than the first lateral width of each of the bonding fingers, the top first plating material having a top surface vertically covering the upper surface of the die side of the accumulated laminate; and a line bonding section comprising a row of bonding fingers, the top first plating material and the top second plating material, the solder resist extending from a portion of the upper surface and receding from the bonding fingers, and the solder resist only peripherally adjacent to the line bonding section.

[0076] Additional non-limiting example embodiments of this disclosure are described below.

[0077] Example 1: An embedded trace substrate assembly comprising: an accumulated laminate material including: a die side having an upper surface; and a board side opposite to the die side; a solder resist material on the upper surface of the die side of the accumulated laminate material; a bonding pad exposed at the die side by the accumulated laminate material and having a first lateral width; a top first plating material on the bonding pad, the top first plating material including a top surface substantially coplanar with the upper surface of the accumulated laminate material; a top second plating material on the top first plating material and having a second lateral width less than the first lateral width, the top first plating material including a top surface covering the upper surface of the die side of the accumulated laminate material; and a wire bonding section including a row of the bonding pads, the top first plating material, and the top second plating material, the solder resist material extending from a portion of the upper surface of the die side of the accumulated laminate material and receding from the bonding pads.

[0078] Example 2: The embedded trace substrate assembly according to Example 1, wherein the solder resist material is only adjacent to the wire bonding section on the periphery.

[0079] Example 3: An embedded trace substrate assembly according to one of Examples 1 and 2, wherein: the top first plating material comprises nickel; and the top second plating material comprises gold.

[0080] Example 4: The embedded trace substrate assembly according to Example 3, wherein a portion of the top second plating material covering the upper surface of the accumulated laminate material has a height ranging from about 0.5 μm to about 1.33 μm.

[0081] Example 5: The embedded trace substrate assembly according to Example 3, wherein the top second plating material and the bonding finger pad have a relative height ratio in the range of about 0.03:1 to about 0.08:1.

[0082] Example 6: An embedded trace substrate assembly according to any one of Examples 1 to 5, wherein the bonding pads are spaced apart by a line spacing distance ranging from about 10 μm to about 50 μm.

[0083] Example 7: An embedded trace substrate assembly according to any one of Examples 1 to 5, wherein the bonding fingers are spaced apart by a line spacing distance and further includes a bonding line that contacts the top second plating material, the bonding line including: a bonding finger attachment portion that physically and metallurgically contacts the top second plating material, the bonding finger attachment portion having a lateral width smaller than the line spacing distance.

[0084] Example 8: An embedded trace substrate assembly according to any one of Examples 1 to 5, wherein the bonding fingers are spaced apart by a line spacing distance and further includes a bonding line that contacts the top second plating material, the bonding line including: a bonding finger attachment portion that contacts the top second plating material, the bonding finger attachment portion having a lateral width less than or equal to the second lateral width.

[0085] Example 9: An embedded trace substrate assembly according to any one of Examples 1 to 8, further comprising: a trace on the die side and at least partially encapsulated by the solder resist; a top pass contact on the die side; and a through-substrate filling pass comprising: a bottom pass pad portion on the board side; and a through-substrate portion contacting the top pass contact.

[0086] Example 10: A microelectronic device assembly comprising: a microelectronic device wire-bonded to an embedded trace substrate assembly, the embedded trace substrate assembly comprising: an accumulated laminate material including: a board side; and a die side opposite to the board side and including an upper surface; a solder resist material on the upper surface of the die side; a bonding pad exposed through the accumulated laminate material on the die side, the bonding pad having a first lateral width; and a top first plating material on the bonding pad and including the die side of the accumulated laminate material. The top surface of the wafer side is substantially coplanar; a second top plating material is on the first top plating material and has a second lateral width less than the first lateral width, the first top plating material being contained above the top surface of the wafer side of the accumulated laminate; a wire bonding section including the row of bonding pads, the first top plating material and the second top plating material, wherein the solder resist material is only adjacent to the wire bonding section peripherally; and a bonding line that couples the microelectronic device to the second top plating material.

[0087] Example 11: A microelectronic device assembly according to Example 10, wherein: the top first plating material comprises a nickel material; the top second plating material comprises a gold material, and a portion of the top second plating material above the upper surface of the die side of the accumulated laminate has a height in the range of about 1 μm to about 3 μm; and the bonding pads are spaced apart by a line spacing distance in the range of about 10 μm to about 50 μm.

[0088] Example 12: The microelectronic device assembly according to Example 11, wherein the top second plating material and the bonding finger pad have a relative height ratio in the range of about 0.03:1 to about 0.08:1.

[0089] Example 13: The microelectronic device assembly according to Example 11, wherein the microelectronic device includes a first wire-bonded memory device wire-bonded to a first bonding pad row, and further includes a subsequent wire-bonded microelectronic device that is above the first wire-bonded memory device and wire-bonded to a subsequent bonding pad row positioned substantially parallel to the first bonding pad row.

[0090] Example 14: The microelectronic device assembly according to Example 10 further includes: an electrical bump section on the embedded trace substrate assembly and including a bonding finger pad exposed through the accumulated laminate material at the die side, the bonding finger pad having a first lateral width; a top first plating material on the bonding finger pad and including a top surface substantially coplanar with the upper surface of the die side of the accumulated laminate material; and a top second plating material on the top first plating material and having a second lateral width less than the first lateral width, the top first plating material having a top surface above the upper surface of the die side of the accumulated laminate material.

[0091] Example 15: A process for forming an embedded trace substrate assembly, comprising: patterning a masking material on an upper surface of an accumulated laminate and on a bonding pad to form a patterned masking material overlapping a portion of the bonding pad, the bonding pad having a first lateral width; forming a first top plating material on the bonding pad to a height of the upper surface of the accumulated laminate; forming a second top plating material on the first top plating material, the second top plating material being at least partially above the upper surface of the accumulated laminate and having a second lateral width smaller than the first lateral width of the bonding pad; removing the patterned masking material; and forming a top solder resist on the upper surface to define a wire bonding segment, the top solder resist being adjacent only to the periphery of the wire bonding segment.

[0092] Example 16: The process according to Example 15 further includes bonding microelectronic device lines to the bonding finger pad.

[0093] Example 17: An electronic system comprising: an input device; an output device; a processor device operatively coupled to the input device and the output device; a memory device operatively coupled to the processor device; and an embedded trace substrate assembly comprising: an accumulated laminate material including: a die side having an upper surface; and a board side opposite to the die side; a solder resist material on the upper surface of the die side of the accumulated laminate material; bonding pads exposed at the die side through the accumulated laminate material and each having a first lateral width; and a top first plating material on the bonding pads and having The material comprises: a top surface substantially coplanar with the upper surface of the die side of the accumulated laminate; a top second plating material on the top first plating material and having a second lateral width less than the first lateral width of each of the bonding fingers, the top first plating material having a top surface vertically covering the upper surface of the die side of the accumulated laminate; and a line bonding section comprising a row of bonding fingers, the top first plating material and the top second plating material, the solder resist extending from a portion of the upper surface and receding from the bonding fingers, and the solder resist only adjacent to the line bonding section at its periphery.

[0094] Example 18: The electronic system according to Example 17, wherein: the memory device is wire-bonded to the embedded trace substrate assembly within the wire bonding section; and the processor device is flip-chip coupled to the embedded trace substrate assembly within the electrical bump section.

[0095] Example 19: According to the electronic system of Example 18, the memory device includes a first wire-bonded memory device wire-bonded to a first row of bonding pads, a top first plating material, and a top second plating material, and further includes a second wire-bonded memory device above the first wire-bonded memory device, the second wire-bonded memory device being wire-bonded to a subsequent row of bonding pads, a top first plating material, and a top second plating material.

[0096] Example 20: The electronic system according to Example 18, wherein the memory device includes a first wire-bonded memory device wire-bonded to a first row bonding pad, a top first plating material, and a top second plating material, and further includes: a second wire-bonded memory device above the first wire-bonded memory device, the second wire-bonded memory device being wire-bonded to a subsequent row bonding pad, a top first plating material, and a top second plating material; and an additional processor device above the processor device and flip-chip coupled to the processor device via a through-silicon via in the processor device.

[0097] While various modifications and alternatives are permissible with respect to this disclosure, specific embodiments have been shown by way of example in the drawings and described in detail herein. However, this disclosure is not limited to the specific forms disclosed. Rather, this disclosure is intended to cover all modifications, equivalents, and alternatives falling within the scope of the appended claims and their legal equivalents.

Claims

1. An embedded trace substrate assembly, comprising: Accumulated laminate materials, including: The bare wafer side includes the upper surface; and The plate side, which is opposite to the bare sheet side; Solder resist material on the upper surface of the bare sheet side of the cumulative laminate; A bonding pad, which is exposed by the cumulative laminate material at the bare sheet side and has a first lateral width; A top first plating material on the engagement finger pad, the top first plating material including a top surface substantially coplanar with the upper surface of the cumulative laminate material; A second top plating material, which is on top of the first top plating material and has a second lateral width smaller than the first lateral width, the second top plating material being substantially located at the center of the first lateral width and receding from the lateral boundary of the engagement finger pad, the first top plating material comprising a top surface covering the upper surface of the bare side of the accumulated laminate material; and The bonding section includes the row of bonding finger pads, the top first plating material and the top second plating material, wherein the solder resist extends from a portion of the upper surface of the die side of the accumulated laminate and retracts from the bonding finger pads.

2. The embedded trace substrate assembly of claim 1, wherein the solder resist material is only present in the periphery adjacent to the line bonding section.

3. The embedded trace substrate assembly according to claim 1, wherein: The first plating material on the top includes nickel; and The second plating material on the top includes gold.

4. The embedded trace substrate assembly of claim 3, wherein a portion of the top second plating material covering the upper surface of the accumulated laminate has a height ranging from about 0.5 μm to about 1.33 μm.

5. The embedded trace substrate assembly of claim 3, wherein the top second plating material and the bonding finger pad have a relative height ratio in the range of about 0.03:1 to about 0.08:

1.

6. The embedded trace substrate assembly of claim 1, wherein the bonding fingers are spaced apart by a line spacing distance ranging from about 10 μm to about 50 μm.

7. The embedded trace substrate assembly of claim 1, wherein the bonding fingers are spaced apart by a line spacing, and the embedded trace substrate assembly further includes a bonding line contacting the top second plating material, the bonding line comprising: The joining finger attachment portion is in physical and metallurgical contact with the top second plating material, and the joining finger attachment portion has a lateral width smaller than the line spacing distance.

8. The embedded trace substrate assembly of claim 1, wherein the bonding fingers are spaced apart by a line spacing, and the embedded trace substrate assembly further includes a bonding line contacting the top second plating material, the bonding line comprising: The joining finger attachment portion contacts the top second plating material, and the joining finger attachment portion has a lateral width less than or equal to the second lateral width.

9. The embedded trace substrate assembly of claim 1, further comprising: The trace is encapsulated on the die side and at least partially by the solder resist material; Top access contact, located on the die side; and Substrate-filled pathways, including: The bottom passage pad portion is located on the side of the plate; and The portion that penetrates the substrate contacts the top passage contact.

10. A microelectronic device assembly comprising: A microelectronic device, wire-bonded to an embedded trace substrate assembly, the embedded trace substrate assembly comprising: Accumulated laminate materials, including: Side of the board; and The bare die side, which is opposite to the plate side and includes the upper surface; Solder resist material, on the upper surface of the bare die side; A bonding finger pad, exposed at the bare sheet side by the cumulative laminate material, the bonding finger pad having a first lateral width; A first plating material on the top, which is on the bonding finger pad and includes a top surface that is substantially coplanar with the upper surface of the bare sheet side of the accumulated laminate material; A second top plating material, which is on top of the first top plating material and has a second lateral width smaller than the first lateral width, the second top plating material being substantially located at the center of the first lateral width and receding from the lateral boundary of the engagement finger pad, the first top plating material being contained on a top surface above the upper surface of the bare side of the accumulated laminate material; and A wire bonding section, comprising the row of the bonding pads, the top first plating material, and the top second plating material, wherein the solder resist material is only peripherally adjacent to the wire bonding section; and A bonding line that couples the microelectronic device to the top second plating material.

11. The microelectronic device assembly according to claim 10, wherein: The first plating material on the top includes nickel. The top second plating material comprises gold, and a portion of the top second plating material above the upper surface of the bare side of the accumulated laminate has a height ranging from about 1 μm to about 3 μm; and The bonding finger pads are spaced apart by a line spacing ranging from about 10 μm to about 50 μm.

12. The microelectronic device assembly of claim 11, wherein the top second plating material and the bonding finger pad have a relative height ratio in the range of about 0.03:1 to about 0.08:

1.

13. The microelectronic device assembly of claim 11, wherein the microelectronic device includes a first wire-bonded memory device wire-bonded to a first bonding pad row, and the microelectronic device assembly further includes: A subsequent wire-bonded microelectronic device is located above the first wire-bonded memory device and wire-bonded to a subsequent bonding row positioned substantially parallel to the first bonding pad row.

14. The microelectronic device assembly of claim 10, further comprising: An electrical bump section, which is on the embedded trace substrate assembly and includes a bonding finger pad exposed by the accumulated laminate material at the die side, the bonding finger pad having a first lateral width; A first plating material on the top, which is on the bonding finger pad and includes a top surface that is substantially coplanar with the upper surface of the bare sheet side of the accumulated laminate material; and A second top plating material, which is on the first top plating material and has a second lateral width less than the first lateral width, the first top plating material having a top surface above the upper surface of the bare side of the accumulated laminate material.

15. An electronic system comprising: Input device; Output device; A processor device operatively coupled to the input device and the output device; A memory device operatively coupled to the processor device; and An embedded trace substrate assembly, comprising: Accumulated laminate materials, including: The bare wafer side has an upper surface; and The plate side, which is opposite to the bare sheet side; Solder resist material on the upper surface of the bare sheet side of the cumulative laminate; The bonding pads are exposed at the bare sheet side by the cumulative laminate material and each has a first lateral width; A first plating material on the top, which is on the bonding finger pad and has a top surface that is substantially coplanar with the upper surface of the bare sheet side of the cumulative laminate material; A second top plating material, which is on the first top plating material and has a second lateral width smaller than the first lateral width of each of the bonding fingers, the second top plating material being substantially located at the center of the first lateral width and receding from the lateral boundary of the bonding fingers, the first top plating material having a top surface vertically covering the upper surface of the bare side of the accumulated laminate; and The line bonding section includes the row of the bonding finger pads, the top first plating material, and the top second plating material. The solder resist material extends from a portion of the upper surface and retracts from the bonding finger pad, and The solder resist material is only applied to the periphery adjacent to the wire bonding section.

16. The electronic system according to claim 15, wherein: The memory device is wire-bonded to the embedded trace substrate assembly within the wire-bonded section; and The processor device is flip-chip coupled to the embedded trace substrate assembly within the electrical bump section.

17. The electronic system of claim 16, wherein the memory device comprises a first wire-bonded memory device wire-bonded to a first row of bonding pads, a top first plating material, and a top second plating material, the electronic system further comprising: A second wire bonding memory device is located above the first wire bonding memory device, and the second wire bonding memory device is wire bonded to a subsequent row bonding pad, a top first plating material, and a top second plating material.

18. The electronic system of claim 16, wherein the memory device comprises a first wire-bonded memory device wire-bonded to a first row of bonding pads, a top first plating material, and a top second plating material, and the electronic system further comprises: A second wire bonding memory device is located above the first wire bonding memory device, and the second wire bonding memory device is wire bonded to a subsequent row bonding pad, a top first plating material, and a top second plating material; and An additional processor device, which is flip-chip coupled to the processor device above the processor device and via a through-silicon path in the processor device.

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