Semiconductor structure and method of fabricating the same

Abstract

The embodiment of the present disclosure discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a logic chip located on the substrate and electrically connected with the substrate, a communication module located on the logic chip and electrically connected with the logic chip, and a first core particle located on the logic chip and electrically connected with the logic chip, comprising a first storage chip and a first communication chip. The first storage chip is electrically connected with the first communication chip, and the first storage chip performs wireless communication with the logic chip through the first communication chip and the communication module.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor structure and its fabrication method. Background Technology

[0002] As people's demands for electronic products become smaller and more multifunctional, packaging technology is also developing towards higher density and higher integration. For example, at least two memory chips (dies) are stacked in three dimensions along a direction perpendicular to the horizontal plane.

[0003] However, there are still many technical problems to be solved in the three-dimensional stacked packaging structure, such as the large differences in communication latency between different memory chips and the high process cost. Summary of the Invention

[0004] According to a first aspect of the present disclosure, a semiconductor structure is provided, comprising:

[0005] substrate;

[0006] A logic chip is located on the substrate and electrically connected to the substrate;

[0007] A communication module is located on the logic chip and is electrically connected to the logic chip;

[0008] The first chip, located on and electrically connected to the logic chip, includes: a first memory chip and a first communication chip; wherein the first memory chip is electrically connected to the first communication chip, and the first memory chip communicates wirelessly with the logic chip through the first communication chip and the communication module.

[0009] In some embodiments, the semiconductor structure includes:

[0010] At least two first chips are located on the logic chip and electrically connected to the logic chip respectively; wherein the distance between the first communication chip and the communication module of the first first chip is the same as the distance between the first communication chip and the communication module of the second first chip.

[0011] In some embodiments, the semiconductor structure further includes:

[0012] The second chip, located on the first chip and electrically connected to the logic chip, includes: a second memory chip and a second communication chip; wherein the second memory chip is electrically connected to the second communication chip; the second memory chip communicates wirelessly with the logic chip through the second communication chip and the communication module.

[0013] In some embodiments, the first core chip further includes:

[0014] A first molding layer covers the first memory chip and the first communication chip;

[0015] The first pathway extends through the first molding layer;

[0016] The semiconductor structure also includes:

[0017] A first dielectric layer is located between the logic chip and the first chip;

[0018] A second dielectric layer is located between the first passage and the second core particle;

[0019] A first conductive structure is located in the first dielectric layer; wherein the active surface of the first memory chip is electrically connected to the logic chip through the first conductive structure;

[0020] The second conductive structure is located in the second dielectric layer; wherein the active surface of the second memory chip is electrically connected to the logic chip through the second conductive structure, the first path, and the first conductive structure.

[0021] In some embodiments, the semiconductor structure further includes:

[0022] A first electrical connection structure is located in the first dielectric layer; wherein the first memory chip is electrically connected to the first communication chip through the first electrical connection structure.

[0023] A second electrical connection structure is located in the second dielectric layer; wherein the second memory chip is electrically connected to the second communication chip through the second electrical connection structure.

[0024] In some embodiments, the first core chip further includes: a second passage extending through the first molding layer;

[0025] The semiconductor structure also includes:

[0026] A first interconnect structure is located in the first dielectric layer; wherein the active surface of the first communication chip is electrically connected to the logic chip through the first interconnect structure;

[0027] The second interconnect structure is located in the second dielectric layer; wherein the active surface of the second communication chip is electrically connected to the logic chip through the second interconnect structure, the second path, and the first interconnect structure.

[0028] In some embodiments, the semiconductor structure further includes:

[0029] A first stress structure is located in the first dielectric layer; wherein the first stress structure is electrically insulated from the first memory chip and the first communication chip;

[0030] The second stress structure is located in the second dielectric layer; wherein the second stress structure is electrically insulated from the second memory chip and the second communication chip.

[0031] In some embodiments, the semiconductor structure further includes:

[0032] A first conductive block is located between the logic chip and the first memory chip; wherein the active surface of the first memory chip is electrically connected to the logic chip through the first conductive block;

[0033] A second conductive block is located between the logic chip and the communication module; wherein the active surface of the communication module is electrically connected to the logic chip through the second conductive block.

[0034] According to a second aspect of the present disclosure, a method for fabricating a semiconductor structure is provided, comprising:

[0035] Provide logic chips;

[0036] A communication module electrically connected to the logic chip is formed on the logic chip;

[0037] A first chip is formed on the logic chip and electrically connected to the logic chip; wherein the first chip includes a first memory chip and a first communication chip; wherein the first memory chip is electrically connected to the first communication chip, and the first memory chip communicates wirelessly with the logic chip through the first communication chip and the communication module;

[0038] After the first chip is formed, the logic chip is bonded to the substrate.

[0039] In some embodiments, forming a first die on the logic chip that is electrically bonded to the logic chip includes:

[0040] At least two of the first chips are electrically connected to the logic chip respectively; wherein the distance between the first communication chip and the communication module of the first first chip is the same as the distance between the first communication chip and the communication module of the second first chip.

[0041] In some embodiments, before bonding the logic chip to the substrate, the fabrication method further includes: forming a second chip electrically bonded to the logic chip on the first chip; wherein the second chip includes a second memory chip and a second communication chip; wherein the second memory chip is electrically bonded to the second communication chip; and the second memory chip communicates wirelessly with the logic chip through the second communication chip and the communication module.

[0042] In some embodiments, forming a first die on the logic chip that is electrically bonded to the logic chip includes:

[0043] Provide the primary carrier;

[0044] The active surfaces of the first memory chip and the first communication chip are joined to the first carrier.

[0045] A first molding layer covering the first memory chip and the first communication chip is formed on the first carrier;

[0046] Remove the first carrier to expose the active surface of the first memory chip and the active surface of the first communication chip;

[0047] A first dielectric layer is formed covering the active surface of the first memory chip and the active surface of the first communication chip;

[0048] A first conductive structure is formed in the first dielectric layer;

[0049] The active surface of the first memory chip and the logic chip are bonded together through the first conductive structure.

[0050] In some embodiments, after forming the first conductive structure and before bonding the first memory chip and the logic chip, the fabrication method further includes:

[0051] A first via hole is formed that penetrates the first molding layer, and the bottom of the first via hole exposes the first conductive structure;

[0052] A conductive material is filled into the first passage hole to form a first passage;

[0053] The step of forming a second chip electrically bonded to the logic chip on the first chip includes:

[0054] Provide a second carrier;

[0055] The active surfaces of the second memory chip and the second communication chip are joined to the second carrier.

[0056] A second molding layer covering the second memory chip and the second communication chip is formed on the second carrier;

[0057] Remove the second carrier to expose the active surface of the second memory chip and the active surface of the second communication chip;

[0058] A second dielectric layer is formed covering the active surface of the second memory chip and the active surface of the second communication chip;

[0059] A second conductive structure is formed in the second dielectric layer;

[0060] Before bonding the first memory chip and the logic chip, the active surface of the second memory chip and the first path are bonded together through the second conductive structure;

[0061] After bonding the first memory chip and the logic chip, the active surface of the second memory chip is electrically connected to the logic chip through the second conductive structure, the first path, and the first conductive structure.

[0062] In some embodiments, the manufacturing method further includes:

[0063] When forming the first conductive structure, a first electrical connection structure is formed in the first dielectric layer; wherein the first electrical connection structure is electrically bonded to the first memory chip and the first communication chip respectively;

[0064] When forming the second conductive structure, a second electrical connection structure is formed in the second dielectric layer; wherein the second electrical connection structure is electrically bonded to the second memory chip and the second communication chip respectively.

[0065] In some embodiments, the manufacturing method further includes:

[0066] When forming the first conductive structure, a first interconnect structure is formed in the first dielectric layer; wherein the first interconnect structure is electrically bonded to the active surface of the first communication chip;

[0067] When forming the first via, a second via is formed that penetrates the first molding layer, and the bottom of the second via exposes the first interconnect structure;

[0068] A conductive material is filled into the second passage hole to form a second passage;

[0069] When forming the second conductive structure, a second interconnect structure is formed in the second dielectric layer; when bonding the second memory chip and the first path, the active surface of the second communication chip and the second path are bonded through the second interconnect structure.

[0070] When bonding the first memory chip and the logic chip, the active surface of the first communication chip and the logic chip are bonded together through the first interconnect structure;

[0071] After bonding the first communication chip and the logic chip, the active surface of the second communication chip is electrically connected to the logic chip through the second interconnect structure, the second path, and the first interconnect structure.

[0072] In some embodiments, the manufacturing method further includes:

[0073] When forming the first conductive structure, a first stress structure is formed in the first dielectric layer; wherein the first stress structure is electrically insulated from the first memory chip and the first communication chip;

[0074] When forming the second conductive structure, a second stress structure is formed in the second dielectric layer; wherein the second stress structure is electrically insulated from the second memory chip and the second communication chip.

[0075] In some embodiments, the manufacturing method further includes: forming a first conductive block on the active surface of the first core particle;

[0076] The process of forming a first chip electrically bonded to the logic chip on the logic chip includes: bonding the first conductive block to the logic chip.

[0077] In some embodiments, the manufacturing method further includes: forming a second conductive block on the active surface of the communication module;

[0078] The method of forming a communication module electrically connected to the logic chip on the logic chip includes: connecting the second conductive block to the logic chip while connecting the first conductive block to the logic chip.

[0079] In this embodiment, by incorporating a first chip, which includes a first memory chip and a first communication chip, the first memory chip can wirelessly communicate with the logic chip via the first communication chip and a communication module. This allows for the stacking of multiple chips on the logic chip, achieving three-dimensional stacked packaging and improving semiconductor structure integration. Furthermore, compared to wired communication, this embodiment enables wireless communication by incorporating a first communication chip, ensuring minimal differences in communication latency between memory chips within different chips. Moreover, the first memory chip and the first communication chip can be manufactured using different process technologies, which helps reduce chip design complexity and save on process costs. Attached Figure Description

[0080] Figure 1a and Figure 1bThis is a schematic diagram illustrating a semiconductor structure according to an exemplary embodiment;

[0081] Figure 2 This is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0082] Figure 3 This is a schematic diagram illustrating another semiconductor structure according to an embodiment of the present disclosure;

[0083] Figure 4 This is a schematic diagram illustrating yet another semiconductor structure according to an embodiment of the present disclosure;

[0084] Figure 5 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0085] Figures 6 to 9 This is a schematic diagram illustrating the fabrication process of a semiconductor structure according to an embodiment of the present disclosure. Detailed Implementation

[0086] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0087] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0088] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0089] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0090] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0091] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0092] Figure 1a and Figure 1b This is a schematic diagram of a semiconductor structure 100 according to an exemplary embodiment. The semiconductor structure 100 includes a logic chip 110 and a plurality of memory chips (such as memory chips stacked on the logic chip) Figure 1a The four memory chips shown are labeled as memory chips 101, 102, 103, and 104, respectively; or, (as shown in the image) Figure 1b The six memory chips shown are labeled as memory chips 101, 102, 103, 104, 105, and 106, respectively.

[0093] In the semiconductor structure 100, the memory chip and the logic chip transmit data signals via wired communication and power and ground signals via wired power supply. For example, the memory chip and the logic chip are physically connected through a through-silicon via (TSV) 120 and a bump 130 for wired communication and wired power supply.

[0094] However, the varying communication distances between different memory chips and logic chips will lead to inconsistent communication latency among them. Furthermore, the more memory chips stacked, the greater the communication distance between the topmost memory chip and the logic chip (e.g., ...). Figure 1b The communication distance between the dashed box ① and the lowest-level memory chip and logic chip (as shown in the middle) is (e.g.) Figure 1b The difference between the two (as shown in the dashed box ②) is significant, resulting in a large difference in communication delay between the top-level memory chip and the bottom-level memory chip and the logic chip, which affects the operating speed of the product.

[0095] In view of this, the present disclosure provides a semiconductor structure and a method for fabricating the same.

[0096] Figure 2 This is a schematic diagram illustrating a semiconductor structure 200 according to an embodiment of the present disclosure. (Refer to...) Figure 2As shown, the semiconductor structure 200 includes:

[0097] substrate 270;

[0098] The logic chip 210 is located on the substrate 270 and is electrically connected to the substrate 270;

[0099] The communication module 220 is located on the logic chip 210 and is electrically connected to the logic chip 210;

[0100] The first chip 201 is located on and electrically connected to the logic chip 210, and includes a first memory chip 2011 and a first communication chip 2012; wherein the first memory chip 2011 is electrically connected to the first communication chip 2012, and the first memory chip 2011 communicates wirelessly with the logic chip 210 through the first communication chip 2012 and the communication module 220.

[0101] Semiconductor structure 200 may be a memory including logic chips and memory chips, such as high-bandwidth memory, or other memory known in the art.

[0102] The substrate 270 includes a packaging substrate for carrying the chip. For example, a low-temperature co-fired ceramic substrate or a printed circuit board.

[0103] Logic chip 210 may be one or more processors that communicate with the memory chip to access data from the memory chip or to store data in the memory chip. Logic chip 210 includes: a graphics processing unit (GPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a central processing unit (CPU), or other known electronic circuitry used as a processor.

[0104] The communication module 220 is used to realize the transmission of data signals between the logic chip and the memory chip. For example, the communication module 220 is used to transmit data signals sent from the logic chip to the memory chip that will be stored in the memory chip to the memory chip, or to receive data signals accessed from the memory chip and transmit them to the logic chip. The communication module 220 can be a Bluetooth chip, a WIFI chip, or other known wireless communication chip.

[0105] A chip can integrate chips with different functions and / or chips with different process nodes. For example, in this embodiment, the first chip 201 integrates a first memory chip 2011 and a first communication chip 2012, where the process technology of the first memory chip 2011 is less advanced than that of the first communication chip 2012. In a specific example, the first memory chip 2011 can be a DRAM chip, and the first communication chip 2012 can be a Wi-Fi chip. In other embodiments, the first memory chip 2011 can be other known memory chips, the first communication chip 2012 can be other known wireless communication chips, and the first chip 201 can also integrate other functional chips and / or chips with other process nodes.

[0106] In one example, logic chip 210 transmits data signals to be stored in first memory chip 2011 via communication module 220 and first communication chip 2012. In another example, logic chip 210 receives data signals accessed from first memory chip 2011 via first communication chip 2012 and communication module 220.

[0107] In this embodiment, by incorporating a first chip, which includes a first memory chip and a first communication chip, the first memory chip can wirelessly communicate with the logic chip via the first communication chip and a communication module. This allows for the stacking of multiple chips on the logic chip, achieving three-dimensional stacked packaging and improving semiconductor structure integration. Furthermore, compared to wired communication, this embodiment enables wireless communication by incorporating a first communication chip, ensuring minimal differences in communication latency between memory chips within different chips. Moreover, the first memory chip and the first communication chip can be manufactured using different process technologies, which helps reduce chip design complexity and save on process costs.

[0108] In some embodiments, refer to Figure 2 As shown, the semiconductor structure 200 includes at least two first chips 201, located on the logic chip 210 and electrically connected to the logic chip 210 respectively; wherein the distance between the first communication chip and the communication module 220 of the first first chip is the same as the distance between the first communication chip and the communication module 220 of the second first chip. For example, as Figure 2 As shown, the distance between the first communication chip 2012 located on the left side of the communication module 220 and the communication module 220 is the same as the distance between the first communication chip 2012 located on the right side of the communication module 220 and the communication module 220. In this way, the communication delay of the first memory chip in each first chip can be basically consistent.

[0109] It should be noted that the number of the first core 201 is not limited to... Figure 2The two shown can also be three or more.

[0110] Figure 3 This is a schematic diagram illustrating another semiconductor structure 200 according to an embodiment of the present disclosure. (Refer to...) Figure 3 As shown, the semiconductor structure 200 also includes:

[0111] The second chip 204, located on the first chip 201 and electrically connected to the logic chip 210, includes: a second memory chip 2041 and a second communication chip 2042; wherein the second memory chip 2041 and the second communication chip 2042 are electrically connected; the second memory chip 2041 communicates wirelessly with the logic chip 210 through the second communication chip 2042 and the communication module 220.

[0112] Semiconductor structure 200 includes multiple memory stacks, such as Figure 3 As shown, there is a first memory stack 200-1 and a second memory stack 200-2. Taking the first memory stack 200-1 as an example, the first memory stack 200-1 includes at least two cores. The first core 201 may be the lowest core in the first memory stack 200-1, and the second core 204 may be the highest core in the first memory stack 200-1.

[0113] The second chip 204 integrates a second memory chip 2041 and a second communication chip 2042. In this embodiment, the second memory chip 2041 is the same as the first memory chip 2011, and the second communication chip 2042 is the same as the first communication chip 2012; that is, the second memory chip 2041 is a DRAM chip, and the second communication chip 2042 is a WIFI chip. In other embodiments, the second memory chip 2041 and the first memory chip 2011 may be different; and / or, the second communication chip 2042 and the first communication chip 2012 may be different. The second chip 204 may also integrate other functional chips and / or chips from other process nodes.

[0114] In one example, the second storage stack 200-2 may have the same structure as the first storage stack 200-1. In another example, the communication module 220 may be located between the first storage stack 200-1 and the second storage stack 200-2.

[0115] In one example, logic chip 210 transmits data signals to be stored in second memory chip 2041 via communication module 220 and second communication chip 2042. In another example, logic chip 210 receives data signals accessed from second memory chip 2041 via second communication chip 2042 and communication module 220.

[0116] In one example, the distance between the first communication chip 2012 and the communication module 220 in the first storage stack 200-1 is the same as the distance between the first communication chip 2012 and the communication module 220 in the second storage stack 200-2; the distance between the second communication chip 2042 and the communication module 220 in the first storage stack 200-1 is the same as the distance between the second communication chip 2042 and the communication module 220 in the second storage stack 200-2. In this way, the communication latency of storage chips at the same level in different storage stacks can be basically consistent.

[0117] In this embodiment, by providing a second chip, which includes a second memory chip and a second communication chip, the second memory chip can wirelessly communicate with the logic chip via the second communication chip and a communication module. Data signals are transmitted wirelessly between the first and second memory chips and the logic chip, effectively reducing the latency of signal transmission between the memory chips and the logic chip and improving data transmission efficiency. Furthermore, the second memory chip and the second communication chip can be manufactured using different process technologies, which helps reduce chip design complexity and save process costs.

[0118] In some embodiments, refer to Figure 3 As shown, the first core 201 also includes:

[0119] The first molding compound 2013 covers the first memory chip 2011 and the first communication chip 2012;

[0120] First pathway 2014, penetrating the first sealing layer 2013;

[0121] Semiconductor structure 200 also includes:

[0122] The first dielectric layer 231 is located between the logic chip 210 and the first chip 201;

[0123] The second dielectric layer 234 is located between the first passage 2014 and the second core 204;

[0124] The first conductive structure 241a is located in the first dielectric layer 231; wherein, the active surface of the first memory chip 2011 is electrically connected to the logic chip 210 through the first conductive structure 241a.

[0125] The second conductive structure 244a is located in the second dielectric layer 234; wherein, the active surface of the second memory chip 2041 is electrically connected to the logic chip 210 through the second conductive structure 244a, the first path 2014, and the first conductive structure 241a.

[0126] by Figure 3Taking the first memory stack 200-1, which includes two chips (i.e., the first chip 201 and the second chip 204), as an example, power and ground signals are transmitted between the logic chip 210 and the first memory chip 2011 through a first conductive structure 241a. Power and ground signals are transmitted between the logic chip 210 and the second memory chip 2041 through the first conductive structure 241a, a first path 2014, and a second conductive structure 244a. In one example, the second conductive structure 244a is in direct contact with the first path 2014, meaning no other conductive structure is provided between the second conductive structure 244a and the first path 2014. In another example, the second conductive structure 244a and the first path 2014 are electrically connected through other conductive structures, such as... Figure 3 As shown, electrical bonding is achieved through a conductive structure located on the non-active surface (denoted as the back side of the first core) of the first core 201.

[0127] The material of the first molding layer 2013 includes epoxy molding compound, such as epoxy resin.

[0128] The first via 2014 is located in the first molding layer 2013 and can be a through-mold via (TMV). The material of the first via 2014 includes a conductive material, such as any one or a combination of tantalum, titanium, tungsten, copper, titanium nitride, tantalum nitride, or tungsten nitride. In one example, the first via 2014 includes an adhesion layer, a seed layer, and a conductive layer (not shown in the figure) sequentially disposed from the via wall to the via axis. The adhesion layer is used to increase the adhesion between the seed layer and the first molding layer 2013. The seed layer serves as a nucleation center for the conductive layer, which is beneficial for the subsequent deposition of the conductive layer. In a specific example, the seed layer and the conductive layer are made of the same material.

[0129] The materials of the first dielectric layer 231 and the second dielectric layer 234 include dielectric materials, such as silicon oxide, silicon nitride, or silicon nitride. The first dielectric layer 231 covers the active surface of the first chip 201 (denoted as the front side of the first chip), and the second dielectric layer 234 covers the active surface of the second chip 204 (denoted as the front side of the second chip). The materials of the first dielectric layer 231 and the second dielectric layer 234 may be the same or different.

[0130] The materials of the first conductive structure 241a and the second conductive structure 244a include conductive materials, such as copper, aluminum, platinum, gold, tungsten, or nickel. The first conductive structure 241a constitutes part of the redistribution layer (RDL) on the front side of the first chip, and the second conductive structure 244a constitutes part of the redistribution layer on the front side of the second chip. The materials of the first conductive structure 241a and the second conductive structure 244a may be the same or different.

[0131] In this embodiment of the disclosure, by setting a first conductive structure, a second conductive structure, and a first passage penetrating the first molding layer, memory chips and logic chips in different chips can be electrically connected, thereby vertically transmitting power signals and ground signals of memory chips in different layers of the memory stack, without the need to fabricate TSVs, which helps to reduce process costs.

[0132] In some embodiments, refer to Figure 3 As shown, the semiconductor structure 200 also includes:

[0133] The first electrical connection structure 241b is located in the first dielectric layer 231; wherein the first memory chip 2011 is electrically connected to the first communication chip 2012 through the first electrical connection structure 241b.

[0134] The second electrical connection structure 244b is located in the second dielectric layer 234; wherein the second memory chip 2041 is electrically connected to the second communication chip 2042 through the second electrical connection structure 244b.

[0135] In a specific example, the length of the first electrical connection structure 241b is the same as the length of the second electrical connection structure 244b. The first communication chip 2012 transmits the data signal to be stored in the first memory chip 2011 to the first memory chip 2011 through the first electrical connection structure 241b, and the second communication chip 2042 transmits the data signal to be stored in the second memory chip 2041 to the second memory chip 2041 through the second electrical connection structure 244b. Since the first memory chip 2011 and the second memory chip 2041 transmit data signals to the logic chip 210 wirelessly, the delay of signal transmission between each memory chip and the logic chip can be effectively reduced, and the data transmission efficiency can be improved.

[0136] The materials of the first electrical connection structure 241b and the second electrical connection structure 244b can be similar to those of the first conductive structure 241a and the second conductive structure 244a, and will not be described in detail here. The first electrical connection structure 241b constitutes part of the redistribution layer on the front side of the first core, and the second electrical connection structure 244b constitutes part of the redistribution layer on the front side of the second core. The materials of the first electrical connection structure 241b and the second electrical connection structure 244b can be the same or different.

[0137] In a specific example, the first conductive structure 241a, the second conductive structure 244a, the first electrical connection structure 241b, and the second electrical connection structure 244b are made of the same material. Thus, the first conductive structure 241a, the second conductive structure 244a, the first electrical connection structure 241b, and the second electrical connection structure 244b can be completed in the same manufacturing process, which helps to reduce manufacturing processes and save manufacturing costs.

[0138] In some embodiments, the first chip 201 further includes: a second passage 2015 penetrating the first molding compound 2013; the semiconductor structure 200 further includes:

[0139] The first interconnect structure 241c is located in the first dielectric layer 231; wherein, the active surface of the first communication chip 2012 is electrically connected to the logic chip 210 through the first interconnect structure 241c.

[0140] The second interconnect structure 244c is located in the second dielectric layer 234; wherein, the active surface of the second communication chip 2042 is electrically connected to the logic chip 210 through the second interconnect structure 244c, the second path 2015, and the first interconnect structure 241c.

[0141] The second channel 2015 is located within the first molding compound 2013. The second channel 2015 can be similar to the first channel 2014, and will not be described in detail here. The height of the second channel 2015 is greater than or equal to the thickness of the first molding compound 2013; and / or, the height of the first channel 2014 is greater than or equal to the thickness of the first molding compound 2013. It should be noted that "height" and "thickness" here refer to dimensions perpendicular to the plane of the substrate.

[0142] Still with Figure 3 Taking the first memory stack 200-1 as an example, which includes two chips, the logic chip 210 and the first communication chip 2012 transmit power signals and ground signals through the first interconnect structure 241c, and the logic chip 210 and the second communication chip 2042 transmit power signals and ground signals through the first interconnect structure 241c, the second path 2015 and the second interconnect structure 244c.

[0143] The materials of the first interconnect structure 241c and the second interconnect structure 244c can be similar to those of the first conductive structure 241a and the second conductive structure 244a, and will not be described in detail here. The first interconnect structure 241c constitutes part of the redistribution layer on the front side of the first chip, and the second interconnect structure 244c constitutes part of the redistribution layer on the front side of the second chip. The materials of the first interconnect structure 241c and the second interconnect structure 244c can be the same or different.

[0144] In a specific example, the first conductive structure 241a, the second conductive structure 244a, the first electrical connection structure 241b, the second electrical connection structure 244b, the first interconnect structure 241c, and the second interconnect structure 244c are made of the same material. Thus, the first conductive structure 241a, the second conductive structure 244a, the first electrical connection structure 241b, the second electrical connection structure 244b, the first interconnect structure 241c, and the second interconnect structure 244c can be completed in the same manufacturing process, which helps to reduce manufacturing processes and save manufacturing costs.

[0145] It should be understood that the redistribution layer on the front side of the first chip includes: a first conductive structure 241a, a first electrical connection structure 241b, and a first interconnect structure 241c, and the redistribution layer on the front side of the second chip includes: a second conductive structure 244a, a second electrical connection structure 244b, and a second interconnect structure 244c.

[0146] In one example, the second interconnect structure 244c is in direct contact with the second path 2015, meaning no other interconnect structure is provided between the second interconnect structure 244c and the second path 2015. In another example, the second interconnect structure 244c and the second path 2015 are electrically connected through other interconnect structures, such as... Figure 3 As shown, the interconnects are electrically joined through an interconnect structure located on the non-active surface of the first core 201.

[0147] In this embodiment of the present disclosure, by setting a first interconnect structure, a second interconnect structure, and a second path penetrating the first molding layer, communication chips and logic chips in different chips can be electrically connected, thereby vertically transmitting power signals and ground signals of communication chips in different layers of the storage stack, without the need to fabricate TSVs, which helps to reduce process costs.

[0148] Figure 4 This is a schematic diagram illustrating yet another semiconductor structure 200 according to an embodiment of the present disclosure. (Refer to...) Figure 4 As shown, the semiconductor structure 200 further includes: at least one third chip located between the first chip 201 and the second chip 204, and electrically connected to the logic chip 210, including: a third memory chip and a third communication chip; wherein the third memory chip and the third communication chip are electrically connected; the third memory chip communicates wirelessly with the logic chip 210 through the third communication chip and the communication module 220.

[0149] The third core can be a core located between the bottommost and topmost cores in either the first memory stack 200-1 or the second memory stack 200-2. The number of third cores can be one, two, or even more. Figure 4 Two third core particles are shown (referred to as third core particles 202 and 203, respectively).

[0150] Taking the first memory stack 200-1, which includes three chips (e.g., first chip 201, third chip 202, and second chip 204), as an example, power and ground signals are transmitted between the logic chip 210 and the third memory chip through a first conductive structure 241a, a first path 2014, and a third conductive structure. The third conductive structure is located in a third dielectric layer, which is located between the first path 2014 and the third chip 202. For example, the third dielectric layer covers the active surface of the third chip 202. Power and ground signals are transmitted between the logic chip 210 and the third communication chip through a first interconnect structure 241c, a second path 2015, and a third interconnect structure, which is located in the third dielectric layer. The third memory chip and the third communication chip are electrically connected through a third electrical connection structure, which is located in the third dielectric layer.

[0151] It should be noted that when the chip is packaged in a flip-chip manner (i.e., the active side of the chip faces the logic chip), the topmost chip in the memory stack may not have through-holes, such as... Figure 4 As shown, this reduces the number of through-holes in the semiconductor structure, thereby lowering the manufacturing cost.

[0152] In some embodiments, refer to Figure 3 or Figure 4 As shown, the semiconductor structure 200 also includes:

[0153] The first stress structure 241d is located in the first dielectric layer 231; wherein the first stress structure 241d is electrically insulated from the first memory chip 2011 and the first communication chip 2012.

[0154] The second stress structure 244d is located in the second dielectric layer 234; wherein the second stress structure 244d is electrically insulated from the second memory chip 2041 and the second communication chip 2042.

[0155] It should be noted that the first conductive structure 241a, the first electrical connection structure 241b, and the first interconnect structure 241c are usually metals. By setting the first stress structure 241d in the first dielectric layer 231, the stress in different areas of the first dielectric layer can be balanced, making the stress distribution more uniform and reducing the warping of the first memory chip 2011 caused by uneven stress distribution, which would affect the molding effect.

[0156] Similarly, the second conductive structure 244a, the second electrical connection structure 244b, and the second interconnection structure 244c are typically metals. By providing a second stress structure 244d in the second dielectric layer 234, the stress in different regions of the second dielectric layer can be balanced, resulting in a more uniform stress distribution and improved stability of the package.

[0157] In some embodiments, refer to Figure 3 or Figure 4 As shown, the semiconductor structure 200 also includes:

[0158] The first conductive block 251 is located between the logic chip 210 and the first chip 201; wherein, the active surface of the first memory chip 2011 is electrically connected to the logic chip 210 through the first conductive block 251.

[0159] The second conductive block 252 is located between the logic chip 210 and the communication module 220; wherein the active surface of the communication module 220 is electrically connected to the logic chip 210 through the second conductive block 252.

[0160] The first conductive block 251 is located between the logic chip and the memory stack. Power and ground signals can be transmitted between the logic chip 210 and the first memory chip 2011 via the first conductive block 251. Power and ground signals can also be transmitted between the logic chip 210 and the first communication chip 2012 via the first conductive block 251. There can be one or more first conductive blocks 251. Power and ground signals can be transmitted between the logic chip 210 and the communication module 220 via a second conductive block 252. There can also be one or more second conductive blocks 252.

[0161] In some embodiments, refer to Figure 2 As shown, the semiconductor structure 200 further includes a protective layer 260, located on the logic chip 210 and covering the communication module 220 and the first chip 201. The material of the protective layer 260 includes an epoxy molding compound, such as epoxy resin. Figure 3 In the example shown, the protective layer 260 also covers the second core 204. Figure 4 In the example shown, the protective layer 260 also covers the third core particles 202 and 203.

[0162] In some embodiments, refer to Figure 3 or Figure 4 As shown, the semiconductor structure 200 further includes: a first solder ball 281 and a second solder ball 282 located on opposite sides of the substrate 270; wherein the first solder ball 281 is located between the logic chip 210 and the substrate 270. The materials of the first solder ball 281 and the second solder ball 282 include conductive materials, such as one or more of copper, zinc, nickel, lead, gold and silver.

[0163] Figure 5 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure. (Refer to...) Figure 5 As shown, the manufacturing method includes at least the following steps:

[0164] S100: Provides logic chips;

[0165] S200: A communication module electrically connected to the logic chip is formed on the logic chip;

[0166] S300: A first chip is formed on the logic chip and electrically connected to the logic chip; wherein the first chip includes a first memory chip and a first communication chip; wherein the first memory chip and the first communication chip are electrically connected, and the first memory chip communicates wirelessly with the logic chip through the first communication chip and a communication module;

[0167] S400: After the first chip is formed, the logic chip is bonded to the substrate.

[0168] In this embodiment, a first chip electrically bonded to the logic chip is formed. Since the first chip includes a first memory chip and a first communication chip, the first memory chip can wirelessly communicate with the logic chip through the first communication chip and a communication module. Thus, multiple chips can be stacked on the logic chip to achieve three-dimensional stacked packaging, improve semiconductor structure integration, and ensure minimal differences in communication latency between memory chips in different chips. Furthermore, the first memory chip and the first communication chip can be fabricated using different process technologies, which helps reduce chip design complexity and save process costs.

[0169] In some embodiments, refer to Figure 9 As shown, step S300 includes: electrically connecting at least two first chips 301 to the logic chip 310 respectively; wherein the distance between the first communication chip and the communication module 320 of the first first chip is the same as the distance between the first communication chip and the communication module 320 of the second first chip.

[0170] In some embodiments, combined with Figure 8 and Figure 9 As shown, before performing step S400, the manufacturing method further includes: forming a second chip 304 electrically connected to the logic chip 310 on the first chip 301; wherein the second chip 304 includes a second memory chip 3041 and a second communication chip 3042; wherein the second memory chip 3041 and the second communication chip 3042 are electrically connected; the second memory chip 3041 communicates wirelessly with the logic chip 310 through the second communication chip 3042 and the communication module 320. For example, the first chip 301 and the second chip 304 can be packaged first to form a structure as shown in the figure. Figure 8 The first memory stack 300-1 shown is then electrically connected to the logic chip 310, as follows: Figure 9 As shown.

[0171] In some embodiments, refer to Figure 9As shown, the above manufacturing method further includes: forming multiple memory stacks (e.g., a first memory stack 300-1 and a second memory stack 300-2), and electrically connecting the multiple memory stacks to the logic chip 310.

[0172] In some embodiments, refer to Figure 6 As shown, step S300 includes: providing a first carrier (not shown in the figure); bonding the active surface of the first memory chip 3011 and the active surface of the first communication chip 3012 to the first carrier; referring to... Figure 7 As shown, a first molding compound 3013 is formed on a first carrier to cover the first memory chip 3011 and the first communication chip 3012; the first carrier is removed to expose the active surfaces of the first memory chip 3011 and the first communication chip 3012; a first dielectric layer 331 is formed to cover the active surfaces of the first memory chip 3011 and the first communication chip 3012; a first conductive structure 341a is formed in the first dielectric layer 331; and the active surfaces of the first memory chip 3011 and the logic chip 310 are bonded together through the first conductive structure 341a.

[0173] The first carrier can be a substrate used to carry the first memory chip and the first communication chip. The material of the first carrier includes metal, silicon, silicon dioxide, organic materials, or glass, etc. The first memory chip and the first communication chip can be bonded to the first carrier through an adhesive film. In some embodiments, the adhesive film is an adhesive material that can be peeled off from the adhesive surface after being heated.

[0174] In a specific example, the first memory chip 3011 and the first communication chip 3012 can be integrated into a single unit using a fan-out packaging process. Figure 7 In the first core 301 shown, a first dielectric layer 331 can be formed on the active surface of the first core 301 using a thin film deposition process, and a first conductive structure 341a can be formed in the first dielectric layer 331 using photolithography and etching processes.

[0175] In some embodiments, refer to Figure 7 As shown, after forming the first conductive structure 341a and before bonding the first memory chip 3011 and the logic chip 310, the above-mentioned fabrication method further includes: forming a first via hole penetrating the first molding compound 3013, with the bottom of the first via hole exposing the first conductive structure 341a; filling the first via hole with conductive material to form a first via 3014. After forming the first via 3014, a dielectric layer covering the first molding compound 3013 may also be formed, and a structure such as... may be formed in the dielectric layer. Figure 7 The conductive structure shown has a first passage 3014 located between the conductive structure and the first conductive structure 341a.

[0176] Reference Figure 8 As shown, the formation of a second chip 304 electrically bonded to a logic chip on the first chip 301 includes: providing a second carrier; bonding the active surfaces of the second memory chip 3041 and the second communication chip 3042 to the second carrier; forming a second molding compound 3043 on the second carrier covering the second memory chip 3041 and the second communication chip 3042; removing the second carrier to expose the active surfaces of the second memory chip 3041 and the second communication chip 3042; and forming a second molding compound 3043 covering the active surfaces of the second memory chip 3041 and the second communication chip 3042. The second communication chip 3042 has a second dielectric layer 334 on its active surface; a second conductive structure 344a is formed in the second dielectric layer 334; before bonding the first memory chip 3011 and the logic chip, the active surface of the second memory chip 3041 and the first path 3014 are bonded through the second conductive structure 344a; after bonding the first memory chip 3011 and the logic chip, the active surface of the second memory chip 3041 is electrically connected to the logic chip through the second conductive structure 344a, the first path 3014, and the first conductive structure 341a.

[0177] The second carrier can be similar to the first carrier, and the fabrication process of the second core 304 can be similar to the fabrication process of the first core 301 described above, which will not be repeated here. (Refer to...) Figure 8 As shown, by flip-chip bonding the second chip 304 onto the first chip 301, a first memory stack 300-1 comprising two chips can be formed. The first memory stack 300-1 and the logic chip 310 can be bonded together via the first conductive block 351, as shown. Figure 9 As shown.

[0178] After the first storage stack 300-1 is bonded to the logic chip 310, the logic chip 310 and the first storage chip 3011 can transmit power signals and ground signals through the first conductive block 351 and the first conductive structure 341a. The logic chip 310 and the second storage chip 3041 can transmit power signals and ground signals through the first conductive block 351, the first conductive structure 341a, the first path 3014 and the second conductive structure 344a.

[0179] In some embodiments, refer to Figure 8 As shown, the above manufacturing method further includes: when forming the first conductive structure 341a, forming a first electrical connection structure 341b in the first dielectric layer 331; wherein the first electrical connection structure 341b is electrically bonded to the first memory chip 3011 and the first communication chip 3012 respectively; when forming the second conductive structure 344a, forming a second electrical connection structure 344b in the second dielectric layer 334; wherein the second electrical connection structure 344b is electrically bonded to the second memory chip 3041 and the second communication chip 3042 respectively.

[0180] After forming the first dielectric layer 331, photolithography and etching processes can be used to simultaneously form the first conductive structure 341a and the first electrical connection structure 341b in the first dielectric layer 331. The first conductive structure 341a and the first electrical connection structure 341b are made of the same material, which helps to reduce fabrication steps and save fabrication costs. After forming the second dielectric layer 334, photolithography and etching processes can be used to simultaneously form the second conductive structure 344a and the second electrical connection structure 344b in the second dielectric layer 334. The second conductive structure 344a and the second electrical connection structure 344b are made of the same material, which helps to reduce fabrication steps and save fabrication costs.

[0181] In some embodiments, refer to Figure 8 As shown, the above manufacturing method further includes: when forming the first conductive structure 341a, forming a first interconnect structure 341c in the first dielectric layer 331; wherein the first interconnect structure 341c is electrically bonded to the active surface of the first communication chip 3012; when forming the first via, forming a second via penetrating the first molding layer 3013, the bottom of the second via exposing the first interconnect structure 341c; filling the second via with conductive material to form a second via 3015; when forming the second conductive structure 344a, forming a second interconnect structure 34 in the second dielectric layer 334. 4c; When bonding the second memory chip 3041 and the first path 3014, the active surface of the second communication chip 3042 and the second path 3015 are bonded together through the second interconnect structure 344c; When bonding the first memory chip 3011 and the logic chip, the active surface of the first communication chip 3012 and the logic chip are bonded together through the first interconnect structure 341c; After bonding the first communication chip 3012 and the logic chip, the active surface of the second communication chip 3042 is electrically connected to the logic chip through the second interconnect structure 344c, the second path 3015, and the first interconnect structure 341c.

[0182] The first conductive structure 341a, the first electrical connection structure 341b, and the first interconnection structure 341c can be formed simultaneously, which helps to reduce manufacturing steps and save manufacturing costs. In other embodiments, the first conductive structure 341a, the first electrical connection structure 341b, and the first interconnection structure 341c can also be formed separately.

[0183] The first and second passage holes can be formed simultaneously, which helps reduce manufacturing steps and saves manufacturing costs. In other embodiments, the first and second passage holes can also be formed separately, as can the first and second passages.

[0184] The second conductive structure 344a, the second electrical connection structure 344b, and the second interconnection structure 344c can be formed simultaneously, which helps to reduce manufacturing steps and save manufacturing costs. In other embodiments, the second conductive structure 344a, the second electrical connection structure 344b, and the second interconnection structure 344c can also be formed separately.

[0185] After the first storage stack 300-1 is bonded to the logic chip 310, the logic chip 310 and the first communication chip 3012 can transmit power signals and ground signals through the first conductive block 351 and the first interconnect structure 341c. The logic chip 310 and the second communication chip 3042 can transmit power signals and ground signals through the first conductive block 351, the first interconnect structure 341c, the second path 3015 and the second interconnect structure 344c.

[0186] In some embodiments, refer to Figure 8 As shown, the above manufacturing method further includes: when forming the first conductive structure 341a, forming a first stress structure 341d in the first dielectric layer 331; wherein the first stress structure 341d is electrically insulated from the first memory chip 3011 and the first communication chip 3012; when forming the second conductive structure 344a, forming a second stress structure 344d in the second dielectric layer 334; wherein the second stress structure 344d is electrically insulated from the second memory chip 3041 and the second communication chip 3042.

[0187] After forming the first dielectric layer 331, photolithography and etching processes can be used to simultaneously form the first conductive structure 341a and the first stress structure 341d within the first dielectric layer 331. The first conductive structure 341a and the first stress structure 341d are made of the same material, which helps reduce fabrication steps and saves manufacturing costs. After forming the second dielectric layer 334, photolithography and etching processes can be used to simultaneously form the second conductive structure 344a and the second stress structure 344d within the second dielectric layer 334. The second conductive structure 344a and the second stress structure 344d are made of the same material, which helps reduce fabrication steps and saves manufacturing costs.

[0188] In one specific embodiment, the first conductive structure 341a, the first electrical connection structure 341b, the first interconnect structure 341c, and the first stress structure 341d can be formed simultaneously to constitute the redistribution layer on the front side of the first core 301; the second conductive structure 344a, the second electrical connection structure 344b, the second interconnect structure 344c, and the second stress structure 344d can be formed simultaneously to constitute the redistribution layer on the front side of the second core 304.

[0189] In some embodiments, after forming the first chip and before forming the second chip, the above manufacturing method further includes: forming at least one third chip electrically bonded to the logic chip on the first chip; wherein the third chip includes a third memory chip and a third communication chip; wherein the third memory chip is electrically bonded to the third communication chip; and the third memory chip communicates wirelessly with the logic chip through the third communication chip and a communication module.

[0190] The fabrication process of the third core chip is similar to that of the first core chip 301 described above, and will not be repeated here. The third core chip can be the core chip located between the bottommost and topmost core chips in the first storage stack 300-1. Figure 8 Two third core particles are shown (labeled third core particles 302 and 303, respectively). See reference... Figure 8 As shown, two third chips are first flip-chip bonded to the first chip 301, and then the second chip 304 is flip-chip bonded to the third chips, forming a first memory stack 300-1 comprising four chips. The first memory stack 300-1 and the logic chip 310 can be bonded together through the first conductive block 351, as shown. Figure 9 As shown.

[0191] In some embodiments, refer to Figure 9 As shown, the above manufacturing method further includes: forming a first conductive block 351 on the active surface of the first chip 301; the above step S300 includes: bonding the first conductive block 351 to the logic chip 310.

[0192] In some embodiments, refer to Figure 9 As shown, the above manufacturing method further includes: forming a second conductive block 352 on the active surface of the communication module 320; the above step S200 includes: when the first conductive block 351 is bonded to the logic chip 310, the second conductive block 352 is bonded to the logic chip 310.

[0193] For example, at least one first conductive block 351 can be formed on the surface of the first dielectric layer facing the logic chip 310, and at least one second conductive block 352 can be formed on the active surface of the communication module 320, connecting the first conductive block 351 and the second conductive block 352 to the logic chip 310. The logic chip 310 can transmit power signals and ground signals to the memory chip or communication chip through the first conductive block 351, and can also transmit power signals and ground signals to the communication module 320 through the second conductive block 352.

[0194] In some embodiments, after forming the first chip 301 and before bonding the logic chip 310 to the substrate, the above manufacturing method further includes: forming a protective layer on the logic chip 310 covering the communication module 320 and the first chip 301. The protective layer can be formed by an injection molding process, and the material of the protective layer includes epoxy molding compound, such as epoxy resin.

[0195] In some embodiments, refer to Figure 9 As shown, after the protective layer is formed, a plurality of first solder balls 381 are formed on one side of the logic chip 310. The material of the first solder balls 381 includes conductive materials, such as one or more of copper, zinc, nickel, lead, gold, and silver. The logic chip 310 and the substrate ( Figure 9 (Not shown in the image) can be welded together via the first solder ball 381.

[0196] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: substrate; A logic chip is located on the substrate and electrically connected to the substrate; A communication module is located on the logic chip and electrically connected to the logic chip; The first chip, located on and electrically connected to the logic chip, includes: a first memory chip and a first communication chip; wherein the first memory chip is electrically connected to the first communication chip, and the first memory chip communicates wirelessly with the logic chip through the first communication chip and the communication module; The semiconductor structure includes: At least two first chips are located on the logic chip and electrically connected to the logic chip respectively; wherein the distance between the first communication chip and the communication module of the first first chip is the same as the distance between the first communication chip and the communication module of the second first chip.

2. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a second chip located on the first chip and electrically connected to the logic chip, comprising a second memory chip and a second communication chip; wherein the second memory chip is electrically connected to the second communication chip; and the second memory chip communicates wirelessly with the logic chip through the second communication chip and the communication module.

3. The semiconductor structure according to claim 2, characterized in that, The first core also includes: A first molding layer covers the first memory chip and the first communication chip; The first pathway extends through the first molding layer; The semiconductor structure also includes: A first dielectric layer is located between the logic chip and the first chip; A second dielectric layer is located between the first passage and the second core particle; A first conductive structure is located in the first dielectric layer; wherein the active surface of the first memory chip is electrically connected to the logic chip through the first conductive structure; The second conductive structure is located in the second dielectric layer; wherein the active surface of the second memory chip is electrically connected to the logic chip through the second conductive structure, the first path, and the first conductive structure.

4. The semiconductor structure according to claim 3, characterized in that, The semiconductor structure also includes: A first electrical connection structure is located in the first dielectric layer; wherein the first memory chip is electrically connected to the first communication chip through the first electrical connection structure. A second electrical connection structure is located in the second dielectric layer; wherein the second memory chip is electrically connected to the second communication chip through the second electrical connection structure.

5. The semiconductor structure according to claim 3, characterized in that, The first chip also includes a second passage extending through the first molding layer; The semiconductor structure also includes: A first interconnect structure is located in the first dielectric layer; wherein the active surface of the first communication chip is electrically connected to the logic chip through the first interconnect structure; The second interconnect structure is located in the second dielectric layer; wherein the active surface of the second communication chip is electrically connected to the logic chip through the second interconnect structure, the second path, and the first interconnect structure.

6. The semiconductor structure according to claim 3, characterized in that, The semiconductor structure also includes: A first stress structure is located in the first dielectric layer; wherein the first stress structure is electrically insulated from the first memory chip and the first communication chip; The second stress structure is located in the second dielectric layer; wherein the second stress structure is electrically insulated from the second memory chip and the second communication chip.

7. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: A first conductive block is located between the logic chip and the first memory chip; wherein the active surface of the first memory chip is electrically connected to the logic chip through the first conductive block; A second conductive block is located between the logic chip and the communication module; wherein the active surface of the communication module is electrically connected to the logic chip through the second conductive block.

8. A method for fabricating a semiconductor structure, characterized in that, include: Provide logic chips; A communication module electrically connected to the logic chip is formed on the logic chip; A first chip is formed on the logic chip and electrically connected to the logic chip; wherein the first chip includes a first memory chip and a first communication chip; wherein the first memory chip is electrically connected to the first communication chip, and the first memory chip communicates wirelessly with the logic chip through the first communication chip and the communication module; After the first chip is formed, the logic chip is bonded to the substrate; The process of forming a first chip electrically bonded to the logic chip on the logic chip includes: At least two of the first chips are electrically connected to the logic chip respectively; wherein the distance between the first communication chip and the communication module of the first first chip is the same as the distance between the first communication chip and the communication module of the second first chip.

9. The manufacturing method according to claim 8, characterized in that, Before bonding the logic chip to the substrate, the fabrication method further includes: A second chip electrically connected to the logic chip is formed on the first chip; wherein the second chip includes a second memory chip and a second communication chip; wherein the second memory chip is electrically connected to the second communication chip; the second memory chip communicates wirelessly with the logic chip through the second communication chip and the communication module.

10. The manufacturing method according to claim 9, characterized in that, The process of forming a first chip electrically bonded to the logic chip on the logic chip includes: Provide the primary carrier; The active surfaces of the first memory chip and the first communication chip are joined to the first carrier. A first molding layer covering the first memory chip and the first communication chip is formed on the first carrier; Remove the first carrier to expose the active surface of the first memory chip and the active surface of the first communication chip; A first dielectric layer is formed covering the active surface of the first memory chip and the active surface of the first communication chip; A first conductive structure is formed in the first dielectric layer; The active surface of the first memory chip and the logic chip are bonded together through the first conductive structure.

11. The manufacturing method according to claim 10, characterized in that, After forming the first conductive structure and before bonding the first memory chip and the logic chip, the fabrication method further includes: A first via hole is formed that penetrates the first molding layer, and the bottom of the first via hole exposes the first conductive structure; A conductive material is filled into the first passage hole to form a first passage; The step of forming a second chip electrically bonded to the logic chip on the first chip includes: Provide a second carrier; The active surfaces of the second memory chip and the second communication chip are joined to the second carrier. A second molding layer covering the second memory chip and the second communication chip is formed on the second carrier; Remove the second carrier to expose the active surface of the second memory chip and the active surface of the second communication chip; A second dielectric layer is formed covering the active surface of the second memory chip and the active surface of the second communication chip; A second conductive structure is formed in the second dielectric layer; Before bonding the first memory chip and the logic chip, the active surface of the second memory chip and the first path are bonded together through the second conductive structure; After bonding the first memory chip and the logic chip, the active surface of the second memory chip is electrically connected to the logic chip through the second conductive structure, the first path, and the first conductive structure.

12. The manufacturing method according to claim 11, characterized in that, The manufacturing method further includes: When forming the first conductive structure, a first electrical connection structure is formed in the first dielectric layer; wherein the first electrical connection structure is electrically bonded to the first memory chip and the first communication chip respectively; When forming the second conductive structure, a second electrical connection structure is formed in the second dielectric layer; wherein the second electrical connection structure is electrically bonded to the second memory chip and the second communication chip respectively.

13. The manufacturing method according to claim 11, characterized in that, The manufacturing method further includes: When forming the first conductive structure, a first interconnect structure is formed in the first dielectric layer; wherein the first interconnect structure is electrically bonded to the active surface of the first communication chip; When forming the first via, a second via is formed that penetrates the first molding layer, and the bottom of the second via exposes the first interconnect structure; A conductive material is filled into the second passage hole to form a second passage; When forming the second conductive structure, a second interconnect structure is formed in the second dielectric layer; when bonding the second memory chip and the first path, the active surface of the second communication chip and the second path are bonded through the second interconnect structure. When bonding the first memory chip and the logic chip, the active surface of the first communication chip and the logic chip are bonded together through the first interconnect structure; After bonding the first communication chip and the logic chip, the active surface of the second communication chip is electrically connected to the logic chip through the second interconnect structure, the second path, and the first interconnect structure.

14. The manufacturing method according to claim 11, characterized in that, The manufacturing method further includes: When forming the first conductive structure, a first stress structure is formed in the first dielectric layer; wherein the first stress structure is electrically insulated from the first memory chip and the first communication chip; When forming the second conductive structure, a second stress structure is formed in the second dielectric layer; wherein the second stress structure is electrically insulated from the second memory chip and the second communication chip.

15. The manufacturing method according to claim 8, characterized in that, The manufacturing method further includes: A first conductive block is formed on the active surface of the first core particle; The process of forming a first chip electrically bonded to the logic chip on the logic chip includes: The first conductive block is bonded to the logic chip.

16. The manufacturing method according to claim 15, characterized in that, The manufacturing method further includes: A second conductive block is formed on the active surface of the communication module; The communication module formed on the logic chip and electrically connected to the logic chip includes: When the first conductive block is bonded to the logic chip, the second conductive block is bonded to the logic chip.

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