Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises: a substrate and a word line structure; wherein the word line structure comprises: a work function stack structure located in the substrate; the work function stack structure comprises a plurality of first work function layers and second work function layers which are alternately stacked in sequence, the work function of the first work function layer is greater than the work function of the second work function layer; a word line conductive layer located in the substrate and on the upper surface of the work function stack structure; a gate oxide layer located between the work function stack structure and the substrate and between the word line conductive layer and the substrate. The problem of increased gate leakage current caused by the thinning of the gate oxide layer thickness can be improved, and the problems of polysilicon depletion effect, boron punch-through and incompatibility with high-K dielectric layer existing in the word line conductive layer can be improved, so as to reduce the occurrence of leakage and better protect the gate.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] As semiconductor process technology continues to improve, the feature size of devices is also shrinking proportionally. This shrinking device size leads to a continuous reduction in the thickness of the gate oxide layer, which in turn causes an exponential increase in gate leakage current.

[0003] The gate oxide layer is thinned, and the word line conductive layer cannot provide good protection for the gate due to problems such as polysilicon depletion effect, boron punch-through, and incompatibility with high-k dielectric layers (such as Fermi level pinning), which can easily lead to leakage. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the problem that thinning the gate oxide layer can lead to poor protection of the gate by the word line conductive layer, which can easily cause leakage.

[0005] To achieve the above objectives, in one aspect, this disclosure provides a semiconductor structure, including: a substrate and a word line structure; wherein, the word line structure includes:

[0006] A work function stacked structure is located within the substrate; the work function stacked structure includes a plurality of first work function layers and second work function layers stacked alternately in sequence, wherein the work function of the first work function layer is greater than the work function of the second work function layer;

[0007] The word line conductive layer is located within the substrate and on the upper surface of the work function stack structure;

[0008] A gate oxide layer is located between the work function stack and the substrate, and between the word line conductive layer and the substrate.

[0009] In one embodiment, the word line conductive layer includes a first portion and a second portion, the first portion being located below the second portion, the work function stack structure surrounding the sidewalls and bottom surface of the first portion, and the second portion covering the top surface of the first portion and the top surface of the work function stack structure.

[0010] In one embodiment, the first part and the second part are made of the same material, both being doped polycrystalline silicon.

[0011] In one embodiment, the first portion and the second portion are made of different materials, the first portion comprising a titanium nitride layer and the second portion comprising a doped polycrystalline silicon layer.

[0012] In one embodiment, the first part and the second part are made of different materials. The first part includes a tungsten metal layer, and the second part includes a doped polysilicon layer and a barrier layer, the barrier layer covering the sidewalls and bottom surface of the doped polysilicon layer.

[0013] In one embodiment, the first work function layer includes a titanium nitride layer, and the second work function layer includes at least one of a titanium layer, a tantalum layer, or a tantalum nitride layer.

[0014] In one embodiment, the substrate has word line trenches; the gate oxide layer covers the sidewalls and bottom of the word line trenches; the first work function layer is located on the surface of the gate oxide layer; the word line conductive layer is located within the word line trenches, and the upper surface of the word line conductive layer is lower than the top of the word line trenches.

[0015] In one embodiment, the surface of the gate oxide layer located within the word line trench is roughened.

[0016] In one embodiment, the word line structure further includes an insulating layer located on the upper surface of the word line conductive layer and filling the word line trench.

[0017] This disclosure also provides a method for fabricating a semiconductor structure, including:

[0018] Provide a base;

[0019] Word line grooves are formed within the substrate;

[0020] A gate oxide layer is formed on the sidewalls and bottom of the word line trench, and a power function stack structure is formed on the surface of the gate oxide layer; the upper surface of the power function stack structure is lower than the top surface of the word line trench; the power function stack structure includes a plurality of sequentially and alternately stacked first power function layers and second power function layers, wherein the power function of the first power function layer is greater than the power function of the second power function layer;

[0021] A word line conductive layer is formed within the word line trench, and the word line conductive layer is located on the upper surface of the work function stack structure.

[0022] In one embodiment, a gate oxide layer is formed on the sidewalls and bottom of the word line trench, including: forming a gate oxide material layer on the substrate, the sidewalls of the word line trench, and the bottom of the word line trench; and roughening the surface of the gate oxide material layer located in the word line trench.

[0023] In one embodiment, forming a work function stack structure on the surface of the gate oxide layer includes: forming a plurality of sequentially alternating first work function material layers and second work function material layers on the gate oxide material layer; etching back the first work function material layers and the second work function material layers to obtain the work function stack structure, wherein the work function stack structure forms a filling region around the word line trench.

[0024] In one embodiment, forming a word line conductive layer within the word line trench includes: depositing a conductive material layer, the conductive material layer filling the filling area and the word line trench, and etching back the conductive material layer to obtain the word line conductive layer located within the word line trench.

[0025] In one embodiment, forming a word line conductive layer within the word line trench includes: forming a first conductive layer that fills the filling area; and forming a second conductive layer, wherein the second conductive material layer is located within the word line trench and covers the top surface of the first conductive layer and the top surface of the work function stack structure.

[0026] In one embodiment, the first conductive layer is formed using a metal layer, and the second conductive layer includes a barrier layer and a doped polysilicon layer, wherein the barrier layer is formed between the doped polysilicon layer and the substrate.

[0027] The semiconductor structure and its fabrication method disclosed herein have the following beneficial effects:

[0028] The semiconductor structure disclosed herein includes a substrate and a word line structure. The word line structure includes a work function stack structure, a word line conductive layer, and a gate oxide layer. The gate oxide layer is located between the work function stack structure and the substrate, and between the word line conductive layer and the substrate. That is, the work function stack structure is located on the surface of the gate oxide layer, which can improve the problem of increased gate leakage current caused by the reduction of the gate oxide layer thickness. The work function stack structure includes multiple sequentially alternating first work function layers and second work function layers. The work function of the first work function layer is greater than that of the second work function layer. The word line conductive layer is located on the upper surface of the work function stack structure, which can improve the problems of polysilicon depletion effect, boron punch-through, and incompatibility with high-k dielectric layers present in the word line conductive layer, thereby reducing leakage current and better protecting the gate.

[0029] The semiconductor structure fabrication method disclosed herein involves forming word line trenches within a substrate, forming gate oxide layers on the sidewalls and bottom of the word line trenches, and forming a power function stack structure on the surface of the gate oxide layers. This method can improve the problem of increased gate leakage current caused by thinning of the gate oxide layer. The power function stack structure includes multiple sequentially alternating first power function layers and second power function layers, where the power function of the first power function layer is greater than that of the second power function layer. By forming a word line conductive layer within the word line trenches, and with the word line conductive layer located on the upper surface of the power function stack structure, the polysilicon depletion effect, boron penetration, and incompatibility with high-k dielectric layers present in the word line conductive layer can be improved, thereby reducing leakage current and better protecting the gate. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure provided in one embodiment;

[0032] Figure 2 This is a schematic cross-sectional view of the structure obtained in step S11 of the semiconductor structure fabrication method provided in one embodiment.

[0033] Figure 3 This is a schematic cross-sectional view of the structure obtained by the step of forming a shallow trench isolation structure in the substrate in a semiconductor structure fabrication method provided in one embodiment.

[0034] Figure 4 This is a schematic cross-sectional view of the structure obtained by forming a covering dielectric layer on the upper surface of a substrate in a semiconductor structure fabrication method provided in one embodiment.

[0035] Figure 5 This is a top view of the structure obtained in step S12 of the semiconductor structure fabrication method provided in one embodiment.

[0036] Figure 6 for Figure 5 A schematic diagram of the cross-sectional structure of the structure intercepted at point A-A';

[0037] Figure 7 This is a flowchart of step S13 in the method for fabricating a semiconductor structure provided in one embodiment;

[0038] Figure 8This is a schematic cross-sectional view of the structure obtained in step S131 of the semiconductor structure fabrication method provided in one embodiment.

[0039] Figure 9 This is a schematic cross-sectional view of the structure obtained by roughening the surface of the gate oxide material layer located in the word line trench in a semiconductor structure fabrication method provided in one embodiment.

[0040] Figure 10 This is a schematic cross-sectional view of the structure obtained in step S1331 of the semiconductor structure fabrication method provided in one embodiment.

[0041] Figure 11 This is a schematic cross-sectional view of the structure obtained in step S1332 of the semiconductor structure fabrication method provided in one embodiment.

[0042] Figure 12 This is a schematic cross-sectional view of the structure obtained in step S1333 of the semiconductor structure fabrication method provided in one embodiment.

[0043] Figure 13 This is a schematic cross-sectional view of the structure obtained in step S133 of the semiconductor structure fabrication method provided in one embodiment.

[0044] Figure 14 This is a schematic cross-sectional view of the structure obtained in step S141 of the semiconductor structure fabrication method provided in one embodiment.

[0045] Figure 15 This is a flowchart of step S142 in the method for fabricating a semiconductor structure provided in one embodiment;

[0046] Figure 16 This is a schematic cross-sectional view of the structure obtained by the step of forming an insulating isolation layer on the upper surface of the word line conductive layer and filling the word line trench in a semiconductor structure fabrication method provided in one embodiment.

[0047] Figure 17 This is a schematic cross-sectional view of the structure obtained in step S14111 of the semiconductor structure fabrication method provided in one embodiment.

[0048] Figure 18 This is a schematic cross-sectional view of the structure obtained in step S14112 of the semiconductor structure fabrication method provided in one embodiment;

[0049] Figure 19 This is a schematic cross-sectional view of the structure obtained in step S1412 of the semiconductor structure fabrication method provided in one embodiment.

[0050] Figure 20This is a schematic cross-sectional view of the structure obtained by the step of forming an insulating isolation layer on the upper surface of the word line conductive layer and filling the word line trench in a semiconductor structure fabrication method provided in one embodiment.

[0051] Figure 21 This is a schematic cross-sectional view of the structure obtained in step S14121 of the semiconductor structure fabrication method provided in one embodiment.

[0052] Figure 22 This is a schematic cross-sectional view of the structure obtained in step S14122 of the semiconductor structure fabrication method provided in one embodiment;

[0053] Figure 23 This is a schematic cross-sectional view of the structure obtained in step S14123 of the semiconductor structure fabrication method provided in one embodiment;

[0054] Figure 24 This is a cross-sectional schematic diagram of the structure obtained by forming an insulating isolation layer on the upper surface of the word line conductive layer and filling the word line trench in a semiconductor structure fabrication method provided in one embodiment.

[0055] Explanation of reference numerals in the attached figures:

[0056] 1. Substrate; 11. Shallow trench isolation structure; 12. Active region; 2. Cover dielectric layer; 3. Word line structure; 31. Word line trench; 32. Gate oxide layer; 321. Gate oxide material layer; 33. Work function stack structure; 331. First work function layer; 3311. First work function material layer; 332. Second work function layer; 3321. Second work function material layer; 333. Filled region; 34. Word line conductive layer; 340. Conductive material layer; 341. First conductive layer; 3411. First conductive material layer; 342. Second conductive layer; 3421. Second conductive material layer; 3422. Barrier layer; 34221. Barrier material layer; 3423. Doped polysilicon layer; 34231. Doped polysilicon material layer; 4. Insulating isolation layer. Detailed Implementation

[0057] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0059] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0060] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0061] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0062] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the present disclosure.

[0063] As semiconductor process technology continues to improve, the feature size of devices is also shrinking proportionally. This shrinking device size leads to a continuous reduction in the thickness of the gate oxide layer, which in turn causes an exponential increase in gate leakage current.

[0064] With the gate oxide layer thinned, the word line conductive layer, due to problems such as polysilicon depletion effect, boron punch-through, and incompatibility with high-k dielectric layers (such as Fermi level pinning), cannot provide good protection for the gate and is prone to leakage.

[0065] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the problem that thinning the gate oxide layer can lead to poor protection of the gate by the word line conductive layer, which can easily cause leakage.

[0066] To achieve the above objectives, this disclosure provides a method for fabricating a semiconductor structure, such as... Figure 1 As shown, the method for fabricating a semiconductor structure may include the following steps:

[0067] S11: Provides a substrate;

[0068] S12: Forming letter line grooves within the substrate;

[0069] S13: A gate oxide layer is formed on the sidewall and bottom of the word line trench, and a power function stack structure is formed on the surface of the gate oxide layer; the upper surface of the power function stack structure is lower than the top surface of the word line trench; the power function stack structure includes multiple sequentially stacked first power function layers and second power function layers, and the power function of the first power function layer is greater than the power function of the second power function layer.

[0070] S14: A word line conductive layer is formed in the word line groove, and the word line conductive layer is located on the upper surface of the work function stack structure.

[0071] The semiconductor structure fabrication method in the above embodiments, by forming word line trenches in the substrate, forming gate oxide layers on the sidewalls and bottom of the word line trenches, and forming a power function stacked structure on the surface of the gate oxide layers, can improve the problem of increased gate leakage current caused by the thinning of the gate oxide layer. The power function stacked structure includes multiple sequentially alternating first power function layers and second power function layers, where the power function of the first power function layer is greater than that of the second power function layer. By forming a word line conductive layer in the word line trenches, and the word line conductive layer being located on the upper surface of the power function stacked structure, the problems of polysilicon depletion effect, boron penetration, and incompatibility with high-k dielectric layers present in the word line conductive layer can be improved, thereby reducing leakage current and better protecting the gate.

[0072] Specifically, the first work function layer may include a titanium nitride layer; the second work function layer may include, but is not limited to, a titanium layer, a tantalum layer, or a tantalum nitride layer.

[0073] In step S11, please refer to Figure 1 Step S11 in the middle and Figure 2 Provides base 1.

[0074] Specifically, substrate 1 may include, but is not limited to, at least one of silicon substrate, germanium substrate, silicon-germanium substrate, gallium arsenide substrate, gallium nitride substrate, and silicon carbide substrate; specifically, substrate 1 may be any one of silicon substrate, germanium substrate, silicon-germanium substrate, gallium arsenide substrate, gallium nitride substrate, and silicon carbide substrate, or may be a composite substrate composed of two or more of them.

[0075] In one embodiment, before forming the word line groove 31 in the substrate 1, the method further includes: forming a shallow trench isolation structure 11 in the substrate 1; the shallow trench isolation structure 11 isolates a plurality of spaced active regions 12 in the substrate 1, the active regions 12 extending along a first direction; the word line groove 31 extends along a second direction, the second direction intersecting the first direction; the resulting structure is as follows: Figure 3 As shown.

[0076] Specifically, the shallow trench isolation structure 11 can be a structure in which a shallow trench is filled with a shallow trench dielectric layer; the shallow trench dielectric layer can be, but is not limited to, a silicon dioxide layer.

[0077] In some examples, a first ion implantation can be performed on the active region 12 to form a well region within the active region 12; a second ion implantation can be performed on the active region 12 to form a lightly doped region within the well region.

[0078] Specifically, if the first ion is an N-type ion, then the second ion is a P-type ion; if the first ion is a P-type ion, then the second ion is an N-type ion; the N-type ion may include at least one of phosphorus ions, arsenic ions, or antimony ions; the P-type ion may include at least one of boron ions, indium ions, or gallium ions.

[0079] In this design, the depth of the lightly doped region is less than the depth of the well region. For example, if the upper surface of the well region is flush with the upper surface of the lightly doped region, the bottom of the well region is lower than the bottom of the lightly doped region. The lightly doped region can include both source and drain regions.

[0080] In one embodiment, forming a shallow trench isolation structure 11 within the substrate 1 may include:

[0081] A shallow trench is formed within the base 1;

[0082] A trench medium layer is filled into the shallow trench to form a shallow trench isolation structure 11.

[0083] Specifically, shallow trenches can be formed in the substrate 1 by dry etching; trench dielectric layers can be filled in the shallow trenches by deposition; the trench dielectric layer can be, but is not limited to, a silicon dioxide layer.

[0084] Furthermore, forming shallow trenches within the substrate 1 may include:

[0085] A photoresist layer is formed on the upper surface of substrate 1; the method for forming the photoresist layer can be spin coating, a coating method.

[0086] The photoresist layer is exposed based on the first patterned photomask;

[0087] The exposed photoresist layer is developed to obtain a patterned photoresist layer;

[0088] The substrate 1 is etched based on a patterned photoresist layer to form shallow trenches within the substrate 1.

[0089] In some examples, the photoresist layer may include a positive photoresist layer or a negative photoresist layer.

[0090] In one embodiment, after forming the shallow trench isolation structure 11 in the substrate 1 and before forming the word line trench 31 in the substrate 1, the step may further include: forming a covering dielectric layer 2 on the upper surface of the substrate 1, such as... Figure 4 As shown. The character line groove 31 penetrates the covering dielectric layer 2 along the thickness direction and extends into the substrate 1, as shown. Figure 6As shown.

[0091] Specifically, the covering dielectric layer 2 may include a silicon dioxide layer or a silicon nitride layer.

[0092] In step S12, please refer to Figure 1 Step S12 in the middle and Figures 5 to 6 A groove 31 for letter lines is formed within the base 1. Figure 5 This is a top view of the structure obtained by forming the word line groove 31 in the substrate 1 in step S12; Figure 6 for Figure 5 A schematic diagram of the cross-section of the structure taken at point A-A'.

[0093] Specifically, word line trenches 31 can be formed within the cover dielectric layer 2 and the active region 12 by etching along the thickness direction of the cover dielectric layer 2 and the substrate 12. The depth of the word line trenches 31 can be 30 to 400 nm; for example, the depth of the word line trenches 31 can be 30 nm, 50 nm, 100 nm, 200 nm, 300 nm or 400 nm, or other depths between 30 and 400 nm, without being limited to the exemplified embodiments.

[0094] Furthermore, forming the character line groove 31 within the substrate 1 may include:

[0095] S121: A mask layer is formed on the upper surface of the covering dielectric layer 2; the mask layer may be at least one of silicon nitride layer, silicon carbide layer and silicon oxynitride layer;

[0096] S122: Expose the mask layer based on the second patterned photomask;

[0097] S123: Develop the exposed mask layer to obtain a patterned mask layer;

[0098] S124: Based on the patterned mask layer, the covering dielectric layer 2 and the substrate 1 are sequentially etched along the thickness direction to form word line trenches 31 in the active region 12.

[0099] The etching of the dielectric layer 2 and the substrate 1 can be performed using, but is not limited to, dry etching processes. The depth of the word line trench 31 can be 30–400 nm; for example, the depth of the word line trench 31 can be 30 nm, 50 nm, 100 nm, 200 nm, 300 nm, or 400 nm, or other depths between 30 and 400 nm, without being limited to the exemplified embodiments.

[0100] In one embodiment, such as Figure 7 As shown, the formation of a gate oxide layer 32 on the sidewalls and bottom of the trench 31 in step S13 may include the following steps:

[0101] S131: A gate oxide material layer 321 is formed on the substrate 1, on the sidewalls of the word line groove 31, and at the bottom of the word line groove 31, such as... Figure 8 As shown;

[0102] S132: The surface of the gate oxide material layer 321 located in the word line trench 31 is roughened, such as... Figure 9 As shown.

[0103] It should be noted that, since the covering dielectric layer 2 is located on the upper surface of the substrate, the gate oxide material layer 321 formed on the substrate 1, the sidewalls of the word line trench 31, and the bottom of the word line trench 31 can be formed on the covering dielectric layer 2, the sidewalls of the word line trench 31, and the bottom of the word line trench 31. Specifically, the gate oxide material layer 321 can be obtained by thermally oxidizing the upper surface of the covering dielectric layer 2, the sidewalls of the word line trench 31, and the bottom of the word line trench 31 to consume part of the covering dielectric layer 2, part of the sidewalls and bottom of the word line trench 31.

[0104] Furthermore, an in-situ steam generation (ISSG) process can be used to thermally oxidize the upper surface of the covering dielectric layer 2, the sidewalls of the word line trench 31, and the bottom to obtain the gate oxide material layer 321. The gate oxide material layer 321 may include at least one of a silicon oxide layer, a silicon oxynitride layer, and a silicon oxycarbide layer. In-situ steam generation technology is a novel low-pressure rapid thermal oxidation annealing (RTP) technology, currently mainly used for the growth of ultrathin oxide films, the preparation of sacrificial oxide layers, and oxygen oxynitride films.

[0105] In step S132, the surface of the gate oxide material layer 321 located in the word line trench 31 is roughened so that the surface of the gate oxide material layer 321 is a rough surface, thereby making the surface of the gate oxide layer 32 obtained after removing the gate oxide material layer 321 located outside the word line trench 31 a rough surface.

[0106] Specifically, the surface of the gate oxide material layer 321 located in the word line trench 31 can be roughened by using APM (short for Ammonia / Peroxide Mix) reagent. APM reagent is obtained by mixing NH4OH (ammonium hydroxide) and H2O2 (hydrogen peroxide). APM reagent will roughen the surface of the gate oxide material layer 321, thereby making the structure of the first work function material layer 3311 located on the surface of the gate oxide material layer 321 more compact.

[0107] In one embodiment, see still Figure 7The formation of a functional stack structure on the surface of the gate oxide layer in step S13 may include:

[0108] S133: A plurality of first work function material layers 3311 and second work function material layers 3321 are formed on the gate oxide material layer 321 in sequence and alternately stacked;

[0109] S134: The first work function material layer 3311 and the second work function material layer 3321 are etched back to obtain the work function stack structure 33, which forms a filling region 333 around the word line groove 31.

[0110] In one embodiment, step S133, forming a plurality of sequentially alternating first work function material layers 3311 and second work function material layers 3321 on the gate oxide material layer 321, may include the following steps:

[0111] S1331: A first work function material layer 3311 is formed on the gate oxide material layer 321, such as Figure 10 As shown;

[0112] S1332: A second work function material layer 3321 is formed on the first work function material layer 3311, such as Figure 11 As shown;

[0113] S1333: Repeat steps S1331 and S1332 to obtain multiple alternating layers of first work function material 3311 and second work function material 3321; as follows Figure 12 As shown.

[0114] Specifically, a titanium nitride material layer can be formed on the gate oxide material layer 321 as the first work function material layer 3311; a titanium material layer, a tantalum material layer, or a tantalum nitride material layer can be formed on the first work function material layer 3311 as the second work function material layer 3321. That is, the first work function material layer 3311 may include a titanium nitride material layer; the second work function material layer 3321 may include, but is not limited to, a titanium material layer, a tantalum material layer, or a tantalum nitride material layer. Titanium nitride has fine grains and low resistivity and stable chemical properties (good thermal stability and corrosion resistance). Using a titanium nitride material layer for the first work function material layer 3311 can help improve the performance and reduce the overall size of semiconductor devices.

[0115] It should be noted that the work function of the first work function material layer 3311 can be greater than that of the second work function material layer 3321. The first work function material layer 3311 has a higher work function, and stress will accumulate when the first work function material layer 3311 is formed. Therefore, by combining the second work function material layer 3321 with the first work function material layer 3311, which has a lower work function, the bonding force can be improved, the stress can be reduced, and the leakage current can be reduced.

[0116] For example, the thickness of the first work function material layer 3311 can be 0.7nm to 1.2nm; specifically, the thickness of the first work function material layer 3311 can be 0.7nm, 0.8nm, 0.9nm, 1nm, 1.1nm or 1.2nm, or any other thickness between 0.7nm and 1.2nm, not limited to the exemplified embodiments.

[0117] In step S134, see [reference needed]. Figure 13 The first work function material layer 3311 and the second work function material layer 3321 located within the word line groove 31 are etched back to obtain a work function stack structure 33. The work function stack structure 33 forms a filling region 333 around the word line groove 31. The work function stack structure 33 includes a plurality of first work function layers 331 and second work function layers 332 stacked alternately in sequence.

[0118] The depth of the first work function material layer 3311 and the second work function material layer 3321 can be 20-150 nm; the etching method can be dry etching; further, the etching gas used for etching the first work function material layer 3311 and the second work function material layer 3321 located in the word line trench 31 can include at least one of sulfur hexafluoride, chlorine, methane, silicon chloride and argon.

[0119] In one embodiment, see Figure 13 The process includes etching back the first work function material layer 3311 and the second work function material layer 3321 located in the word line trench 31 to obtain the work function stack structure 33, and also includes etching away the gate oxide material layer 321 located outside the word line trench 31 to obtain the gate oxide layer 32.

[0120] In one embodiment, forming a word line conductive layer 34 within the word line trench 31 in step S14 may include the following steps:

[0121] S141: Deposit conductive material layer 340, the conductive material layer 340 fills the filling area 333 and the word line trench 31, such as Figure 14 As shown; specifically, a portion of the conductive material layer 340 may also be formed on the upper surface of the covering dielectric layer 2;

[0122] S142: Etch back the conductive material layer 340 to obtain the word line conductive layer 34 located within the word line trench 31, such as Figure 15 As shown.

[0123] Specifically, a doped polysilicon material layer can be formed on the substrate 1 and within the word line trench 31 as a conductive material layer 340; that is, the conductive material layer 340 may include a doped polysilicon material layer, and the word line conductive layer 34 may include a doped polysilicon layer. The etch-back depth can be 30–70 nm; the etch-back method can be dry etching. In this embodiment, the word line conductive layer 34 may include a first portion and a second portion, the first portion being located within the filling region 333, and the second portion covering the top surface of the first portion and the top surface of the work function stacked structure 33. The gate oxide layer 32, the work function stacked structure 33, and the word line conductive layer 34 together constitute the word line structure 3.

[0124] In some examples, a low-step overlay process can be used to form the conductive material layer 340. Further, an N-type doped polysilicon material layer can be formed as the conductive material layer 340 using a low-step overlay process; that is, both the conductive material layer 340 and the word line conductive layer 34 can be made of N-type doped polysilicon, and the dopant ions can include, but are not limited to, at least one of phosphorus ions, arsenic ions, or antimony ions. The doping concentration of the dopant ions in the doped polysilicon material can be 10E20cm⁻¹. -3 ~20E20cm -3 Specifically, the doping concentration can be 10E20cm. -3 12E20cm -3 15E20cm -3 18E20cm -3 Or 20E20cm -3 It could also be another location located at 10E20cm -3 ~20E20cm -3 The concentrations are not limited to the exemplified embodiments. The work function of the word line conductive layer 34 can be changed by altering the concentration of dopant ions, thus reducing the risk of leakage by controlling the concentration of N doping.

[0125] Specifically, the low-step capping process can improve the film uniformity of the conductive material layer 340. The process features extremely low spatter and high deposition rate, reducing material spatter and increasing arc stability, thus obtaining a high-quality conductive material layer 340. The deposition of N-type doped polysilicon using the low-step capping process is simple. Compared to traditional N-type doping processes where dopant ions are easily consumed by etching, the low-step capping process disclosed here replenishes dopant ions. These N-type ions effectively prevent leakage current and increase leakage current, improving device performance. Furthermore, the process is simple and cost-effective.

[0126] In this embodiment, refer to Figure 15The upper surface of the word line conductive layer 34 may be lower than the top of the word line trench 31; after forming the word line conductive layer 34 in the word line trench 31, the method may further include: forming an insulating isolation layer 4 on the upper surface of the word line conductive layer 34, the insulating isolation layer 4 filling the word line trench 31, the resulting structure is as follows Figure 16 As shown. Specifically, the insulating layer 4 may include, but is not limited to, a silicon nitride layer or a silicon carbide layer.

[0127] In other embodiments, forming a word line conductive layer 34 within the word line trench 31 in step S14 may include the following steps:

[0128] S1411: Form a first conductive layer 341, the first conductive layer 341 fills the filling area 333;

[0129] S1412: Form a second conductive layer 342, which is located in the word line trench 31 and covers the top surface of the first conductive layer 341 and the top surface of the work function stack structure 33.

[0130] In step S1411, a first conductive layer 341 is formed, which fills the filling region 333. This may include:

[0131] S14111: A first conductive material layer 3411 is formed on the upper surface of the covering dielectric layer 2, in the filling area 333, and in the word line trench 31, such as Figure 17 As shown;

[0132] S14112: Etch back the first conductive material layer 3411 to obtain the first conductive layer 341 located within the filling region 333, as shown. Figure 18 As shown.

[0133] Specifically, a titanium nitride layer can be formed on the upper surface of the covering dielectric layer 2, within the filling region 333, and within the word line trench 31 as the first conductive material layer 3411. The first conductive material layer 3411 can be etched back using dry etching; the etch depth can be 50–200 nm; the etching gas used for etching back can include at least one of sulfur hexafluoride, chlorine, methane, silicon chloride, and argon.

[0134] In step S1412, see Figure 19 A second conductive layer 342 is formed, which is located in the word line trench 31 and covers the top surface of the first conductive layer 341 and the top surface of the work function stack structure 33.

[0135] Specifically, a doped polysilicon material layer can be formed on the upper surface of the covering dielectric layer 2 and within the word line trench 31 as a second conductive layer 342. The doped ions in the doped polysilicon material layer can include, but are not limited to, at least one of phosphorus ions, arsenic ions, or antimony ions; the doping concentration of the doped ions in the doped polysilicon material can be 10E20cm⁻¹. -3 ~20E20cm -3 Specifically, the doping concentration can be 10E20cm. -3 12E20cm -3 15E20cm -3 18E20cm -3 Or 20E20cm -3 It could also be another location located at 10E20cm -3 ~20E20cm -3 The concentration of dopant ions is not limited to the illustrated embodiments. The work function of the word line conductive layer 34 can be altered by changing the concentration of dopant ions; therefore, the work function can be reduced by adjusting the concentration of N doping, thereby reducing the risk of leakage. In this embodiment, the word line conductive layer 34 may include a first part and a second part. The first part is a first conductive layer 341 filling the region 333, and the second part is a second conductive layer 342 covering the top surface of the first conductive layer 341 and the top surface of the work function stack structure 33.

[0136] In this embodiment, refer to Figure 19 The upper surface of the word line conductive layer 34 may be lower than the top of the word line trench 31; after forming the word line conductive layer 34 in the word line trench 31, the method may further include: forming an insulating isolation layer 4 on the upper surface of the word line conductive layer 34, the insulating isolation layer 4 filling the word line trench 31, the resulting structure is as follows Figure 20 As shown. Specifically, the insulating layer 4 may include, but is not limited to, a silicon nitride layer or a silicon carbide layer.

[0137] In other embodiments, a metal layer may be used to form the first conductive material layer 3411. Specifically, the first conductive material layer 3411 may be formed using a metal layer, which may be a tungsten metal layer, meaning that both the first conductive material layer 3411 and the first conductive layer 341 may be metal layers.

[0138] In this embodiment, the second conductive layer 342 may include a barrier layer 3422 and a doped polysilicon layer 3423. The barrier layer 3422 is formed between the doped polysilicon layer 3423 and the substrate 1. The second conductive layer 342 is located within the word line trench 31 and covers the top surface of the first conductive layer 341 and the top surface of the work function stack structure 33. Therefore, forming the second conductive layer 342 may include:

[0139] S14121: A barrier material layer 34221 is formed on the upper surface of the covering dielectric layer 2, the top surface of the first conductive layer 341, the top surface of the covering work function stack structure 33, and the sidewall of the word line trench 31, such as... Figure 21 As shown;

[0140] S14122: A doped polycrystalline silicon material layer 34231 is formed on the upper surface of the barrier material layer 34221, such as... Figure 22 As shown;

[0141] S14123: Etching back the doped polysilicon material layer 34231 and the barrier material layer 34221 to obtain the barrier layer 3422 located on the top surface of the first conductive layer 341, the top surface of the work function stack structure 33, and the sidewall of the word line trench, and to obtain the doped polysilicon layer 3423 located on the upper surface of the barrier layer 3422, as shown. Figure 23 As shown.

[0142] Specifically, a titanium nitride layer can be formed on the upper surface of the covering dielectric layer 2, the top surface of the first conductive layer 341, the top surface of the covering work function stack structure 33, and the sidewall of the word line trench 31 as a barrier material layer 34221, that is, the barrier layer 3422 can be a titanium nitride layer; the word line conductive layer 34 can include a first part and a second part, with the first conductive layer 341 in the filling region 333 as the first part, and the second conductive layer 342, which is composed of the barrier layer 3422 and the doped polysilicon layer 3423, as the second part.

[0143] In this embodiment, refer to Figure 23 The upper surface of the word line conductive layer 34 may be lower than the top of the word line trench 31; after forming the word line conductive layer 34 in the word line trench 31, the method may further include: forming an insulating isolation layer 4 on the upper surface of the word line conductive layer 34, the insulating isolation layer 4 filling the word line trench 31, the resulting structure is as follows Figure 24 As shown. Specifically, the insulating layer 4 may include, but is not limited to, a silicon nitride layer or a silicon carbide layer.

[0144] It should be understood that although the steps in the flowcharts of various embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of various embodiments may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0145] This disclosure also provides a semiconductor structure. For example... Figure 20 As shown, the semiconductor structure includes: a substrate 1 and a word line structure 3; wherein, the word line structure 3 includes: a work function stacked structure 33, a word line conductive layer 34, and a gate oxide layer 32; the work function stacked structure 33 is located within the substrate 1; the work function stacked structure 33 includes a plurality of sequentially alternating first work function layers 331 and second work function layers 332, wherein the work function of the first work function layer 331 is greater than the work function of the second work function layer 332; the word line conductive layer 34 is located within the substrate 1 and is located on the upper surface of the work function stacked structure 33; the gate oxide layer 32 is located between the work function stacked structure 33 and the substrate 1 and between the word line conductive layer 34 and the substrate 1.

[0146] The semiconductor structure in the above embodiments includes a substrate 1 and a word line structure. The word line structure includes a work function stack structure 33, a word line conductive layer 34, and a gate oxide layer 32. The gate oxide layer 32 is located between the work function stack structure 33 and the substrate 1, and between the word line conductive layer 34 and the substrate 1. That is, the work function stack structure 33 is located on the surface of the gate oxide layer 32, which can improve the problem of increased gate leakage current caused by the thinning of the gate oxide layer 32. The work function stack structure 33 includes a plurality of sequentially alternating first work function layers 331 and second work function layers 332. The work function of the first work function layer 331 is greater than the work function of the second work function layer 332. The word line conductive layer 34 is located on the upper surface of the work function stack structure 33, which can improve the problems of polysilicon depletion effect, boron penetration, and incompatibility with high-k dielectric layers in the word line conductive layer 34, so as to reduce leakage current and better protect the gate.

[0147] Specifically, substrate 1 may include, but is not limited to, at least one of silicon substrate, germanium substrate, silicon-germanium substrate, gallium arsenide substrate, gallium nitride substrate, and silicon carbide substrate; specifically, substrate 1 may be any one of silicon substrate, germanium substrate, silicon-germanium substrate, gallium arsenide substrate, gallium nitride substrate, and silicon carbide substrate, or may be a composite substrate 1 composed of two or more of them. The first work function layer 331 may include a titanium nitride layer; the second work function layer 332 may include, but is not limited to, a titanium layer, a tantalum layer, or a tantalum nitride layer.

[0148] In one embodiment, the first work function layer 331 may include a titanium nitride layer, the second work function layer 332 may include a titanium layer, a tantalum layer, or a tantalum nitride layer, and the word line conductive layer 34 may include a doped polysilicon layer.

[0149] Specifically, the work function of the first work function layer 331 can be greater than that of the second work function layer 332. The work function of the first work function layer 331 is higher, and stress will accumulate when the first work function layer 331 is formed. Therefore, by combining the second work function layer 332 with the first work function layer 331, which has a lower work function, the bonding force can be improved, the stress can be reduced, and the leakage current can be reduced.

[0150] For example, the thickness of the first work function layer 331 can be 0.7nm to 1.2nm; specifically, the thickness of the first work function layer 331 can be 0.7nm, 0.8nm, 0.9nm, 1nm, 1.1nm or 1.2nm, or any other thickness between 0.7nm and 1.2nm, not limited to the exemplified embodiments.

[0151] In one embodiment, see Figure 15 , Figure 19 and Figure 23 The word line conductive layer 34 may include a first part and a second part. The first part is located below the second part. The work function stack structure 33 surrounds the sidewalls and bottom surface of the first part. The second part covers the top surface of the first part and the top surface of the work function stack structure 33.

[0152] Specifically, in combination Figures 13 to 14 ,exist Figure 15 In the middle, the first portion of the word line conductive layer 34 is located within the filling region 333, and the second portion covers the top surface of the first portion and the top surface of the work function stacked structure 33. Figure 19 In the first conductive layer 341 within the filling region 333, the word line conductive layer 341 serves as the first part of the word line conductive layer 34, and the second conductive layer 342, covering the top surface of the first conductive layer 341 and the top surface of the work function stack structure 33, serves as the second part of the word line conductive layer 34. Figure 23 In the filling region 333, the first conductive layer 341 serves as the first part of the word line conductive layer 34, and the second conductive layer 342, which is composed of the barrier layer 3422 and the doped polysilicon layer 3423, serves as the second part of the word line conductive layer 34.

[0153] In one embodiment, see Figure 15 The word line conductive layer 34 can be an N-type doped polysilicon layer, meaning that the first and second parts of the word line conductive layer 34 are made of the same material, both of which can be doped polysilicon. The dopant ions in the doped polysilicon material can include, but are not limited to, at least one of phosphorus ions, arsenic ions, or antimony ions; the doping concentration of the dopant ions in the doped polysilicon material can be 10E20cm⁻¹. -3 ~20E20cm -3 Specifically, the doping concentration can be 10E20cm. -3 12E20cm -3 15E20cm -3 18E20cm -3 Or 20E20cm -3 It could also be another location located at 10E20cm -3 ~20E20cm -3The concentrations are not limited to the exemplified embodiments. The work function of the word line conductive layer 34 can be changed by altering the concentration of doped ions, thus the work function can be reduced by controlling the concentration of N doping, thereby reducing the risk of leakage.

[0154] In one embodiment, see Figure 19 The first conductive layer 341 within the filling region 333 serves as the first part of the word line conductive layer 34, and the second conductive layer 342 covering the top surface of the first conductive layer 341 and the top surface of the work function stack structure 33 serves as the second part of the word line conductive layer 34.

[0155] In this embodiment, the first part and the second part are made of different materials. The first part may include a titanium nitride layer; the second part may include a doped polycrystalline silicon layer. The dopant ions in the doped polycrystalline silicon layer may include, but are not limited to, at least one of phosphorus ions, arsenic ions, or antimony ions, and the doping concentration of each dopant ion can be 10E20cm⁻¹. -3 ~20E20cm -3 Specifically, the doping concentration can be 10E20cm. -3 12E20cm -3 15E20cm -3 18E20cm -3 Or 20E20cm -3 It could also be another location located at 10E20cm -3 ~20E20cm -3 The concentrations are not limited to those in the exemplified examples.

[0156] In one embodiment, see Figure 23 The first conductive layer 341 within the filling region 333 serves as the first part of the word line conductive layer 34, and the second conductive layer 342, composed of the barrier layer 3422 and the doped polysilicon layer 3423, serves as the second part of the word line conductive layer 34. That is, the first and second parts are made of different materials; the first part may include a tungsten metal layer, and the second part includes the doped polysilicon layer 3423 and the barrier layer 3422, with the barrier layer 3422 covering the sidewalls and bottom surface of the doped polysilicon layer 3423.

[0157] Specifically, the barrier layer may include a titanium nitride layer.

[0158] In one embodiment, see Figure 6 The base 1 has a character line groove 31; see reference. Figure 9 The gate oxide layer 32 covers the sidewalls and bottom of the word line trench 31; see reference Figure 13 The first work function layer 331 is located on the surface of the gate oxide layer 32; the upper surface of the work function stack structure 33 is lower than the top of the word line trench 31; see reference Figure 15The word line conductive layer 34 is located inside the word line trench 31, and the upper surface of the word line conductive layer 34 is lower than the top of the word line trench.

[0159] Specifically, the depth of the word line trench 31 can be 30 to 400 nm; for example, the depth of the word line trench 31 can be 30 nm, 50 nm, 100 nm, 200 nm, 300 nm or 400 nm, or other depths between 30 and 400 nm, without being limited to the exemplified embodiments.

[0160] In one embodiment, see Figures 13 to 23 The surface of the gate oxide layer 32 can be a rough surface.

[0161] Specifically, the gate oxide layer 32 has a rough surface, which makes the structure of the first work function layer 331 located on the surface of the gate oxide layer 32 more compact.

[0162] In one embodiment, see Figure 4 The semiconductor structure also includes a cover dielectric layer 2, which is located on the upper surface of the substrate 1; the word line trench 31 penetrates the cover dielectric layer 2 along the thickness direction and extends into the substrate 1.

[0163] Specifically, the covering dielectric layer 2 may include a silicon dioxide layer or a silicon nitride layer.

[0164] In one embodiment, see Figure 5 The substrate 1 may also be provided with a shallow trench isolation structure 11, which isolates multiple spaced active regions 12 within the substrate 1. The active regions 12 extend along a first direction; the word line structure extends along a second direction, which intersects with the first direction.

[0165] Specifically, the shallow trench isolation structure 11 can be a structure in which a shallow trench is filled with a shallow trench dielectric layer; the shallow trench dielectric layer can be, but is not limited to, a silicon dioxide layer.

[0166] In one embodiment, see Figure 16 , Figure 20 and Figure 24 The upper surface of the word line conductive layer 34 is lower than the top of the word line trench 31. The semiconductor structure also includes an insulating isolation layer 4, which is located on the upper surface of the word line conductive layer 34 and fills the word line trench 31.

[0167] Specifically, the insulating layer 4 may include, but is not limited to, a silicon nitride layer or a silicon carbide layer.

[0168] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0169] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: A base and character line structure; wherein the character line structure includes: A work function stacked structure is located within the substrate; the work function stacked structure includes a plurality of first work function layers and second work function layers stacked alternately in sequence, wherein the work function of the first work function layer is greater than the work function of the second work function layer; The word line conductive layer is located within the substrate and on the upper surface of the work function stack structure; A gate oxide layer is located between the work function stack and the substrate, and between the word line conductive layer and the substrate.

2. The semiconductor structure according to claim 1, characterized in that, The word line conductive layer includes a first part and a second part, the first part being located below the second part, the work function stack structure surrounding the sidewalls and bottom surface of the first part, and the second part covering the top surface of the first part and the top surface of the work function stack structure.

3. The semiconductor structure according to claim 2, characterized in that, The first part and the second part are made of the same material, both of which are doped polycrystalline silicon.

4. The semiconductor structure according to claim 2, characterized in that, The first part and the second part are made of different materials. The first part includes a titanium nitride layer, and the second part includes a doped polycrystalline silicon layer.

5. The semiconductor structure according to claim 2, characterized in that, The first part and the second part are made of different materials. The first part includes a tungsten metal layer, and the second part includes a doped polycrystalline silicon layer and a barrier layer. The barrier layer covers the sidewalls and bottom surface of the doped polycrystalline silicon layer.

6. The semiconductor structure according to claim 1, characterized in that, The first work function layer includes a titanium nitride layer, and the second work function layer includes at least one of a titanium layer, a tantalum layer, or a tantalum nitride layer.

7. The semiconductor structure according to claim 1, characterized in that, The substrate has word line trenches; the gate oxide layer covers the sidewalls and bottom of the word line trenches; the first work function layer is located on the surface of the gate oxide layer; the word line conductive layer is located in the word line trenches, and the upper surface of the word line conductive layer is lower than the top of the word line trenches.

8. The semiconductor structure according to claim 7, characterized in that, The surface of the gate oxide layer located within the word line groove is rough.

9. The semiconductor structure according to claim 7, characterized in that, The word line structure also includes an insulating layer located on the upper surface of the word line conductive layer and filling the word line groove.

10. A method for fabricating a semiconductor structure, characterized in that, include: Provide a base; Word line grooves are formed within the substrate; A gate oxide layer is formed on the sidewalls and bottom of the word line trench, and a function stack structure is formed on the surface of the gate oxide layer; The upper surface of the work function stack structure is lower than the top surface of the word line groove; the work function stack structure includes a plurality of first work function layers and second work function layers stacked alternately in sequence, wherein the work function of the first work function layer is greater than the work function of the second work function layer; A word line conductive layer is formed within the word line trench, and the word line conductive layer is located on the upper surface of the work function stack structure.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that, Forming a gate oxide layer on the sidewalls and bottom of the word line trench includes: forming a gate oxide material layer on the substrate, on the sidewalls of the word line trench, and at the bottom of the word line trench; and roughening the surface of the gate oxide material layer located in the word line trench.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that, Forming a work function stack structure on the surface of the gate oxide layer includes: forming a plurality of sequentially alternating first work function material layers and second work function material layers on the gate oxide material layer; etching back the first work function material layers and the second work function material layers to obtain the work function stack structure, wherein the work function stack structure forms a filling region around the word line trench.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that, Forming a word line conductive layer within the word line trench includes: depositing a conductive material layer, the conductive material layer filling the filling area and the word line trench, and etching back the conductive material layer to obtain the word line conductive layer located within the word line trench.

14. The method for preparing a semiconductor structure according to claim 12, characterized in that, Forming a word line conductive layer within the word line trench includes: forming a first conductive layer that fills the filling area; and forming a second conductive layer located within the word line trench, covering the top surface of the first conductive layer and the top surface of the work function stack structure.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that, The first conductive layer is formed using a metal layer, and the second conductive layer includes a barrier layer and a doped polysilicon layer, wherein the barrier layer is formed between the doped polysilicon layer and the substrate.

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