Standard cell layout and integrated circuit

Abstract

The standard cell layout includes a substrate including a well region, an active region located in the well region, a first conductive pattern located above the well region, a second conductive pattern located on the opposite side of the first conductive pattern, a plurality of active region patterns located in a first region and a second region between the first conductive pattern and the second conductive pattern, and each active region pattern is isolated from each other, a first central conductive pattern located between the active region patterns adjacent to the first region and partially overlapping the first conductive pattern, a second central conductive pattern located between the active region patterns adjacent to the second region and partially overlapping the second conductive pattern, a plurality of auxiliary conductive patterns located on one side of one of the plurality of active region patterns, and a first communication layer pattern located above the first conductive pattern and overlapping the first central conductive pattern. By using the above scheme, the number of masks used can be reduced, and the cost can be reduced.

Description

Technical Field

[0001] This specification relates to the field of semiconductor manufacturing technology, and in particular to a standard cell layout and integrated circuit. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, integrated circuits (e.g., application-specific integrated circuits, ASICs) are becoming increasingly larger, with their internal gates potentially reaching millions. Although they undergo verification processes such as logic analysis and simulation before tape-out, it is still difficult to cover all functional combinations. Chips after tape-out may have some functional defects or some functions may not meet customer requirements.

[0003] Currently, Engineering Change Order (ECO) techniques are typically used to address the aforementioned functional defects or add new functions to meet customer needs. ECO refers to altering the metal traces of the chip after fabrication to change the original connections, thereby repairing logic functionality or adding new features.

[0004] However, existing solutions use a lot of vias to connect conductive patterns in the standard cell layout of integrated circuits. When performing ECO, more masks are needed to break down the vias, which increases costs. Summary of the Invention

[0005] The problem addressed by the embodiments in this specification is to provide a standard cell layout and integrated circuit that can reduce the number of masks used and lower costs.

[0006] First, this specification provides a standard cell layout, including: Substrate, including the well region; The active region, located within the well region, includes a channel layer, a gate, a source / drain, and a conductive layer; A first conductive pattern is located above the well region; The second conductive pattern is located on the side opposite to the first conductive pattern; Multiple active region patterns are located in a first region and a second region between the first conductive pattern and the second conductive pattern, and each active region pattern is isolated from the others; The first central conductive pattern is located between the adjacent active region patterns in the first region and partially overlaps with the first conductive pattern. The second central conductive pattern is located between the adjacent active region patterns in the second region and partially overlaps with the second conductive pattern. Multiple auxiliary conductive patterns are located on one side of one of the multiple active patterns, and are used to isolate the multiple active patterns. The first connected layer pattern is located below the first conductive pattern and overlaps with the first central conductive pattern; The second connected layer pattern is located below the second conductive pattern and overlaps with the second central conductive pattern.

[0007] Accordingly, embodiments of this specification also provide an integrated circuit including multiple standard cell layouts, wherein the standard cell layouts are those described in the foregoing embodiments, and the multiple standard cell layouts are connected according to a preset connection relationship.

[0008] Compared with the prior art, the technical solutions of the embodiments in this specification have the following advantages: In the standard cell layout provided in the embodiments of this specification, the first connecting layer pattern is located above the first conductive pattern and overlaps with the first central conductive pattern, and the second connecting layer pattern is located above the second conductive pattern and overlaps with the second central conductive pattern. Compared with the method of connecting through multiple vias, the number of vias used per unit area can be reduced. Consequently, fewer masks are needed for ECO (Enhanced Clean Operation). Furthermore, compared with the via connection method, the first connecting layer pattern can connect more first conductive patterns and the first central conductive pattern, and the second connecting layer pattern can connect more second conductive patterns and the second central conductive pattern, improving the space utilization of the standard cell layout. Therefore, adopting the standard cell layout in the embodiments of this specification can reduce the number of masks used and lower costs. Attached Figure Description

[0009] Figure 1 A schematic diagram of a standard unit layout is shown; Figure 2 A schematic diagram of a standard cell layout in an embodiment of this specification is shown; Figure 3 A schematic diagram of another standard cell layout in an embodiment of this specification is shown; Figure 4 A structural schematic diagram of yet another standard unit layout in an embodiment of this specification is shown; Figure 5 This specification shows a schematic diagram of a standard cell layout for performing ECO in an embodiment of the present specification; Figure 6 A schematic diagram of the structure of an integrated circuit in an embodiment of this specification is shown; Figure 7 A schematic diagram of another integrated circuit structure is shown in an embodiment of this specification. Detailed Implementation

[0010] As the background technology shows, current standard cell layouts require a greater number of masks to decompose vias during ECO, resulting in higher costs. This paper analyzes the reasons for the high cost of current standard cell layouts during ECO, using a structural diagram of a standard cell layout.

[0011] Reference Figure 1 The diagram illustrates a standard cell layout. The standard cell layout 100 may include a first conductive pattern 111, a second conductive pattern 112; a first active region pattern OD1a and a second active region pattern OD2a disposed in a first region I between the first conductive pattern 111 and the second conductive pattern 112; a third active region pattern OD1b and a fourth active region pattern OD2b disposed in a second region II; a first central conductive pattern MD-P3 disposed between the first active region pattern OD1a and the second active region pattern OD2a; and a third active region pattern MD-P3 disposed in the third active region I. The second central conductive pattern MD-N3 of the pattern OD1b and the fourth active region pattern OD2b, and the first central conductive pattern MD-P3 partially overlaps with the first conductive pattern 111, and the second central conductive pattern MD-N3 partially overlaps with the second conductive pattern 112; the additional conductive pattern PD1a1 overlaps with the first active region pattern OD1a, the additional conductive pattern PD2a1 overlaps with the second active region pattern OD2a, the additional conductive pattern PD2b1 overlaps with the third active region pattern OD1b, and the additional conductive pattern PD2b2 overlaps with the fourth active region pattern OD2b.

[0012] Continue to refer to Figure 1 The standard cell layout 100 may further include a common gate conductive pattern Poly1 overlapping the first active region pattern OD1a and the second active region pattern OD2a, and a common gate conductive pattern Poly2 overlapping the third active region pattern OD1b and the fourth active region pattern OD2b, and conductive patterns MP1 and MP2 electrically connected to the common gate conductive pattern Poly1 and the common gate conductive pattern Poly2; a plurality of third conductive patterns MD-P1, MD-P2, MD-P4, MD-P5 and MD-N1, MD-N2, MD-N4, MD-N5; and a first via V0-P for connecting the first center conductive pattern MD-P3 to the first conductive pattern 111, and a second via V0-N for connecting the second center conductive pattern MD-N3 to the second conductive pattern 112.

[0013] Using a standard cell layout with the above structure, during ECO operation, due to the large number of through-holes in the standard cell layout ( Figure 1 (Only two are shown in the image) Connecting conductive patterns requires more masks to break down vias, which increases production costs accordingly.

[0014] To address the aforementioned issues, in the standard cell layout provided in the embodiments of this specification, the first connecting layer pattern is located above the first conductive pattern and overlaps with the first central conductive pattern, and the second connecting layer pattern is located above the second conductive pattern and overlaps with the second central conductive pattern. Compared to the method of connecting through multiple vias, this reduces the number of vias used per unit area. Consequently, fewer masks are required for ECO (Enhanced Clean Operation). Furthermore, compared to the via connection method, the first connecting layer pattern can connect more first conductive patterns and the first central conductive pattern, and the second connecting layer pattern can connect more second conductive patterns and the second central conductive pattern, improving the space utilization of the standard cell layout. Therefore, adopting the standard cell layout in the embodiments of this specification can reduce the number of masks used and lower costs.

[0015] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0016] Reference Figure 2 The schematic diagram shown in this specification illustrates a standard cell layout in an embodiment. The standard cell layout 200 may include a substrate ( Figure 1 (Not shown), the substrate includes a well region 210; an active region ( Figure 1 (Not shown), located within the well region 210, including a channel layer ( Figure 1 (not shown), gate ( Figure 1 (not shown), source and drain ( Figure 1 (not shown) and conductive layer ( Figure 1(Not shown); a first conductive pattern 211, located above the well region 210; a second conductive pattern 212, located on the side opposite to the first conductive pattern 211; a plurality of active region patterns (e.g., may include active region patterns AA1a, AA2a, AA3a, AA1b, AA2b, and AA3b), located in a first region I and a second region II between the first conductive pattern 211 and the second conductive pattern 212, and each active region pattern is isolated from the others; a first central conductive pattern (e.g., first central conductive sub-patterns MD-P1 and MD-P2), located between adjacent active region patterns in the first region I, and partially overlapping with the first conductive pattern 211; a second central conductive pattern (e.g., second central... Conductive electronic patterns MD-N1 and MD-N2 are located between adjacent active region patterns in the second region II and partially overlap with the second conductive pattern 212; multiple auxiliary conductive patterns (e.g., may include auxiliary conductive patterns AR1a1, AR2a1, AR3a1, AR1b2, AR2b1, AR2b2, AR3b2) are located on one side of one of the active region patterns in the multiple active patterns to isolate the multiple active region patterns; a first connecting layer pattern VR1 is located above the first conductive pattern 211 and overlaps with the multiple first central conductive patterns; a second connecting layer pattern VR2 is located above the second conductive pattern 212 and overlaps with the multiple second central conductive patterns.

[0017] In specific implementations, different types of well regions 210 can be obtained by diffusing different ions on the substrate. For example, well region 210 can be an N-well region, which can be obtained by diffusing N-type ions on a P-type substrate, or a P-well region can be obtained by diffusing P-type ions on an N-type substrate. The embodiments in this specification do not limit the type of well region 210, which can be obtained by implanting different ions on the substrate according to specific process requirements.

[0018] In some embodiments of this specification, the first conductive pattern 211 can serve as a power line VDD, and through the first connecting layer pattern VR1, the first central conductive pattern and the first metal layer M1 ( Figure 2 (Not shown) connection, for example, to realize the connection between the first central conductive pattern MD-P1 and the first metal layer M1; the second conductive pattern 212 can be used as a ground wire VSS, and through the second connecting layer pattern VR2, to realize the connection between the second central conductive pattern and the first metal layer M1, for example, to realize the connection between the second central conductive pattern MD-N1 and the first metal layer M1.

[0019] In a specific implementation, the first conductive pattern 211 and the second conductive pattern 212 can be formed on the first metal layer M1.

[0020] In actual manufacturing processes, the number of active area patterns can be flexibly set according to specific requirements. In some embodiments of this specification, reference continues to be made to... Figure 2 The first region I is adjacent to the first conductive pattern 211, and the multiple active region patterns located in the first region I include the first active region pattern AA1a, the second active region pattern AA2a, and the third active region pattern AA3a; the second region II is adjacent to the second conductive pattern 212, and the multiple active region patterns located in the second region II include the fourth active region pattern AA1b, the fifth active region pattern AA2b, and the sixth active region pattern AA3b, and the first active region pattern AA1a and the second active region pattern AA2a are symmetrically arranged on both sides of the first central conductive electronic pattern MD-P1, the second active region pattern AA2a and the third active region pattern AA3a are symmetrically arranged on both sides of the first central conductive electronic pattern MD-P2; the fourth active region pattern AA1b and the fifth active region pattern AA2b are symmetrically arranged on both sides of the second central conductive electronic pattern MD-N1, and the fifth active region pattern AA2b and the sixth active region pattern AA3b are symmetrically arranged on both sides of the second central conductive electronic pattern MD-N2.

[0021] In specific implementations, at least one of the multiple active region patterns can serve as an active device in the standard cell layout 200. For example, any one or more of the first active region pattern AA1a, the second active region pattern AA2a, the third active region pattern AA3a, the fourth active region pattern AA1b, the fifth active region pattern AA2b, and the sixth active region pattern AA3b can serve as active devices in the standard cell layout 200.

[0022] More specifically, the plurality of active region patterns can serve as active devices of different types formed above the active regions. As a specific example, any one of the multiple active region patterns can serve as a device such as a metal-oxide-semiconductor field-effect transistor (MOSFET) or a complementary metal-oxide-semiconductor (CMOS) transistor in the standard cell layout 200.

[0023] In specific implementations, the P-region of a PMOS transistor is formed in the first active region pattern AA1a, the second active region pattern AA2a, and the third active region AA3a; and the N-region of an NMOS transistor is formed in the fourth active region pattern AA1b, the fifth active region pattern AA2b, and the sixth active region AA3b. Alternatively, the N-region of an NMOS transistor is formed in the first active region pattern AA1a, the second active region pattern AA2a, and the third active region AA3a; and the P-region of a PMOS transistor is formed in the fourth active region pattern AA1b, the fifth active region pattern AA2b, and the sixth active region AA3b. The embodiments in this specification do not limit the type of transistor formed by the corresponding active region patterns.

[0024] In some embodiments of this specification, the active region patterns located in the first region I and the second region II can be isolated by the intermediate region III.

[0025] In actual manufacturing processes, the number of the first and second central conductive patterns can be flexibly set according to specific requirements. In some embodiments of this specification, reference continues to be made to... Figure 2 The first central conductive pattern may include multiple first central conductive electronic patterns, such as first central conductive electronic patterns MD-P1 and MD-P2, and the first central conductive electronic patterns MD-P1 and MD-P2 may be located between corresponding active region patterns and partially overlap with the first conductive pattern 211. For example, the first central conductive electronic pattern MD-P1 may be located between the first active region pattern AA1a and the second active region pattern AA2a, and the first central conductive electronic pattern MD-P2 may be located between the second active region pattern AA2a and the third active region pattern AA3a.

[0026] Accordingly, the second central conductive pattern may include multiple second central conductive sub-patterns, such as second central conductive sub-patterns MD-N1 and MD-N2, and the second central conductive sub-patterns MD-N1 and MD-N2 may be located between the corresponding active region patterns and partially overlap with the second conductive pattern 212. For example, the second central conductive pattern MD-N1 may be located between the fourth active region pattern AA1b and the fifth active region pattern AA2b, and the second central conductive pattern MD-N2 may be located between the fifth active region pattern AA2b and the sixth active region pattern AA3b.

[0027] In the embodiments described in this specification, reference continues to be made to... Figure 2The first central conductive pattern and the second central conductive pattern are isolated. That is, the first central conductive pattern MD-P1 and the second central conductive pattern MD-N1 are isolated from each other, and the first central conductive pattern MD-P2 and the second central conductive pattern MD-N2 are separated, so that the devices formed later (such as NMOS devices and PMOS devices) can receive signals separately and avoid crosstalk between signals.

[0028] In some embodiments of this specification, the first connecting layer pattern VR1 can electrically connect the first central conductive pattern (e.g., the first central conductive patterns MD-P1 and MD-P2) to the power line VDD, and the second connecting layer pattern VR2 can electrically connect the second central conductive pattern (e.g., the second central conductive patterns MD-N1 and MD-N2) to the ground line VSS. Thus, through the first connecting layer pattern VR1 and the second connecting layer pattern VR2, an electrical connection between the external power supply and the standard cell layout 200 can be achieved.

[0029] As mentioned above, the active area pattern can be used to form active devices in the standard cell layout 200, and the active area patterns located in the first region I and the second region II can be isolated by the intermediate region III. In specific implementation, in order to prevent mutual interference between active devices in the same region (e.g., the first region or the second region), a corresponding auxiliary conductive pattern can be set on one side of each active area pattern to isolate the multiple active area patterns.

[0030] More specifically, refer to Figure 2 An auxiliary conductive pattern AR1a1 can be set on one side of the first active region pattern AA1a and the fourth active region pattern, an auxiliary conductive pattern AR1a2 can be set on the other side of the first active region pattern AA1a, and an auxiliary conductive pattern AR1b2 can be set on the other side of the fourth active region pattern. An auxiliary conductive pattern AR2a1 is provided on one side of the second active region pattern AA2a, and an auxiliary conductive pattern AR1a2 is provided on the other side. An auxiliary conductive pattern AR31a1 is provided on one side of the third active region pattern AA3a and the sixth active region pattern AA3b, an auxiliary conductive pattern AR3a2 is provided on the other side of the third active region pattern AA3a, and an auxiliary conductive pattern AR3b2 is provided on the other side of the sixth active region pattern AA3b. An auxiliary conductive pattern AR2b1 is set on one side of the fifth active region pattern AA2b, and an auxiliary conductive pattern AR2b2 is set on the other side.

[0031] Furthermore, the integrated circuit may include multiple standard cell layouts 200. To achieve isolation between different standard cell layouts 200, refer to... Figure 2The auxiliary conductive patterns located on one side of the first active region pattern AA1a and the fourth active region pattern AA1b are continuous, that is, the auxiliary conductive patterns AR1a1 are simultaneously overlapped on the same side of the first active region pattern AA1a and the fourth active region pattern AA1b; the auxiliary conductive patterns located on one side of the third active region pattern AA3a and the sixth active region pattern AA3b are continuous, that is, the auxiliary conductive patterns AR3a1 are simultaneously overlapped on the same side of the third active region pattern AA3a and the sixth active region pattern AA3b.

[0032] It should be noted that in some embodiments of this specification, the auxiliary conductive pattern only serves an isolation function and does not constitute any functional component of the active device.

[0033] In practical implementation, when performing ECO on standard unit 200, the active area pattern, acting as an active device, needs to be electrically connected to the external circuit. Based on this, continue referring to... Figure 2 The standard cell layout 200 may further include multiple third conductive patterns (e.g., third conductive patterns MD-P3 to MD-P8), which are located above the first active region pattern AA1a, the second active region pattern AA2a, and the third active region pattern AA3a, respectively, and partially overlap with the first conductive pattern 211; and multiple fourth conductive patterns (e.g., third conductive patterns MD-N3 to MD-N8), which are located above the fourth active region pattern AA1b, the fifth active region pattern AA2b, and the sixth active region pattern AA3b, respectively, and partially overlap with the second conductive pattern 212.

[0034] Specifically, the third conductive patterns MD-P3 and MD-P4 can be located above the first active region pattern AA1a and partially overlap with the first conductive pattern 211; the third conductive patterns MD-P5 and MD-P6 can be located above the second active region pattern AA2a and partially overlap with the first conductive pattern 211; the third conductive patterns MD-P7 and MD-P8 can be located above the third active region pattern AA3a and partially overlap with the first conductive pattern 211.

[0035] The fourth conductive patterns MD-N3 and MD-N4 may be located above the third active region pattern AA1b and partially overlap with the second conductive pattern 212; the third conductive patterns MD-N5 and MD-N6 may be located above the second active region pattern AA2b and partially overlap with the second conductive pattern 212; the third conductive patterns MD-N7 and MD-N8 may be located above the third active region pattern AA3b and partially overlap with the second conductive pattern 212.

[0036] In some embodiments, the plurality of third conductive patterns may not overlap with the first conductive pattern, and the plurality of fourth conductive patterns may not overlap with the second conductive pattern.

[0037] Thus, the third and fourth conductive patterns can define the electrical connection between the active device in the active region pattern and the external circuit.

[0038] It is understandable that the aforementioned third and fourth conductive patterns are both located among multiple auxiliary conductive patterns in the same active region pattern.

[0039] In specific implementations, the third and fourth conductive patterns can be formed of metal and can be formed in the zero metal layer M0, which can serve as the lowest metal layer above the active device in a standard cell layout.

[0040] In some embodiments of this specification, reference continues to be made to... Figure 2 The standard cell layout 200 may also include a plurality of blocking layers (e.g., blocking layers MOC1 to MOC7) located on the plurality of third conductive patterns and the plurality of fourth conductive patterns, respectively, and an intermediate region III located between the first region I and the second region II, for respectively isolating the plurality of third conductive patterns and the plurality of fourth conductive patterns, and blocking the plurality of third conductive patterns and the plurality of fourth conductive patterns.

[0041] For example, the blocking layer MOC1 is located above the third conductive layers MD-P3 and MD-P4, and is used to block the third conductive layers MD-P3 and MD-P4; the blocking layer MOC5 is located above the fourth conductive layers MD-N3 and MD-N4, and is used to block the fourth conductive layers MD-N3 and MD-N4; the blocking layer MOC4 is located in the middle region III, and can block the third conductive layers MD-P3 and MD-N3, the third conductive layers MD-P4 and MD-N4, the third conductive layers MD-P5 and MD-N5, the third conductive layers MD-P6 and MD-N6, the third conductive layers MD-P7 and MD-N7, and the third conductive layers MD-P7 and MD-N8.

[0042] Continue to refer to Figure 2 The standard cell layout 200 may further include at least one gate conductive pattern that overlaps with at least one active region pattern. For example, the standard cell layout 200 may include a gate conductive pattern that overlaps with a first active region pattern AA1a, a gate conductive pattern that overlaps with a second active region pattern AA2a, and a gate conductive pattern that overlaps with a third active region pattern AA3a, etc.

[0043] In some embodiments, a single gate conduction pattern may be shared by the mutually symmetrical first active region pattern AA1a and fourth active region pattern AA1b. (Continuing to refer to...) Figure 2 At least one gate conductive pattern overlapping the first active region pattern AA1a and at least one gate conductive pattern overlapping the fourth active region pattern AA1b are continuous, forming a first common gate conductive pattern GT1 that overlaps the first active region pattern AA1a and the fourth active region pattern AA1b.

[0044] Similarly, the second active region pattern AA2a and the fifth active region pattern AA2b, which are symmetrical to each other, can share a single gate conduction pattern. (Continue to refer to...) Figure 2 At least one gate conductive pattern overlapping the second active region pattern AA2a and at least one gate conductive pattern overlapping the fifth active region pattern AA2b are continuous, forming a second common gate conductive pattern GT2 that overlaps the second active region pattern AA2a and the fourth active region pattern AA2b1.

[0045] The mutually symmetrical third active region pattern AA3a and sixth active region pattern AA3b can share a single gate conduction pattern. (Continue referring to...) Figure 2 At least one gate conductive pattern overlapping the third active region pattern AA3a and at least one gate conductive pattern overlapping the sixth active region pattern AA3b are continuous, forming a third common gate conductive pattern GT3 that overlaps the third active region pattern AA3a and the sixth active region pattern AA3b.

[0046] In some embodiments of this specification, a first common gate conductive pattern GT1, a second common gate conductive pattern GT2, and a third common gate conductive pattern GT3 may be formed above the corresponding active region pattern and configured to jointly define the active device in the standard cell layout 200 with the corresponding active region pattern.

[0047] For example, the first common gate conductive pattern GT1 can be formed in the first active region pattern AA1a and the fourth active region pattern AA1b, and define active devices with the first active region pattern AA1a and the fourth active region pattern AA1b, respectively.

[0048] As a specific example, the first common gate conductive pattern GT1 defines a gate formed in the first active region pattern AA1a and the fourth active region pattern AA1b.

[0049] Similarly, the second common gate conductive pattern GT2 can be formed in the second active region pattern AA2a and the fifth active region pattern AA2b, and defines active devices with the second active region pattern AA2a and the fifth active region pattern AA2b, respectively; the third common gate conductive pattern GT3 can be formed in the third active region pattern AA3a and the sixth active region pattern AA3b, and defines active devices with the third active region pattern AA3a and the sixth active region pattern AA3b, respectively.

[0050] Understandably, based on actual process requirements, multiple first common gate conductive patterns GT1 can be formed above the first active region pattern AA1a and the fourth active region pattern AA1b, multiple second common gate conductive patterns GT2 can be formed above the second active region pattern AA2a and the fifth active region pattern AA2b, and multiple third common gate conductive patterns GT3 can be formed above the third active region pattern AA3a and the sixth active region pattern AA3b, thereby enabling the formation of multiple gates on the corresponding active region patterns.

[0051] Continue to refer to Figure 2 The gate conductive pattern can be disposed above the same active region pattern as the third conductive pattern and the fourth conductive pattern, respectively. As an optional example, for n gate conductive patterns formed above a certain active region pattern, (n+1) third conductive patterns or fourth conductive patterns can be formed above the same active region pattern, where n is an integer greater than or equal to 0.

[0052] For example, for the first common gate conductive pattern GT1 formed above the first active region AA1a and the fourth active region AA1b, two third conductive patterns PD-P3 and MD-P4 can be formed above the first active region AA1a, and two fourth conductive patterns PD-N3 and MD-N4 can be formed above the fourth active region AA1b.

[0053] It should be noted that the quantity relationship between the gate conductive pattern and the third or fourth conductive pattern formed in the same active region pattern is merely illustrative. The embodiments in this specification do not limit the number of gate conductive patterns and the third or fourth conductive patterns formed in the same active region pattern.

[0054] Continue to refer to Figure 2The standard cell layout 200 may further include: a first conductive pattern C1 formed on the first common gate conductive pattern GT1, located in the intermediate region III between the first region I and the second region II, and electrically contacting the first common gate conductive pattern GT1; a second conductive pattern C2 formed on the second common gate conductive pattern GT2, located in the intermediate region III between the first region I and the second region II, and electrically contacting the second common gate conductive pattern GT2; and a third conductive pattern C3 formed on the third common gate conductive pattern GT3, located in the intermediate region III between the first region I and the second region II, and electrically contacting the third common gate conductive pattern GT3.

[0055] The first conductive pattern C1, the second conductive pattern C2, and the third conductive pattern C3 can be formed of metal and are located in the zeroth metal layer M0. The first conductive pattern C1, the second conductive pattern C2, and the third conductive pattern C3 can connect the first metal layer M1 and the corresponding gate conductive pattern, so as to allow the signal to enter the gate of the active region from the first metal layer M1 or a higher metal layer.

[0056] It should be noted that the structure and positional relationships of the standard units described above are for illustrative purposes only and do not represent actual positional relationships. For example, Figure 2 The first central conductive pattern MD-P1 shown is located above the first conductive pattern 211. However, in the actual layout design, the first central conductive pattern MD-P1 is located below the first conductive pattern 211, and the first central conductive pattern MD-P1 is connected to the first conductive pattern 211 through the first connecting layer pattern VR1.

[0057] In specific implementation, the standard cell layout from bottom to top is as follows: the bottommost well region, followed by the active region within the well region, the active region pattern, the common gate conductive pattern and the auxiliary conductive pattern on the same layer, the first central conductive pattern, the second central conductive pattern, multiple third conductive patterns and the fourth conductive pattern on the same layer, the conduction pattern and multiple blocking layers on the same layer, the first connecting layer pattern and the second connecting layer pattern on the same layer, and the top layer consists of the first conductive pattern and the second conductive pattern.

[0058] It is understood that the above-described standard unit layout is merely an illustrative example. In practical applications, those skilled in the art can adaptively select and / or modify the standard unit layout provided in the embodiments of this specification according to actual needs and application scenarios. For example, the number of the first central conductive pattern and / or the second central conductive pattern can be reduced, or other structures can be added. Based on this, many different solutions can be derived, and the embodiments of this specification do not limit these derived solutions.

[0059] For example, to further reduce the number of photomasks used and eliminate process risks, refer to Figure 3 The schematic diagram shown in this specification illustrates another standard unit layout in an embodiment, such as... Figure 3 As shown, the standard cell layout 300 differs from the standard cell layout 200 in the following ways: In the standard cell layout 300, the first active region pattern AA1a and the fourth active region pattern AA1b do not share an auxiliary conductive pattern. Instead, the first active region pattern AA1a has an auxiliary conductive pattern AR1a1 overlapping on one side, and the fourth active region pattern AA1b has an auxiliary conductive pattern AR1b1 overlapping on one side. Similarly, the third active region pattern AA3a and the sixth active region pattern AA3b do not share an auxiliary conductive pattern. Instead, the third active region pattern AA3a has an auxiliary conductive pattern AR3a1 overlapping on one side, and the sixth active region pattern AR1b1 overlapping on one side. One side of the domain pattern AA3b overlaps with the auxiliary conductive pattern AR1b1. Compared to the standard cell layout 200, the standard cell layout 300 may also include multiple fifth conductive patterns (e.g., fifth conductive patterns MD-P9 and MD-P10) located in the first region I of the first conductive pattern 311 and partially overlapping with the first conductive pattern 311 and the first connected layer pattern VR1; multiple sixth conductive patterns (e.g., sixth conductive patterns MD-N9 and MD-N10) located in the second region II of the second conductive pattern 312 and partially overlapping with the second conductive pattern 312 and the second connected layer pattern VR2.

[0060] Therefore, by setting multiple fifth conductive patterns and multiple sixth conductive patterns, it is not necessary to perform masking on multiple active area patterns in the standard cell layout. The process is relatively simple, thus further reducing the number of masks used and eliminating process risks.

[0061] For example, the number of first and second center conductive patterns in a standard cell layout can be reduced. (See reference...) Figure 4 The schematic diagram shown in this specification illustrates another standard unit layout in an embodiment, such as... Figure 4 As shown, the difference between the standard cell layout 400 and the standard cell layout 200 in the aforementioned embodiments is that the number of the first central conductive pattern and the second central conductive pattern in the standard cell layout 400 is less than the number in the standard cell layout 200. Correspondingly, the number of the active region pattern, the auxiliary conductive pattern and the gate conductive pattern are all less than the number in the standard cell layout 200.

[0062] More specifically, in the standard cell layout 400, the first region I is adjacent to the first conductive pattern 411, and the plurality of active region patterns located in the first region I include a first active region pattern AA1a and a second active region pattern AA2a; the second region II is adjacent to the second conductive pattern 412, and the plurality of active region patterns located in the second region II include a third active region pattern AA4a and a fourth active region pattern AA4b, and the first active region pattern AA1a and the second active region pattern AA2a are symmetrically arranged on both sides of the first central conductive pattern MD-P1, and the third active region pattern AA4b and the fourth active region pattern AA5b are symmetrically arranged on both sides of the second central conductive pattern MD-N1. The functions of the first active region pattern AA1a, the second active region pattern AA2a, the third active region pattern AA4b, and the fourth active region pattern AA5b can be found in the description of the standard cell layout 200 of the aforementioned embodiment, and will not be elaborated here.

[0063] Continue to refer to Figure 4 The standard cell layout 400 may include a first central conductive pattern MD-P1 and a second central conductive pattern MD-N1. The first central conductive pattern MD-P1 may be located in the first active region pattern AA1a and the second active region pattern AA2a; the second central conductive pattern may be located in the third active region pattern AA4b and the fourth active region pattern AA5b. The functions of the first central conductive pattern MD-P1 and the second central conductive pattern MD-N1 can be found in the description of the standard cell layout 200 in the foregoing embodiment, and will not be elaborated upon here.

[0064] In specific implementations, to prevent mutual interference between active devices in the same region (e.g., the first region or the second region), a corresponding auxiliary conductive pattern can be set on one side of each active region pattern to isolate the multiple active region patterns.

[0065] More specifically, refer to Figure 4 An auxiliary conductive pattern AR1a1 may be provided on one side of the first active region pattern AA1a and the third active region pattern AA4b, an auxiliary conductive pattern AR1a2 may be provided on the other side of the first active region pattern AA1a, and an auxiliary conductive pattern AR1b2 may be provided on the other side of the third active region pattern AA4b; and an auxiliary conductive pattern AR2a1 may be provided on one side of the second active region pattern AA2a and the fourth active region pattern AA5b, an auxiliary conductive pattern AR2a2 may be provided on the other side of the second active region pattern AA2a, and an auxiliary conductive pattern AR2b2 may be provided on the other side of the fourth active region pattern AA5b.

[0066] Furthermore, the integrated circuit may include multiple standard cell layouts 400. To achieve isolation between different standard cell layouts 400, refer to... Figure 4 The auxiliary conductive patterns located on one side of the first active region pattern AA1a and the third active region pattern AA4b are continuous, that is, the auxiliary conductive patterns AR1a1 are simultaneously overlapped on the same side of the first active region pattern AA1a and the third active region pattern AA4b; the auxiliary conductive patterns located on one side of the second active region pattern AA2a and the fourth active region pattern AA5b are continuous, that is, the auxiliary conductive patterns AR2a1 are simultaneously overlapped on the same side of the second active region pattern AA2a and the fourth active region pattern AA5b.

[0067] Reference Figure 2 and Figure 4 , Figure 2 The standard cell layout 200 in the text may include 10 auxiliary conductive patterns, while Figure 4 The standard cell layout 400 in the model includes only 6 auxiliary conductive patterns.

[0068] Continue to refer to Figure 4 The standard cell layout 400 may further include a third conductive pattern (e.g., third conductive patterns MD-P3~MD-P6), which are located above the first active region pattern AA1a and the second active region pattern AA2a, respectively, and partially overlap with the first conductive pattern 411; and a fourth conductive pattern (e.g., third conductive patterns MD-N3~MD-N6), which are located above the third active region pattern AA4b and the fifth active region pattern AA5b, respectively, and partially overlap with the second conductive pattern 412.

[0069] Specifically, the third conductive patterns MD-P3 and MD-P4 can be located above the first active region pattern AA1a and partially overlap with the first conductive pattern 211; the third conductive patterns MD-P5 and MD-P6 can be located above the second active region pattern AA2a and partially overlap with the first conductive pattern 211; the fourth conductive patterns MD-N3 and MD-N4 can be located above the third active region pattern AA4b and partially overlap with the second conductive pattern 212; the fourth conductive patterns MD-N5 and MD-N6 can be located above the fourth active region pattern AA5b and partially overlap with the second conductive pattern 212. The functions and positions of the third and fourth conductive patterns in the standard cell can be found in the description of the standard cell layout 200 of the aforementioned embodiment, and will not be elaborated upon here.

[0070] Reference Figure 2 and Figure 4 , Figure 2The standard cell layout 200 can include 6 third conductive patterns and 6 fourth conductive patterns, while Figure 4 The standard cell layout 400 in the model includes only 4 third conductive patterns and 4 fourth conductive patterns.

[0071] Continue to refer to Figure 4 To isolate the third conductive pattern and the fourth conductive pattern, the standard unit layout 400 may further include an blocking layer MOC1 located on the third conductive patterns MD-P3 and MD-P4, a blocking layer MOC2 located on the third conductive patterns MD-P5 and MD-P6, a blocking layer MOC3 located in the intermediate region III, and a blocking layer MOC4 located on the fourth conductive patterns MD-N5 and MD-N6, and a blocking layer MOC5 located on the fourth conductive patterns MD-N3 and MD-N4, respectively.

[0072] Reference Figure 2 and Figure 4 , Figure 2 The standard cell layout 200 in the model can include 7 blocking layers, while Figure 4 The standard cell layout 400 in the model includes only 4 third conductive patterns and 5 blocking elements. Accordingly, Figure 4 The number of gate conductive patterns in the standard cell layout 400 is also less than Figure 2 Standard unit layout 200.

[0073] For details, please refer to... Figure 4 The standard cell layout 400 may further include at least one gate conductive pattern that overlaps with at least one active region pattern. For example, the standard cell layout 400 may include a gate conductive pattern that partially overlaps with a first active region AA1a, a second active region AA2a, a third active region AA4b, and a fourth active region AA5b.

[0074] In some embodiments, a single gate conductive pattern can be shared by the mutually symmetrical first active region pattern AA1a and third active region pattern AA4b. (Continuing to refer to...) Figure 4 At least one gate conductive pattern overlapping the first active region pattern AA1a and at least one gate conductive pattern overlapping the third active region pattern AA4b are continuous, forming a fourth common gate conductive pattern GT4 that overlaps the first active region pattern AA1a and the third active region pattern AA4b.

[0075] Similarly, the second active region pattern AA2a and the fourth active region pattern AA5b, which are symmetrical to each other, can share a single gate conduction pattern. (Continue to refer to...) Figure 4At least one gate conductive pattern overlapping the second active region pattern AA2a and at least one gate conductive pattern overlapping the fourth active region pattern AA5b are continuous, forming a fifth common gate conductive pattern GT5 that overlaps the second active region pattern AA2a and the fourth active region pattern AA5b. The fourth common gate conductive pattern GT4 and the fifth common gate conductive pattern GT5 can be found in the description of the first common gate conductive pattern GT1, the second common gate conductive pattern GT2, and the third common gate conductive pattern GT3 in the foregoing embodiments.

[0076] Continue to refer to Figure 4 The standard cell layout 400 may further include: a fourth conductive pattern C4, formed on the fourth common gate conductive pattern GT4, located in the intermediate region III between the first region I and the second region II, and electrically contacting the fourth common gate conductive pattern GT4; and a fifth conductive pattern C5, formed on the fifth common gate conductive pattern GT5, located in the intermediate region III between the first region I and the second region II, and electrically contacting the fifth common gate conductive pattern GT5. The functions of the fourth conductive pattern C4 and the fifth conductive pattern C5 are as described in the foregoing embodiments and will not be elaborated here.

[0077] In some embodiments of this specification, the above standard cell layout can be subjected to corresponding ECO processing to form a device with corresponding functions, so as to repair logic function defects or add new functions.

[0078] Reference Figure 5 The embodiment shown in this specification illustrates a standard cell layout for ECO, such as... Figure 5 As shown, modifications to the first metal layer M1 can be made through multiple connection patterns 221 to 228 and multiple through-holes (such as...). Figure 5 Modifications to the second metal layer M2 can be achieved by setting connection holes (as shown in the CT diagram). Figure 5 (as indicated by VT) and implemented with connection patterns 221, 223, 227 and 296.

[0079] Specifically, the standard unit layout 500 can achieve electrical connection between the third conductive patterns MD-P3, MD-P5, and MD-P63 and the first metal layer M1 through two vias CT and the connecting pattern 221. Specifically, the first via CT can be formed on and electrically connected to the third conductive pattern MD-P3; the second via CT can be formed on and electrically connected to the third conductive pattern MD-P5; and the connecting pattern 221 can be formed on these two vias CT and electrically connected to each of them.

[0080] Continue to refer to Figure 5 The standard unit layout 500 can also achieve electrical connection between the third conductive patterns MD-P7 and MD-P8 and the first metal layer M1 through two through-hole CTs and the connecting pattern 222. Specifically, the first through-hole CT can be formed on and electrically connected to the third conductive pattern MD-P7; the second through-hole CT can be formed on and electrically connected to the third conductive pattern MD-P8; and the connecting pattern 222 can be formed on both through-hole CTs and electrically connected to each of them.

[0081] Continue to refer to Figure 5 The standard unit layout 500 can also achieve electrical connection between the third conductive pattern MD-P4, MD-P6, the first central conductive pattern MD-P2, and the first metal layer M1 through three through-hole CTs and the connecting pattern 223. Specifically, the first through-hole CT is formed on the third conductive pattern MD-P4 and electrically connected to the third conductive pattern MD-P7; the second through-hole CT is formed on the third conductive pattern MD-P6 and electrically connected to it; the third through-hole CT is formed on the first central conductive pattern MD-P2 and electrically connected to it; and the connecting pattern 223 is formed on these three through-hole CTs and electrically connected to each of them.

[0082] Continue to refer to Figure 5 The standard unit layout 500 can also achieve electrical connection between the fourth conductive patterns MD-N4 and MD-N6 and the first metal layer M1 through two through-hole CTs and the connecting pattern 224. Specifically, the first through-hole CT is formed on and electrically connected to the fourth conductive pattern MD-N4; the second through-hole CT is formed on and electrically connected to the fourth conductive pattern MD-N6; and the connecting pattern 224 is formed on both through-hole CTs and electrically connected to each of them.

[0083] Continue to refer to Figure 5 The standard unit layout 500 can also directly achieve electrical connection between the fourth conductive pattern MD-N7, MD-N8, the second central conductive pattern MD-N2 and the first metal layer M1 through the connection pattern 225. The connection pattern 224 can be formed on the fourth conductive pattern MD-N7 and MD-N8 and the second central conductive pattern MD-N2.

[0084] Continue to refer to Figure 5The standard unit layout 500 can also achieve electrical connection between the fourth conductive pattern MD-N3, the second central conductive pattern MD-N1, and the first metal layer M1 through two through-holes CT and a connecting pattern 226. Specifically, the first through-hole is formed on and electrically connected to the fourth conductive pattern MD-N3; the second through-hole CT is formed on and electrically connected to the second central conductive pattern MD-N1; and the connecting pattern 226 is formed on both through-holes CT and electrically connected to both through-holes CT respectively.

[0085] Continue to refer to Figure 5 The standard unit layout 500 can also achieve electrical connection between the fourth conductive patterns MD-N7 and MD-N8 and the first metal layer M1 through two through-hole CTs and connecting patterns 228. Specifically, the first through-hole CT is formed on and electrically connected to the fourth conductive pattern MD-N7; the second through-hole CT is formed on and electrically connected to the fourth conductive pattern MD-N8; and connecting patterns 229 are formed on these two through-hole CTs and electrically connected to them respectively.

[0086] In addition, continue to refer to Figure 5 The standard unit layout 500 can achieve electrical connection between the first metal layer M1 and the second metal layer M2 through connection pattern 221, connection pattern 227, and two connection holes CT. The connection holes CT are formed at the intersection of the third conductive pattern MD-P6 and the connection pattern 221, and at the intersection of the fourth conductive pattern MD-N6 and the connection pattern 227, respectively, and are electrically connected to the connection pattern 221 and the connection pattern 227.

[0087] It is understood that the above ECO description of the standard unit layout is only an example. In actual implementation, the number and location of through holes (CT) and connecting holes (VT) can be flexibly set to meet different design requirements.

[0088] Continue to refer to Figure 5 , Figure 5 It also defines the input and output terminals of the standard cell layout. Specifically, such as... Figure 5 The first input port A1 can be set above the first conductive pattern C1, the second input port A2 can be set above the second conductive pattern C2, and the output port ZN can be set above the first metal layer M1.

[0089] It should be noted that since the first central conductive pattern, the second central conductive pattern, the first conductive pattern disposed on the first common gate conductive pattern, the second conductive pattern disposed on the second common gate conductive pattern, the third conductive pattern disposed on the third common gate conductive pattern, as well as the first connecting layer pattern, the second connecting layer pattern, and multiple blocking layers are fixedly disposed inside the standard cell layout, it is not necessary to process the layers containing the above patterns during ECO processing. By setting the positions of the connecting holes VT and through holes CT in the standard cell layout, their connection relationship with the first metal layer M1 and the second metal layer M2 located above the first metal layer M1 can be changed, thus reducing the number of photomasks used.

[0090] This specification also provides an integrated circuit that may include a plurality of standard cell layouts, wherein the standard cell layouts may be as described in the foregoing embodiments. Figure 2 The standard cell layout described in any one of the claims, wherein multiple standard cell layouts are connected according to a preset connection relationship.

[0091] To enable those skilled in the art to better understand and implement the integrated circuits in the embodiments of this specification, a detailed description is provided below with reference to the accompanying drawings and specific application examples.

[0092] Reference Figure 6 The schematic diagram of an integrated circuit structure shown in the embodiment of this specification is as follows: Figure 6 As shown, integrated circuit IC1 may include multiple standard cell layouts (e.g., Figure 6 The example shows m auxiliary conductive patterns (where m is an integer greater than 1), and the outermost auxiliary conductive patterns of the plurality of standard cell layouts overlap and are connected to each other. The description of the standard cell layout can be found above.

[0093] To facilitate understanding, the following example illustrates the connection between the first and second standard cell layouts. (Combined with...) Figure 2 and Figure 6 The outermost auxiliary conductive pattern AR3a1 of the first standard cell layout can overlap and connect with the outermost auxiliary conductive pattern AR1a1 of the second standard cell layout.

[0094] Similarly, the outermost auxiliary conductive pattern AR3a1 of the (m-1)th standard cell layout can overlap and connect with the outermost auxiliary conductive pattern AR1a1 of the mth standard cell layout.

[0095] Therefore, by overlapping the auxiliary conductive patterns located on the outermost sides of multiple standard cell layouts, multiple series-connected functional devices can be formed simultaneously during ECO. For example, multiple inverters can be formed simultaneously.

[0096] In practical implementation, when performing an ECO (Engineering Changeover), it may be necessary to form more complex functional devices (e.g., a data selector MUX). Therefore, embodiments of this specification also provide a schematic diagram of another integrated circuit structure, such as... Figure 7 As shown, integrated circuit IC2 may include multiple mirror-symmetric standard cell layouts, and the well regions and first conductive patterns of the multiple mirror-symmetric standard cell layouts are respectively overlapped and connected to each other. The description of the standard cell layouts can be found in the foregoing.

[0097] It should be noted that the aforementioned integrated circuit IC2 can be extended horizontally. For example, multiple identical integrated circuit IC2s can be arranged according to... Figure 6 The connection shown connects multiple identical integrated circuits IC2 horizontally.

[0098] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A standard unit layout, characterized in that, include: Substrate, including well region; The active region, located within the well region, includes a channel layer, a gate, a source / drain, and a conductive layer; A first conductive pattern is located above the well region; The second conductive pattern is located on the side opposite to the first conductive pattern; Multiple active region patterns are located in a first region and a second region between the first conductive pattern and the second conductive pattern, and each active region pattern is isolated from the others; The first central conductive pattern is located between the adjacent active region patterns in the first region and partially overlaps with the first conductive pattern. The second central conductive pattern is located between the adjacent active region patterns in the second region and partially overlaps with the second conductive pattern. Multiple auxiliary conductive patterns are located on one side of one of the multiple active patterns, and are used to isolate the multiple active patterns. The first connected layer pattern is located below the first conductive pattern and overlaps with the first central conductive pattern; The second connected layer pattern is located below the second conductive pattern and overlaps with the second central conductive pattern.

2. The standard unit layout according to claim 1, characterized in that, The first central conductive pattern is isolated from the second central conductive pattern.

3. The standard unit layout according to claim 1, characterized in that, The first region is adjacent to the first conductive pattern, and the multiple active region patterns located in the first region include a first active region pattern, a second active region pattern, and a third active region pattern. The second region is adjacent to the second conductive pattern, and the multiple active region patterns located in the second region include a fourth active region pattern, a fifth active region pattern, and a sixth active region pattern.

4. The standard unit layout according to claim 3, characterized in that, The first central conductive pattern includes a plurality of first central conductive sub-patterns, which are respectively located between the first active region pattern and the second active region pattern, and between the second active region pattern and the third active region pattern; The plurality of second central conductive patterns include a plurality of second central conductive sub-patterns, and are respectively located between the fourth active region pattern and the fifth active region pattern, and between the fifth active region pattern and the sixth active region pattern.

5. The standard unit layout according to claim 3, characterized in that, Also includes: Multiple third conductive patterns are respectively located above the first active region pattern, the second active region pattern and the third active region pattern, and partially overlap with the first conductive pattern; Multiple fourth conductive patterns are located above the fourth active region pattern, the fifth active region pattern, and the sixth active region pattern, respectively, and partially overlap with the second conductive pattern.

6. The standard unit layout according to claim 5, characterized in that, Also includes: Multiple blocking layers are respectively located on the multiple third conductive patterns and fourth conductive patterns, and in the intermediate region between the first region and the second region, for isolating the third conductive patterns and fourth conductive patterns.

7. The standard unit layout according to claim 3, characterized in that, Also includes: At least one gate conductive pattern that overlaps with at least one active region pattern.

8. The standard unit layout according to claim 6, characterized in that, At least one gate conductive pattern that overlaps with the first active region pattern and at least one gate conductive pattern that overlaps with the fourth active region pattern are continuous, forming a first common gate conductive pattern that overlaps the first active region pattern and the fourth active region pattern. At least one gate conductive pattern overlapping the second active region pattern and at least one gate conductive pattern overlapping the fifth active region pattern are continuous, forming a second common gate conductive pattern that overlaps the first active region pattern and the fourth active region pattern. At least one gate conductive pattern overlapping the third active region pattern and at least one gate conductive pattern overlapping the sixth active region pattern are continuous, forming a third common gate conductive pattern that overlaps the first active region pattern and the fourth active region pattern.

9. The standard unit layout according to claim 8, characterized in that, Also includes: A first conductive pattern is formed on the first common gate conductive pattern, located in the middle region between the first region and the second region, and is electrically contacted with the first common gate conductive pattern. The second conductive pattern is formed on the second common gate conductive pattern, located in the middle region between the first region and the second region, and is in electrical contact with the second common gate conductive pattern; A third conductive pattern is formed on the third common gate conductive pattern, located in the middle region between the first region and the second region, and is in electrical contact with the third common gate conductive pattern.

10. The standard unit layout according to claim 3, characterized in that, The auxiliary conductive pattern located on one side of the first active region pattern and the fourth active region pattern is continuous. The auxiliary conductive pattern located on one side of the patterns of the third active region and the sixth active region is continuous.

11. The standard cell layout according to any one of claims 1-10, characterized in that, Also includes: Multiple fifth conductive patterns are located in a first region of the first conductive pattern and partially overlap with the first conductive pattern and the first connected layer pattern. Multiple sixth conductive patterns are located in the second region of the second conductive pattern and partially overlap with the second conductive pattern and the second connected layer pattern.

12. The standard unit layout according to claim 1, characterized in that, The first region is adjacent to the first conductive pattern, and the plurality of active region patterns include a first active region pattern and a second active region pattern. The second region is adjacent to the second conductive pattern, and the plurality of active region patterns include a third active region pattern and a fourth active region pattern.

13. The standard unit layout according to claim 12, characterized in that, The first central conductive pattern is located between the first active region pattern and the second active region pattern; The second central conductive pattern is located between the third active region pattern and the fourth active region pattern.

14. The standard unit layout according to claim 13, characterized in that, Also includes: The third conductive pattern is located above the first active region pattern and the second active region pattern, and partially overlaps with the first conductive pattern. The fourth conductive pattern is located above the third active region pattern and the fourth active region pattern, and partially overlaps with the second conductive pattern.

15. The standard unit layout according to claim 13, characterized in that, Also includes: At least one gate conductive pattern that overlaps with at least one active region pattern.

16. The standard cell layout according to claim 15, characterized in that, At least one gate conductive pattern that overlaps with the first active region pattern and at least one gate conductive pattern that overlaps with the third active region pattern are continuous, forming a fourth common gate conductive pattern that overlaps the first active region pattern and the third active region pattern. At least one gate conductive pattern overlapping the second active region pattern and at least one gate conductive pattern overlapping the fourth active region pattern are continuous, forming a fifth common gate conductive pattern that overlaps the first active region pattern and the fourth active region pattern.

17. The standard cell layout according to claim 16, characterized in that, Also includes: A fourth conductive pattern is formed on the fourth common gate conductive pattern, located in the middle region between the first region and the second region, and is in electrical contact with the fourth common gate conductive pattern; A fifth conductive pattern is formed on the fifth common gate conductive pattern, located in the middle region between the first region and the second region, and is in electrical contact with the fifth common gate conductive pattern.

18. An integrated circuit, characterized in that, It includes multiple standard unit layouts, wherein the standard unit layout is the standard unit layout described in any one of claims 1-10, wherein the multiple standard unit layouts are connected according to a preset connection relationship.

19. The integrated circuit according to claim 18, characterized in that, The auxiliary conductive patterns located on the outermost side of the plurality of standard cell layouts overlap and connect with each other.

20. The integrated circuit according to claim 19, characterized in that, include: Multiple mirror-symmetric standard cell layouts, wherein the well regions and the first conductive patterns of the multiple mirror-symmetric standard cell layouts overlap and are connected to each other.

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