Standard cell layout and integrated circuit

Abstract

The standard cell layout comprises a well region, a first conductive pattern located above the well region, a second conductive pattern located on the opposite side of the first conductive pattern, a plurality of active region patterns located in a first region and a second region between the first conductive pattern and the second conductive pattern, and part of the active region patterns are located above the well region, a third conductive pattern partially overlapping the first conductive pattern, a fourth conductive pattern partially overlapping the second conductive pattern, a plurality of gate conductive patterns respectively located above the plurality of active region patterns, a plurality of cutting patterns for cutting the plurality of active region patterns and part of the gate conductive patterns located above the plurality of active region patterns, a first communication layer pattern located below the first conductive pattern, and a second communication layer pattern located below the second conductive pattern. By using the above scheme, the area of the standard cell layout can be reduced, and the size of the integrated circuit can be reduced.

Description

Technical Field

[0001] This specification relates to the field of semiconductor manufacturing technology, and in particular to a standard cell layout and integrated circuit. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, integrated circuits (e.g., application-specific integrated circuits, ASICs) are becoming increasingly larger, with their internal gates potentially reaching millions. Although they undergo verification processes such as logic analysis and simulation before tape-out, it is still difficult to cover all functional combinations. Chips after tape-out may have some functional defects or some functions may not meet customer requirements.

[0003] Currently, Engineering Change Order (ECO) techniques are typically used to address the aforementioned functional defects or add new functions to meet customer needs. ECO refers to altering the metal traces of the chip after fabrication to change the original connections, thereby repairing logic functionality or adding new features.

[0004] However, when performing ECO, the standard cell layout used in existing solutions has a large area, which cannot meet the requirements for small integrated circuit size. Summary of the Invention

[0005] The problem addressed by the embodiments in this specification is to provide a standard cell layout and integrated circuit that can reduce the area of ​​the standard cell layout, thereby reducing the size of the integrated circuit.

[0006] First, this specification provides a standard cell layout, including:

[0007] Trap area;

[0008] A first conductive pattern is located above the well region;

[0009] The second conductive pattern is located on the side opposite to the first conductive pattern;

[0010] Multiple active region patterns are located in a first region and a second region between the first conductive pattern and the second conductive pattern, and some of the active region patterns are located above the well region;

[0011] The third conductive pattern is located above the active region pattern adjacent to the first region and partially overlaps with the first conductive pattern.

[0012] The fourth conductive pattern is located above the active region pattern adjacent to the second region and partially overlaps with the second conductive pattern.

[0013] Multiple gate conductive patterns are respectively located above the multiple active region patterns and partially overlap with the active region patterns;

[0014] Multiple cutting patterns are used to cut the multiple active region patterns and a portion of the gate conductive pattern located above the multiple active region patterns;

[0015] The first connected layer pattern is located below the first conductive pattern and partially overlaps with the third conductive pattern;

[0016] The second connected layer pattern is located below the second conductive pattern and partially overlaps with the fourth conductive pattern.

[0017] Accordingly, embodiments of this specification also provide an integrated circuit including a plurality of standard cell layouts, wherein the standard cell layouts are the standard cell layouts described in any of the foregoing embodiments, and the plurality of standard cell layouts are connected according to a preset connection relationship.

[0018] Compared with the prior art, the technical solutions of the embodiments in this specification have the following advantages:

[0019] In the standard cell layout provided in the embodiments of this specification, the number of gate conductive patterns in the standard cell layout can be reduced by cutting the multiple active area patterns and the partial gate conductive patterns located above the multiple active area patterns using multiple cutting patterns. Compared with the standard cell layout in the prior art, the area of ​​the entire standard cell layout can be reduced and the size of the integrated circuit can be reduced when completing the same circuit layout design by reducing the area corresponding to the contact spacing between the gate conductive patterns in the standard cell layout. Attached Figure Description

[0020] Figure 1 A schematic diagram of a standard unit layout is shown;

[0021] Figure 2 A schematic diagram of a standard cell layout in an embodiment of this specification is shown;

[0022] Figure 3 This specification shows a schematic diagram of a standard cell layout for performing ECO in an embodiment of the present specification;

[0023] Figure 4 A schematic diagram of the structure of an integrated circuit in an embodiment of this specification is shown;

[0024] Figure 5 A schematic diagram of another integrated circuit structure is shown in an embodiment of this specification. Detailed Implementation

[0025] As the background technology shows, the standard cell layout currently used in ECO (Engineering, Procurement, and Construction) has a relatively large area, which cannot meet the requirements for small integrated circuit dimensions. This paper analyzes the reasons for the large area of ​​current standard cell layouts, using a structural diagram of one such layout.

[0026] Reference Figure 1 The diagram illustrates a standard cell layout. The standard cell layout 100 may include a first conductive pattern 111, a second conductive pattern 112; a first active region pattern OD1a and a second active region pattern OD2a disposed in a first region I between the first conductive pattern 111 and the second conductive pattern 112; a third active region pattern OD1b and a fourth active region pattern OD2b disposed in a second region II; a first conductive center pattern MD-P3 disposed between the first active region pattern OD1a and the second active region pattern OD2a; and a third active region pattern MD-P3 disposed in the third active region pattern OD1a. The second central conductive pattern MD-N3 of OD1b and the fourth active region pattern OD2b, and the first conductive central pattern MD-P3 partially overlaps with the first conductive pattern 111, and the second central conductive pattern MD-N3 partially overlaps with the second conductive pattern 112; the additional conductive pattern PD1a1 overlaps with the first active region pattern OD1a, the additional conductive pattern PD2a1 overlaps with the second active region pattern OD2a, the additional conductive pattern PD2b1 overlaps with the third active region pattern OD1b, and the additional conductive pattern PD2b2 overlaps with the fourth active region pattern OD2a.

[0027] Continue to refer to Figure 1 The standard cell layout 100 may further include a common gate conductive pattern Poly1 overlapping the first active region pattern OD1a and the second active region pattern OD2a, and a common gate conductive pattern Poly2 overlapping the third active region pattern OD1b and the fourth active region pattern OD2b, and conductive patterns MP1 and MP2 electrically connected to the common gate conductive pattern Poly1 and the common gate conductive pattern Poly2; a plurality of third conductive patterns MD-P1, MD-P2, MD-P4, MD-P5 and MD-N1, MD-N2, MD-N4, MD-N5; and a first via V0-P for connecting the first conductive center pattern MD-P3 to the first conductive pattern 111, and a second via V0-N for connecting the second conductive center pattern MD-N3 to the second conductive pattern 112.

[0028] However, the standard cell layout 100 in the above embodiments uses a double diffusion break (DDB) structure to isolate the active region. Compared with a single diffusion break (SDB) structure, it requires an additional area corresponding to the contact spacing, and Figure 1 The additional conductive pattern PD1a1 and the common gate conductive pattern Poly1, the common gate conductive pattern Poly1 and the additional conductive pattern PD1a1, the additional conductive pattern PD1a1 and the additional conductive pattern PD2a1, the additional conductive pattern PD2a1 and the common gate conductive pattern Poly2, and the common gate conductive pattern Poly2 and the additional conductive pattern PD2a1 constitute the five contact pitches of the standard cell layout 100. In other words, the standard cell layout 100 includes the area corresponding to the six contact pitch intervals, resulting in a large area of ​​the standard cell layout 100.

[0029] To address the aforementioned issues, in the standard cell layout provided in the embodiments of this specification, the number of gate conductive patterns in the standard cell layout is reduced by cutting the multiple active area patterns and the portion of the gate conductive patterns located above the multiple active area patterns using multiple cutting patterns. Compared to the standard cell layout in existing solutions, the area of ​​the entire standard cell layout can be reduced by decreasing the area corresponding to the contact spacing between the gate conductive patterns in the standard cell layout when completing the same circuit layout design, thereby reducing the size of the integrated circuit.

[0030] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the standard unit layout of the embodiments of this specification will be described in detail below with reference to the accompanying drawings.

[0031] Reference Figure 2The schematic diagram shown in this specification illustrates a standard cell layout 200. The standard cell layout 200 may include a well region 210; a first conductive pattern 211 located above the well region 210; a second conductive pattern 212 located on the side opposite to the first conductive pattern 211; multiple active region patterns (e.g., the first active region pattern AA1 and the second active region pattern AA2 shown in the figure) located in a first region I and a second region II between the first conductive pattern 211 and the second conductive pattern 212, with some of the active region patterns located above the well region 211 (e.g., the first active region pattern AA1 may be located above the well region 210); a third conductive pattern MD-P1 located above the active region pattern adjacent to the first region I and partially overlapping with the first conductive pattern 211; a fourth conductive pattern MD-P2 located above the active region pattern adjacent to the second region II and partially overlapping with the second conductive pattern 212; and multiple gate conductive patterns ( Figure 1 (Not shown), respectively located above the plurality of active region patterns and partially overlapping the active region patterns; a plurality of cutting patterns (e.g. Figure 1 The cut patterns AR1 to AR3 shown are used to cut the plurality of active region patterns and a portion of the gate conductive pattern located above the plurality of active region patterns; the first connecting layer pattern VR1 is located below the first conductive pattern 211 and partially overlaps with the third conductive pattern MD-P1; the second connecting layer pattern VR2 is located below the second conductive pattern 212 and partially overlaps with the fourth conductive pattern MD-P2.

[0032] In specific implementations, different types of well regions 210 can be obtained by diffusing different ions on the substrate. For example, well region 210 can be an N-well region, which can be obtained by diffusing N-type ions on a P-type substrate, or a P-well region can be obtained by diffusing P-type ions on an N-type substrate. The embodiments in this specification do not limit the type of well region 210, which can be obtained by implanting different ions on the substrate according to specific process requirements.

[0033] Continue to refer to Figure 2 In some embodiments of this specification, the lateral dimension of the well region 210 in the standard cell layout 200 is the largest, so some areas of the well region 210 do not form any pattern.

[0034] In other examples, the lateral dimension of the well region 210 in the standard cell layout 200 may be the same as the lateral dimension of the first conductive pattern 211 and the first active region pattern AA1.

[0035] In some embodiments of this specification, the first conductive pattern 211 can serve as a power line VDD, and the third conductive pattern MD-P1 and the first metal layer M1 are realized through the first connecting layer pattern VR1. Figure 2 (Not shown) connection; the second conductive pattern 212 can serve as a ground wire VSS, and through the second connecting layer pattern VR2, the fourth conductive pattern MD-P2 is connected to the first metal layer M1.

[0036] In a specific implementation, the first conductive pattern 211 and the second conductive pattern 212 can be formed on the first metal layer M1.

[0037] In actual manufacturing processes, the number of active area patterns can be flexibly set according to specific requirements. In some embodiments of this specification, reference continues to be made to... Figure 2 The first region I is adjacent to the first conductive pattern 211, and the active region pattern located in the first region I includes the first active region pattern AA1; the second region II is adjacent to the second conductive pattern 212, and the active region pattern located in the second region II includes the second active region pattern AA2. That is, the standard unit layout in the embodiments of this specification may include two active region patterns. In other embodiments, it may also include four, five, or more active region patterns.

[0038] In specific implementations, at least one of the multiple active area patterns can serve as an active device in the standard cell layout 200. For example, any one or more of the first active area pattern AA1 and the second active area pattern AA2 can serve as active devices in the standard cell layout 200.

[0039] As a specific example, any one of the multiple active region patterns can serve as a device such as a metal-oxide-semiconductor field-effect transistor (MOSFET) or a complementary metal-oxide-semiconductor (CMOS) transistor in the standard cell layout 200.

[0040] In specific implementations, the P-region of a PMOS transistor can be formed in the first active region pattern AA1, and the N-region of an NMOS transistor can be formed in the second active region pattern AA2. Alternatively, the N-region of an NMOS transistor can be formed in the first active region pattern AA1, and the P-region of a PMOS transistor can be formed in the second active region pattern AA2. The embodiments in this specification do not limit the type of transistor formed by the active region patterns.

[0041] In some embodiments of this specification, the active region patterns in the plurality of active region patterns are isolated from each other. For example, the first active region pattern AA1 located in the first region I and the second active region pattern AA2 located in the second region II are isolated from each other.

[0042] As a specific example, the first active region pattern AA1 and the second active region pattern AA2 can be isolated by a single diffusion region cut-off structure.

[0043] In actual manufacturing processes, the number of the third and fourth conductive patterns can be flexibly set according to specific requirements. In some embodiments of this specification, reference continues to be made to... Figure 2 The standard cell layout 200 may include a third conductive pattern MD-P1 and a fourth conductive pattern MD-P1, wherein the third conductive pattern MD-P1 may be located above the first active region pattern AA1, and the fourth conductive pattern MD-P1 may be located above the second active region pattern AA2.

[0044] It is understood that, based on the needs of actual scenarios, the standard unit layout 200 may also include multiple third conductive patterns and multiple fourth conductive patterns. The embodiments in this specification do not limit the number of third conductive patterns and fourth conductive patterns.

[0045] In the embodiments described in this specification, reference continues to be made to... Figure 2 The third conductive pattern MD-P1 and the fourth conductive pattern MD-P2 are isolated. By isolating them from each other, subsequent devices (such as NMOS and PMOS transistors) can receive signals separately, avoiding crosstalk between signals.

[0046] In some embodiments of this specification, the first connecting layer pattern VR1 can electrically connect the third conductive pattern MD-P1 to the power line VDD, and the second connecting layer pattern VR2 can electrically connect the fourth conductive pattern MD-P2 to the ground line VSS. Thus, through the first connecting layer pattern VR1 and the second connecting layer pattern VR2, an electrical connection between the external power supply and the standard cell layout 200 can be achieved.

[0047] In practical implementation, when performing ECO on standard unit 200, the active area pattern, as the region forming the active device, needs to be electrically connected to the external circuit. Based on this, continue referring to... Figure 2 The standard cell layout 200 may further include a plurality of fifth conductive patterns (e.g., fifth conductive patterns MD-P31 to MD-P33), which are respectively located above the first active region pattern AA1 and on both sides of the third conductive pattern MD-P1, and partially overlap with the first conductive pattern 211; and a plurality of sixth conductive patterns (e.g., sixth conductive patterns MD-P41 to MD-P43), which are respectively located above the second active region pattern AA2 and on both sides of the fourth conductive pattern MD-P2, and partially overlap with the second conductive pattern 212.

[0048] Specifically, the fifth conductive patterns MD-P31 and MD-P33 can both be located above the first active region pattern AA1 and on both sides of the third conductive pattern MD-P1, respectively. The fifth conductive pattern MD-P31 can be located to the left of the third conductive pattern MD-P1 and the fifth conductive pattern MD-P33 can be located to the right of the third conductive pattern MD-P1, and both can partially overlap with the first conductive pattern 211.

[0049] The sixth conductive patterns MD-P41 and MD-P43 can both be located above the second active region pattern AA2 and on both sides of the fourth conductive pattern MD-P2, respectively. The sixth conductive pattern MD-P41 can be located to the left of the fourth conductive pattern MD-P2 and the sixth conductive pattern MD-P43 can be located to the right of the fourth conductive pattern MD-P2. Both can partially overlap with the second conductive pattern 212.

[0050] Therefore, by means of the aforementioned plurality of fifth conductive patterns and plurality of sixth conductive patterns, the electrical connection between the active device in the active region pattern and the external circuit can be defined.

[0051] In some embodiments, the plurality of fifth conductive patterns may not overlap with the first conductive pattern, and the plurality of sixth conductive patterns may not overlap with the second conductive pattern.

[0052] In specific implementation, multiple fifth conductive patterns and multiple sixth conductive patterns can be formed of metal and can be formed in the zero metal layer M0, which can serve as the lowest metal layer above the active device in the standard cell layout.

[0053] In some embodiments of this specification, reference continues to be made to... Figure 2 The number of fifth conductive patterns on both sides of the third conductive pattern MD-P1 is different. For example, the right side of the third conductive pattern MD-P1 may have only one fifth conductive pattern MD-P33, while the left side may include two fifth conductive patterns MD-P31 and MD-P32.

[0054] Furthermore, the number of sixth conductive patterns located on both sides of the fourth conductive pattern MD-P2 can also be different. For example, the right side of the fourth conductive pattern MD-P2 may have only one sixth conductive pattern MD-P43, while the left side may have two sixth conductive patterns MD-P41 and MD-P42.

[0055] By making the fifth and sixth conductive patterns asymmetrical along the third and fourth conductive patterns, the number of the required fifth and sixth conductive patterns can be reduced, thereby reducing the area of ​​the standard cell layout.

[0056] In some other examples, the number of fifth conductive patterns on both sides of the third conductive pattern can be the same, and the number of sixth conductive patterns on both sides of the fourth conductive pattern can also be the same. This specification does not limit this, as long as the number of fifth and sixth conductive patterns meets the design requirements.

[0057] In some embodiments of this specification, reference continues to be made to... Figure 2 The standard cell layout 200 may also include a plurality of blocking layers (e.g., blocking layers MOC1 to MOC5) located above a portion of the plurality of fifth conductive patterns and the plurality of sixth conductive patterns, respectively, and an intermediate region III located between the first region I and the second region II, for blocking the fifth conductive patterns and / or the sixth conductive patterns.

[0058] For example, the blocking layer M0C1 can be located in a portion of the fifth conductive patterns MD-P31 and MD-P32 (e.g. Figure 2 The blocking layer MOC2 is located above a portion of the fifth conductive pattern MD-P33 (shown as the region between the first active region AA1 and the first connected layer pattern VR1), and is used to block the fifth conductive patterns MD-P31 and MD-P32, respectively; the blocking layer MOC2 can be located above a portion of the fifth conductive pattern MD-P33, and is used to block the fifth conductive pattern MD-P33; the blocking layer MOC3 can be located in the middle region III, and is used to block the fifth conductive pattern MD-P31 and the sixth conductive pattern MD-P41, the fifth conductive pattern MD-P32 and the sixth conductive pattern MD-P42, and the fifth conductive pattern MD-P33 and the sixth conductive pattern MD-P43; the blocking layer MOC4 can be located in a portion of the sixth conductive patterns MD-P41 and MD-P42 (e.g., Figure 2 The region above the second active region AA2 and the region between the second connected layer pattern layer VR2 is used to block the sixth conductive patterns MD-P41 and MD-P42, respectively; the blocking layer M0C5 can be located above a portion of the sixth conductive pattern MD-P43 to block the fifth conductive pattern MD-P33.

[0059] Through the aforementioned multiple blocking layers, on the one hand, the fifth and sixth conductive patterns can be made discontinuous and isolated from each other, thus avoiding crosstalk between signals; on the other hand, the fifth and sixth conductive patterns can be cut into portions of their lengths, such that the length of the fifth conductive pattern is less than the length of the third conductive pattern and the length of the sixth conductive pattern is less than the length of the fourth conductive pattern.

[0060] In other examples, the fifth, sixth, third, and fourth conductive patterns may also have the same length. This specification does not limit this, as long as the lengths of the fifth, sixth, third, and fourth conductive patterns meet the design requirements.

[0061] As previously described, the standard cell layout 200 may include a plurality of gate conductive patterns, and the plurality of gate conductive patterns may be located above the plurality of active region patterns and partially overlap with the active region patterns. For example, the standard cell layout 200 may include a gate conductive pattern located above and partially overlapping with the first active region pattern AA1, and a gate conductive pattern located above and partially overlapping with the second active region pattern AA2.

[0062] In some examples, the first active region pattern AA1 and the second active region pattern AA1, with the intermediate region III as the axis of symmetry, can share a common gate conduction pattern. (Continue to refer to...) Figure 2 At least one gate conductive pattern overlapping the first active region pattern AA1 and at least one gate conductive pattern overlapping the second active region pattern AA2A are continuous, forming at least one common gate conductive pattern overlapping the first active region pattern AA1 and the second active region pattern AA2 (e.g., Figure 2 The two common gate conductive patterns GT1 and GT2 are shown in the figure.

[0063] In some embodiments of this specification, common gate conductive patterns GT1 and GT2 may be formed over corresponding active region patterns and configured to jointly define active devices in standard cell layout 200 with the corresponding active region patterns.

[0064] For example, common gate conductive patterns GT1 and GT2 can be formed above the first active region pattern AA1 and the second active region pattern AA2, and define active devices with the first active region pattern AA1 and the second active region pattern AA2, respectively.

[0065] As a specific example, the common gate conductive pattern GT1 may define a gate formed in the first active region pattern AA1 and the second active region pattern AA2.

[0066] Understandably, multiple common gate conductive patterns can be formed above the first active region pattern AA1 and the second active region pattern AA2 according to actual process requirements, thereby enabling the formation of multiple gates on the corresponding active region patterns.

[0067] In some embodiments of this specification, the standard cell layout may further include: at least one conductive pattern formed on a corresponding common gate conductive pattern and located in an intermediate region between the first region and the second region, and electrically contacting the corresponding common gate conductive pattern.

[0068] As a specific example, such as Figure 2As shown, the standard cell layout 200 may include conductive patterns C1 and C2, wherein conductive pattern C1 may be formed on a common gate conductive pattern GT1 and located in the intermediate region III between the first region I and the second region II, and is electrically contacted with the common gate conductive pattern GT1; conductive pattern C2 may be formed on the common gate conductive pattern GT2 and located in the intermediate region III between the first region I and the second region II, and is electrically contacted with the common gate conductive pattern GT2.

[0069] In a specific implementation, the conductive patterns C1 and C2 can be formed of metal and located on the zeroth metal layer M0. Through the conductive patterns C1 and C2, the first metal layer M1 and the corresponding gate conductive pattern can be connected to allow the signal to enter the gate formed on the gate conductive pattern from the first metal layer M1 or a higher metal layer.

[0070] In some embodiments of this specification, the standard cell layout 200 may include multiple (more than two) gate conductive patterns, not necessarily... Figure 2 The common gate conductive patterns GT1 and GT2 shown result in a standard cell layout 200 with a large area. Therefore, some of the common gate conductive patterns can be removed, leaving only the gate conductive patterns GT1 and GT2 at the corresponding positions.

[0071] In specific implementation, to improve the efficiency of removing part of the common gate conductive pattern, we continue to refer to... Figure 2 The plurality of cutting patterns are continuous between the plurality of active region patterns. For example, cutting patterns AR1, AR2 and AR3 are continuous between the first active region pattern AA1 and the second active region pattern AA2. By using a plurality of continuous cutting patterns, the common gate conductive pattern at a preset position can be removed in one go.

[0072] In other words, the positions of the cutting patterns AR1, AR2, and AR3 were previously occupied by common gate conductive patterns. Therefore, the standard cell layout 200 can actually include five common gate conductive patterns. Correspondingly, four contact pitches can be formed between the five common gate conductive patterns. Therefore, the standard cell layout 200 can include the area corresponding to the four contact pitches, compared to... Figure 1 The standard cell layout 100 in the circuit can reduce the area corresponding to the contact spacing by 33% when completing the same circuit layout design.

[0073] Therefore, by adopting the above standard cell layout, the area of ​​the entire standard cell layout can be reduced, thereby reducing the size of the integrated circuit.

[0074] Moreover, the continuity of multiple cutting patterns among the multiple active area patterns enables isolation between active area patterns at different locations in the same region and mutual isolation between different standard unit layouts, thus avoiding crosstalk between signals.

[0075] For example, continue to refer to Figure 2 After being cut by cutting patterns AR1, AR2 and AR3, the first active region is divided into two first sub-active region patterns. Since cutting pattern AR2 is continuous, isolation between the two first sub-active region patterns can be achieved, and cutting patterns AR1 and AR3 can achieve isolation between the standard cell layout and other standard cell layouts.

[0076] It should be noted that the structure and positional relationships of the standard units described above are for illustrative purposes only and do not represent actual positional relationships. For example, Figure 2 The third conductive pattern MD-P1 shown is located above the first conductive pattern 211. However, in the actual layout design, the third conductive pattern MD-P1 is located below the first conductive pattern 211, and the third conductive pattern MD-P1 is connected to the first conductive pattern 211 through the first connecting layer pattern VR1.

[0077] In a specific implementation, the standard cell layout 200, from bottom to top, consists of the bottommost well region 210, followed by active region patterns AA1 and AA2, common gate conductive patterns GT1 and GT2 on the same layer, cut patterns AR1 to AR3, third conductive patterns MD-P1, fourth conductive patterns MD-P2, fifth conductive patterns MD-P31 to MD-P33, sixth conductive patterns MD-P31 to MD-P33 on the same layer, conduction patterns C1 and C2 on the same layer, blocking layers MOC1 to MOC5, first connecting layer pattern VR1 and second connecting layer pattern VR2 on the same layer, and the top layer consists of the first conductive pattern 211 and the second conductive pattern 212.

[0078] It is understood that the above standard unit layout is merely an illustrative example. In practical applications, those skilled in the art can adaptively select and / or modify the standard unit layout provided in the embodiments of this specification according to actual needs and application scenarios. For example, increasing the number of third conductive patterns and / or the number of third conductive patterns, or increasing the length of the fifth and sixth conductive patterns. Based on this, many different solutions can be derived, and the embodiments of this specification do not limit these derived solutions.

[0079] In some embodiments of this specification, the above standard cell layout can be subjected to corresponding ECO processing to form a device with corresponding functions, so as to repair logic function defects or add new functions.

[0080] Reference Figure 3 The embodiment shown in this specification illustrates a standard cell layout for ECO, such as... Figure 3 As shown, modifications to the first metal layer M1 can be made through multiple connection patterns 321 to 324 and multiple through-holes (such as...). Figure 3 As shown in the CT diagram, modifications to the second metal layer M2 can be achieved by setting connection holes (such as...). Figure 3 (as indicated by VT) and implemented with connection patterns 321 and 324.

[0081] Specifically, the standard unit layout 300 can achieve electrical connection between the fifth conductive patterns MD-P31 and MD-P33 and the first metal layer M1 through two through-hole CTs and a connecting pattern 321. Specifically, the first through-hole CT can be formed on and electrically connected to the fifth conductive pattern MD-P31; the second through-hole CT is formed on and electrically connected to the fifth conductive pattern MD-P33; and the connecting pattern 321 is formed on both through-hole CTs and electrically connected to them respectively.

[0082] The standard unit layout 300 can achieve electrical connection between the fifth conductive pattern MD-P32, the third conductive pattern MD-P1, and the first metal layer M1 through two vias CT and a connecting pattern 322. Specifically, the first via CT can be formed on and electrically connected to the fifth conductive pattern MD-P32; the second via CT is formed on and electrically connected to the third conductive pattern MD-P1; and the connecting pattern 322 is formed on both vias CT and electrically connected to them respectively.

[0083] Continue to refer to Figure 3 The standard unit layout 300 can achieve electrical connection between the sixth conductive patterns MD-P42 and MD-P43 and the first metal layer M1 through two through-hole CTs and the connecting pattern 323. Specifically, the first through-hole CT can be formed on and electrically connected to the sixth conductive pattern MD-P42; the second through-hole CT is formed on and electrically connected to the sixth conductive pattern MD-P43; and the connecting pattern 323 is formed on both through-hole CTs and electrically connected to them respectively.

[0084] Continue to refer to Figure 3 The standard unit layout 300 can also achieve electrical connection between the sixth conductive pattern MD-P41 and the first metal layer M1 through through-hole CT and connection pattern 324. Specifically, the through-hole CT can be formed on and electrically connected to the sixth conductive pattern MD-P41; the connection pattern 324 is formed on and electrically connected to the through-hole CT.

[0085] In addition, continue to refer to Figure 3 The standard unit layout 300 can also achieve electrical connection between the first metal layer M1 and the second metal layer M2 through two connecting holes VT and connecting patterns 321 and 324. The connecting holes VT can be formed at the intersection of the cutting pattern AR2 and the connecting pattern 321, and at the intersection of the cutting pattern AR2 and the connecting pattern 324, respectively, and are electrically connected to the connecting pattern 321 and the connecting pattern 324, respectively.

[0086] It is understood that the above ECO description of the standard unit layout is only an example. In actual implementation, the number and location of through holes (CT) and connecting holes (VT) can be flexibly set to meet different design requirements.

[0087] Continue to refer to Figure 3 , Figure 3 It also defines the input and output ports for the standard cell layout. Specifically, such as... Figure 3 The first input port A1 can be set above the conductive pattern C1, the second input port A2 can be set above the conductive pattern C2, and the output port ZN can be set above the first metal layer M1.

[0088] It should be noted that since the third conductive pattern, the fourth conductive pattern, the first connected layer pattern, the second connected layer pattern, and the multiple blocking layers are fixedly set inside the standard cell layout, it is not necessary to process the layers containing the above patterns during ECO processing. By setting the positions of the connecting hole VT and the through hole CT in the standard cell layout, their connection relationship with the first metal layer M1 and the second metal layer M2 located above the first metal layer M1 can be changed.

[0089] This specification also provides an integrated circuit that may include multiple standard cell layouts. The standard cell layouts may be any of the standard cell layouts described in the foregoing embodiments, wherein the multiple standard cell layouts are connected according to a preset connection relationship.

[0090] To enable those skilled in the art to better understand and implement the integrated circuits in the embodiments of this specification, a detailed description is provided below with reference to the accompanying drawings and specific application examples.

[0091] Reference Figure 4 The schematic diagram of an integrated circuit structure shown in the embodiment of this specification is as follows: Figure 4 As shown, integrated circuit IC1 may include multiple standard cell layouts (e.g., Figure 4 The m shown are integers (where m is a number greater than 1), and the cutting patterns located on the outermost edge of the plurality of standard cell layouts overlap and connect with each other. The description of the standard cell layout can be found in the foregoing.

[0092] To facilitate understanding, the following example illustrates the connection between the first and second standard cell layouts. (Combined with...) Figure 2 and Figure 4 The outermost cutting pattern AR3 of the first standard cell layout can overlap and connect with the outermost cutting pattern AR1 of the second standard cell layout.

[0093] Similarly, the outermost cutting pattern AR3 of the (m-1)th standard cell layout can overlap and connect with the outermost cutting pattern AR1 of the mth standard cell layout.

[0094] Understandably, since the lateral dimension of the well region is the largest among all standard cells, it is necessary to consider the following when using... Figure 4 When the connection method shown results in integrated circuit IC1, the well regions in the standard cells will partially overlap. For example, the well regions of the first standard cell layout and the second standard cell layout partially overlap.

[0095] Therefore, by overlapping the auxiliary conductive patterns located on the outermost sides of multiple standard cell layouts, multiple series-connected functional devices can be formed simultaneously. For example, multiple series-connected inverters can be formed simultaneously.

[0096] It should be noted that the number of standard cell layouts included in the integrated circuit IC1 in the embodiments of this specification can be set according to actual needs, and the embodiments of this specification do not limit the number of standard cell layouts.

[0097] In practical implementation, more complex functional devices may need to be formed (e.g., a data selector MUX). Therefore, embodiments of this specification also provide a schematic diagram of another integrated circuit structure, such as... Figure 5 As shown, integrated circuit IC2 may include multiple mirror-symmetric standard cell layouts, and the well regions and first conductive patterns of the multiple mirror-symmetric standard cell layouts are respectively overlapped and connected to each other. The description of the standard cell layouts can be found in the foregoing.

[0098] It should be noted that the aforementioned integrated circuit IC2 can be extended horizontally. For example, multiple identical integrated circuit IC2s can be arranged according to... Figure 4 The connection shown connects multiple identical integrated circuits IC2 horizontally.

[0099] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A standard unit layout, characterized in that, include: Trap area; A first conductive pattern is located above the well region; The second conductive pattern is located on the side opposite to the first conductive pattern; Multiple active region patterns are located in a first region and a second region between the first conductive pattern and the second conductive pattern, and some of the active region patterns are located above the well region; The third conductive pattern is located above the active region pattern adjacent to the first region and partially overlaps with the first conductive pattern. The fourth conductive pattern is located above the active region pattern adjacent to the second region and partially overlaps with the second conductive pattern. Multiple gate conductive patterns are respectively located above the multiple active region patterns and partially overlap with the active region patterns; Multiple cutting patterns are used to cut the multiple active region patterns and a portion of the gate conductive pattern located above the multiple active region patterns; The first connected layer pattern is located below the first conductive pattern and partially overlaps with the third conductive pattern; The second connected layer pattern is located below the second conductive pattern and partially overlaps with the fourth conductive pattern.

2. The standard unit layout according to claim 1, characterized in that, The third conductive pattern is isolated from the fourth conductive pattern.

3. The standard unit layout according to claim 1, characterized in that, The first region is adjacent to the first conductive pattern, and the active region pattern located in the first region includes the first active region pattern; The second region is adjacent to the second conductive pattern, and the active region pattern located in the second region includes the second active region pattern.

4. The standard unit layout according to claim 3, characterized in that, The third conductive pattern is located above the first active region pattern; The fourth conductive pattern is located above the second active region pattern.

5. The standard unit layout according to claim 3, characterized in that, Also includes: Multiple fifth conductive patterns are respectively located above the first active region pattern and on both sides of the third conductive pattern, and partially overlap with the first conductive pattern; Multiple sixth conductive patterns are located above the second active region pattern and on both sides of the fourth conductive pattern, respectively, and partially overlap with the second conductive pattern.

6. The standard unit layout according to claim 5, characterized in that, The number of fifth conductive patterns located on both sides of the third conductive pattern is different; The number of sixth conductive patterns located on both sides of the fourth conductive pattern is different.

7. The standard unit layout according to claim 5, characterized in that, Also includes: Multiple blocking layers are respectively located above a portion of the multiple fifth conductive patterns and the multiple sixth conductive patterns, and in an intermediate region between the first region and the second region, for blocking the fifth conductive patterns and / or the sixth conductive patterns.

8. The standard unit layout according to claim 3, characterized in that, At least one gate conductive pattern overlapping the first active region pattern and at least one gate conductive pattern overlapping the second active region pattern are continuous, forming at least one common gate conductive pattern that overlaps the first active region pattern and the second active region pattern.

9. The standard unit layout according to claim 8, characterized in that, Also includes: At least one conductive pattern is formed on a corresponding common gate conductive pattern and located in the intermediate region between the first region and the second region, and is in electrical contact with the corresponding common gate conductive pattern.

10. The standard unit layout according to claim 1, characterized in that, The plurality of cutting patterns are continuous among the plurality of active region patterns.

11. An integrated circuit, characterized in that, It includes multiple standard unit layouts, wherein the standard unit layout is the standard unit layout described in any one of claims 1-10, wherein the multiple standard unit layouts are connected according to a preset connection relationship.

12. The integrated circuit according to claim 11, characterized in that, The cutting patterns located on the outermost side of the multiple standard unit layouts overlap and connect with each other.

13. The integrated circuit according to claim 11, characterized in that, include: Multiple mirror-symmetric standard cell layouts, wherein the well regions and the first conductive patterns of the multiple mirror-symmetric standard cell layouts overlap and are connected to each other.

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