Standard cell layout and integrated circuit

Abstract

The standard cell layout comprises a well region, a first conductive pattern located above the well region, a second conductive pattern located on the opposite side of the first conductive pattern, a plurality of active region patterns located in a first region and a second region between the first conductive pattern and the second conductive pattern, a first central conductive pattern partially overlapping the first conductive pattern, a second central conductive pattern partially overlapping the second conductive pattern, a plurality of gate conductive patterns respectively located above the plurality of active region patterns, a plurality of single diffusion isolation patterns located on the side of the plurality of active region patterns away from the first central conductive pattern and the second central conductive pattern, a first via layer pattern located below the first conductive pattern, and a second via layer pattern located below the second conductive pattern. By using the above scheme, the area utilization of the standard cell layout can be improved, and thus the size of the integrated circuit can be reduced.

Description

Technical Field

[0001] This specification relates to the field of semiconductor manufacturing technology, and in particular to a standard cell layout and integrated circuit. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, integrated circuits (e.g., application-specific integrated circuits, ASICs) are becoming increasingly larger, with their internal gates potentially reaching millions. Although they undergo verification processes such as logic analysis and simulation before tape-out, it is still difficult to cover all functional combinations. Chips after tape-out may have some functional defects or some functions may not meet customer requirements.

[0003] Currently, Engineering Change Order (ECO) techniques are typically used to address the aforementioned functional defects or add new functions to meet customer needs. ECO refers to altering the metal traces of the chip after fabrication to change the original connections, thereby repairing logic functionality or adding new features.

[0004] However, the standard cell layout in the existing scheme is achieved through a double diffusion partition pattern, which results in a large area of ​​the standard cell layout. Moreover, during ECO, only a portion of the standard cell layout can be used, leading to low area utilization of the standard cell layout in the existing scheme. Summary of the Invention

[0005] The problem addressed by the embodiments in this specification is to provide a standard cell layout and integrated circuit that can improve the area utilization of the standard cell layout and thus reduce the size of the integrated circuit.

[0006] First, this specification provides a standard cell layout, including: Trap area; A first conductive pattern is located above the well region; The second conductive pattern is located on the side opposite to the first conductive pattern; Multiple active region patterns are located in a first region and a second region between the first conductive pattern and the second conductive pattern; The first central conductive pattern is located above the active region pattern adjacent to the first region and partially overlaps with the first conductive pattern. The second central conductive pattern is located above the active region pattern adjacent to the second region and partially overlaps with the second conductive pattern. Multiple gate conductive patterns are respectively located above the multiple active region patterns and partially overlap with the active region patterns; Multiple single-diffusion blocking patterns are located on the side of the multiple active region patterns that is far away from the first central conductive pattern and the second central conductive pattern; The first connected layer pattern is located below the first conductive pattern and partially overlaps with the first central conductive pattern; The second connected layer pattern is located below the second conductive pattern and partially overlaps with the second central conductive pattern.

[0007] Accordingly, embodiments of this specification also provide an integrated circuit including multiple standard cell layouts, wherein the standard cell layouts are the standard cell layouts described in any of the foregoing embodiments, and the multiple standard cell layouts are connected according to a preset connection relationship.

[0008] Compared with the prior art, the technical solutions of the embodiments in this specification have the following advantages: In the standard cell layout provided in the embodiments of this specification, a single diffusion barrier pattern is set on the side away from the first central conductive pattern and the second central conductive pattern in multiple active area patterns. Compared with the standard cell layout using a double diffusion barrier pattern in the prior art, the area of ​​the standard cell layout can be reduced. Even with the same area, by setting multiple gate conductive patterns, multiple corresponding devices can be formed on the gate conductive patterns, thereby improving the area utilization of the standard cell layout. As a result, when completing the same circuit layout design, the number of standard cell layouts used can be reduced, and the size of the integrated circuit can be reduced. Attached Figure Description

[0009] Figure 1 A schematic diagram of a standard cell layout is shown; Figure 2 A schematic diagram of a standard cell layout in an embodiment of this specification is shown; Figure 3 A schematic diagram of another standard cell layout in an embodiment of this specification is shown; Figure 4 An embodiment of this specification is shown. Figure 2 The diagram shows a standard cell layout for ECO. Figure 5 An embodiment of this specification is shown. Figure 3 The diagram shows a standard cell layout for ECO. Figure 6 This specification shows a schematic diagram of the structure of a device for ECO formation of a standard cell layout according to an embodiment of the present specification; Figure 7 An embodiment of this specification is shown, consisting of... Figure 2 A schematic diagram of the structure of an integrated circuit formed by the standard cell layout in the diagram; Figure 8 Another embodiment of this specification is shown. Figure 2 A schematic diagram of the structure of an integrated circuit formed by the standard cell layout in the diagram; Figure 9 An embodiment of this specification is shown, consisting of... Figure 3 A schematic diagram of the structure of an integrated circuit formed by the standard cell layout in the diagram; Figure 10 Another embodiment of this specification is shown. Figure 3 A schematic diagram of the structure of an integrated circuit formed by the standard cell layout in the diagram. Detailed Implementation

[0010] As can be seen from the background technology, the area utilization rate of existing standard unit layouts is low. This paper analyzes the reasons for the low area utilization rate of current standard unit layouts by combining a structural diagram of a standard unit layout.

[0011] Reference Figure 1 The diagram illustrates a standard cell layout. The standard cell layout 100 may include a first conductive pattern 111, a second conductive pattern 112; a first active region pattern OD1a and a second active region pattern OD2a disposed in a first region I between the first conductive pattern 111 and the second conductive pattern 112; a third active region pattern OD1b and a fourth active region pattern OD2b disposed in a second region II; a first central conductive pattern MD-P3 disposed between the first active region pattern OD1a and the second active region pattern OD2a; and a third active region pattern MD-P3 disposed in the third active region I. The second central conductive pattern MD-N3 of the pattern OD1b and the fourth active region pattern OD2b, and the first central conductive pattern MD-P3 partially overlaps with the first conductive pattern 111, and the second central conductive pattern MD-N3 partially overlaps with the second conductive pattern 112; the additional conductive pattern PD1a1 overlaps with the first active region pattern OD1a, the additional conductive pattern PD2a1 overlaps with the second active region pattern OD2a, the additional conductive pattern PD2b1 overlaps with the third active region pattern OD1b, and the additional conductive pattern PD2b2 overlaps with the fourth active region pattern OD2a.

[0012] Continue to refer to Figure 1The standard cell layout 100 may further include a common gate conductive pattern Poly1 overlapping the first active region pattern OD1a and the second active region pattern OD2a, and a common gate conductive pattern Poly2 overlapping the third active region pattern OD1b and the fourth active region pattern OD2b, and conductive patterns MP1 and MP2 electrically connected to the common gate conductive pattern Poly1 and the common gate conductive pattern Poly2; a plurality of third conductive patterns MD-P1, MD-P2, MD-P4, MD-P5 and MD-N1, MD-N2, MD-N4, MD-N5; and a first via V0-P for connecting the first center conductive pattern MD-P3 to the first conductive pattern 111, and a second via V0-N for connecting the second center conductive pattern MD-N3 to the second conductive pattern 112.

[0013] However, the standard cell layout 100 in the above embodiments uses a double diffusion break (DDB) structure to isolate the active region. Compared with a single diffusion break (SDB) structure, it requires an additional area corresponding to the contact spacing, and Figure 1 The additional conductive pattern PD1a1 and the common gate conductive pattern Poly1, the common gate conductive pattern Poly1 and the additional conductive pattern PD1a2, the additional conductive pattern PD1a2 and the additional conductive pattern PD2a2, the additional conductive pattern PD2a2 and the common gate conductive pattern Poly2, and the common gate conductive pattern Poly2 and the additional conductive pattern PD2a1 constitute the five contact pitches of the standard cell layout 100. That is to say, the standard cell layout 100 includes the area corresponding to the six contact pitch intervals. However, during ECO processing, no devices are formed on the additional conductive patterns PD1a1 and PD2a1, and the additional conductive patterns PD1a1 and PD2a1 occupy a large area, resulting in a low utilization rate of the standard cell layout 100.

[0014] To address the aforementioned issues, the standard cell layout provided in the embodiments of this specification incorporates a single diffusion barrier pattern on the side of multiple active region patterns furthest from the first and second central conductive patterns. Compared to the standard cell layout employing a double diffusion barrier pattern in existing solutions, this reduces the area of ​​the standard cell layout. Even with the same area, by setting multiple gate conductive patterns, multiple corresponding devices can be formed on the gate conductive patterns, thereby improving the area utilization of the standard cell layout. Consequently, when completing the same circuit layout design, the number of standard cell layouts used can be reduced, thus decreasing the size of the integrated circuit.

[0015] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the standard unit layout of the embodiments of this specification will be described in detail below with reference to the accompanying drawings.

[0016] Reference Figure 2 The schematic diagram shown in this specification illustrates a standard cell layout in an embodiment of the present invention. The standard cell layout 200 may include a well region 210 and a first conductive pattern 211 located above the well region 210. The second conductive pattern 212 is located on the side opposite to the first conductive pattern 211; a plurality of active region patterns are located in the first region I and the second region II between the first conductive pattern 211 and the second conductive pattern 212, and some of the active region patterns are located above the well region 210; the first central conductive pattern MD-P1 is located above the active region pattern adjacent to the first region I and partially overlaps with the first conductive pattern 211; the second central conductive pattern MD-N1 is located above the active region pattern adjacent to the second region II and partially overlaps with the second conductive pattern 212; a plurality of gate conductive patterns are respectively located above the plurality of active region patterns and partially overlap with the active region patterns; a plurality of single diffusion barrier patterns are located on the side of the plurality of active region patterns away from the first central conductive pattern and the second central conductive pattern; the first connecting layer pattern VR1 is located below the first conductive pattern 211 and partially overlaps with the first central conductive pattern MD-P1; the second connecting layer pattern VR2 is located below the second conductive pattern 212 and partially overlaps with the second central conductive pattern MD-N1.

[0017] In specific implementations, different types of well regions 210 can be obtained by diffusing different ions on the substrate. For example, well region 210 can be an N-well region, which can be obtained by diffusing N-type ions on a P-type substrate, or a P-well region can be obtained by diffusing P-type ions on an N-type substrate. The embodiments in this specification do not limit the type of well region 210, which can be obtained by implanting different ions on the substrate according to specific process requirements.

[0018] In some embodiments of this specification, the first conductive pattern 211 can serve as a power line VDD, and through the first connecting layer pattern VR1, the first central conductive pattern MD-P1 and the first metal layer M1 ( Figure 2 (Not shown) connection; the second conductive pattern 212 can serve as a ground wire VSS, and through the second connecting layer pattern VR2, the connection between the first central conductive pattern MD-N2 and the first metal layer M1 is realized.

[0019] In a specific implementation, the first conductive pattern 211 and the second conductive pattern 212 can be formed on the first metal layer M1.

[0020] In actual manufacturing processes, the number of active area patterns can be flexibly set according to specific requirements. In some embodiments of this specification, reference continues to be made to... Figure 2 The first region I is adjacent to the first conductive pattern 211, and the multiple active region patterns located in the first region I may include the first active region pattern AA1 and the second active region pattern AA2. The second region II is adjacent to the second conductive pattern 212, and the multiple active region patterns located in the second region II may include a third active region pattern AA3 and a fourth active region pattern AA4. That is, the standard cell layout 200 in the embodiments of this specification may include four active region patterns.

[0021] In other embodiments, an even number of active region patterns, such as 6, 8, or more, may be included.

[0022] In specific implementations, at least one of the multiple active area patterns can serve as an active device in the standard cell layout 200. For example, any one or more of the first active area pattern AA1 to the fourth active area pattern AA4 can serve as an active device in the standard cell layout 200.

[0023] As a specific example, any one of the multiple active region patterns can serve as a device such as a metal-oxide-semiconductor field-effect transistor (MOSFET) or a complementary metal-oxide-semiconductor (CMOS) transistor in the standard cell layout 200.

[0024] In specific implementations, the P-region of a PMOS transistor can be formed in the first active region pattern AA1, and the N-region of an NMOS transistor can be formed in the third active region pattern AA3. Alternatively, the N-region of an NMOS transistor can be formed in the first active region pattern AA1, and the P-region of a PMOS transistor can be formed in the third active region pattern AA3. The embodiments in this specification do not limit the type of transistor formed by the active region patterns.

[0025] In some embodiments of this specification, the active region patterns in the plurality of active region patterns can be isolated from each other. For example, the first active region pattern AA1 and the second active region pattern AA2 located in the first region I are isolated from each other; the third active region pattern AA3 and the fourth active region pattern AA4 located in the second region II are isolated from each other.

[0026] In actual manufacturing processes, the number of the first and second central conductive patterns can be flexibly set according to specific requirements. In some embodiments of this specification, reference continues to be made to... Figure 2The standard cell layout 200 may include a first central conductive pattern MD-P1 and a second central conductive pattern MD-N1, and the first central conductive pattern MD-P1 may be isolated from the second central conductive pattern MD-N1.

[0027] By isolating the first and second central conductive patterns from each other, subsequent devices (such as NMOS and PMOS transistors) can receive signals separately, avoiding crosstalk between signals.

[0028] In some embodiments of this specification, the first central conductive pattern MD-P1 and the second central conductive pattern MD-N1 may be arranged along the symmetry axis of the standard cell layout 200. For example, the first central conductive pattern MD-P1 and the second central conductive pattern MD-N1 may be arranged along the symmetry axis of the intermediate region III.

[0029] It is understood that, based on the needs of actual scenarios, the standard unit layout 200 may also include more first central conductive patterns and more second central conductive patterns, and the embodiments in this specification do not limit this.

[0030] Continue to refer to Figure 2 The first active region AA1 and the second active region AA2 are discontinuous, and the first central conductive pattern MD-P1 may be located above the area between the first active region pattern AA1 and the second active region pattern AA2; the third active region AA3 and the fourth active region AA4 are discontinuous, and the second central conductive pattern MD-N1 may be located above the area between the third active region pattern AA3 and the fourth active region pattern AA4.

[0031] In some embodiments of this specification, the first connecting layer pattern VR1 can electrically connect the first central conductive pattern MD-P1 to the power line VDD, and the second connecting layer pattern VR2 can electrically connect the second central conductive pattern MD-N2 to the ground line VSS. Thus, through the first connecting layer pattern VR1 and the second connecting layer pattern VR2, an external power supply can be electrically connected to the standard cell layout 200. The first connecting layer pattern VR1 can connect more first conductive patterns 211 and the first central conductive pattern MD-P1, and the second connecting layer pattern VR2 can connect more second conductive patterns 212 and the second central conductive pattern MD-N1, improving the space utilization of the standard cell layout 200.

[0032] As previously described, the standard cell layout 200 may include multiple gate conductive patterns, and these multiple gate conductive patterns may be located above the multiple active region patterns and partially overlap with the active region patterns. For example, the standard cell layout 200 may include a gate conductive pattern located above and partially overlapping with the first active region pattern AA1, a gate conductive pattern located above and partially overlapping with the second active region pattern AA2, a gate conductive pattern located above and partially overlapping with the third active region pattern AA3, and a gate conductive pattern located above and partially overlapping with the fourth active region pattern AA4.

[0033] In some examples, the first active region pattern AA1 and the third active region pattern AA3, with the middle region III as the axis of symmetry, can share a gate conductive pattern, and the second active region pattern AA2 and the fourth active region pattern AA4 can share a gate conductive pattern.

[0034] Continue to refer to Figure 2 At least one gate conductive pattern that partially overlaps with the first active region pattern AA1 and at least one gate conductive pattern that partially overlaps with the third active region pattern AA3 are continuous, forming a first common gate conductive pattern GT1 that overlaps the first active region pattern and the third active region pattern; at least one gate conductive pattern that partially overlaps with the second active region pattern AA2 and at least one gate conductive pattern that partially overlaps with the fourth active region pattern AA4 are continuous, forming a second common gate conductive pattern GT2 that overlaps the second active region pattern and the fourth active region pattern.

[0035] In some embodiments of this specification, a first common gate conductive pattern GT1 and a second common gate conductive pattern GT2 may be formed above the corresponding active region pattern and configured to jointly define active devices in the standard cell layout 200 with the corresponding active region pattern.

[0036] For example, a first common gate conductive pattern GT1 may be formed above a first active region pattern AA1 and a third active region pattern AA3, and define an active device with the first active region pattern AA1 and the third active region pattern AA3, respectively.

[0037] As a specific example, the first common gate conductive pattern GT1 may define a gate formed in the first active region pattern AA1 and the third active region pattern AA3.

[0038] Understandably, multiple common gate conductive patterns can be formed above the first active region pattern AA1 and the third active region pattern AA3, and above the second active region pattern AA2 and the fourth active region pattern AA4, according to actual process requirements, thereby enabling the formation of multiple gates on the corresponding active region patterns.

[0039] In some embodiments of this specification, the standard cell layout 200 may further include conductive patterns C1 and C2, wherein the first conductive pattern C1 may be formed on the first common gate conductive pattern GT1, located in the intermediate region III between the first region I and the second region II, and electrically contacted with the first common gate conductive pattern GT1; the second conductive pattern C2 may be formed on the second common gate conductive pattern GT2, located in the intermediate region III between the first region I and the second region II, and electrically contacted with the common gate conductive pattern GT2.

[0040] In a specific implementation, the first conductive pattern C1 and the second conductive pattern C2 can be formed of metal and located on the zeroth metal layer M0. The first conductive pattern C1 and the second conductive pattern C2 can connect the first metal layer M1 and the corresponding gate conductive pattern, so as to allow the signal to enter the gate formed on the gate conductive pattern from the first metal layer M1 or a higher metal layer.

[0041] In some embodiments of this specification, reference continues to be made to... Figure 2 The first conductive pattern C1 and the second conductive pattern C2 are located on the same horizontal line.

[0042] In practical implementation, when performing ECO on the standard cell, the active area pattern, as the region forming the active device, needs to be electrically connected to the external circuit. Based on this, the standard cell layout 200 may further include multiple third conductive patterns, respectively located above the first active area pattern and the second active area pattern, and partially overlapping with the first conductive pattern; and multiple fourth conductive patterns, respectively located above the third active area pattern and the fourth active area pattern, and partially overlapping with the second conductive pattern.

[0043] Specifically, the third conductive patterns MD-P3 and MD-P4 can be located above the first active region pattern AA1 and partially overlap with the first conductive pattern 211; the third conductive patterns MD-P5 and MD-P6 can be located above the second active region pattern AA2 and partially overlap with the first conductive pattern 211; the fourth conductive patterns MD-N3 and MD-N4 can be located above the third active region pattern AA3 and partially overlap with the second conductive pattern 212; the fourth conductive patterns MD-N5 and MD-N6 can be located above the fourth active region pattern AA4 and partially overlap with the second conductive pattern 212.

[0044] Therefore, by setting multiple third conductive patterns and multiple fourth conductive patterns, the electrical connection between the active device in the active region pattern and the external circuit can be defined.

[0045] Continue to refer to Figure 2 ,like Figure 2 As shown, the bottom of the third conductive patterns MD-P3 to MD-P6 is located in the middle region III and is lower than the bottom of the first active region pattern AA1 and the second active region pattern AA2.

[0046] The tops of the fourth conductive patterns MD-N3 to MD-N6 are located in the intermediate region III and are higher than the tops of the third active region pattern AA3 and the fourth active region pattern AA4.

[0047] In some embodiments, the plurality of third conductive patterns may not overlap with the first conductive pattern, and the plurality of fourth conductive patterns may not overlap with the second conductive pattern.

[0048] In specific implementation, multiple third conductive patterns and multiple fourth conductive patterns can be formed of metal and can be formed in the zero metal layer M0, which can serve as the lowest metal layer above the active device in the standard cell layout.

[0049] In some embodiments of this specification, the number of third conductive patterns located above the first active region pattern and the second active region pattern is the same. For example, as Figure 2 As shown, the number of third conductive patterns located on the first active region pattern AA1 is 2, that is... Figure 2 The third conductive patterns MD-P3 and MD-P4 are shown; the number of third conductive patterns located on the second active region pattern AA2 is two, namely... Figure 2 The third conductive patterns MD-P5 and MD-P6 are shown.

[0050] The number of fourth conductive patterns located above the third active region pattern and the fourth active region pattern is the same. For example, such as Figure 2As shown, the number of fourth conductive patterns located on the third active region pattern AA3 is 2, that is... Figure 2 The fourth conductive patterns MD-N3 and MD-N4 are shown; the number of fourth conductive patterns located on the fourth active region pattern AA4 is 2, that is... Figure 2 The third conductive patterns MD-N5 and MD-N6 are shown.

[0051] Continue to refer to Figure 2 In some embodiments of this specification, from a spatial perspective, the third conductive patterns MD-P3 and MD-P4 can be symmetrically arranged along the first common gate conductive pattern GT1, and the third conductive patterns MD-P5 and MD-P6 can be symmetrically arranged along the second common gate conductive pattern GT2; the fourth conductive patterns MD-N3 and MD-N4 can be symmetrically arranged along the first common gate conductive pattern GT1, and the fourth conductive patterns MD-N5 and MD-N6 can be symmetrically arranged along the second common gate conductive pattern GT2.

[0052] In some embodiments of this specification, the standard cell layout may further include multiple blocking layers, respectively located above partial areas of the multiple third conductive patterns and the multiple fourth conductive patterns, and in an intermediate region between the first region and the second region, for blocking the third conductive patterns and / or the fourth conductive patterns. As a specific example, such as Figure 2 As shown, the standard cell layout 200 may include blocking layers MOC1 to MOC5, wherein blocking layer MOC1 may be located in a portion of the fourth conductive patterns MD-P3 and MD-P4 (e.g., Figure 2 The region shown is above the first active region AA1 and the first connected layer pattern VR1, used to block the third conductive patterns MD-P3 and MD-P4; the blocking layer MOC2 may be located in a portion of the third conductive patterns MD-P5 and MD-P6 (e.g. Figure 2 The region shown above the second active region AA2 and the first connected layer pattern VR1 is used to block the third conductive patterns MD-P5 and MD-P6; the blocking layer MOC3 can be located in the middle region III, used to block the third conductive patterns MD-P3, MD-P4 and the fourth conductive patterns MD-N3, MD-N4, and to block the third conductive patterns MD-P5, MD-P6 and the fourth conductive patterns MD-N3, MD-N4; the blocking layer MOC4 can be located in a portion of the fourth conductive patterns MD-N3 and MD-N4 (e.g., Figure 2 The region shown above the third active region AA3 and the area between the second connected layer pattern layer VR2 is used to block the fourth conductive patterns MD-N3 and MD-N4; the blocking layer MOC5 may be located in a portion of the fourth conductive patterns MD-N5 and MD-N6 (e.g. Figure 2Above the fourth active region AA3 shown (between the second connected layer pattern layer VR2), it is used to block the fourth conductive patterns MD-N5 and MD-N6.

[0053] By using the aforementioned multiple blocking layers, the fourth conductive pattern and the third conductive pattern can be made discontinuous and isolated from each other, thus avoiding crosstalk between signals.

[0054] As mentioned above, active area patterns can be used to form active devices in a standard cell layout, and active area patterns located in the first region and the second region can be isolated by an intermediate region. In specific implementations, in order to prevent mutual interference between active devices in the same region (e.g., the first region or the second region), the standard cell layout may also include multiple isolation patterns located on the side of the multiple active area patterns closer to the first central conductive pattern or the second central conductive pattern, for isolating the multiple active area patterns.

[0055] Specifically, continue to refer to Figure 2 The standard unit layout 200 may further include isolation patterns AR1 to AR4, wherein isolation pattern AR1 may be located in the first active region AA1 on the side close to the first central conductive pattern MD-P1, isolation pattern AR2 may be located in the second active region AA2 on the side close to the first central conductive pattern MD-P1, isolation pattern AR3 may be located in the third active region AA3 on the side close to the second central conductive pattern MD-N1, and isolation pattern AR4 may be located in the fourth active region AA4 on the side close to the second central conductive pattern MD-N1.

[0056] It should be noted that in some embodiments of this specification, the isolation pattern only serves an isolation function and does not constitute any functional component of the active device.

[0057] Furthermore, an integrated circuit may include multiple standard cell layouts. To achieve isolation between different standard cell layouts, refer to... Figure 2 The single-diffusion blocking pattern SDB1 located in the first active region pattern AA1 and the third active region pattern AA3, which is far away from the first central conductive pattern MD-P1 and the second central conductive pattern MD-P2, is continuous. The single-diffusion blocking pattern SDB1 located in the second active region pattern AA2 and the fourth active region pattern AA4, which is far away from the first central conductive pattern MD-P1 and the second central conductive pattern MD-P2, is also continuous. Thus, multiple standard cell layouts can be isolated.

[0058] It should be noted that the structure and positional relationships of the standard units described above are for illustrative purposes only and do not represent actual positional relationships. For example, Figure 2The first central conductive pattern MD-P1 shown is located above the first conductive pattern 211. However, in the actual layout design, the first central conductive pattern MD-P1 is located below the first conductive pattern 211, and the first central conductive pattern MD-P1 is connected to the first conductive pattern 211 through the first connecting layer pattern VR1.

[0059] In a specific implementation, the standard cell layout 200, from bottom to top, consists of the bottommost well region 210, followed by active region patterns AA1 to AA4, the first common gate conductive pattern GT1 and the second common gate conductive pattern GT2 on the same layer, and single diffusion isolation patterns SDB1 and SDB2, the first center conductive pattern MD-P1, the second center conductive pattern MD-N1, the third conductive patterns MD-P3 to MD-P6, the fourth conductive patterns MD-N3 to MD-N6 on the same layer, the first conductive pattern C1 and the second conductive pattern C2 on the same layer, the isolation patterns MOC1 to MOC5, the first connected layer pattern VR1 and the second connected layer pattern VR2 on the same layer, and the top layer consists of the first conductive pattern 211 and the second conductive pattern 212.

[0060] It is understood that the structure of the standard cell layout described above is merely illustrative. In practical applications, those skilled in the art can adaptively select and / or modify the standard cell layout provided in the embodiments of this specification according to actual needs and application scenarios. For example, the number of third conductive patterns can be increased. Based on this, many different solutions can be derived, and the embodiments of this specification do not limit these derived solutions.

[0061] Reference Figure 3 The schematic diagram shown in this specification illustrates another standard unit layout in an embodiment, such as... Figure 3 As shown, the standard cell layout 300 is similar to the standard cell layout 200 in the aforementioned embodiments, as can be seen from the previous examples. The differences between the two are: First, such as Figure 3 As shown, in the standard cell layout 300, at least one gate conductive pattern that partially overlaps with the first active region pattern AA1 and at least one gate conductive pattern that partially overlaps with the third active region pattern AA3 are continuous, forming a third common gate conductive pattern GT3 and a fourth common gate conductive pattern GT4 that overlap the first active region pattern AA1 and the third active region pattern AA3; at least one gate conductive pattern that partially overlaps with the second active region pattern AA2 and at least one gate conductive pattern that partially overlaps with the fourth active region pattern AA4 are continuous, forming a fifth common gate conductive pattern GT5 that overlaps the second active region pattern AA2 and the fourth active region pattern AA4.

[0062] Compared to Figure 2 The standard cell layout in the 200, Figure 3 The standard cell layout 300 can include three common gate conductive patterns, thereby enabling the formation of three active devices on the standard cell layout 300. This reduces the number of standard cell layouts used when completing the same circuit layout design. For example, if six active devices need to be formed, only two standard cell layouts 300 can be used.

[0063] Since the first active region pattern AA1 and the third active region pattern AA3 are both above the third common gate conductive pattern GT3 and the fourth common gate conductive pattern GT4, therefore, Figure 3 The areas of the first active region pattern AA1 and the third active region pattern AA3 can be greater than [the area of ​​the first active region pattern AA1]. Figure 2 The areas of the first active region pattern AA1 and the third active region pattern AA3.

[0064] Accordingly, the standard unit layout may include three conduction patterns. For example... Figure 3 As shown, the standard unit layout 300 may further include a third conductive pattern C3, a fourth conductive pattern C4, and a fifth conductive pattern C5, wherein: The third conductive pattern C3 is formed on the third common gate conductive pattern GT3, located in the lower middle region between the first region I and the second region II, and is in electrical contact with the third common gate conductive pattern GT3. The fourth conductive pattern C4 is formed on the fourth common gate conductive pattern GT4, located in the middle region between the first region I and the second region II, and is in electrical contact with the fourth common gate conductive pattern GT4. The fifth conductive pattern C5 is formed on the fifth common gate conductive pattern GT5, located in the middle region between the first region I and the second region II, and is in electrical contact with the fifth common gate conductive pattern CT5.

[0065] Continue to refer to Figure 3 The third conductive pattern C3, the fourth conductive pattern C4, and the fifth conductive pattern C5 are not located on the same horizontal line. The third conductive pattern C3 is located in the downward part of the middle region III, so that active devices with different potentials can be constructed on the first active region pattern AA1 and the second active region pattern AA2.

[0066] Secondly, in the standard cell layout, the number of third conductive patterns located above the first active region pattern and the second active region pattern is different; the number of fourth conductive patterns located above the third active region pattern and the fourth active region pattern is different.

[0067] Specifically, such as Figure 3 As shown, the number of third conductive patterns located on the first active region pattern AA1 is 3, that is... Figure 3 The third conductive patterns MD-P3, MD-P4, and MD-P7 are shown; the number of fourth conductive patterns located on the second active region pattern AA2 is two, namely... Figure 3 The third conductive patterns MD-P5 and MD-P6 are shown; the number of fourth conductive patterns located on the third active region pattern AA3 is 3, namely... Figure 3 The fourth conductive patterns MD-N3, MD-N4, and MD-N7 are shown; the number of fourth conductive patterns located on the fourth active region pattern AA4 is two, i.e. Figure 3 The third conductive patterns MD-N5 and MD-N6 are shown.

[0068] Furthermore, from a spatial perspective, the third conductive patterns MD-P3 and MD-P7 located above the first active region pattern AA1 can be symmetrically arranged along the third conductive pattern MD-P4, and the fourth conductive patterns MD-N3 and MD-N7 located above the third active region pattern AA3 can be symmetrically arranged along the fourth conductive pattern MD-N4. Moreover, the third conductive pattern located above the first active region pattern AA1 and the second active region pattern AA2 has an asymmetrical structure, and the fourth conductive pattern located above the third active region pattern AA3 and the fourth active region pattern AA4 has an asymmetrical structure. This can reduce the number of required third and fourth conductive patterns, thereby reducing the area of ​​the standard unit layout 300.

[0069] As can be seen from the foregoing, the blocking layer is used to isolate the third conductive pattern and / or the fourth conductive pattern. When the number of the third conductive pattern and the fourth conductive pattern changes, the blocking layer located above the third conductive pattern and the fourth conductive pattern also changes accordingly.

[0070] like Figure 3 As shown, Figure 3 The length ratio of the blocking layers MOC1 and MOC4 in the middle Figure 2 The intermediate blocking layers MOC1 and MOC4 are longer, and because Figure 3 The third conduction pattern C3 is located in the lower part of the middle region III, resulting in Figure 3 The intermediate blocking layer MOS3 has an irregular shape, and its length is also greater than that of the intermediate blocking layer MOS3. Figure 2 The length of the intermediate blocking layer MOC3.

[0071] In some embodiments of this specification, the above standard cell layout can be subjected to corresponding ECO processing to form a device with corresponding functions, so as to repair logic function defects or add new functions.

[0072] Reference Figure 4 The embodiment shown in this specification is a type of... Figure 2 The diagram shown illustrates the structure of an ECO-compliant standard cell layout. Figure 4 As shown, modifications to the first metal layer M1 can be made through multiple connection patterns 231 to 235 and multiple through-holes (such as...). Figure 4 Modifications to the second metal layer M2 can be achieved by setting connection holes (as shown in the CT diagram). Figure 4 (As indicated by VT), connecting patterns 231 and 235 are implemented.

[0073] Specifically, the standard unit layout can achieve electrical connections between the third conductive patterns MD-P3 and MD-P6, the first central conductive pattern MD-P1, and the first metal layer M1 through three through-hole CTs and connecting patterns 231. Specifically, the first through-hole CT can be formed on and electrically connected to the third conductive pattern MD-P3; the second through-hole CT can be formed on and electrically connected to the first central conductive pattern MD-P1; the third through-hole CT can be formed on and electrically connected to the third conductive pattern MD-P6; and connecting patterns 232 can be formed on these three through-hole CTs and electrically connected to them respectively.

[0074] The standard cell layout can achieve electrical connection between the third conductive patterns MD-P4 and MD-P5 and the first metal layer M1 through two vias CT and connecting pattern 232. Specifically, the first via CT can be formed on and electrically connected to the three conductive patterns MD-P4; the second via CT can be formed on and electrically connected to the third conductive pattern MD-P5; and the connecting pattern 232 can be formed on both vias CT and electrically connected to them respectively.

[0075] Continue to refer to Figure 4 The standard unit layout can achieve electrical connection between the fourth conductive patterns MD-N3 and MD-N6 and the first metal layer M1 through two vias CT and connecting pattern 233. Specifically, the first via CT can be formed on and electrically connected to the fourth conductive pattern MD-N3; the second via CT can be formed on and electrically connected to the fourth conductive pattern MD-N6; and the connecting pattern 233 is formed on both vias CT and electrically connected to them respectively.

[0076] Continue to refer to Figure 4The standard unit layout can also achieve electrical connection between the fourth conductive pattern MD-N4, the second central conductive pattern MD-N1, and the first metal layer M1 through two through-hole CTs and the connecting pattern 234. Specifically, the first through-hole CT can be formed on and electrically connected to the fourth conductive pattern MD-N4; the second through-hole CT can be formed on and electrically connected to the second central conductive pattern MD-N1; and the connecting pattern 234 is formed on and electrically connected to these two through-hole CTs.

[0077] Continue to refer to Figure 4 The standard unit layout can also achieve electrical connection between the fourth conductive pattern MD-N5 and the first metal layer M1 through through-hole CT and connection pattern 235. Specifically, the through-hole CT can be formed on and electrically connected to the fourth conductive pattern MD-N5; the connection pattern 234 is formed on and electrically connected to the through-hole CT.

[0078] In addition, continue to refer to Figure 4 The standard cell layout can also achieve electrical connection between the first metal layer M1 and the second metal layer M2 through two connecting holes VT and connecting patterns 232 and 235. The connecting holes VT can be formed at the intersection of the second common gate conductive pattern GT2 and the connecting pattern 232, and at the intersection of the second common gate conductive pattern GT2 and the connecting pattern 235, respectively, and are electrically connected to the connecting pattern 232 and the connecting pattern 235, respectively.

[0079] It is understood that the above ECO description of the standard unit layout is only an example. In actual implementation, the number and location of through holes (CT) and connecting holes (VT) can be flexibly set to meet different design requirements.

[0080] Continue to refer to Figure 4 , Figure 4 It also defines the input and output ports for the standard cell layout. Specifically, such as... Figure 4 The first input port A can be set above the conductive pattern C1, the second input port B can be set above the conductive pattern C2, and the output port ZN can be set above the first metal layer M1.

[0081] It should be noted that since the first central conductive pattern, the second central conductive pattern, the third conductive pattern, the fourth conductive pattern, the first connecting layer pattern, the second connecting layer pattern, and the multiple blocking layers are fixedly set inside the standard cell layout, it is not necessary to process the layers containing the above patterns during ECO processing. By setting the positions of the connecting hole VT and the through hole CT in the standard cell layout, their connection relationship with the first metal layer M1 and the second metal layer M2 located above the first metal layer M1 can be changed.

[0082] Reference Figure 5 The embodiment shown in this specification is a type of... Figure 3 The diagram shown illustrates the structure of an ECO-compliant standard cell layout. Figure 5 As shown, modifications to the first metal layer M1 can be made through multiple connection patterns 331 to 334 and multiple through-holes (such as... Figure 5 Modifications to the second metal layer M2 can be achieved by setting connection holes (as shown in the CT diagram). Figure 5 (As indicated by VT), connecting patterns 231 and 235 are implemented.

[0083] Specifically, the standard unit layout can achieve electrical connections between the third conductive patterns MD-P3, MD-P4, MD-P6, the first central conductive pattern MD-P1, and the first metal layer M1 through four through-hole CTs and connecting patterns 331. Specifically, the first through-hole CT can be formed on and electrically connected to the third conductive pattern MD-P3; the second through-hole CT can be formed on and electrically connected to the third conductive pattern MD-P4; the third through-hole CT can be formed on and electrically connected to the first central conductive pattern MD-P1; and the fourth through-hole CT can be formed on and electrically connected to the third conductive pattern MD-P6. Connecting patterns 331 can be formed on these three through-hole CTs and electrically connected to them respectively.

[0084] The standard unit layout can achieve electrical connection between the third conductive patterns MD-P7 and MD-P5 and the first metal layer M1 through two vias CT and a connecting pattern 332. Specifically, the first via CT can be formed on and electrically connected to the three conductive patterns MD-P7; the second via CT can be formed on and electrically connected to the third conductive pattern MD-P5; and the connecting pattern 332 can be formed on both vias CT and electrically connected to them respectively.

[0085] Continue to refer to Figure 5 The standard unit layout can achieve electrical connection between the fourth conductive patterns MD-N7 and MD-N6 and the first metal layer M1 through two vias CT and connecting pattern 333. Specifically, the first via CT can be formed on and electrically connected to the fourth conductive pattern MD-N7; the second via CT can be formed on and electrically connected to the fourth conductive pattern MD-N6; and the connecting pattern 333 is formed on both vias CT and electrically connected to them respectively.

[0086] Continue to refer to Figure 5The standard unit layout can also achieve electrical connection between the fourth conductive pattern MD-N5 and the first metal layer M1 through a through-hole CT and a connecting pattern 334. Specifically, the through-hole CT can be formed on and electrically connected to the fourth conductive pattern MD-N5, and the connecting pattern 334 is formed on and electrically connected to the through-hole CT.

[0087] Continue to refer to Figure 5 The standard unit layout can also achieve electrical connection between the fourth conductive pattern MD-N3, MD-N4, the second central conductive pattern MD-N1, and the first metal layer M1 through three through-hole CTs and connecting patterns 335. Specifically, the first through-hole CT can be formed on and electrically connected to the fourth conductive pattern MD-N3; the second through-hole CT can be formed on and electrically connected to the fourth conductive pattern MD-N4; the third through-hole CT can be formed on and electrically connected to the second central conductive pattern MD-N1; and connecting patterns 335 can be formed on these three through-hole CTs and electrically connected to them respectively.

[0088] In addition, continue to refer to Figure 5 The standard cell layout can also achieve electrical connection between the first metal layer M1 and the second metal layer M2 through two connecting holes VT and connecting patterns 332 and 334. The connecting holes VT can be formed at the intersection of the fifth common gate conductive pattern GT5 and the connecting pattern 332, and at the intersection of the fifth common gate conductive pattern GT5 and the connecting pattern 334, respectively, and are electrically connected to the connecting patterns 332 and 334, respectively.

[0089] It is understood that the above ECO description of the standard unit layout is only an example. In actual implementation, the number and location of through holes (CT) and connecting holes (VT) can be flexibly set to meet different design requirements.

[0090] In specific implementation, Figure 2 and Figure 3 The standard cell layout shown can be used to form a device with specific functions after ECO.

[0091] As a specific example, such as Figure 6 The diagram shown in this specification illustrates the structure of a device for ECO formation of a standard cell layout, as described in an embodiment of this specification. Figure 6 As shown, when the standard cell layout in the embodiments of this specification is ECO'd, four switching transistors can be formed, i.e. Figure 6 The switches M1 to M4 are shown, wherein switches M1 and M2 share a common input terminal A, and switches M3 and M4 share a common input terminal B, and output corresponding signals through the output terminal ZN.

[0092] When both input terminals A and B are low, switching transistors M1 and M3 are turned on; when switching transistors M1 and M3 are turned off, output terminal ZN outputs a high level VDD.

[0093] When input A is low and input B is high, switches M1 and M4 are turned on, and switches M2 and M3 are turned off, and output ZN outputs a high level VDD.

[0094] When input A is high and input B is low, switches M2 and M3 are turned on, and switches M1 and M4 are turned off, and output ZN outputs a high level VDD.

[0095] When both input terminals A and B are high, switching transistors M2 and M4 are turned on, while switching transistors M1 and M3 are turned off, and output terminal ZN outputs a low level VCC.

[0096] Therefore, it can be seen that by performing an ECO on the standard cell layout in the embodiments of this specification, NAND gates can be formed.

[0097] Understandably, in practical implementation, depending on actual needs, the positions of vias and / or connection holes can be changed to form devices with different logic functions. For example, the formed device can also be a NOR gate.

[0098] This specification also provides an integrated circuit that may include multiple standard cell layouts. The standard cell layouts may be any of the standard cell layouts described in the foregoing embodiments, wherein the multiple standard cell layouts are connected according to a preset connection relationship.

[0099] To enable those skilled in the art to better understand and implement the integrated circuits in the embodiments of this specification, a detailed description is provided below with reference to the accompanying drawings and specific application examples.

[0100] Reference Figure 7 The embodiment shown in this specification is a type of... Figure 2 A schematic diagram of the structure of an integrated circuit formed by the standard cell layout in the diagram, such as... Figure 7 As shown, integrated circuit IC1 may include multiple standard cell layouts (e.g., Figure 7 The m shown are single-diffusion barrier patterns that overlap and connect with each other in the plurality of standard cell layouts. The description of the standard cell layout can be found above. Figure 2 The content described.

[0101] To facilitate understanding, the following example illustrates the connection between the first and second standard cell layouts. (Combined with...) Figure 2 and Figure 7The outermost single-diffusion barrier pattern SDB2 of the first standard cell layout can overlap and connect with the outermost single-diffusion barrier pattern SDB1 of the second standard cell layout.

[0102] Similarly, the outermost single-diffusion barrier pattern SDB2 of the (m-1)th standard cell layout can overlap and connect with the single-diffusion barrier pattern SDB1 of the mth standard cell layout.

[0103] Therefore, by overlapping the auxiliary conductive patterns located on the outermost sides of multiple standard cell layouts, multiple series-connected functional devices can be formed simultaneously. For example, multiple series-connected inverters can be formed simultaneously.

[0104] It should be noted that the number of standard cell layouts included in the integrated circuit IC1 in the embodiments of this specification can be set according to actual needs, and the embodiments of this specification do not limit the number of standard cell layouts.

[0105] In practical implementation, more complex functional devices may need to be formed (e.g., a data selector MUX). Therefore, embodiments of this specification also provide a schematic diagram of another integrated circuit structure, such as... Figure 8 As shown, integrated circuit IC2 may include multiple mirror-symmetric standard cell layouts, and the well regions and first conductive patterns of the multiple mirror-symmetric standard cell layouts are respectively overlapped and connected to each other. The description of the standard cell layout can be found above. Figure 2 The content described.

[0106] like Figure 8 As shown, the well region 210 of the first standard cell layout can overlap and connect with the well region 210 of the second standard cell, and the first conductive pattern 211 of the first standard cell layout can overlap and connect with the first conductive pattern 211 of the second standard cell.

[0107] It should be noted that the aforementioned integrated circuit IC2 can be extended horizontally. For example, multiple identical integrated circuit IC2s can be arranged according to... Figure 7 The connection shown connects multiple identical integrated circuits IC2 horizontally, and the connection method is as follows: Figure 7 same.

[0108] This description also provides a schematic diagram of an integrated circuit structure, such as... Figure 9 As shown, integrated circuit IC3 may include multiple standard cell layouts (e.g., Figure 9 The n shown are single-diffusion barrier patterns that overlap and connect with each other in the plurality of standard cell layouts. The description of the standard cell layout can be found above. Figure 3 The content described.

[0109] To facilitate understanding, the following example illustrates the connection between the first and second standard cell layouts. (Combined with...) Figure 3 and Figure 9 The outermost single-diffusion barrier pattern SDB2 of the first standard cell layout can overlap and connect with the outermost single-diffusion barrier pattern SDB1 of the second standard cell layout.

[0110] Similarly, the outermost single-diffusion barrier pattern SDB2 of the (m-1)th standard unit layout can overlap and connect with the single-diffusion barrier pattern SDB1 of the mth standard unit layout.

[0111] In practical implementation, more complex functional devices may need to be formed (e.g., a data selector MUX). Therefore, embodiments of this specification also provide a schematic diagram of another integrated circuit structure, such as... Figure 10 As shown, integrated circuit IC4 may include multiple mirror-symmetric standard cell layouts, and the well regions and first conductive patterns of the multiple mirror-symmetric standard cell layouts are respectively overlapped and connected to each other. The description of the standard cell layout can be found above. Figure 3 The content described.

[0112] like Figure 10 As shown, the well region 310 of the first standard cell layout can overlap and connect with the well region 310 of the second standard cell, and the first conductive pattern 311 of the first standard cell layout can overlap and connect with the first conductive pattern 311 of the second standard cell.

[0113] It should be noted that the aforementioned integrated circuit IC4 can be extended horizontally. For example, multiple identical integrated circuit IC4s can be arranged in a lateral direction. Figure 9 The connection shown connects multiple identical integrated circuits IC4 horizontally, and the connection method is as follows: Figure 9 same.

[0114] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A standard unit layout, characterized in that, include: Trap area; A first conductive pattern is located above the well region; The second conductive pattern is located on the side opposite to the first conductive pattern; Multiple active region patterns are located in a first region and a second region between the first conductive pattern and the second conductive pattern; The first central conductive pattern is located above the active region pattern adjacent to the first region and partially overlaps with the first conductive pattern. The second central conductive pattern is located above the active region pattern adjacent to the second region and partially overlaps with the second conductive pattern. Multiple gate conductive patterns are respectively located above the multiple active region patterns and partially overlap with the active region patterns; Multiple single-diffusion blocking patterns are located on the side of the multiple active region patterns that is far away from the first central conductive pattern and the second central conductive pattern; The first connected layer pattern is located below the first conductive pattern and partially overlaps with the first central conductive pattern; The second connected layer pattern is located below the second conductive pattern and partially overlaps with the second central conductive pattern.

2. The standard unit layout according to claim 1, characterized in that, The first central conductive pattern is isolated from the second central conductive pattern.

3. The standard unit layout according to claim 1, characterized in that, The first region is adjacent to the first conductive pattern, and the plurality of active region patterns located in the first region include the first active region pattern and the second active region pattern. The second region is adjacent to the second conductive pattern, and the plurality of active region patterns located in the second region include a third active region pattern and a fourth active region pattern.

4. The standard unit layout according to claim 3, characterized in that, The first central conductive pattern is located above the area between the first active region pattern and the second active region pattern; The second central conductive pattern is located above the third active region pattern and the fourth active region pattern.

5. The standard unit layout according to claim 3, characterized in that, At least one gate conductive pattern that overlaps with the first active region pattern portion and at least one gate conductive pattern that overlaps with the third active region pattern portion are continuous, forming a first common gate conductive pattern that overlaps the first active region pattern and the third active region pattern. At least one gate conductive pattern that overlaps with the second active region pattern and at least one gate conductive pattern that overlaps with the fourth active region pattern are continuous, forming a second common gate conductive pattern that overlaps the second active region pattern and the fourth active region pattern.

6. The standard unit layout according to claim 5, characterized in that, Also includes: A first conductive pattern is formed on the first common gate conductive pattern, located in the middle region between the first region and the second region, and is in electrical contact with the first common gate conductive pattern; The second conductive pattern is formed on the second common gate conductive pattern, located in the middle region between the first region and the second region, and is in electrical contact with the second common gate conductive pattern.

7. The standard unit layout according to claim 3, characterized in that, At least one gate conductive pattern that overlaps with the first active region pattern portion and at least one gate conductive pattern that overlaps with the third active region pattern portion are continuous, forming a third common gate conductive pattern and a fourth common gate conductive pattern that overlap the first active region pattern and the third active region pattern. At least one gate conductive pattern that partially overlaps with the second active region pattern and at least one gate conductive pattern that partially overlaps with the fourth active region pattern are continuous, forming a fifth common gate conductive pattern that overlaps the second active region pattern and the fourth active region pattern.

8. The standard unit layout according to claim 7, characterized in that, Also includes: The third conductive pattern is formed on the third common gate conductive pattern, located in the lower middle region between the first region and the second region, and is in electrical contact with the third common gate conductive pattern. A fourth conductive pattern is formed on the fourth common gate conductive pattern, located in the middle region between the first region and the second region, and is in electrical contact with the fourth common gate conductive pattern; A fifth conductive pattern is formed on the fifth common gate conductive pattern, located in the middle region between the first region and the second region, and is in electrical contact with the fifth common gate conductive pattern.

9. The standard unit layout according to claim 3, characterized in that, Also includes: Multiple third conductive patterns are located above the first active region pattern and the second active region pattern, respectively, and partially overlap with the first conductive pattern; Multiple fourth conductive patterns are located above the third active region pattern and the fourth active region pattern, respectively, and partially overlap with the second conductive pattern.

10. The standard unit layout according to claim 9, characterized in that, The number of third conductive patterns located above the first active region pattern and the second active region pattern is the same; The number of fourth conductive patterns located above the third active region pattern and the fourth active region pattern is the same.

11. The standard unit layout according to claim 9, characterized in that, The number of third conductive patterns located above the first active region pattern and the second active region pattern is different; The number of fourth conductive patterns located above the third active region pattern and the fourth active region pattern is different.

12. The standard cell layout according to any one of claims 9, characterized in that, Also includes: Multiple blocking layers are respectively located above the multiple third conductive patterns and the multiple fourth conductive patterns in a portion of the region, and in an intermediate region between the first region and the second region, for blocking the third conductive patterns and / or the fourth conductive patterns.

13. The standard unit layout according to claim 1, characterized in that, Also includes: Multiple isolation patterns are located on the side of the multiple active area patterns closest to the first central conductive pattern or the second central conductive pattern, for isolating the multiple active area patterns.

14. An integrated circuit, characterized in that, It includes multiple standard unit layouts, wherein the standard unit layout is the standard unit layout described in any one of claims 1-13, wherein the multiple standard unit layouts are connected according to a preset connection relationship.

15. The integrated circuit according to claim 14, characterized in that, The single-diffusion partition patterns of the multiple standard unit layouts overlap and connect with each other.

16. The integrated circuit according to claim 14, characterized in that, include: Multiple mirror-symmetric standard cell layouts, wherein the well regions and the first conductive patterns of the multiple mirror-symmetric standard cell layouts overlap and are connected to each other.

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