Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, wherein the structure comprises: a substrate comprising a first region and a second region; a first fin structure located in the first region, comprising a plurality of first channel layers; a second fin structure located in the second region, comprising a barrier channel layer and a second channel layer, the material in the second channel layer is silicon germanium doped with second doping ions, and the second doping ions are different in electrical type from third doping ions and first doping ions respectively. By using the second channel layer of silicon germanium material as the PMOS transistor channel region, the demand of PMOS transistor for hole mobility is met. By additionally arranging the barrier channel layer, the doping concentration of the third doping ions in the barrier channel layer makes the barrier channel layer unable to be turned on during the operation of the transistor, thereby reducing the bottom leakage problem of the PMOS transistor. In the formation of the first gate structure, damage to the gate structure of the second channel layer is avoided, and the influence on the threshold voltage of the PMOS transistor is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are among the most important components in modern integrated circuits. The basic structure of a MOSFET includes: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, the gate structure including: a gate dielectric layer located on the surface of the semiconductor substrate and a gate electrode layer located on the surface of the gate dielectric layer; and source and drain doped regions located in the semiconductor substrate on both sides of the gate structure.

[0003] With the development of semiconductor technology, traditional planar MOSFETs have become less capable of controlling channel current, resulting in severe leakage current. FinFETs are a new type of multi-gate device that typically includes fins protruding from the surface of a semiconductor substrate, a gate structure covering part of the top surface and sidewalls of the fins, and source / drain doped regions located in the fins on both sides of the gate structure. Compared to planar MOSFETs, finFETs have stronger short-channel rejection and higher operating current.

[0004] With the further development of semiconductor technology, traditional fin field-effect transistors (FETs) face limitations in increasing their operating current. Specifically, because only the area near the top surface and sidewalls of the fin is used as the channel region, the volume of the channel region within the fin is relatively small, which limits the increase in the operating current of the FET. Therefore, a gate all-around (GAA) MOSFET structure has been proposed, which increases the volume of the channel region and further increases the operating current of the GAA structure MOSFET.

[0005] However, there are still many problems in the device structure of GAA in the existing technology. Summary of the Invention

[0006] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the final semiconductor structure.

[0007] To address the aforementioned problems, the present invention provides a semiconductor structure comprising: a substrate, the substrate including a first region and a second region; a first fin structure located on the first region, the first fin structure including a plurality of first channel layers overlapping along the normal direction of the substrate surface, the first channel layers being made of silicon doped with first dopant ions or undoped silicon; and a second fin structure located on the second region, the second fin structure including a barrier channel layer and a plurality of second channel layers located on the barrier channel layer, the barrier channel layer and the plurality of second channel layers overlapping along the normal direction of the substrate surface. The substrate surface normals are arranged in overlapping directions. The material in the second channel layer is silicon-germanium doped with a second dopant ion. The material in the isolation channel layer is silicon doped with a third dopant ion. The second dopant ion has a different electrical type from the third dopant ion and the first dopant ion, respectively. The third dopant ion has the same electrical type as the first dopant ion, and the first dopant ion and the third dopant ion are different ions of the same electrical type. The doping concentration of the third dopant ion in the isolation channel layer is such that the isolation channel layer cannot be turned on when the transistor is working.

[0008] Optionally, the first doped ion is an N-type ion; the second doped ion is a P-type ion; and the third doped ion is an N-type ion.

[0009] Optionally, it further includes: a first gate structure located on the substrate and spanning the first fin structure, the first gate structure surrounding the first channel layer; and a second gate structure located on the substrate and spanning the second fin structure, the second gate structure surrounding the isolation channel layer and the second channel layer.

[0010] Optionally, it may also include: an isolation trench located within the substrate; and an isolation layer located within the isolation trench, the top surface of the isolation layer being flush with the bottom surface of the isolation trench layer.

[0011] Optionally, it further includes: a first source / drain doped layer located within the first fin structure, the first source / drain doped layer having first source / drain ions; and a second source / drain doped layer located within the second fin structure, the second source / drain doped layer having second source / drain ions, wherein the first source / drain ions and the second source / drain ions have different electrical types.

[0012] Optionally, the first source / drain ion is an N-type ion; the second source / drain ion is a P-type ion.

[0013] Optionally, it further includes: a sidewall located on the sidewalls of the first gate structure and the second gate structure; a first barrier layer located between the first channel layer and the substrate, and between adjacent first channel layers; and a second barrier layer located between adjacent isolation channel layers and the second channel layer, and between adjacent second channel layers.

[0014] Optionally, it further includes: a dielectric layer located on the substrate, the dielectric layer covering the first gate structure, the second gate structure and the sidewalls, and the dielectric layer exposing the top surfaces of the first gate structure, the second gate structure and the sidewalls.

[0015] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region and a second region; forming a first fin structure on the first region, the first fin structure including a plurality of first channel layers overlapping along the normal direction of the substrate surface, the material of the first channel layers being silicon doped with first dopant ions or undoped silicon; forming a second fin structure on the second region, the second fin structure including a barrier channel layer and a plurality of second channel layers located on the barrier channel layer, the barrier channel layer and the plurality of second channel layers... The layers overlap along the normal direction of the substrate surface. The material of the second channel layer is silicon germanium doped with a second dopant ion, and the material of the isolation channel layer is silicon doped with a third dopant ion. The second dopant ion has a different electrical type from the third dopant ion and the first dopant ion, respectively. The third dopant ion has the same electrical type as the first dopant ion, and the first dopant ion and the third dopant ion are different ions of the same electrical type. The doping concentration of the third dopant ion in the isolation channel layer is such that the isolation channel layer cannot be turned on when the transistor is working.

[0016] Optionally, the first doped ion is an N-type ion; the second doped ion is a P-type ion; and the third doped ion is an N-type ion.

[0017] Optionally, after forming the first fin structure and the second fin structure, the method further includes: forming a first gate structure on the substrate that spans the first fin structure, the first gate structure surrounding the first channel layer; and forming a second gate structure on the substrate that spans the second fin structure, the second gate structure surrounding the isolation channel layer and the second channel layer.

[0018] Optionally, before forming the first fin structure and the second fin structure, the method further includes: forming a barrier channel material layer, a plurality of first channel material layers and a plurality of second channel material layers on the substrate, wherein the first channel material layers are located between adjacent barrier channel material layers and second channel material layers, or between adjacent second channel material layers.

[0019] Optionally, after forming the isolation channel material layer, the first channel material layer, and the second channel material layer, the method further includes: performing a patterning process on the isolation channel material layer, the plurality of first channel material layers, and the plurality of second channel material layers to form a first initial fin structure and a second initial fin structure. The first initial fin structure includes the isolation channel layer, the plurality of first channel layers, and the plurality of second channel layers. The first channel layers are located between adjacent isolation channel layers and second channel layers, or between adjacent second channel layers. The second initial fin structure includes the isolation channel layer, the plurality of first channel layers, and the plurality of second channel layers. The first channel layers are located between adjacent isolation channel layers and second channel layers, or between adjacent second channel layers.

[0020] Optionally, the patterning process further includes: etching the substrate to form isolation trenches within the substrate; and after the patterning process, the process further includes: forming an isolation layer within the isolation trenches, wherein the top surface of the isolation layer is flush with the bottom surface of the isolation trench layer.

[0021] Optionally, after forming the first initial fin structure and the second initial fin structure, the method further includes: forming a pseudo-gate structure spanning adjacent first and second initial fin structures on the substrate; forming a sidewall material layer on the sidewalls and top surface of the pseudo-gate structure; forming a first patterned layer on the substrate, the first patterned layer exposing the sidewall material layer on the second region; etching the sidewall material layer using the first patterned layer as a mask until the top surface of the pseudo-gate structure is exposed, forming a sidewall on the sidewall of the pseudo-gate structure in the second region; and etching the second initial fin structure using the first patterned layer, the pseudo-gate structure located on the second region, and the sidewall as a mask. A second source / drain opening is formed within the second initial fin structure; a portion of the first channel layer exposed by the second source / drain opening is etched to form a second groove; the first patterned layer is removed; after removing the first patterned layer, a second barrier layer film is deposited on the first and second regions; a second patterned layer is formed on the substrate, the second patterned layer exposing the second barrier layer film on the second region; the second barrier layer film is etched using the second patterned layer as a mask to form a second barrier layer within the second groove; after forming the second barrier layer, the second patterned layer is removed; after removing the second patterned layer, a second source / drain doped layer is formed within the second source / drain opening, the second source / drain... The drain doped layer contains second source / drain ions; after forming the second source / drain doped layer, a third patterned layer is formed on the substrate, the third patterned layer exposing the sidewall material layer and the second barrier layer film on the first region; the sidewall material layer and the second barrier layer film are etched using the third patterned layer as a mask until the top surface of the dummy gate structure is exposed, forming a sidewall on the sidewall of the dummy gate structure in the first region; the first initial fin structure is etched using the third patterned layer, the dummy gate structure on the first region, and the sidewall as a mask, forming a first source / drain opening within the first initial fin structure; a portion of the isolation channel layer and a portion of the first source / drain opening are etched to expose the first source / drain opening. The second channel layer forms a first groove; the third patterned layer is removed; after removing the third patterned layer, a first barrier layer film is deposited on the first region and the second region; a fourth patterned layer is formed on the substrate, the fourth patterned layer exposing the first barrier layer film on the first region; the first barrier layer film is etched using the fourth patterned layer as a mask to form a first barrier layer in the first groove; after forming the first barrier layer, the fourth patterned layer is removed; after removing the fourth patterned layer, a first source / drain doped layer is formed in the first source / drain opening, the first source / drain doped layer containing first source / drain ions, the first source / drain ions and the second source / drain ions having different electrical types;The first barrier layer film on the second source / drain doped layer is removed by cleaning; a dielectric layer is formed on the substrate, the dielectric layer covering the dummy gate structure, sidewalls, the first source / drain doped layer, and the second source / drain doped layer, and the dielectric layer exposing the top surfaces of the dummy gate structure and the sidewalls.

[0022] Optionally, the first source / drain ion is an N-type ion; the second source / drain ion is a P-type ion.

[0023] Optionally, the method for forming the first fin structure and the second fin structure includes: forming a fifth patterned layer on the dielectric layer, the fifth patterned layer exposing the top surface of the dummy gate structure located on the second region; removing the dummy gate structure located on the second region using the fifth patterned layer as a mask to form a second gate opening; after forming the second gate opening, removing the first channel layer exposed by the second gate opening to form a second gate recess and the second fin structure; after forming the second fin structure, removing the fifth patterned layer and forming a sixth patterned layer on the dielectric layer, the sixth patterned layer exposing the top surface of the dummy gate structure located on the first region; removing the dummy gate structure located on the first region using the sixth patterned layer as a mask to form a first gate opening; after forming the first gate opening, removing the isolation channel layer and the second channel layer exposed by the first gate opening to form a first gate recess and the first fin structure; and after forming the second fin structure, removing the sixth patterned layer.

[0024] Optionally, the method for forming the first gate structure and the second gate structure includes: forming a gate oxide layer in the first gate opening, the first gate recess, the second gate opening, and the second gate recess, the gate oxide layer surrounding the first channel layer, the barrier channel layer, and the second channel layer; forming a second gate work function layer on the surface of the gate oxide layer; forming a seventh patterning layer on the substrate, the seventh patterning layer exposing the second gate work function layer located in the first region; removing the second gate work function layer located in the first region using the seventh patterning layer as a mask; removing the seventh patterning layer; forming a first gate work function layer on the surface of the gate oxide layer in the first region and on the surface of the second gate work function layer in the second region; forming a gate material layer on the first gate work function layer and on the dielectric layer; planarizing the gate material layer until the surface of the dielectric layer is exposed to form a gate layer; the first gate structure is formed by the gate oxide layer, the first gate work function layer, and the gate layer located in the first region; and the second gate structure is formed by the gate oxide layer, the first gate work function layer, the second gate work function layer, and the gate layer located in the second region.

[0025] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0026] In the semiconductor structure of the present invention, by using the second channel layer of silicon-germanium material with a second doped ion as the channel region of the PMOS transistor, the hole mobility requirement of the PMOS transistor can be met, thereby effectively improving the performance of the final semiconductor structure. By adding the isolation channel layer, the material of the isolation channel layer is silicon doped with a third doped ion, and the third doped ion has the opposite electrical type to the second doped ion in the second channel layer, so that the parasitic transistor formed at the bottom of the PMOS transistor is of the opposite type to the PMOS transistor, thereby effectively reducing the leakage current problem at the bottom of the PMOS transistor.

[0027] In the semiconductor structure formation method of the present invention, by using the second channel layer of silicon-germanium material with a second doped ion as the channel region of the PMOS transistor, the hole mobility requirement of the PMOS transistor can be met, thereby effectively improving the performance of the final semiconductor structure. By adding the isolation channel layer, the material of which is silicon doped with a third doped ion, and the electrical type of the third doped ion being opposite to that of the second doped ion in the second channel layer, the parasitic transistor formed at the bottom of the PMOS transistor is of the opposite type to that of the PMOS transistor, thereby effectively reducing the leakage current problem at the bottom of the PMOS transistor. Furthermore, since the isolation channel layer is located below the second channel layer, during the subsequent formation of the first gate structure, only the second gate structure covering the isolation channel layer is damaged, without damaging the second gate structure covering the second channel layer, thereby reducing the impact on the threshold voltage of the PMOS transistor and improving the performance of the final semiconductor structure.

[0028] Further, the method for forming the first gate structure and the second gate structure includes: forming a gate oxide layer in the first gate opening, the first gate recess, the second gate opening, and the second gate recess, the gate oxide layer surrounding the first channel layer, the barrier channel layer, and the second channel layer; forming a second gate work function layer on the surface of the gate oxide layer; forming a seventh patterning layer on the substrate, the seventh patterning layer exposing the second gate work function layer located on the first region; removing the second gate work function layer located on the first region using the seventh patterning layer as a mask; removing the seventh patterning layer; forming a first gate work function layer on the surface of the gate oxide layer in the first region and on the surface of the second gate work function layer in the second region; forming a gate material layer on the first gate work function layer and on the dielectric layer; planarizing the gate material layer until the surface of the dielectric layer is exposed to form a gate layer; the first gate structure is formed by the gate oxide layer, the first gate work function layer, and the gate layer located in the first region; and the second gate structure is formed by the gate oxide layer, the first gate work function layer, the second gate work function layer, and the gate layer located in the second region. Since the isolation channel layer is located below the second channel layer, when etching the second gate work function layer located on the first region, only the second gate work function layer covering the isolation channel layer is damaged, and the second gate work function layer covering the second channel layer is not damaged, thereby reducing the impact on the threshold voltage of the PMOS transistor and improving the performance of the final semiconductor structure. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of a semiconductor structure.

[0030] Figures 2 to 19 This is a schematic diagram of the steps in an embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0031] As described in the background section, there are still many problems with the existing device structure of GAA. These will be explained in detail below with reference to the accompanying drawings.

[0032] Figure 1 This is a schematic diagram of a semiconductor structure.

[0033] Please refer to Figure 1A substrate 100 is provided, the substrate 100 including a first region I and a second region II adjacent to each other; a first fin structure parallel to the surface direction of the substrate 100 is formed on the first region I, the first fin including a plurality of first channel layers 101 spaced apart along the normal direction of the surface of the substrate 100; and a second fin structure parallel to the surface direction of the substrate 100 is formed on the second region II, the second fin structure including a plurality of second channel layers 102 spaced apart along the normal direction of the surface of the substrate; a first gate structure 103 is formed on the substrate 100 spanning the first fin structure, the first gate structure 103 surrounding the first channel layer 101; and a second gate structure 104 is formed on the substrate 100 spanning the second fin structure, the second gate structure 104 surrounding the second channel layer 102.

[0034] In this embodiment, the first fin structure is used to form an NMOS transistor, and the second fin structure is used to form a PMOS transistor. The PMOS transistor has a higher requirement for hole mobility in the second channel layer 102, but the hole mobility along the (100) crystal orientation of the second channel layer is low and cannot meet the hole mobility requirements of the PMOS transistor. Furthermore, since the first gate structure 103 and the second gate structure 104 also cover a portion of the substrate 100, parasitic transistors (such as...) are formed at the bottom of the NMOS and PMOS transistors. Figure 1 As shown in Part A, this can easily cause leakage problems.

[0035] In this embodiment, the formation process of the first gate structure 103 and the second gate structure 104 involves first covering the first fin structure with a first patterned layer (not shown) and then depositing the second gate structure 104 to form a PMOS transistor. After the PMOS transistor is formed, a second patterned layer (not shown) is used to cover the formed PMOS transistor, and then the first gate structure 103 is deposited to form an NMOS transistor. Before forming the first gate structure 103, the dummy gate structure (not shown) on the first region I needs to be removed. However, in the process of removing the dummy gate structure on the first region I, the formed second gate structure 104 (specifically the gate dielectric layer) will be damaged, thereby affecting the threshold voltage of the PMOS transistor and reducing the performance of the finally formed semiconductor structure.

[0036] Based on this, the present invention provides a semiconductor structure and its formation method. The material of the first channel layer is different from that of the second channel layer. By using a silicon-germanium material with a second doped ion as the channel region of the PMOS transistor, the hole mobility requirement of the PMOS transistor can be met, thereby effectively improving the performance of the final semiconductor structure. By adding the isolation channel layer, the material of which is silicon doped with a third doped ion, and the electrical type of the third doped ion is opposite to that of the second doped ion in the second channel layer, so that the parasitic transistor formed at the bottom of the PMOS transistor is of the opposite type to that of the PMOS transistor, thereby effectively reducing the leakage current problem at the bottom of the PMOS transistor. Furthermore, the isolation channel layer is located below the second channel layer, so that when the first gate structure is subsequently formed, only the second gate structure covering the isolation channel layer is damaged, without damaging the second gate structure covering the second channel layer, thereby reducing the impact on the threshold voltage of the PMOS transistor and improving the performance of the final semiconductor structure.

[0037] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] Figures 2 to 19 This is a schematic diagram of the formation process of a semiconductor structure according to an embodiment of the present invention.

[0039] Please refer to Figure 2 A substrate 200 is provided, the substrate 200 including a first region I and a second region II.

[0040] The substrate 200 can be made of silicon or germanium-silicon; in this embodiment, the substrate 200 is made of silicon.

[0041] After providing the substrate 200, the process further includes: forming a first fin structure on the first region I and forming a second fin structure on the second region. Please refer to [reference needed] for details. Figures 3 to 19 .

[0042] Please refer to Figure 3 A barrier channel material layer 201, a plurality of first channel material layers 202 and a plurality of second channel material layers 203 are formed on the substrate 200, wherein the first channel material layers 202 are located between adjacent barrier channel material layers 201 and second channel material layers 203, or between adjacent second channel material layers 203.

[0043] In this embodiment, the process of forming the isolation channel material layer 201 and the first channel material layer 202 further includes: doping the first channel material layer 202 with a first doped ion; doping the second channel material layer 203 with a second doped ion; and doping the isolation channel material layer 201 with a third doped ion; wherein the second doped ion has a different electrical type from the first doped ion, and the third doped ion has the same electrical type as the first doped ion.

[0044] In other embodiments, the first channel material layer may not be doped with any dopant ions.

[0045] In this embodiment, the first doped ion is an N-type ion; the second doped ion is a P-type ion; and the third doped ion is an N-type ion, wherein the first doped ion and the third doped ion are different N-type ions.

[0046] Please refer to Figure 4 The partition channel material layer 201, the plurality of first channel material layers 202 and the plurality of second channel material layers 203 are patterned to form a first initial fin structure and a second initial fin structure.

[0047] In this embodiment, the first initial fin structure includes the isolation channel layer 204, a plurality of first channel layers 205, and a plurality of second channel layers 206. The first channel layers 205 are located between adjacent isolation channel layers 204 and second channel layers 206, or between adjacent second channel layers 206. The second initial fin structure includes the isolation channel layer 204, a plurality of first channel layers 205, and a plurality of second channel layers 206. The first channel layers 205 are located between adjacent isolation channel layers 204 and second channel layers 206, or between adjacent second channel layers 206.

[0048] In this embodiment, the material of the first channel layer 205 is silicon doped with a first dopant ion; the material of the second channel layer is silicon germanium doped with a second dopant ion; and the material of the barrier channel layer is silicon doped with a third dopant ion.

[0049] In other embodiments, the first channel layer may not be doped with any dopant ions.

[0050] In this embodiment, the material of the second channel layer 206 is silicon germanium doped with second doped ions. Silicon germanium has a high hole mobility, which is usually 6 to 25 times that of silicon. Therefore, by using silicon germanium as the channel material of the PMOS transistor, the performance of the device can be greatly improved.

[0051] In this embodiment, the patterning process further includes etching the substrate 200 to form isolation trenches 207 within the substrate 200.

[0052] Please refer to Figure 5 After the graphical processing, the method further includes: forming an isolation layer 208 in the isolation trench 207, wherein the top surface of the isolation layer 208 is flush with the bottom surface of the isolation channel layer 204.

[0053] In this embodiment, the method for forming the isolation layer 208 includes: forming an isolation material layer (not shown) within the isolation trench 207 and on the substrate 200, the isolation material layer covering the first initial fin structure and the second initial fin structure; planarizing the isolation material layer until the top surfaces of the first initial fin structure and the second initial fin structure are exposed, thereby forming an initial isolation layer (not shown); and etching back the initial isolation layer to form the isolation layer 208.

[0054] In this embodiment, the material of the isolation layer 208 is silicon oxide.

[0055] Please refer to Figure 6 A pseudo-gate structure 209 is formed on the substrate 200, spanning adjacent first initial fin structures and second initial fin structures.

[0056] In this embodiment, the pseudo-gate structure 209 includes: a pseudo-gate dielectric layer and a pseudo-gate layer (not shown) located on the pseudo-gate dielectric layer.

[0057] In this embodiment, the material of the pseudo-gate dielectric layer is silicon oxide.

[0058] In this embodiment, the dummy gate layer is made of polycrystalline silicon; in other embodiments, the dummy gate layer may also be made of amorphous silicon.

[0059] In this embodiment, the sidewall 210 is made of silicon nitride.

[0060] Please refer to Figures 7 to 8 , Figure 8 yes Figure 7A cross-sectional view along line AA shows a sidewall material layer (not shown) formed on the sidewalls and top surface of the dummy gate structure 209; a first patterned layer (not shown) is formed on the substrate 200, exposing the sidewall material layer on the second region II; the sidewall material layer is etched using the first patterned layer as a mask until the top surface of the dummy gate structure 209 is exposed, forming a sidewall 210 on the sidewall of the dummy gate structure 209 in the second region II; the second initial fin structure is etched using the first patterned layer, the dummy gate structure 209 and the sidewall 210 on the second region II as masks, forming a second source / drain opening 212 within the second initial fin structure.

[0061] In this embodiment, the second source / drain opening 212 provides space for the subsequently formed second source / drain doped layer.

[0062] Please refer to Figure 9 , Figure 9 and Figure 8 With the view direction consistent, the portion of the first channel layer 205 exposed by the second source drain opening 212 is etched to form a second groove 214.

[0063] In this embodiment, the function of the second groove 214 is to provide space for the subsequent formation of the second barrier layer.

[0064] Please refer to Figure 10 A second barrier layer 216 is formed within the second groove 214.

[0065] In this embodiment, the method for forming the second barrier layer 216 includes: removing the first patterned layer; after removing the first patterned layer, depositing a second barrier layer film (not shown) on the first region I and the second region II; forming a second patterned layer (not shown) on the substrate 200, wherein the second patterned layer exposes the second barrier layer film on the second region II; and etching the second barrier layer film using the second patterned layer as a mask to form the second barrier layer 216.

[0066] The process for forming the second barrier layer film includes physical vapor deposition, chemical vapor deposition, or atomic layer deposition. In this embodiment, atomic layer deposition is used to form the second barrier layer film.

[0067] In this embodiment, the material of the second barrier layer 216 is silicon nitride.

[0068] Please refer to Figure 11After the second barrier layer 216 is formed, the second patterned layer is removed; after the second patterned layer is removed, a second source / drain doped layer 218 is formed in the second source / drain opening 212, and the second source / drain doped layer 218 contains second source / drain ions.

[0069] In this embodiment, the second source / drain ion is a P-type ion.

[0070] Please refer to Figures 12 to 13 , Figure 13 yes Figure 12 A schematic cross-sectional view along the BB line shows that after forming the second source / drain doped layer 218, a third patterned layer (not shown) is formed on the substrate 200. The third patterned layer exposes the sidewall material layer and the second barrier layer film on the first region I. The sidewall material layer and the second barrier layer film are etched using the third patterned layer as a mask until the top surface of the dummy gate structure 209 is exposed, forming a sidewall 210 on the sidewall of the dummy gate structure 209 in the first region I. The first initial fin structure is etched using the third patterned layer, the dummy gate structure 209 on the first region I, and the sidewall as a mask, forming a first source / drain opening 211 within the first initial fin structure.

[0071] In this embodiment, the first source / drain opening 211 provides space for the subsequently formed first source / drain doped layer.

[0072] Please refer to Figure 14 , Figure 14 and Figure 13 With the view direction consistent, the portion of the isolation channel layer 204 and the portion of the second channel layer 206 exposed by the first source drain opening 211 are etched to form a first groove 213.

[0073] In this embodiment, the first groove 213 serves to provide space for the subsequently formed first barrier layer.

[0074] Please refer to Figure 15 A first barrier layer 215 is formed in the first groove 213.

[0075] In this embodiment, the method for forming the first barrier layer 215 includes: removing the third patterned layer; after removing the third patterned layer, depositing a first barrier layer film (not shown) on the first region I and the second region II; forming a fourth patterned layer (not shown) on the substrate 200, the fourth patterned layer exposing the first barrier layer film on the first region I; and etching the first barrier layer film using the fourth patterned layer as a mask to form the first barrier layer 215.

[0076] The process for forming the first barrier layer film includes physical vapor deposition, chemical vapor deposition, or atomic layer deposition. In this embodiment, atomic layer deposition is used to form the first barrier layer film.

[0077] In this embodiment, the first barrier layer 215 is made of silicon nitride.

[0078] Please refer to Figure 16 After the first barrier layer 21 is formed, the fourth patterned layer is removed; after the fourth patterned layer is removed, a first source-drain doped layer 217 is formed in the first source-drain opening 211, the first source-drain doped layer 217 contains first source-drain ions, and the first source-drain ions and the second source-drain ions have different electrical types.

[0079] In this embodiment, the first source / drain ion is an N-type ion.

[0080] In this embodiment, a CMOS transistor is formed by the PMOS transistor and the NMOS transistor.

[0081] Please refer to Figure 17 and Figure 18 , Figure 18 yes Figure 17 A schematic cross-sectional view along the CC line shows the first barrier layer film on the second source / drain doped layer 218 being cleaned and removed. A dielectric layer 219 is formed on the substrate 200, covering the dummy gate structure 209, sidewall 210, first source / drain doped layer 217, and second source / drain doped layer 218, and exposing the top surfaces of the dummy gate structure 209 and the sidewall 210.

[0082] In this embodiment, the dielectric layer 219 is made of silicon oxide.

[0083] Please refer to Figure 19 , Figure 19 and Figure 18 With the view orientation consistent, after the medium layer 219 is formed, the first fin structure and the second fin structure are formed.

[0084] In this embodiment, the method for forming the first fin structure and the second fin structure includes: forming a fifth patterned layer (not shown) on the dielectric layer 219, the fifth patterned layer exposing the top surface of the dummy gate structure 209 located on the second region II; removing the dummy gate structure 209 located on the second region II using the fifth patterned layer as a mask to form a second gate opening (not shown); after forming the second gate opening, removing the first channel layer 205 exposed by the second gate opening to form a second gate recess (not shown) and the second fin structure; after forming the second fin structure... The fifth patterned layer is removed and a sixth patterned layer (not shown) is formed on the dielectric layer 219, the sixth patterned layer exposing the top surface of the pseudo-gate structure 209 located on the first region I; the pseudo-gate structure 209 located on the first region I is removed using the sixth patterned layer as a mask to form a first gate opening (not shown); after forming the first gate opening, the isolation channel layer 204 and the second channel layer 206 exposed by the first gate opening are removed to form a first gate recess (not shown) and the first fin structure; after forming the second fin structure, the sixth patterned layer is removed.

[0085] In this embodiment, although the ions doped in the isolation channel layer and the first channel layer belong to the same electrical type, they are different ions of the same electrical type. Therefore, they have different selectivity ratios for the removal reagent. So, the isolation channel layer is retained when the first channel layer is removed.

[0086] Please continue to refer to this. Figure 19After forming the first fin and the second fin, the method further includes: forming a gate oxide layer (not shown) in the first gate opening, the first gate recess, the second gate opening, and the second gate recess, the gate oxide layer surrounding the first channel layer 205, the barrier channel layer 204, and the second channel layer 206; forming a second gate work function layer (not shown) on the surface of the gate oxide layer; forming a seventh patterned layer (not shown) on the substrate 200, the seventh patterned layer exposing the second gate work function layer located on the first region I; using the seventh patterned layer as a mask, removing the second gate work function layer located on the first region I; removing the seventh patterned layer... A first gate work function layer (not shown) is formed on the surface of the gate oxide layer in the first region I and on the surface of the second gate work function layer in the second region II; a gate material layer (not shown) is formed on the first gate work function layer and on the dielectric layer; the gate material layer is planarized until the surface of the dielectric layer 219 is exposed to form a gate layer; a first gate structure 220 is formed by the gate oxide layer, the first gate work function layer and the gate layer located in the first region II; and a second gate structure 221 is formed by the gate oxide layer, the first gate work function layer, the second gate work function layer and the gate layer in the second region II.

[0087] In this embodiment, the first gate work function layer is used to adjust the threshold voltage of the NMOS transistor, and the second gate work function layer is used to adjust the threshold voltage of the PMOS transistor.

[0088] In this embodiment, by using the second channel layer 206 of silicon-germanium material with a second doped ion as the channel region of the PMOS transistor, the hole mobility requirement of the PMOS transistor can be met, thereby effectively improving the performance of the final semiconductor structure. By adding the isolation channel layer 204, the material of the isolation channel layer 204 is silicon doped with a third doped ion, and the third doped ion has the opposite electrical type to the second doped ion in the second channel layer 206, so that the parasitic transistor formed at the bottom of the PMOS transistor is of the opposite type to the PMOS transistor, thereby effectively reducing the leakage current problem at the bottom of the PMOS transistor.

[0089] Since the isolation channel layer 204 is located below the second channel layer 206, when etching the second gate work function layer located on the first region I, only the second gate work function layer covering the isolation channel layer 204 is damaged, and the second gate work function layer covering the second channel layer 206 is not damaged, thereby reducing the impact on the threshold voltage of the PMOS transistor and improving the performance of the final semiconductor structure.

[0090] Accordingly, an embodiment of the present invention also provides a semiconductor structure, please refer to [link / reference needed]. Figure 19 The system includes: a substrate 200, which includes a first region I and a second region II; a first fin structure located on the first region I, the first fin structure including a plurality of first channel layers 205 overlapping along the normal direction of the surface of the substrate 200, the first channel layers 205 being made of silicon doped with first doped ions or undoped silicon; and a second fin structure located on the second region II, the second fin structure including a barrier channel layer 204 and a plurality of second channel layers 206 located on the barrier channel layer 204, the barrier channel layer 204 and the plurality of second channel layers 206 overlapping along the normal direction of the surface of the substrate 200. The substrate 200 has overlapping normals on its surface. The material in the second channel layer 206 is silicon-germanium doped with a second dopant ion, and the material in the isolation channel layer 204 is silicon doped with a third dopant ion. The second dopant ion has a different electrical type from the third dopant ion and the first dopant ion, respectively. The third dopant ion has the same electrical type as the first dopant ion, and the first dopant ion and the third dopant ion are different ions of the same electrical type. The doping concentration of the third dopant ion in the isolation channel layer 204 is such that the isolation channel layer 204 cannot be turned on when the transistor is working.

[0091] In this embodiment, by using the second channel layer 206, made of silicon-germanium material with a second dopant ion, as the channel region of the PMOS transistor, the hole mobility requirement of the PMOS transistor can be met, thereby effectively improving the performance of the final semiconductor structure. By adding the isolation channel layer 204, made of silicon doped with a third dopant ion, and the third dopant ion having the opposite electrical type to the second dopant ion in the second channel layer 206, the parasitic transistor formed at the bottom of the PMOS transistor is of the opposite type to the PMOS transistor, thus effectively reducing the leakage current problem at the bottom of the PMOS transistor. Furthermore, the isolation channel layer 204 is located below the second channel layer 206, so that when the first gate structure 220 is subsequently formed, only the second gate structure 221 covering the isolation channel layer 204 is damaged, without damaging the second gate structure 221 covering the second channel layer 206. This reduces the impact on the threshold voltage of the PMOS transistor and improves the performance of the final semiconductor structure.

[0092] In this embodiment, the following are also included: the first doped ion is an N-type ion; the second doped ion is a P-type ion; the third doped ion is an N-type ion, and the first doped ion and the third doped ion are different N-type ions.

[0093] In this embodiment, it further includes: a first gate structure 220 located on the substrate 200 and spanning the first fin structure, the first gate structure 220 surrounding the first channel layer 205; and a second gate structure 221 located on the substrate 200 and spanning the second fin structure, the second gate structure 221 surrounding the isolation channel layer 204 and the second channel layer 206.

[0094] In this embodiment, it further includes: an isolation trench 207 located within the substrate 200; and an isolation layer 208 located in the isolation trench 207, the top surface of the isolation layer 208 being flush with the bottom surface of the isolation channel layer 204.

[0095] In this embodiment, it further includes: a first source / drain doped layer 211 located within the first fin structure, the first source / drain doped layer 211 having first source / drain ions; and a second source / drain doped layer 212 located within the second fin structure, the second source / drain doped layer 212 having second source / drain ions, the first source / drain ions and the second source / drain ions having different electrical types.

[0096] In this embodiment, the first source / drain ion is an N-type ion; the second source / drain ion is a P-type ion.

[0097] In this embodiment, it further includes: a sidewall 210 located on the sidewalls of the first gate structure 220 and the second gate structure 221; a first barrier layer 215 located between the first channel layer 205 and the substrate 200, and between adjacent first channel layers 205; and a second barrier layer 216 located between adjacent isolation channel layers 204 and the second channel layer 206, and between adjacent second channel layers 206.

[0098] In this embodiment, it further includes a dielectric layer 219 located on the substrate 200, the dielectric layer 219 covering the first gate structure 220, the second gate structure 221 and the sidewall 210, and the dielectric layer 219 exposing the top surfaces of the first gate structure 220, the second gate structure 221 and the sidewall 210.

[0099] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate, the substrate comprising a first region and a second region; The first fin structure located on the first region includes several layers of first channel layers that are overlapped along the normal direction of the substrate surface. The material of the first channel layers is silicon doped with first doped ions or undoped silicon. The second fin structure located on the second region includes a barrier channel layer and a plurality of second channel layers located on the barrier channel layer. The barrier channel layer and the plurality of second channel layers are arranged overlappingly along the normal direction of the substrate surface. The material in the second channel layer is silicon-germanium doped with second dopant ions, and the material in the barrier channel layer is silicon doped with third dopant ions. The second dopant ions are different in electrical type from the third dopant ions and the first dopant ions, respectively. The third dopant ions are the same in electrical type as the first dopant ions, and the first dopant ions and the third dopant ions are different ions of the same electrical type. The doping concentration of the third dopant ions in the barrier channel layer is such that the barrier channel layer cannot be turned on when the transistor is working.

2. The semiconductor structure as described in claim 1, characterized in that, The first doped ion is an N-type ion; the second doped ion is a P-type ion; and the third doped ion is an N-type ion.

3. The semiconductor structure as described in claim 1, characterized in that, Also includes: A first gate structure located on the substrate, spanning the first fin structure, the first gate structure surrounding the first channel layer; A second gate structure located on the substrate, spanning the second fin structure, the second gate structure surrounding the isolation channel layer and the second channel layer.

4. The semiconductor structure as described in claim 1, characterized in that, Also includes: Isolation trenches located within the substrate; An isolation layer located in the isolation trench, the top surface of which is flush with the bottom surface of the isolation trench layer.

5. The semiconductor structure as described in claim 1, characterized in that, Also includes: A first source / drain doped layer is located within the first fin structure, and the first source / drain doped layer contains first source / drain ions; a second source / drain doped layer is located within the second fin structure, and the second source / drain doped layer contains second source / drain ions, wherein the first source / drain ions and the second source / drain ions have different electrical types.

6. The semiconductor structure as described in claim 5, characterized in that, The first source leakage ion is an N-type ion; the second source leakage ion is a P-type ion.

7. The semiconductor structure as described in claim 3, characterized in that, Also includes: Sidewalls located on the sidewalls of the first gate structure and the second gate structure; a first barrier layer located between the first channel layer and the substrate, and between adjacent first channel layers; a second barrier layer located between adjacent isolation channel layers and the second channel layer, and between adjacent second channel layers.

8. The semiconductor structure as described in claim 7, characterized in that, Also includes: A dielectric layer is located on the substrate, the dielectric layer covering the first gate structure, the second gate structure and the sidewalls, and the dielectric layer exposes the top surfaces of the first gate structure, the second gate structure and the sidewalls.

9. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a first region and a second region; A first fin structure is formed on the first region. The first fin structure includes several layers of first channel layers that are overlapped along the normal direction of the substrate surface. The material of the first channel layers is silicon doped with first doped ions or undoped silicon. A second fin structure is formed on the second region. The second fin structure includes a barrier channel layer and a plurality of second channel layers located on the barrier channel layer. The barrier channel layer and the plurality of second channel layers are arranged overlappingly along the normal direction of the substrate surface. The material of the second channel layer is silicon germanium doped with second dopant ions. The material of the barrier channel layer is silicon doped with third dopant ions. The second dopant ions are different from the third dopant ions and the first dopant ions in electrical type. The third dopant ions are the same as the first dopant ions in electrical type. The first dopant ions and the third dopant ions are different ions of the same electrical type. The doping concentration of the third dopant ions in the barrier channel layer is such that the barrier channel layer cannot be turned on when the transistor is working.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The first doped ion is an N-type ion; the second doped ion is a P-type ion; and the third doped ion is an N-type ion.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, After forming the first fin structure and the second fin structure, the method further includes: forming a first gate structure on the substrate that spans the first fin structure, the first gate structure surrounding the first channel layer; and forming a second gate structure on the substrate that spans the second fin structure, the second gate structure surrounding the isolation channel layer and the second channel layer.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, Before forming the first fin structure and the second fin structure, the method further includes: forming a barrier channel material layer, a plurality of first channel material layers and a plurality of second channel material layers on the substrate, wherein the first channel material layers are located between adjacent barrier channel material layers and second channel material layers, or between adjacent second channel material layers.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, After forming the isolation channel material layer, the first channel material layer, and the second channel material layer, the method further includes: performing patterning processing on the isolation channel material layer, the plurality of first channel material layers, and the plurality of second channel material layers to form a first initial fin structure and a second initial fin structure. The first initial fin structure includes the isolation channel layer, the plurality of first channel layers, and the plurality of second channel layers. The first channel layers are located between adjacent isolation channel layers and second channel layers, or between adjacent second channel layers. The second initial fin structure includes the isolation channel layer, the plurality of first channel layers, and the plurality of second channel layers. The first channel layers are located between adjacent isolation channel layers and second channel layers, or between adjacent second channel layers.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The patterning process further includes: etching the substrate to form isolation trenches within the substrate; after the patterning process, the process further includes: forming an isolation layer within the isolation trenches, wherein the top surface of the isolation layer is flush with the bottom surface of the isolation trench layer.

15. The method for forming a semiconductor structure as described in claim 13, characterized in that, After forming the first initial fin structure and the second initial fin structure, the method further includes: forming a pseudo-gate structure on the substrate that spans adjacent first initial fin structures and second initial fin structures; forming a sidewall material layer on the sidewalls and top surface of the pseudo-gate structure; forming a first patterned layer on the substrate, the first patterned layer exposing the sidewall material layer on the second region; etching the sidewall material layer using the first patterned layer as a mask until the top surface of the pseudo-gate structure is exposed, forming a sidewall on the sidewall of the pseudo-gate structure in the second region; and etching the second initial fin structure using the first patterned layer, the pseudo-gate structure on the second region, and the sidewall as a mask, forming a sidewall on the sidewall of the pseudo-gate structure in the second region. A second source / drain opening is formed within the second initial fin structure; a portion of the first channel layer exposed by the second source / drain opening is etched to form a second groove; the first patterned layer is removed; after removing the first patterned layer, a second barrier layer film is deposited on the first region and the second region; a second patterned layer is formed on the substrate, the second patterned layer exposing the second barrier layer film on the second region; the second barrier layer film is etched using the second patterned layer as a mask to form a second barrier layer within the second groove; after forming the second barrier layer, the second patterned layer is removed; after removing the second patterned layer, a second source / drain doped layer is formed within the second source / drain opening, the second source / drain doped layer... The doped layer contains second source / drain ions; after forming the second source / drain doped layer, a third patterned layer is formed on the substrate, the third patterned layer exposing the sidewall material layer and the second barrier layer film on the first region; the sidewall material layer and the second barrier layer film are etched using the third patterned layer as a mask until the top surface of the dummy gate structure is exposed, forming a sidewall on the sidewall of the dummy gate structure in the first region; the first initial fin structure is etched using the third patterned layer, the dummy gate structure and the sidewall located on the first region as a mask, forming a first source / drain opening within the first initial fin structure; a portion of the isolation channel layer and a portion of the doped layer exposed by the first source / drain opening are etched. The process involves: forming a second channel layer to create a first groove; removing the third patterned layer; depositing a first barrier layer film on the first and second regions after removing the third patterned layer; forming a fourth patterned layer on the substrate, the fourth patterned layer exposing the first barrier layer film on the first region; etching the first barrier layer film using the fourth patterned layer as a mask to form a first barrier layer within the first groove; removing the fourth patterned layer after forming the first barrier layer; and forming a first source / drain doped layer within the first source / drain opening after removing the fourth patterned layer, the first source / drain doped layer containing first source / drain ions, the first source / drain ions and the second source / drain ions having different electrical types.The first barrier layer film on the second source / drain doped layer is removed by cleaning; a dielectric layer is formed on the substrate, the dielectric layer covering the dummy gate structure, sidewalls, the first source / drain doped layer, and the second source / drain doped layer, and the dielectric layer exposing the top surfaces of the dummy gate structure and the sidewalls.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The first source leakage ion is an N-type ion; the second source leakage ion is a P-type ion.

17. The method for forming a semiconductor structure as described in claim 15, characterized in that, The method for forming the first fin structure and the second fin structure includes: forming a fifth patterned layer on the dielectric layer, the fifth patterned layer exposing the top surface of the dummy gate structure located on the second region; removing the dummy gate structure located on the second region using the fifth patterned layer as a mask to form a second gate opening; after forming the second gate opening, removing the first channel layer exposed by the second gate opening to form a second gate recess and the second fin structure; after forming the second fin structure, removing the fifth patterned layer and forming a sixth patterned layer on the dielectric layer, the sixth patterned layer exposing the top surface of the dummy gate structure located on the first region; removing the dummy gate structure located on the first region using the sixth patterned layer as a mask to form a first gate opening; after forming the first gate opening, removing the isolation channel layer and the second channel layer exposed by the first gate opening to form a first gate recess and the first fin structure; and after forming the second fin structure, removing the sixth patterned layer.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The method for forming the first gate structure and the second gate structure includes: forming a gate oxide layer in the first gate opening, the first gate recess, the second gate opening, and the second gate recess, the gate oxide layer surrounding the first channel layer, the barrier channel layer, and the second channel layer; forming a second gate work function layer on the surface of the gate oxide layer; forming a seventh patterned layer on the substrate, the seventh patterned layer exposing the second gate work function layer located in the first region; removing the second gate work function layer located in the first region using the seventh patterned layer as a mask; removing the seventh patterned layer; forming a first gate work function layer on the surface of the gate oxide layer in the first region and on the surface of the second gate work function layer in the second region; forming a gate material layer on the first gate work function layer and on the dielectric layer; planarizing the gate material layer until the surface of the dielectric layer is exposed to form a gate layer; forming the first gate structure from the gate oxide layer, the first gate work function layer, and the gate layer located in the first region; and forming the second gate structure from the gate oxide layer, the first gate work function layer, the second gate work function layer, and the gate layer located in the second region.

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