Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes a substrate, a III-V compound semiconductor layer, a gate structure, a drain structure, and a field plate. The III-V compound semiconductor layer is disposed on the substrate. The gate structure, the drain structure, and the field plate are disposed on the III-V compound semiconductor layer. The field plate is located between the gate structure and the drain structure. The field plate includes a first arc-shaped sidewall located at an edge of the field plate close to the drain structure. The first arc-shaped sidewall of the field plate can be used to improve the electric field distribution in the semiconductor device, thereby improving the electrical performance of the semiconductor device.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device comprising a III-V compound semiconductor layer and a method for manufacturing the same. Background Technology

[0002] III-V group semiconductor compounds, due to their semiconductor properties, can be used to form many types of integrated circuit devices, such as high-power field-effect transistors, high-frequency transistors, or high electron mobility transistors (HEMTs). In HEMTs, two semiconductor materials with different band gaps are combined to form a heterojunction, providing a channel for charge carriers. In recent years, gallium nitride (GaN) series materials have become suitable for high-power and high-frequency products due to their wide band gap and high saturation velocity. GaN series HEMTs generate a two-dimensional electron gas (2DEG) through the piezoelectric effect of the material itself, which has high electron velocity and density, thus increasing switching speed. Therefore, how to further improve the electrical performance of transistors formed from III-V group compound materials through design changes in materials, structures, and / or fabrication methods has been a research direction for researchers in related fields. Summary of the Invention

[0003] The present invention provides a semiconductor device and a method for manufacturing the same, which improves the electric field distribution in the semiconductor device by using a field plate with arc-shaped sidewalls, thereby enhancing the electrical performance of the semiconductor device.

[0004] An embodiment of the present invention provides a semiconductor device including a substrate, a III-V compound semiconductor layer, a gate structure, a drain structure, and a field plate. The III-V compound semiconductor layer is disposed on the substrate, while the gate structure, drain structure, and field plate are disposed on the III-V compound semiconductor layer. The field plate is located between the gate structure and the drain structure, and the field plate includes a first arcuate sidewall located at an edge of the field plate near the drain structure.

[0005] An embodiment of the present invention provides a method for fabricating a semiconductor device, comprising the following steps: forming a III-V compound semiconductor layer on a substrate, and forming a gate structure, a field plate, and a drain structure on the III-V compound semiconductor layer. The field plate is located between the gate structure and the drain structure, and the field plate includes a first arcuate sidewall located at an edge of the field plate near the drain structure. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0007] Figures 2 to 5 This is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention, wherein...

[0008] Figure 3 for Figure 2 A diagram illustrating the subsequent situation;

[0009] Figure 4 for Figure 3 A diagram illustrating the subsequent situation;

[0010] Figure 5 for Figure 4 A diagram illustrating the subsequent situation.

[0011] Symbol Explanation

[0012] 10: Base

[0013] 10BS: Bottom surface

[0014] 10TS: Top surface

[0015] 12: III-V compound semiconductor layer

[0016] 14: III-V group compound barrier layer

[0017] 16: Isolation Structure

[0018] 20: P-type doped III-V compound layer

[0019] 22: Barrier Layer

[0020] 24: Dielectric layer

[0021] 26: Dielectric layer

[0022] 30: Dielectric layer

[0023] 32: Dielectric layer

[0024] 40: Conductive material layer

[0025] 50: Patterned photoresist layer

[0026] 90: Etching process

[0027] 92: Byproducts

[0028] 100: Semiconductor devices

[0029] A1: Angle

[0030] A2: Angle

[0031] BS1: Bottom surface

[0032] BS2: Bottom surface

[0033] CS1: First arc-shaped sidewall

[0034] CS2: Second arc-shaped sidewall

[0035] D1: Direction

[0036] D2: Direction

[0037] DE: Drain structure

[0038] DS1: Distance

[0039] DS2: Distance

[0040] FP: Field board

[0041] GE: Gate structure

[0042] L: Straight line

[0043] P1: Part 1

[0044] P2: Part Two

[0045] PL1: Tangent plane

[0046] PL2: Tangent plane

[0047] SE: Source structure

[0048] SW: Sidewall

[0049] TS1: Top surface

[0050] TS2: Top surface Detailed Implementation

[0051] The following detailed description of the invention discloses sufficient detail to enable those skilled in the art to practice it. The embodiments described below should be considered illustrative rather than restrictive. It will be apparent to those skilled in the art that various changes and modifications in form and detail can be made without departing from the spirit and scope of the invention.

[0052] Before further describing the various embodiments, the following will explain the specific terms used throughout the text.

[0053] The meanings of the terms “on,” “above,” and “on top of” should be interpreted in the broadest sense, such that “on” means not only “directly on” something but also includes something with other intervening features or layers in between, and that “above” or “on top of” means not only “above” or “on top of” something but can also include something “above” or “on top of” without other intervening features or layers in between (i.e., directly on something).

[0054] The ordinal numbers used in the specification and claims, such as "first" and "second", are used to modify the elements of the claims. Unless otherwise specified, they do not imply or represent any prior ordinal number of the claimed element, nor do they represent the order of one claimed element with another, or the order of manufacturing methods. The use of these ordinal numbers is only to enable a claim element with a certain name to be clearly distinguished from another claim element with the same name.

[0055] The term "etching" is generally used herein to describe a fabrication process for patterning material such that at least a portion of the material is left after etching. When a material is "etched," at least a portion of the material is retained after etching. Conversely, when a material is "removed," essentially all of the material can be removed during the process. However, in some embodiments, "removal" can be considered a broad term that includes etching.

[0056] The terms “forming” or “setting” are used below to describe the behavior of applying a layer of material to a substrate. These terms are intended to describe any feasible layer forming technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0057] Please see Figure 1 . Figure 1 The illustration shows a schematic diagram of a semiconductor device 100 according to an embodiment of the present invention. Figure 1 As shown, the semiconductor device 100 includes a substrate 10, a III-V compound semiconductor layer 12, a gate structure GE, a drain structure DE, and a field plate FP. The III-V compound semiconductor layer 12 is disposed on the substrate 10, while the gate structure GE, the drain structure DE, and the field plate FP are disposed on the III-V compound semiconductor layer 12. The field plate FP is located between the gate structure GE and the drain structure DE, and the field plate FP includes a first arcuate sidewall CS1 located at an edge of the field plate FP near the drain structure DE. The first arcuate sidewall CS1 of the field plate FP can improve the electric field distribution in the semiconductor device 100, for example, but not limited to improving the problem of corona effect, and can thus improve the electrical performance of the semiconductor device 100.

[0058] To further illustrate, in some embodiments, the substrate 10 is in a vertical direction (e.g., Figure 1 The substrate 10 may have an upper surface 10TS and a bottom surface 10BS on the direction D1 shown, and the aforementioned III-V compound semiconductor layer 12, gate structure GE, drain structure DE, and field plate FP may be disposed on one side of the upper surface 10TS. In some embodiments, direction D1 may be regarded as the thickness direction of the substrate 10, and horizontal directions that are generally orthogonal to direction D1 (such as direction D2 and other directions orthogonal to direction D1) may be generally parallel to the upper surface 10TS and / or the bottom surface 10BS of the substrate 10, but are not limited thereto. In this document, the distance in direction D1 between a relatively high position in the vertical direction (e.g., direction D1) and / or between a component and the bottom surface 10BS of the substrate 10 may be greater than the distance in direction D1 between a relatively low position in direction D1 and / or between a component and the bottom surface 10BS of the substrate 10. The lower part or bottom of each component may be closer to the bottom surface 10BS of the substrate 10 in direction D1 than the upper part or top of the component. Another component above a component may be considered to be relatively far away from the bottom surface 10BS of the substrate 10 in direction D1, while another component below a component may be considered to be relatively close to the bottom surface 10BS of the substrate 10 in direction D1.

[0059] In some embodiments, the field plate FP in the semiconductor device 100 can be used to partially deplete the two-dimensional electron gas (2DEG) beneath its covered area, thereby reducing the electric field in the off-state. Furthermore, by altering the electric field distribution through the field plate, the breakdown voltage can be increased and / or current collapse can be suppressed. In some embodiments, Figure 5 The field plate FP in the middle can be regarded as Figure 1 A magnified schematic diagram of a portion of the field plate FP in the diagram, and as shown... Figure 1 and Figure 5As shown, the first arcuate sidewall CS1 of the field plate FP may be recessed toward an upper surface TS1 of the field plate FP. The first arcuate sidewall CS1 may be directly connected to the upper surface TS1 of the field plate FP in a first portion P1, and the first arcuate sidewall CS1 may be directly connected to the bottom surface BS1 of the field plate FP in a second portion P2. In other words, the first portion P1 of the field plate FP may include the portion where the first arcuate sidewall CS1 and the upper surface TS1 are interconnected, and the second portion P2 of the field plate FP may include the portion where the first arcuate sidewall CS1 and the bottom surface BS1 are interconnected. In some embodiments, the upper surface TS1 may be regarded as the topmost surface of the field plate FP in direction D1, the bottom surface BS1 may be regarded as the bottommost surface of the field plate FP in direction D1, the first portion P1 may be regarded as the uppermost part of the edge of the field plate FP near the drain structure DE in direction D1, and the second portion P2 may be regarded as the bottommost part of the edge of the field plate FP near the drain structure DE in direction D1, but is not limited thereto. Furthermore, the portion where the first arc-shaped sidewall CS1 connects to the upper surface TS1 and the portion where the first arc-shaped sidewall CS1 connects to the bottom surface BS1 can be located on a straight line L. Since the first arc-shaped sidewall CS1 of the field plate FP is recessed toward the upper surface TS1 of the field plate FP, the straight line L can be located below the first arc-shaped sidewall CS1 in the direction D1.

[0060] In some embodiments, the angle between the upper surface TS1 and the first arcuate sidewall CS1 may be smaller than the angle between the bottom surface BS1 and the first arcuate sidewall CS1, and the distance DS1 between the first portion P1 of the field plate FP and the drain structure DE in a horizontal direction (e.g., direction D2) may be smaller than the distance DS2 between the second portion P2 of the field plate FP and the drain structure DE in direction D2. In some embodiments, the angle between the upper surface TS1 and the first arcuate sidewall CS1 may include the angle A1 between the tangent plane PL1 on the first arcuate sidewall CS1 near the junction of the first arcuate sidewall CS1 and the upper surface TS1, and the angle between the bottom surface BS1 and the first arcuate sidewall CS1 may include the angle between the tangent plane PL2 on the first arcuate sidewall CS1 near the junction of the first arcuate sidewall CS1 and the bottom surface BS1, but is not limited thereto. The angle between the tangent plane on the first arc-shaped sidewall CS1 and the upper surface TS1 and the bottom surface BS1 can vary depending on the position of the tangent plane on the first arc-shaped sidewall CS1. However, the angle between the tangent plane and the upper surface TS1 will be less than 90 degrees, while the angle between the tangent plane and the bottom surface BS1 will be greater than 90 degrees. In addition, the portion where the first arc-shaped sidewall CS1 and the upper surface TS1 are connected can be regarded as the tip of the field plate FP. With this design, the distance between the tip of the field plate FP and the III-V compound semiconductor layer 12 in the direction D1 can be relatively increased. Therefore, the tip discharge problem can be improved while using the field plate FP to achieve the above-mentioned effect, thereby improving the electrical performance of the semiconductor device 100 (e.g., but not limited to improving the breakdown voltage of the semiconductor device 100) and / or product reliability.

[0061] In some embodiments, the field plate FP may be a conductive structure, such as a metallic conductive structure formed of a single layer or multiple layers of metallic conductive material, but is not limited thereto. For example, the field plate FP may include a single layer of metallic conductive material (e.g., titanium nitride) or multiple layers of metallic conductive material stacked together (e.g., a three-layer structure formed of titanium nitride, aluminum, and titanium nitride). In some embodiments, the field plate FP may be directly connected to the gate structure GE, and the material composition of the field plate FP may be the same as that of the gate structure GE. For example, the field plate FP and the gate structure GE may both be formed of conductive material layer 40, but are not limited thereto. Furthermore, in some embodiments, the field plate FP may produce the desired effect in the semiconductor device 100 by adjusting the relative position of the field plate FP in direction D1 and / or direction D2. Thus, the upper surface TS1 of the field plate FP may be lower than an upper surface TS2 of the gate structure GE in direction D1, but is not limited thereto.

[0062] In some embodiments, the semiconductor device 100 may further include a source structure SE disposed on the III-V compound semiconductor layer 12, and at least a portion of the source structure SE and at least a portion of the drain structure DE may be located on opposite sides of the gate structure GE in direction D2. One end of the gate structure GE in direction D2 may be directly connected to the field plate FP, while the other end of the gate structure GE in direction D2 may be considered as an edge of the gate structure GE near the source structure SE. In some embodiments, the gate structure GE may include a second arcuate sidewall CS2 located at the edge of the gate structure GE near the source structure SE, and the shape and related technical features of the second arcuate sidewall CS2 may be similar to, but not limited to, the first arcuate sidewall CS1 described above. For example, the second arcuate sidewall CS2 may be recessed toward the upper surface TS2 of the gate structure GE, the upper surface TS2 may be the uppermost surface of the gate structure GE in direction D1, and the second arcuate sidewall CS2 may be directly connected to the upper surface TS2 at the edge of the gate structure GE. Furthermore, the second arc-shaped sidewall CS2 can be directly connected to the upper surface TS2 at the upper part of the edge of the gate structure GE near the source structure SE, and the second arc-shaped sidewall CS2 can be directly connected to the lower surface of the gate structure GE at the lower part of the edge of the gate structure GE near the source structure SE. The distance in direction D2 between the upper part of the edge of the gate structure GE and the source structure SE can be less than the distance in direction D2 between the lower part of the edge of the gate structure GE and the source structure SE, but is not limited thereto.

[0063] The substrate 10 may include a silicon substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, a sapphire substrate, or a substrate formed of other suitable materials, while the III-V compound semiconductor layer 12 may include gallium nitride, indium gallium nitride (InGaN), or other suitable III-V compound semiconductor materials. The source structure SE and drain structure DE may include a barrier layer (not shown) and a metal layer (not shown) disposed on the barrier layer, but are not limited thereto. In some embodiments, the source structure SE and drain structure DE may further include another barrier layer disposed on the aforementioned metal layer. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or other suitable conductive barrier materials, while the metal layer may include tungsten, copper, aluminum, titanium-aluminum alloy, aluminum-copper alloy, or other suitable metallic conductive materials. In some embodiments, a buffer layer (not shown) may be disposed between the III-V compound semiconductor layer 12 and the substrate 10. The buffer layer may include, for example, gallium nitride, aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), or other suitable buffer materials.

[0064] In some embodiments, the semiconductor device 100 may further include a III-V compound barrier layer 14, an isolation structure 16, a p-type doped III-V compound layer 20, a barrier layer 22, a dielectric layer 24, a dielectric layer 26, and a dielectric layer 30. The III-V compound barrier layer 14 may be disposed on the III-V compound semiconductor layer 12, and the III-V compound barrier layer 14 may include aluminum gallium nitride, aluminum indium nitride, aluminum gallium indium nitride, aluminum nitride (AlN), or other suitable III-V compound materials. The isolation structure 16 may be at least partially disposed in the III-V compound semiconductor layer 12 and the III-V compound barrier layer 14 to provide isolation, and the isolation structure 16 may include a single layer or multiple layers of insulating material. A p-type doped III-V compound layer 20 may be disposed on the III-V compound barrier layer 14. The p-type doped III-V compound layer 20 may include p-type doped aluminum gallium nitride, p-type doped gallium nitride, or other suitable p-type doped III-V compound materials. The p-type dopant in the p-type doped III-V compound layer 20 may include magnesium, beryllium (Be), zinc (Zn), cyclopentadienyl magnesium (Cp2Mg), combinations of the above materials, or other suitable p-type dopant. A barrier layer 22 may be disposed on the p-type doped III-V compound layer 20. The barrier layer 22 may include titanium, titanium nitride, tantalum, tantalum nitride, or other suitable conductivity barrier materials. A dielectric layer 24 may be conformally disposed on the III-V compound barrier layer 14, the p-type doped III-V compound layer 20, and the barrier layer 22. A dielectric layer 26 may be conformally disposed on the dielectric layer 24. The dielectric layer 24 may include an oxide dielectric material (e.g., aluminum oxide) or other suitable dielectric material, while the dielectric layer 26 may include an oxide dielectric material (e.g., tetraethoxysilane, TEOS), a nitride dielectric material or other suitable dielectric material.

[0065] The gate structure GE can penetrate the dielectric layer 26 and dielectric layer 24 in direction D1 to contact the barrier layer 22, and the gate structure GE can be electrically connected to the p-type doped III-V compound layer 20 through the barrier layer 22, but this is not a limitation. In some embodiments, a bottom surface BS2 of the gate structure GE can be directly connected to the barrier layer 22, and the bottom surface BS1 of the field plate FP can be higher than the bottom surface BS2 of the gate structure GE in direction D1, and the bottom surface BS2 can be regarded as the bottommost surface of the gate structure GE in direction D1, but this is not a limitation. The dielectric layer 30 can be disposed on the dielectric layer 26, and the dielectric layer 30 can include multiple layers of dielectric material, such as tetraethoxysilane, silicon oxide, silicon nitride, or other suitable dielectric materials. In some implementations, at least a portion of the gate structure GE may be considered to be disposed in the dielectric layer 30, a portion of the dielectric layer 30 may cover the gate structure GE in direction D1, and the source structure SE and the drain structure DE may be partially disposed in the III-V compound semiconductor layer 12 through the dielectric layer 30, dielectric layer 26, dielectric layer 24 and III-V compound barrier layer 14 in direction D1, but are not limited thereto.

[0066] Please see Figures 1 to 5 . Figures 2 to 5 The illustration is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention, wherein... Figure 3 It is illustrated Figure 2 A diagram illustrating the subsequent situation. Figure 4 It is illustrated Figure 3 The following is a diagram illustrating the situation, and Figure 5 It is illustrated Figure 4 A schematic diagram of the subsequent situation. In some embodiments, Figures 2 to 5 This can be considered a schematic diagram illustrating the fabrication method of a field plate in a semiconductor device, but it is not limited to this. For example... Figure 1 As shown, the method for fabricating the semiconductor device 100 in this embodiment may include the following steps: A III-V compound semiconductor layer 12 is formed on a substrate 10, and a gate structure GE, a field plate FP, and a drain structure DE are formed on the III-V compound semiconductor layer 12. The field plate FP is located between the gate structure GE and the drain structure DE, and the field plate FP includes a first arcuate sidewall CS1 located at an edge of the field plate FP near the drain structure DE.

[0067] Further explanation: The fabrication method of the semiconductor device 100 in this embodiment may include, but is not limited to, the following steps. A III-V compound semiconductor layer 12 may be formed on the upper surface 10TS of the substrate 10, and a III-V compound barrier layer 14 may be formed on the III-V compound semiconductor layer 12. In some embodiments, an isolation structure 16 may be at least partially formed in the III-V compound semiconductor layer 12 and the III-V compound barrier layer 14 to provide isolation and / or define the active region of the corresponding semiconductor device 100. A P-type doped III-V compound layer 20 may be formed on the III-V compound barrier layer 14, and a barrier layer 22 may be formed on the P-type doped III-V compound layer 20. A dielectric layer 24 may be conformally formed on the III-V compound barrier layer 14, the P-type doped III-V compound layer 20, and the barrier layer 22, and a dielectric layer 26 may be conformally formed on the dielectric layer 24. Furthermore, a portion of the dielectric layer 30 (e.g., Figure 2 The dielectric layer 32 shown can be formed on the dielectric layer 26, and after this portion of the dielectric layer 30 is formed, the gate structure GE and the field plate FP described above can be formed.

[0068] In some embodiments, the method for forming the field plate FP may include, but is not limited to, the following steps. For example... Figure 2 As shown, a conductive material layer 40 can be formed on the dielectric layer 32, and a patterned photoresist layer 50 can be formed on the conductive material layer 40. Then, as... Figure 3 As shown, a patterned photoresist layer 50 can be used as an etching mask to perform an etching process 90 on a conductive material layer 40, and a portion of the conductive material layer 40 can be patterned by the etching process 90 to form a field plate FP. In some embodiments, the etchant used in the etching process 90 may contain fluorine, but is not limited thereto. For example, the etching process 90 may include a dry etching process, and the reactive gas used in this dry etching process may include carbon tetrafluoride (CF4), octafluorocyclobutane (C4F8) or other suitable fluorine-containing reactive gases. Furthermore, during the etching process 90, by-products 92 may be formed, which may accumulate on the surface of the dielectric layer 32 and contact the sidewalls SW of the field plate FP, and by-products 92 may include fluorine-containing by-products, particularly when the etchant used in the etching process 90 contains fluorine, but is not limited thereto.

[0069] like Figure 3 and Figure 4As shown, in some embodiments, a portion of the dielectric layer 32 may be removed by the etching process 90. This situation can be considered as an over-etching design, which is used to ensure that a portion of the conductive material layer 40 can be completely removed by the etching process 90 to form the field plate FP. In some embodiments, the above-described over-etching design may lead to the formation of more byproducts 92, increasing the chance that the byproducts 92 will contact the field plate FP and react with the sidewalls SW of the field plate FP. Figure 4 and Figure 5 As shown, in some embodiments, byproduct 92 can accumulate upwards from the surface of dielectric layer 32 to first contact the lower part of the sidewall SW of field plate FP, and the sidewall SW of field plate FP can be etched by byproduct 92 to form the aforementioned first arcuate sidewall CS1. Furthermore, after etching fabrication process 90, the patterned photoresist layer 50 and byproduct 92 can be removed. Figure 4 , Figure 5 as well as Figure 1 As shown, in some embodiments, the conductive material layer 40 can be patterned using an etching process 90 to simultaneously form the field plate FP and the gate structure GE. Therefore, a portion of the conductive material layer 40 can be patterned using the etching process 90 to become the field plate FP with a first arcuate sidewall CS1, while another portion of the conductive material layer 40 can be patterned using the etching process 90 to become the gate structure GE with a second arcuate sidewall CS2. The formation method of the second arcuate sidewall CS2 can be the same as the formation method of the first arcuate sidewall CS1, but is not limited thereto. It is worth noting that in this invention, the fabrication method of the field plate FP with the first arcuate sidewall CS1 is not limited to the above-described method. Figures 2 to 5 The method shown is limited, and other suitable methods may be used to form, depending on the design requirements. Figure 1 The field plate FP shown has a first arcuate sidewall CS1.

[0070] like Figure 5 and Figure 1 As shown, after forming the field plate FP with the first arcuate sidewall CS1, other portions of the dielectric layer 30 (e.g., portions other than the dielectric layer 32) can be formed, and a source structure SE and a drain structure DE can be formed. In some embodiments, the source structure SE and the drain structure DE can be formed on the III-V compound semiconductor layer 12 and penetrate the dielectric layer 30, dielectric layer 26, dielectric layer 24 and the III-V compound barrier layer 14 in the direction D1, but are not limited thereto.

[0071] In summary, in the semiconductor device and its manufacturing method of the present invention, a field plate with arcuate sidewalls can be formed. The arcuate sidewalls can improve the electric field distribution in the semiconductor device and / or improve problems such as tip discharge while maintaining the function of the field plate, thereby improving the electrical performance and / or product reliability of the semiconductor device.

[0072] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor device, comprising: Base; A III-V compound semiconductor layer is disposed on the substrate; A gate structure is disposed on the III-V compound semiconductor layer; A drain structure is disposed on the III-V compound semiconductor layer; as well as A field plate is disposed on the III-V compound semiconductor layer and located between the gate structure and the drain structure. The field plate includes a first arcuate sidewall located at the edge of the field plate near the drain structure. The first arcuate sidewall is directly connected to the upper surface of the field plate at a first portion of the field plate and directly connected to the bottom surface of the field plate at a second portion of the field plate. The first arcuate sidewall is recessed toward the upper surface of the field plate, and the angle between the bottom surface and the first arcuate sidewall is an obtuse angle.

2. The semiconductor device of claim 1, wherein the angle between the upper surface and the first arcuate sidewall is smaller than the angle between the bottom surface and the first arcuate sidewall.

3. The semiconductor device of claim 1, wherein the horizontal distance between the first portion of the field plate and the drain structure is less than the horizontal distance between the second portion of the field plate and the drain structure.

4. The semiconductor device of claim 1, further comprising: A source structure is disposed on the III-V compound semiconductor layer, wherein the gate structure includes a second arcuate sidewall located at the edge of the gate structure near the source structure.

5. The semiconductor device of claim 4, wherein the second arcuate sidewall is recessed toward the upper surface of the gate structure.

6. The semiconductor device of claim 1, wherein the material composition of the field plate is the same as the material composition of the gate structure.

7. The semiconductor device of claim 1, wherein the field plate is directly connected to the gate structure, and the upper surface of the field plate is lower than the upper surface of the gate structure in the vertical direction.

8. The semiconductor device of claim 1, wherein the field plate is a metal conductive structure.

9. A method for manufacturing a semiconductor device, comprising: A III-V compound semiconductor layer is formed on the substrate; A gate structure is formed on the III-V compound semiconductor layer; A field plate is formed on the III-V compound semiconductor layer; as well as A drain structure is formed on the III-V compound semiconductor layer, wherein the field plate is located between the gate structure and the drain structure, and the field plate includes a first arcuate sidewall located at the edge of the field plate near the drain structure. The first arcuate sidewall is directly connected to the upper surface of the field plate at a first portion of the field plate, and directly connected to the bottom surface of the field plate at a second portion of the field plate. The first arcuate sidewall is recessed toward the upper surface of the field plate, and the angle between the bottom surface and the first arcuate sidewall is an obtuse angle.

10. The method of fabricating a semiconductor device as claimed in claim 9, wherein the method of forming the field plate comprises: An etching process is used to fabricate a conductive material layer, wherein a portion of the conductive material layer is patterned by the etching process to form the field plate, and the etchant used in the etching process contains fluorine.

11. The method of manufacturing a semiconductor device as claimed in claim 10, wherein the fluorine-containing byproduct is formed in the etching process, and the sidewall of the field plate is etched by the fluorine-containing byproduct to form the first arcuate sidewall.

12. The method of fabricating a semiconductor device as claimed in claim 10, wherein another portion of the conductive material layer is patterned by the etching process to form the gate structure.

13. The method of manufacturing a semiconductor device as claimed in claim 9, wherein the angle between the upper surface and the first arcuate sidewall is smaller than the angle between the bottom surface and the first arcuate sidewall.

14. The method of fabricating a semiconductor device as claimed in claim 9, wherein the horizontal distance between the first portion of the field plate and the drain structure is less than the horizontal distance between the second portion of the field plate and the drain structure.

15. The method of manufacturing a semiconductor device as claimed in claim 9, further comprising: A source structure is formed on the III-V compound semiconductor layer, wherein the gate structure includes a second arcuate sidewall located at the edge of the gate structure near the source structure.

16. The method of fabricating a semiconductor device as claimed in claim 15, wherein the second arcuate sidewall is recessed toward the upper surface of the gate structure.

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