Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate; forming a plurality of initial composite layers and a dummy gate structure across the plurality of initial composite layers on a portion of the substrate, the dummy gate structure being located on a portion of top surfaces and a portion of sidewall surfaces of the initial composite layers, the initial composite layers comprising a plurality of layers of superimposed sacrificial layers and initial channel layers between adjacent two of the sacrificial layers, the initial composite layers on two sides of the dummy gate structure having recesses, the sacrificial layer sidewalls exposed by the recesses being recessed relative to the initial channel layer sidewalls; forming inner sidewalls on the sacrificial layer sidewalls exposed by the recesses; after forming the inner sidewalls, etching back the exposed initial channel layers to form channel layers; and after forming the channel layers, forming source / drain layers in the recesses, which reduces the resistance of the adjacent regions and is conducive to improving the working current of the formed surrounding gate device, thereby improving the performance of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] In the current semiconductor field, the FinFET (Fin Field-Effect Transistor) is an emerging multi-gate device. Compared with planar metal-oxide-semiconductor field-effect transistors (MOSFETs), FinFETs have stronger short-channel rejection and higher operating current, and are now widely used in various semiconductor devices. However, with the further development of semiconductor technology, the transistor size has shrunk to below a few nanometers. The size of FinFETs themselves has already reached its limit. Limitations in fin spacing, short-channel effect, leakage current, and materials have made transistor manufacturing precarious, and even the physical structure cannot be completed.

[0003] Gate-all-around (GAA) devices have become a new direction for research and development in the industry. This technology is characterized by the gate completely surrounding the channel on all four sides. The source and drain no longer contact the substrate; instead, multiple source and drain electrodes, arranged laterally or perpendicularly to the gate in linear, planar, or sheet-like shapes, are used to achieve the basic structure and function of a MOSFET. This design largely solves various problems caused by reducing the gate spacing, including capacitance effects. Furthermore, since the channel is surrounded by the gate on all four sides, the channel current flows more smoothly than with the three-sided enclosure of a FinFET.

[0004] However, as an important direction for development in the industry, gate-all-around devices still need further improvement. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0006] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure comprising: a substrate; a plurality of composite layers located on a portion of the substrate, each composite layer including a plurality of overlapping channel layers, with a second gate trench between adjacent channel layers; an interlayer dielectric layer located on the surface of the substrate and the plurality of composite layers; a first gate trench located within the interlayer dielectric layer, the first gate trench spanning a portion of the sidewalls and a portion of the top surface of the plurality of composite layers, and the first gate trench and the second gate trench being interconnected; a gate structure located within the first gate trench, the gate structure including a gate, the gate also being located within the second gate trench to enclose the channel layer; an inner sidewall located between adjacent channel layers and located on the sidewall of the second gate trench, the inner sidewall protruding from the sidewall of the channel layer; a groove located within the composite layers on both sides of the gate structure, the groove exposing the sidewalls of the channel layer and the inner sidewall; and a source / drain layer located within the groove.

[0007] Optionally, the inner sidewall protrudes from the channel layer sidewall in the range of 0 nanometers to 9 nanometers; the thickness of the inner sidewall ranges from 1 nanometer to 10 nanometers.

[0008] Optionally, the gate structure further includes a gate sidewall located between the first gate trench and the interlayer dielectric layer; the inner sidewall is flush with the gate sidewall in the direction normal to the substrate surface.

[0009] Optionally, the groove is also located within the substrate on both sides of the gate structure.

[0010] Optionally, the ratio of the thickness of the channel layer to the size of the second gate trench in the direction normal to the substrate surface ranges from 3:10 to 1:1.

[0011] Accordingly, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a plurality of initial composite layers and a dummy gate structure spanning the plurality of initial composite layers on a portion of the substrate, the dummy gate structure being located on the top and sidewall surfaces of a portion of the initial composite layers, the initial composite layers comprising a plurality of overlapping sacrificial layers and an initial channel layer between two adjacent sacrificial layers, the initial composite layers on both sides of the dummy gate structure having grooves, the sidewalls of the sacrificial layers exposed by the grooves being recessed relative to the sidewalls of the initial channel layers; forming inner sidewalls on the sidewalls of the sacrificial layers exposed by the grooves; after forming the inner sidewalls, etching back the exposed initial channel layers to form a channel layer; and after forming the channel layer, forming source / drain layers within the grooves.

[0012] Optionally, the etching process for the exposed initial trench layer has an etching selectivity ratio greater than 10:1 for the initial trench layer and the inner sidewall.

[0013] Optionally, the depth of the initial trench layer exposed by the etch-back process ranges from 0 nanometers to 9 nanometers; the thickness of the inner wall ranges from 1 nanometer to 10 nanometers.

[0014] Optionally, the etching process for the exposed initial trench layer can include one or both of dry etching and wet etching.

[0015] Optionally, the process parameters of the wet etching process include: the etching solution includes NH4OH and H2O2, wherein the ratio of NH4OH to H2O2 ranges from 1:1 to 50:1, and the process temperature ranges from 25°C to 80°C.

[0016] Optionally, the process parameters of the dry etching process include: the etching gas includes NF3 and H2, wherein the flow rate of NF3 is in the range of 50 sccm to 500 sccm, and the flow rate of H2 is in the range of 2000 sccm to 3000 sccm.

[0017] Optionally, the method for forming the inner sidewall includes: forming an inner sidewall material layer on the substrate, the initial composite layer, and the surface of the dummy gate structure; etching back the inner sidewall material layer until the sidewall of the initial channel layer is exposed to form the inner sidewall.

[0018] Optionally, the dummy gate structure includes a dummy gate; after forming the source / drain layer, the method further includes: forming an interlayer dielectric layer on the substrate surface, the initial composite layer surface, and the sidewall of the dummy gate structure, the interlayer dielectric layer exposing the top surface of the dummy gate; removing the dummy gate and forming a first gate trench within the interlayer dielectric layer; removing the sacrificial layer exposed by the first gate trench and forming a second gate trench between two adjacent channel layers to form a composite layer with the initial composite layer; and forming a gate within the first gate trench and the second gate trench.

[0019] Optionally, the dummy gate structure further includes a gate sidewall located on the dummy gate sidewall; the inner sidewall is flush with the gate sidewall in the direction normal to the substrate surface.

[0020] Optionally, the method for forming the initial composite layer and the dummy gate structure includes: forming a composite material layer on the surface of the substrate, the composite material layer including a plurality of vertically overlapping sacrificial material layers and a channel material layer located between two adjacent sacrificial material layers; forming a mask layer on the surface of the composite material layer, the mask layer exposing a portion of the composite material layer; etching the composite material layer using the mask layer as a mask until the substrate is exposed, forming a plurality of transition composite layers with the composite material layer; forming the dummy gate structure spanning the transition composite layers, the dummy gate structure being located on the top and a portion of the sidewall surface of the transition composite layer; forming the grooves in the transition composite layers on both sides of the dummy gate structure and in the substrate; after forming the grooves, etching the sacrificial material layers exposed by the grooves to form openings between the channel material layers of adjacent layers, forming the sacrificial layer with the sacrificial material layers, and forming the initial channel layer with the channel material layers.

[0021] Optionally, before forming the pseudo-gate structure, an isolation structure is also formed in the substrate, the isolation structure being located between adjacent transition composite layers; the method for forming the isolation structure includes: etching the substrate using the mask layer as a mask to form an isolation trench in the substrate; and forming the isolation structure in the isolation trench.

[0022] Optionally, the groove is also located within the substrate on both sides of the dummy gate structure.

[0023] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0024] In the semiconductor structure formation method provided by the present invention, after forming the inner sidewall, the exposed initial channel layer is etched back to form the channel layer. Without changing the thickness of the inner sidewall, this method helps to reduce the size of the adjacent region between the channel layer and the source / drain layer of the device, increases the doping ion concentration in the adjacent region between the channel layer and the source / drain layer, reduces the resistance of the adjacent region, and helps to increase the operating current of the formed gate-around device, thereby improving the performance of the device.

[0025] In a semiconductor structure provided by the present invention, an inner sidewall is located between two adjacent channel layers and on the sidewall of the second gate trench. The inner sidewall protrudes from the sidewall of the channel layer, which helps to reduce the size of the adjacent region between the channel layer and the source / drain layer of the device, increase the doping ion concentration in the adjacent region between the channel layer and the source / drain layer, reduce the resistance of the adjacent region, and help to increase the operating current of the formed gate-around device, thereby improving the performance of the device. Attached Figure Description

[0026] Figures 1 to 5This is a schematic diagram of a semiconductor structure formation process;

[0027] Figures 6 to 11 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0028] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0029] As described in the background section, the performance of semiconductor structures formed using existing gate-all-around (GAO) device technology urgently needs improvement. The formation process of a semiconductor structure will now be explained and analyzed.

[0030] Figures 1 to 5 This is a schematic diagram of the semiconductor structure formation process.

[0031] Please refer to Figures 1 to 2 , Figure 1 yes Figure 2 A top-view structural diagram. Figure 2 yes Figure 1 A cross-sectional structural schematic diagram along the D1D2 direction is provided, showing a substrate 100; a plurality of composite layers parallel to a first direction X are formed on a portion of the substrate 100, the plurality of composite layers are arranged along a second direction Y, each of the composite layers includes a plurality of overlapping sacrificial layers 101 and a channel layer 102 located between two adjacent sacrificial layers 101; a pseudo gate structure is formed across the composite layers, the pseudo gate structure including a pseudo gate 103, a sidewall 104 located on the sidewall of the pseudo gate 103, and a pseudo gate oxide layer 105 located at the bottom of the pseudo gate 103 and the sidewall 104.

[0032] Please refer to Figure 3 A groove 106 is formed in the composite layer and substrate 100 on both sides of the pseudo gate structure; the sacrificial layer 101 exposed by the groove 106 is etched to form a first opening 107 between two adjacent initial channel layers 102.

[0033] It should be noted that the reference Figure 3 For reference Figure 5 The view directions are all the same Figure 2 .

[0034] Please refer to Figure 4 An inner sidewall 108 is formed within the first opening 107; after the inner sidewall 108 is formed, a source / drain layer 109 is formed within the groove 106.

[0035] Please refer to Figure 5An interlayer dielectric layer 110 is formed on the surface of the substrate 100 and the composite layer, as well as on the sidewall of the dummy gate structure, exposing the surface of the dummy gate 103. The dummy gate 103 and the dummy gate oxide layer 105 are removed, and a gate trench (not shown in the figure) is formed in the interlayer dielectric layer 110. The sacrificial layer 101 exposed by the gate trench is removed, and a second opening (not shown in the figure) is formed between two adjacent channel layers 102. A gate dielectric layer (not shown in the figure) and a gate 111 located on the gate dielectric layer are formed in the second opening and the gate trench.

[0036] The above method is used to form a gate-all-around device, wherein the adjacent region A (e.g., the channel layer 102 and the source / drain layer 109 are in contact) Figure 5 As shown, the channel layer 108 located under the sidewall 104 has a large resistance due to the low concentration of doped ions, which leads to a very low operating current of the formed gate-around device, thus affecting the performance of the device.

[0037] To address the aforementioned issues, one improvement is to reduce the thickness of the inner sidewall 108 (referring to the dimension along the extension direction of the channel layer 102). However, reducing the thickness of the inner sidewall 108 requires stricter control precision and a narrower process window. Furthermore, especially for PMOS devices, where both the source / drain layer 109 and the sacrificial layer 101 are made of germanium-silicon, thinning the inner sidewall 108 during the process of removing the sacrificial layer 101 exposed by the gate trench increases the risk of damage to the source / drain layer 109, which also affects the device's performance.

[0038] To address the aforementioned issues, the present invention provides a semiconductor structure and its formation method in which, after forming the inner sidewall, the exposed initial channel layer is etched back to form the channel layer. Without changing the thickness of the inner sidewall, this method helps to reduce the size of the adjacent region between the channel layer and the source / drain layer, increases the doping ion concentration in the adjacent region, reduces the resistance of the adjacent region, and helps to increase the operating current of the formed gate-all-around device, thereby improving the device performance.

[0039] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0040] Figures 6 to 11 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention.

[0041] Please refer to Figure 6 Substrate 200 is provided.

[0042] In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate is made of silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0043] Please refer to Figure 7 A plurality of initial composite layers and a pseudo-gate structure spanning the plurality of initial composite layers are formed on a portion of the substrate 200. The pseudo-gate structure is located on the top and a portion of the sidewall surface of the initial composite layer. The initial composite layer includes a plurality of overlapping sacrificial layers 201 and an initial channel layer 202 between two adjacent sacrificial layers 201. The initial composite layers on both sides of the pseudo-gate structure have grooves 203, and the sidewalls of the sacrificial layers 201 exposed by the grooves 203 are recessed relative to the sidewalls of the initial channel layer 202.

[0044] In this embodiment, the groove 203 is also located within the substrate 200 on both sides of the dummy gate structure. The purpose of the groove 203 being located within the substrate 200 is to fully expose the sidewalls of the initial channel layer 202, which is beneficial for forming a channel layer with relatively uniform upper and lower dimensions.

[0045] In this embodiment, the process for forming the groove 203 includes a dry etching process.

[0046] In this embodiment, the method for forming the initial composite layer and the dummy gate structure includes: forming a composite material layer (not shown in the figure) on the surface of the substrate, the composite material layer including several vertically overlapping sacrificial material layers (not shown in the figure) and a channel material layer (not shown in the figure) located between two adjacent sacrificial material layers; forming a mask layer (not shown in the figure) on the surface of the composite material layer, the mask layer exposing a portion of the composite material layer; etching the composite material layer using the mask layer as a mask until the substrate 200 is exposed, forming several transition composite layers (not shown in the figure) with the composite material layer; forming the dummy gate structure spanning the transition composite layer, the dummy gate structure being located on the top and part of the sidewall surface of the transition composite layer; forming the groove 203 in the transition composite layer on both sides of the dummy gate structure and in the substrate 200; after forming the groove 203, etching the sacrificial material layer exposed by the groove 203, forming an opening 204 between the adjacent channel material layers, forming the sacrificial layer 201 with the sacrificial material layer, and forming the initial channel layer 202 with the channel material layer.

[0047] In this embodiment, the ratio of the thickness of the initial channel layer 202 to the thickness of the sacrificial layer 201 along the normal direction of the substrate 200 surface ranges from 3:10 to 1:1.

[0048] The sacrificial material layer is made of germanium-silicon; the channel material layer is made of silicon. In this embodiment, the channel material layer is made of silicon; the sacrificial material layer is made of germanium-silicon. In other embodiments, the channel material layer can be Ge or GeSi; the sacrificial material layer can be made of ZnS, ZnSe, BeS, or GaP, etc.

[0049] In this embodiment, before forming the pseudo-gate structure, an isolation structure (not shown in the figure) is also formed in the substrate 200, and the isolation structure is located between adjacent transition composite layers.

[0050] In this embodiment, the method for forming the isolation structure includes: etching the substrate 200 using the mask layer as a mask to form an isolation trench (not shown in the figure) within the substrate 200; and forming the isolation structure within the isolation trench. The isolation structure is used to achieve electrical insulation between different devices.

[0051] The method for forming the isolation structure further includes: after forming the isolation trench, forming an isolation material layer (not shown in the figure) on the surface of the substrate 200, the transition composite layer and the first mask layer, wherein the top surface of the isolation material layer is higher than the top surface of the first mask layer; planarizing the isolation material layer until the top surface of the transition composite layer is exposed; and etching back the isolation material layer until the surface of the transition composite layer is exposed.

[0052] In this embodiment, the dummy gate structure includes a dummy gate 205.

[0053] In this embodiment, the dummy gate structure further includes a gate sidewall 206 located on the sidewall of the dummy gate 205.

[0054] The material of the gate sidewall 206 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride. In this embodiment, the material of the gate sidewall 206 is both silicon nitride and silicon carbonitride.

[0055] In this embodiment, the dummy gate structure further includes a dummy gate oxide layer 207 located at the bottom of the dummy gate 205 and the gate sidewall 206.

[0056] Please refer to Figure 8 An inner sidewall 208 is formed on the sidewall of the sacrificial layer 201 exposed in the groove 203.

[0057] The inner wall 208 is made of a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride. In this embodiment, the inner wall 208 is made of silicon nitride.

[0058] In the subsequent process of removing the sacrificial layer 201, the inner wall 208 is used to block the etchant from flowing to the source / drain layer, reducing the probability of etchant damage to the source / drain layer. Additionally, the inner wall 208 is used to isolate the subsequently formed gate and source / drain layers, reducing leakage current between them.

[0059] In this embodiment, the inner sidewall 208 and the gate sidewall 206 are flush with each other along the normal direction of the substrate 200 surface.

[0060] In this embodiment, the method for forming the inner sidewall 208 includes: forming an inner sidewall material layer (not shown in the figure) on the substrate 200, the initial composite layer and the surface of the dummy gate structure; etching back the inner sidewall material layer until the sidewall of the initial channel layer 202 of the groove 203 is exposed, thereby forming the inner sidewall 208.

[0061] Please refer to Figure 9 After the inner wall 208 is formed, the exposed initial channel layer 202 is etched back to form the channel layer 209.

[0062] The purpose of etching back the exposed channel layer 202 is to reduce the size of the adjacent region between the channel layer and the source / drain layer of the device without changing the thickness of the inner sidewall 208, increase the doping ion concentration of the adjacent region B between the channel layer and the source / drain layer, reduce the resistance of the adjacent region B, and thus improve the operating current of the formed gate-around device, thereby improving the performance of the device.

[0063] In this embodiment, the etching process of the initial channel layer 202 exposed by etching back has an etching selectivity range of greater than 10:1 for the initial channel layer 202 and the inner sidewall 208.

[0064] In this embodiment, the depth d1 of the initial channel layer exposed by the etch-back process ranges from 0 nanometers to 9 nanometers.

[0065] In this embodiment, the thickness d2 of the inner wall ranges from 1 nanometer to 10 nanometers.

[0066] The etching process for the initial trench layer exposed by the etch back includes one or both of dry etching and wet etching processes.

[0067] In this embodiment, the etching process for the initial channel layer exposed by the etch-back is a wet etching process; the process parameters of the wet etching process include: the etching solution includes NH4OH and H2O2, wherein the ratio of NH4OH to H2O2 ranges from 1:1 to 50:1, and the process temperature ranges from 25°C to 80°C.

[0068] The purpose of selecting the wet etching process parameters is to improve the etching selectivity of the initial channel layer 202 for the inner sidewall 208, thereby reducing damage to the inner sidewall during the etch-back process. Specifically, since the isolation structure within the substrate 200 is also exposed to the etching solution, the NH4OH solution also has a high etching selectivity for the initial channel layer 202 and the inner sidewall 208, which can reduce damage to the isolation structure during the etch-back process.

[0069] In another embodiment, the etching process for the initial channel layer exposed by the etch-back is a dry etching process; the process parameters of the dry etching process include: the etching gas includes NF3 and H2, wherein the flow rate of NF3 is in the range of 50 sccm to 500 sccm, and the flow rate of H2 is in the range of 2000 sccm to 3000 sccm.

[0070] Please refer to Figure 10 After the channel layer 209 is formed, the source / drain layer 210 is formed in the groove 203.

[0071] The source / drain layer 210 contains doped ions, including N-type doped ions or P-type doped ions.

[0072] In this embodiment, the source / drain layer 210 is made of germanium-silicon; the dopant ions within the source / drain layer 210 are P-type. The source / drain layer 210 is used to form a P-type device. In another embodiment, the source / drain layer is made of phosphorus-silicon; the dopant ions within the source / drain layer are N-type; the source / drain layer is used to form an N-type device.

[0073] The formation process of the source / drain layer 210 includes an epitaxial growth process.

[0074] In this embodiment, after forming the source / drain layer 210, please also refer to... Figure 11 .

[0075] Please refer to Figure 11An interlayer dielectric layer 211 is formed on the surface of the substrate 200, the surface of the initial composite layer, and the sidewall of the dummy gate structure, exposing the top surface of the dummy gate 205. The dummy gate 205 is removed, and a first gate trench (not shown) is formed in the interlayer dielectric layer 211. The sacrificial layer 201 exposed by the first gate trench is removed, and a second gate trench (not shown) is formed between two adjacent channel layers 209 to form a composite layer with the initial composite layer. A gate 212 is formed in the first gate trench and the second gate trench.

[0076] In this embodiment, the method for forming the first gate trench further includes: removing the pseudo gate oxide layer 207 at the bottom of the pseudo gate 205.

[0077] In this embodiment, the gate 212 includes a gate dielectric layer (not shown) and a gate layer (not shown) located on the gate dielectric layer. The gate dielectric layer includes a high-k dielectric material. The gate layer is made of a metal.

[0078] Accordingly, embodiments of the present invention also provide a semiconductor structure formed using the above method. Please refer to [the documentation for further details]. Figure 11 The system includes: a substrate 200; a plurality of composite layers located on a portion of the substrate 200, each composite layer including a plurality of overlapping channel layers 209, with a second gate trench (not shown) between adjacent channel layers 209; an interlayer dielectric layer 211 located on the surfaces of the substrate 200 and the plurality of composite layers; a first gate trench (not shown) located within the interlayer dielectric layer 211, the first gate trench spanning a portion of the sidewalls and a portion of the top surface of the plurality of composite layers, and the first gate trench and the second gate trench communicating with each other; a gate structure located in the first gate trench, the gate structure including a gate 205, the gate 205 also located within the second gate trench to enclose the channel layer 209; an inner sidewall 208 located between adjacent channel layers 209 and located on the sidewall of the second gate trench, the sidewall of the inner sidewall 208 protruding from the sidewall of the channel layer 209; and recesses 203 located in the composite layers on both sides of the gate structure (e.g., Figure 9 As shown), the groove 203 exposes the sidewalls of the channel layer 209 and the inner sidewall 208; the source / drain layer 210 is located within the groove 203.

[0079] The inner sidewall 208 protrudes from the sidewall of the channel layer 209, which helps to reduce the size of the adjacent region B between the channel layer 209 and the source / drain layer 210, increases the doping ion concentration of the adjacent region B between the channel layer 209 and the source / drain layer 210, reduces the resistance of the adjacent region B, and helps to increase the operating current of the formed gate-around device, thereby improving the performance of the device.

[0080] In this embodiment, the dimension d1 of the inner sidewall 208 protruding from the sidewall of the channel layer 209 ranges from 0 nanometers to 9 nanometers; the thickness d2 of the inner sidewall 208 ranges from 1 nanometer to 10 nanometers.

[0081] In this embodiment, the gate structure further includes a gate sidewall 206 located between the first gate trench and the interlayer dielectric layer 211; the inner sidewall 208 sidewall is flush with the gate sidewall 206 sidewall in the direction normal to the surface of the substrate 200.

[0082] In this embodiment, the groove 203 is also located within the substrate 200 on both sides of the gate structure.

[0083] In this embodiment, the ratio of the thickness of the channel layer 209 to the size of the second gate trench is in the range of 3:10 to 1:1 along the normal direction of the substrate 200 surface.

[0084] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A plurality of composite layers located on a portion of the substrate, each of the composite layers comprising a plurality of overlapping channel layers, wherein a second gate trench is provided between two adjacent channel layers; An interlayer dielectric layer located on the surface of the substrate and the plurality of composite layers; The first gate trench is located within the interlayer dielectric layer, and the first gate trench spans part of the sidewalls and part of the top surface of the plurality of composite layers, and the first gate trench and the second gate trench are interconnected. A gate structure located in the first gate trench, the gate structure including a gate, the gate also being located within the second gate trench to enclose the channel layer; The inner sidewall is located between two adjacent trench layers and on the sidewall of the second grid trench, and the inner sidewall protrudes from the sidewall of the trench layer. The grooves located in the composite layer on both sides of the gate structure expose the sidewalls of the channel layer and the inner sidewalls; The source / drain layer is located within the groove.

2. The semiconductor structure as described in claim 1, characterized in that, The inner sidewall protrudes from the channel layer sidewall in the range of 0 nanometers to 9 nanometers; the thickness of the inner sidewall ranges from 1 nanometer to 10 nanometers.

3. The semiconductor structure as described in claim 1, characterized in that, The gate structure further includes a gate sidewall located between the first gate trench and the interlayer dielectric layer; the inner sidewall is flush with the gate sidewall in the direction normal to the substrate surface.

4. The semiconductor structure as described in claim 1, characterized in that, The groove is also located within the substrate on both sides of the gate structure.

5. The semiconductor structure as described in claim 1, characterized in that, Along the normal direction of the substrate surface, the ratio of the thickness of the channel layer to the size of the second gate trench ranges from 3:10 to 1:

1.

6. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A plurality of initial composite layers and a pseudo gate structure spanning the plurality of initial composite layers are formed on a portion of the substrate. The pseudo gate structure is located on the top and sidewall surfaces of a portion of the initial composite layer. The initial composite layer includes a plurality of overlapping sacrificial layers and an initial channel layer between two adjacent sacrificial layers. The initial composite layers on both sides of the pseudo gate structure have grooves, and the sidewalls of the sacrificial layers exposed by the grooves are recessed relative to the sidewalls of the initial channel layers. An inner sidewall is formed on the sidewall of the sacrificial layer exposed in the groove; After the inner sidewall is formed, the exposed initial trench layer is etched back to form the trench layer; After the channel layer is formed, a source / drain layer is formed within the groove.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The etching process for the exposed initial channel layer has an etching selectivity ratio greater than 10:1 for the initial channel layer and the inner sidewall.

8. The method for forming a semiconductor structure as described in claim 6, characterized in that, The depth of the initial channel layer exposed by the etch is in the range of 0 nanometers to 9 nanometers; the thickness of the inner wall is in the range of 1 nanometer to 10 nanometers.

9. The method for forming a semiconductor structure as described in claim 6, characterized in that, The etching process for the initial trench layer exposed by the etch back includes one or both of dry etching and wet etching processes.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The process parameters of the wet etching process include: the etching solution includes NH4OH and H2O2, wherein the ratio of NH4OH to H2O2 ranges from 1:1 to 50:1, and the process temperature ranges from 25°C to 80°C.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, The process parameters of the dry etching process include: the etching gas includes NF3 and H2, wherein the flow rate of NF3 is in the range of 50 sccm to 500 sccm, and the flow rate of H2 is in the range of 2000 sccm to 3000 sccm.

12. The method for forming a semiconductor structure as described in claim 6, characterized in that, The method for forming the inner sidewall includes: forming an inner sidewall material layer on the substrate, the initial composite layer, and the surface of the dummy gate structure; and etching back the inner sidewall material layer until the sidewall of the initial channel layer is exposed to form the inner sidewall.

13. The method for forming a semiconductor structure as described in claim 6, characterized in that, The dummy gate structure includes a dummy gate; after forming the source / drain layer, it further includes: forming an interlayer dielectric layer on the substrate surface, the initial composite layer surface, and the sidewall of the dummy gate structure, the interlayer dielectric layer exposing the top surface of the dummy gate; removing the dummy gate and forming a first gate trench in the interlayer dielectric layer; removing the sacrificial layer exposed by the first gate trench and forming a second gate trench between two adjacent channel layers to form a composite layer with the initial composite layer; and forming a gate in the first gate trench and the second gate trench.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The dummy gate structure further includes a gate sidewall located on the dummy gate sidewall; the inner sidewall is flush with the gate sidewall in the direction normal to the substrate surface.

15. The method for forming a semiconductor structure as described in claim 6, characterized in that, The method for forming the initial composite layer and the dummy gate structure includes: forming a composite material layer on the surface of a substrate, the composite material layer including a plurality of vertically overlapping sacrificial material layers and a channel material layer located between two adjacent sacrificial material layers; forming a mask layer on the surface of the composite material layer, the mask layer exposing a portion of the composite material layer; etching the composite material layer using the mask layer as a mask until the substrate is exposed, forming a plurality of transition composite layers with the composite material layer; forming the dummy gate structure spanning the transition composite layers, the dummy gate structure being located on the top and a portion of the sidewall surface of the transition composite layer; forming the grooves in the transition composite layers on both sides of the dummy gate structure and in the substrate; after forming the grooves, etching the sacrificial material layers exposed by the grooves to form an opening between the channel material layers of adjacent layers, forming the sacrificial layer with the sacrificial material layers, and forming the initial channel layer with the channel material layers.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, Before forming the pseudo-gate structure, an isolation structure is also formed in the substrate, the isolation structure being located between adjacent transition composite layers; the method for forming the isolation structure includes: etching the substrate using the mask layer as a mask to form an isolation trench in the substrate; and forming the isolation structure in the isolation trench.

17. The method for forming a semiconductor structure as described in claim 6, characterized in that, The groove is also located within the substrate on both sides of the dummy gate structure.

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