Silicon carbide power device structure with improved single event effect immunity and method of fabrication

Abstract

The application provides a silicon carbide power device structure with improved anti-single particle effect capability and a preparation method thereof. + The device structure comprises: a substrate, a multilayer N-type buffer layer, an N-type drift region, a current spreading layer, a multilayer P-type mask layer, a P-type well region, a P-type source region, a central P-type column, two-side N-type source regions, an N-type source region embedded in the P-type column, an oxide, a polysilicon gate, a source and a drain. The application introduces a P-type column with an embedded N-type source region and a multilayer P-type mask layer below the P-type column and the P-type well region. The multilayer P-type mask layer can quickly extract a large amount of accumulated holes, thereby reducing instantaneous heat power and increasing energy dissipation area, thus reducing the peak temperature of the device and improving the anti-single particle burnout capability of the device. The P-type column with the embedded N-type source region and the multilayer P-type mask layer can also quickly extract a large amount of accumulated holes at the gate oxide of the JFET region, thereby reducing the strong electric field of the gate oxide and improving the anti-single particle gate penetration capability of the device.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor device technology, specifically a silicon carbide power device structure and its fabrication method for improving resistance to single-event effects. Background Technology

[0002] Silicon carbide (SiC), as one of the representatives of third-generation wide-bandgap semiconductor materials, possesses excellent material properties such as a large bandgap, high critical breakdown electric field, high thermal conductivity, and high saturation drift velocity. Compared with traditional silicon-based devices, high-voltage power devices based on silicon carbide materials exhibit superior electrical and thermal performance, enabling them to be applied in more demanding extreme application environments such as high voltage, high temperature, and radiation.

[0003] Silicon carbide MOSFETs are currently the most widely used silicon carbide power devices on the market. However, in aerospace applications, the reliability of SiC MOSFETs faces significant challenges. Currently, the single-event immunity of commercially available SiC MOSFET devices falls far short of theoretical expectations. SiC MOSFET devices typically fail due to single-event failure at less than 50% of their rated voltage, making them unsuitable for spacecraft applications.

[0004] In SiC MOSFET devices, single-event effects caused by heavy ions are mainly divided into single-event burn-out and single-event gate-through effects. When heavy ions bombard the vicinity of the source, a large number of electron-hole pairs are generated on the track. A large number of holes that cannot be extracted by the source accumulate in the P-well region, not only causing the parasitic npn transistor to turn on and further amplifying the leakage current, but also resulting in a transient strong electric field. Under the combined effect of the strong electric field and the large current, the local temperature of the device increases rapidly, causing the device to be destroyed due to high temperature, thus resulting in the single-event burn-out effect. When heavy ions bombard the gate, a large number of holes generated on the track cannot be extracted by the source in time, and therefore accumulate below the gate oxide layer, resulting in a transient strong electric field exceeding the critical breakdown electric field of the oxide layer, causing damage to the gate oxide layer, at which point the single-event gate-through effect occurs.

[0005] Currently, the hardening measures for SiC MOSFETs against single-event effects involve adding multiple N-type buffer layers between the drift region and the substrate. However, this hardening structure cannot reduce the gate oxide electric field and exhibits poor resistance to single-event gate breakdown. Improving the single-event resistance of SiC MOSFET devices has become a hot topic in this research field. Therefore, it is necessary to conduct further research on SiC MOSFET devices and propose improved structures to enhance their single-event resistance. Summary of the Invention

[0006] This invention proposes a silicon carbide power device structure to improve resistance to single-event burn-out. A P-type pillar structure, embedded in the N-type source region and connected to the source, is introduced at the center of the cell. Multiple P-type masking layers are introduced below the P-type pillar and the P-type well region. The hole extraction pillar structure, consisting of the P-type pillar embedded in the N-type source region and the multiple P-type masking layers below it, provides an additional hole extraction path. The multiple P-type masking layers can significantly reduce the localized transient thermal power caused by the combined effects of strong electric fields and large currents. The multiple P-type masking layers can also increase the energy dissipation area. Lower thermal power and a larger energy dissipation area can significantly reduce the internal temperature of the device, thereby improving the device's resistance to single-event burn-out. Furthermore, when heavy ions bombard the vicinity of the device's gate oxide, this hole extraction pillar can rapidly extract a large number of holes caused by heavy ion irradiation, thereby reducing the transient strong electric field caused by hole accumulation and improving the device's resistance to single-event gate-through.

[0007] To achieve the above-mentioned objectives, the technical solution of this invention is as follows:

[0008] A silicon carbide power device structure for improving resistance to single-event effects, comprising: N + Substrate 2, N + Drain metal 1, N below substrate 2 + A first N-type buffer layer 3, a second N-type buffer layer 4, and a third N-type buffer layer 5 are sequentially disposed above the substrate 2. An N-type drift region 6 is located above the third N-type buffer layer 5. At least three P-type masking layers are disposed above the N-type drift region 6, namely, a first P-type masking layer 8, a second P-type masking layer 9, and a third P-type masking layer 10 from bottom to top.

[0009] Two current spreading layers 7 are located in the middle above the N-type drift region 6. The upper part of the current spreading layer 7 is flush with the upper surface of the P-type well region 11, and the lower part is flush with the bottom of the lowest first P-type masking layer 8. The two current spreading layers 7 divide the first P-type masking layer 8, the second P-type masking layer 9, and the third P-type masking layer 10 into three parts: left, middle, and right. The center between the two current spreading layers 7 above the third P-type masking layer 10 is a central P-type pillar 12. The two sides of the central P-type pillar 12 are tangent to one side of each of the two current spreading layers 7. The interior of the central P-type pillar 12 is an embedded N-type source region 14. The current spreading layer above the third P-type masking layer 10... P-type well regions 11 are provided on the outer side of layer 7 away from the central P-type pillar 12. N-type source regions 13 are provided on both sides above the interior of the P-type well region 11. The upper surface of the N-type source regions 13 is flush with the upper surface of the P-type well region 11. The P-type source regions 15 are located on both sides of the P-type well region 11 above the third P-type shielding layer 10. One side of the P-type source regions 15 is flush with the side of the P-type well region 11 away from the current expansion layer 7, and the other side is flush with the third P-type shielding layer 10. The N-type source region 14, the central P-type pillar 12 and the first P-type shielding layer 8, the second P-type shielding layer 9 and the third P-type shielding layer 10 below them form a hole extraction pillar structure.

[0010] Above the two P-type source regions 15 are source metals 18, inside which is oxide 16, and inside which is a polysilicon gate 17. The source metals 18 form ohmic contacts with the central P-type pillar 12, the two P-type source regions 15, the embedded N-type source region 14, and the two N-type source regions 13. The drain metal 1 and the N-type source region 1 are connected to the source metals 14 and 15. + An ohmic contact is formed on substrate 2.

[0011] As a preferred embodiment, the current spreading layer 7 is formed by an epitaxial process; the first P-type masking layer 8, the second P-type masking layer 9, and the third P-type masking layer 10 are all formed by multiple ion implantation processes after the epitaxial growth of the current spreading layer 7.

[0012] As a preferred approach, both the P-type masking layer and the hole extraction column structure are formed by ion implantation.

[0013] As a preferred approach, the doping concentration of each P-type masking layer gradually changes, with the doping concentration of the P-type masking layer being lower the closer it is to the N-type drift region 6.

[0014] As a preferred method, N + The substrate 2, first N-type buffer layer 3, second N-type buffer layer 4, third N-type buffer layer 5, N-type drift region 6, current spread layer 7, first P-type masking layer 8, second P-type masking layer 9, third P-type masking layer 10, P-type well region 11, central P-type pillar 12, two N-type source regions 13, embedded N-type source region 14, and two P-type source regions 15 are all made of silicon carbide.

[0015] The present invention also provides a method for fabricating the silicon carbide power device structure with improved resistance to single-event effects, comprising the following steps:

[0016] Step 1: Epitaxial growth, sequentially forming the first N-type buffer layer 3, the second N-type buffer layer 4, and the third N-type buffer layer 5;

[0017] Step 2: Epitaxial growth to form N-type drift region 6 and current spreading layer 7;

[0018] Step 3: Inject aluminum ions to sequentially form the first P-type masking layer 8, the second P-type masking layer 9, the third P-type masking layer 10, the P-type well region 11, and the central P-type pillar 12;

[0019] Step 4: Nitrogen ions are injected to form the embedded N-type source region 14 within the two N-type source regions 13 on both sides and the central P-type column 12;

[0020] Step 5: Inject aluminum ions to form P-type source regions 15 on both sides, and activate annealing;

[0021] Step 6: Dry oxygen oxidation to form a gate oxide layer, followed by annealing in a nitric oxide atmosphere;

[0022] Step 7: Deposit and etch polysilicon;

[0023] Step 8: Formation of the field oxide layer;

[0024] Step 9: Etch source contact holes, deposit source ohmic contact metal and anneal; etch gate contact holes, deposit or evaporate metal to form source and gate;

[0025] Step 10: Deposit metal on the back side and alloy the drain metal.

[0026] The beneficial effects of this invention are as follows: The hole extraction pillar structure, consisting of a P-type pillar embedded in the N-type source region and multiple P-type masking layers below it, provides an additional hole extraction path. The multiple P-type masking layers can significantly reduce the localized transient thermal power caused by the combined effects of strong electric fields and large currents, and increase the energy dissipation area. Lower thermal power and a larger energy dissipation area can significantly reduce the internal temperature of the device, thereby improving the device's resistance to single-event burn-out. Furthermore, this hole extraction pillar can rapidly extract a large number of holes caused by heavy-ion irradiation, thereby reducing the transient strong electric field caused by hole accumulation and improving the device's resistance to single-event gate penetration. Attached Figure Description

[0027] Figure 1 A schematic diagram of a traditional silicon carbide MOSFET device;

[0028] Figure 2This is a schematic diagram of a common single-event hardening structure (multilayer N-type buffer layer silicon carbide MOSFET device structure);

[0029] Figure 3 This is a schematic diagram of the silicon carbide power device structure according to Embodiment 1 of the present invention;

[0030] Figure 4 This is a schematic diagram of the epitaxial growth of a multilayer N-type buffer layer in Embodiment 2 of the present invention;

[0031] Figure 5 This is a schematic diagram of the epitaxial growth of the N-type drift region and the current spreading layer in Embodiment 2 of the present invention;

[0032] Figure 6 This is a schematic diagram of the formation of a multilayer P-type masking layer by multiple aluminum ion implantations in Embodiment 2 of the present invention;

[0033] Figure 7 This is a schematic diagram of the formation of a P-type well region and a central P-type pillar by aluminum ion implantation in Embodiment 2 of the present invention;

[0034] Figure 8 This is a schematic diagram of nitrogen ion implantation forming N-type source regions on both sides and N-type source regions embedded in a P-type column in Embodiment 2 of the present invention;

[0035] Figure 9 This is a schematic diagram of aluminum ion implantation forming P-type source regions on both sides in Embodiment 2 of the present invention;

[0036] Figure 10 This is a schematic diagram of the formation of gate oxide by dry oxygen oxidation in Embodiment 2 of the present invention;

[0037] Figure 11 This is a schematic diagram of the deposition and etching of polysilicon in Embodiment 2 of the present invention;

[0038] Figure 12 This is a schematic diagram of the formation field oxygen in Embodiment 2 of the present invention;

[0039] Figure 13 This is a schematic diagram illustrating the formation of the source and gate in Embodiment 2 of the present invention;

[0040] Figure 14 This is a schematic diagram of the deposition and alloying of drain metal in Embodiment 2 of the present invention;

[0041] Figure 15 This is a schematic diagram of the silicon carbide MOSFET device structure according to Embodiment 3 of the present invention;

[0042] Where 1 is the drain metal and 2 is N +Substrate, 3 is the first N-type buffer layer, 4 is the second N-type buffer layer, 5 is the third N-type buffer layer, 6 is the N-type drift region, 7 is the current spreading layer, 8 is the first P-type masking layer, 9 is the second P-type masking layer, 10 is the third P-type masking layer, 11 is the P-type well region, 12 is the central P-type pillar, 13 is the N-type source regions on both sides, 14 is the embedded N-type source region, 15 is the P-type source regions on both sides, 16 is oxide, 17 is the polysilicon gate, 18 is the source metal, and 19 is the fourth P-type masking layer. Detailed Implementation

[0043] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0044] Example 1

[0045] A silicon carbide power device structure for improving resistance to single-event effects, comprising: N + Substrate 2, N + Drain metal 1, N below substrate 2 + A first N-type buffer layer 3, a second N-type buffer layer 4, and a third N-type buffer layer 5 are sequentially disposed above the substrate 2. An N-type drift region 6 is located above the third N-type buffer layer 5. At least three P-type masking layers are disposed above the N-type drift region 6, namely, a first P-type masking layer 8, a second P-type masking layer 9, and a third P-type masking layer 10 from bottom to top.

[0046] Two current spreading layers 7 are located in the middle above the N-type drift region 6. The upper part of the current spreading layer 7 is flush with the upper surface of the P-type well region 11, and the lower part is flush with the bottom of the lowest first P-type masking layer 8. The two current spreading layers 7 divide the first P-type masking layer 8, the second P-type masking layer 9, and the third P-type masking layer 10 into three parts: left, middle, and right. The center between the two current spreading layers 7 above the third P-type masking layer 10 is a central P-type pillar 12. The two sides of the central P-type pillar 12 are tangent to one side of each of the two current spreading layers 7. The interior of the central P-type pillar 12 is an embedded N-type source region 14. The current spreading layer above the third P-type masking layer 10... P-type well regions 11 are provided on the outer side of layer 7 away from the central P-type pillar 12. N-type source regions 13 are provided on both sides above the interior of the P-type well region 11. The upper surface of the N-type source regions 13 is flush with the upper surface of the P-type well region 11. The P-type source regions 15 are located on both sides of the P-type well region 11 above the third P-type shielding layer 10. One side of the P-type source regions 15 is flush with the side of the P-type well region 11 away from the current expansion layer 7, and the other side is flush with the third P-type shielding layer 10. The N-type source region 14, the central P-type pillar 12 and the first P-type shielding layer 8, the second P-type shielding layer 9 and the third P-type shielding layer 10 below them form a hole extraction pillar structure.

[0047] Above the two P-type source regions 15 are source metals 18, inside which is oxide 16, and inside which is a polysilicon gate 17. The source metals 18 form ohmic contacts with the central P-type pillar 12, the two P-type source regions 15, the embedded N-type source region 14, and the two N-type source regions 13. The drain metal 1 and the N-type source region 1 are connected to the source metals 14 and 15. + An ohmic contact is formed on substrate 2.

[0048] Preferably, the current spreading layer 7 is formed by epitaxial growth; the first P-type masking layer 8, the second P-type masking layer 9, and the third P-type masking layer 10 are all formed by multiple ion implantation processes after the epitaxial growth of the current spreading layer 7.

[0049] Preferably, both the P-type masking layer and the hole extraction column structure are formed by ion implantation.

[0050] Preferably, the doping concentration of each P-type masking layer gradually changes, with the doping concentration of the P-type masking layer being lower the closer it is to the N-type drift region 6.

[0051] Preferably, N + The substrate 2, first N-type buffer layer 3, second N-type buffer layer 4, third N-type buffer layer 5, N-type drift region 6, current spread layer 7, first P-type masking layer 8, second P-type masking layer 9, third P-type masking layer 10, P-type well region 11, central P-type pillar 12, two N-type source regions 13, embedded N-type source region 14, and two P-type source regions 15 are all made of silicon carbide.

[0052] The working principle of this example is as follows:

[0053] This invention introduces a P-type pillar structure embedded in the N-type source region at the center of the cell, connected to the source, and introduces multiple layers of P-type doped masking layers below the P-type pillar and the P-type well region. When the device is bombarded by heavy ions, the hole extraction pillar structure composed of the P-type pillar embedded in the N-type source region and the multiple layers of P-type masking layers below it provides an additional hole extraction path. The multiple layers of P-type masking layers can significantly reduce the local transient thermal power caused by the strong electric field and large current, and increase the energy dissipation area. Lower thermal power and larger energy dissipation area can significantly reduce the internal temperature of the device, thereby improving the device's resistance to single-event burn-out. In addition, when heavy ions bombard the vicinity of the device's gate oxide, this hole extraction pillar can quickly extract a large number of holes caused by heavy ion irradiation, reducing the transient strong electric field of the gate oxide caused by hole accumulation, thereby improving the device's resistance to single-event gate penetration.

[0054] Example 2

[0055] like Figures 4-14 As shown, this embodiment provides a method for manufacturing a silicon carbide power device structure with improved resistance to single-event effects, including the following steps:

[0056] Step 1: Epitaxial growth, sequentially forming the first N-type buffer layer 3, the second N-type buffer layer 4, and the third N-type buffer layer 5, as follows... Figure 4 As shown;

[0057] Step 2: Epitaxial growth to form the N-type drift region 6 and the current spreading layer 7, as shown in the figure. Figure 5 As shown;

[0058] Step 3: Aluminum ions are injected to sequentially form the first P-type masking layer 8, the second P-type masking layer 9, the third P-type masking layer 10, the P-type well region 11, and the central P-type pillar 12, as shown. Figure 6 and Figure 7 As shown;

[0059] Step 4: Nitrogen ions are injected to form the embedded N-type source region 14 within the two N-type source regions 13 on both sides and the central P-type column 12, as shown below. Figure 8 As shown;

[0060] Step 5: Implant aluminum ions to form P-type source regions on both sides 15, and activate annealing, as follows. Figure 9 As shown;

[0061] Step 6: Dry oxygen oxidation forms the gate oxide layer, followed by annealing in a nitric oxide atmosphere, as shown below. Figure 10 As shown;

[0062] Step 7: Deposit and etch polysilicon, such as Figure 11 As shown;

[0063] Step 8: Forming a field oxide layer, such as Figure 12 As shown;

[0064] Step 9: Etch source contact holes, deposit source ohmic contact metal and anneal; etch gate contact holes, deposit or evaporate metal to form source and gate, as shown. Figure 13 As shown;

[0065] Step 10: Deposit metal on the back side, alloy the drain metal, such as... Figure 14 As shown.

[0066] Example 3

[0067] The difference between this embodiment and Embodiment 1 is that the number of P-type masking layers is changed from 3 to 4. In the device structure of this invention, the number of P-type masking layers can be 3 or more; this embodiment only shows a device structure with 4 P-type masking layers.

[0068] like Figure 15 As shown, the fourth P-type shielding layer 19 is located above the third P-type shielding layer 10, and the P-type trap area 11 is located above the fourth P-type shielding layer 19.

[0069] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A silicon carbide power device structure for improving resistance to single-event effects, characterized in that, include: N + Substrate (2), N + Drain metal (1) below substrate (2), N + A first N-type buffer layer (3), a second N-type buffer layer (4), and a third N-type buffer layer (5) are sequentially disposed above the substrate (2). An N-type drift region (6) is located above the third N-type buffer layer (5). At least three P-type masking layers are disposed above the N-type drift region (6), namely, a first P-type masking layer (8), a second P-type masking layer (9), and a third P-type masking layer (10) from bottom to top. Two current spreading layers (7) are provided in the middle above the N-type drift region (6). The upper part of the current spreading layer (7) is flush with the upper surface of the P-type well region (11), and the lower part is flush with the bottom of the lowest first P-type masking layer (8). The two current spreading layers (7) divide the first P-type masking layer (8), the second P-type masking layer (9), and the third P-type masking layer (10) into three parts: left, middle, and right. The center between the two current spreading layers (7) above the third P-type masking layer (10) is a central P-type pillar (12). The two sides of the central P-type pillar (12) are tangent to one side of the two current spreading layers (7). The interior of the central P-type pillar (12) is an embedded N-type source region (14). The current spreading layer above the third P-type masking layer (10) is... 7) P-type well regions (11) are provided on the outer side away from the central P-type pillar (12). N-type source regions (13) are provided on both sides above the interior of the P-type well region (11). The upper surface of the N-type source regions (13) is flush with the upper surface of the P-type well region (11). The P-type source regions (15) are located on both sides of the P-type well region (11) above the third P-type masking layer (10). One side of the P-type source regions (15) is flush with the side of the P-type well region (11) away from the current extension layer (7), and the other side is flush with the third P-type masking layer (10). The N-type source region (14), the central P-type pillar (12) and the first P-type masking layer (8), the second P-type masking layer (9) and the third P-type masking layer (10) below it form a hole extraction pillar structure. Above the two P-type source regions (15) is the source metal (18), inside the source metal (18) is oxide (16), and inside the oxide (16) is the polysilicon gate (17); the source metal (18) forms ohmic contacts with the central P-type pillar (12), the two P-type source regions (15), the embedded N-type source region (14), and the two N-type source regions (13), and the drain metal (1) forms ohmic contacts with the N-type source region (13). + An ohmic contact is formed on the substrate (2).

2. The silicon carbide power device structure for improving single-event immunity according to claim 1, characterized in that: The current spreading layer (7) is formed by epitaxial process; the first P-type masking layer (8), the second P-type masking layer (9), and the third P-type masking layer (10) are all formed by multiple ion implantation processes after the epitaxial growth of the current spreading layer (7).

3. The silicon carbide power device structure for improving single-event immunity according to claim 1, characterized in that: Both the P-type masking layer and the hole extraction column structure are formed by ion implantation.

4. The silicon carbide power device structure for improving single-event immunity according to claim 1, characterized in that: The doping concentration of each P-type masking layer gradually changes, and the doping concentration of the P-type masking layer closer to the N-type drift region (6) is lower.

5. The silicon carbide power device structure for improving single-event immunity according to claim 1, characterized in that: N + The substrate (2), first N-type buffer layer (3), second N-type buffer layer (4), third N-type buffer layer (5), N-type drift region (6), current spread layer (7), first P-type masking layer (8), second P-type masking layer (9), third P-type masking layer (10), P-type well region (11), central P-type pillar (12), two N-type source regions (13), embedded N-type source region (14), and two P-type source regions (15) are all made of silicon carbide.

6. The method for fabricating the silicon carbide power device structure with improved resistance to single-event effects as described in any one of claims 1 to 5, characterized in that... Includes the following steps: Step 1: Epitaxial growth, sequentially forming the first N-type buffer layer (3), the second N-type buffer layer (4), and the third N-type buffer layer (5); Step 2: Epitaxial growth to form an N-type drift region (6) and a current spreading layer (7); Step 3: Inject aluminum ions to sequentially form the first P-type masking layer (8), the second P-type masking layer (9), the third P-type masking layer (10), the P-type well region (11), and the central P-type pillar (12); Step 4: Nitrogen ions are injected to form embedded N-type source regions (14) in the two N-type source regions (13) on both sides and the central P-type column (12); Step 5: Inject aluminum ions to form P-type source regions on both sides (15), and activate annealing; Step 6: Dry oxygen oxidation to form a gate oxide layer, followed by annealing in a nitric oxide atmosphere; Step 7: Deposit and etch polysilicon; Step 8: Formation of the field oxide layer; Step 9: Etch source contact holes, deposit source ohmic contact metal and anneal; Etch the gate contact hole, deposit or evaporate metal to form the source and gate; Step 10: Deposit metal on the back side and alloy the drain metal.

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