Silicon wafers, back contact cells, bifacial contact cells, cell assemblies and photovoltaic systems

Abstract

The application is suitable for the technical field of solar cells, and provides a silicon wafer, a back contact cell, a double-sided contact cell, a cell module and a photovoltaic system. The silicon wafer is doped with at least one of phosphorus elements, boron elements and gallium elements, the sum of the doping concentrations of all the doped elements is less than 5*10 14 atoms / cm 3 , and the resistivity of the silicon wafer is greater than 30 ohm.cm. The back contact cell adopts a first passivation contact structure, a second passivation contact structure and a back passivation film layer to realize back surface passivation. The double-sided contact cell adopts a third passivation contact structure and a fourth passivation contact structure to realize surface passivation. In this way, the doping concentration of the silicon wafer is low, the resistivity is high, the percentage of the remaining pit can be reduced, and the cost can be reduced. At the same time, the effective life of the whole cell can be dominated by the body region, the non-equilibrium carrier concentration at each part of the body region transmission channel can be kept at a high level, the local non-equilibrium carrier concentration is not too low to cause a large resistance loss, and the conversion efficiency can be ensured.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, and more particularly to a silicon wafer, a back-contact cell, a bifacial contact cell, a cell module, and a photovoltaic system. Background Technology

[0002] Currently, to produce silicon wafers for solar cells, group III or group V doping elements such as phosphorus and boron are typically added during the silicon rod formation process. In related technologies, to reduce resistance loss and ensure cell efficiency, silicon rods are usually doped with high-concentration dopants. This keeps the resistivity of the silicon wafer within a reasonable range with minimal fluctuations. For example, to ensure cell performance, high-concentration dopants can be used to control the resistivity within a narrow range such as 1-3 ohm·cm or 0.4-1.1 ohm·cm.

[0003] However, in such a technical solution, in order to ensure that the resistivity is in a small range with minimal fluctuations, the length of the silicon rod is required to be shortened during the crystal pulling process. This means that with a fixed amount of material fed at one time, the amount retained in the crucible needs to be increased. In other words, a certain crucible retention ratio must be maintained during the crystal pulling process. The crucible retention ratio is usually controlled at 30%, 40%, 50%, or even higher. This leads to lower manufacturing efficiency, reduced production capacity, and consequently, increased costs. Summary of the Invention

[0004] This application provides a silicon wafer, a back-contact cell, a bifacial contact cell, a cell module, and a photovoltaic system, aiming to solve the technical problem in the prior art where a large proportion of crucibles are left in the silicon wafer manufacturing process, resulting in decreased efficiency and production capacity, and thus increased costs.

[0005] This application is implemented as follows: the silicon wafer in this application embodiment is used in a solar cell, and the silicon wafer is doped with at least one of phosphorus, boron, and gallium, and the sum of the doping concentrations of all doped elements is less than 5*10. 14 atoms / cm 3 The resistivity of the silicon wafer after the thermal donor elimination treatment is greater than 30 ohm·cm.

[0006] Furthermore, the sum of the doping concentrations of all doped elements in the silicon wafer is less than 2*10⁻⁶. 14 atoms / cm 3 .

[0007] Furthermore, the sum of the doping concentrations of all doped elements in the silicon wafer is less than 1*10. 14 atoms / cm 3 .

[0008] Furthermore, the sum of the doping concentrations of all doped elements in the silicon wafer is less than 1*10. 13 atoms / cm 3 .

[0009] Furthermore, the resistivity of the silicon wafer after the thermal donor elimination treatment is greater than 50 ohm·cm.

[0010] Furthermore, the resistivity of the silicon wafer after the thermal donor elimination treatment is greater than 100 ohm·cm.

[0011] Furthermore, the resistivity of the silicon wafer after the thermal donor elimination treatment is greater than 200 ohm·cm.

[0012] Furthermore, the resistivity of the silicon wafer after the thermal donor elimination treatment is greater than 500 ohm·cm.

[0013] Furthermore, the resistivity of the silicon wafer after the thermal donor elimination treatment is greater than 1000 ohm·cm.

[0014] Furthermore, the resistivity of the silicon wafer after the thermal donor elimination treatment is greater than 5000 ohm·cm.

[0015] Furthermore, the thickness of the silicon wafer is 30μm-300μm.

[0016] Furthermore, the silicon wafer is also doped with at least one of Group III and / or Group V elements other than phosphorus, boron, and gallium, and the sum of the doping concentrations of all doped elements is less than 5*10⁻⁶. 14 atoms / cm 3 .

[0017] Furthermore, the doping elements include phosphorus and boron or gallium;

[0018] When the silicon wafer is a P-type silicon wafer, the ratio between the doping concentration of phosphorus and the doping concentration of boron or gallium is less than 0.2.

[0019] When the silicon wafer is an N-type silicon wafer, the ratio between the doping concentration of phosphorus and the doping concentration of boron or gallium is greater than 5.

[0020] Furthermore, the silicon wafer is a monocrystalline silicon wafer.

[0021] This application also provides a back contact battery, the back contact battery comprising a silicon wafer as described in any of the above claims, the back side of the silicon wafer having a plurality of first regions and second regions, the plurality of first regions and the plurality of second regions being arranged alternately in sequence;

[0022] A first passivated contact structure is stacked on the first region;

[0023] A second passivated contact structure is stacked on the second region, the polarity of the second passivated contact structure being different from the polarity of the first passivated contact structure; and

[0024] A back passivation film layer is stacked on the first passivation contact structure and the second passivation contact structure.

[0025] Furthermore, the first passivated contact structure includes a first tunneling layer and a first polar doped layer stacked on the first tunneling layer, wherein the first polar doped layer includes at least one of doped polycrystalline silicon, doped amorphous silicon, and doped microcrystalline silicon.

[0026] The second passivated contact structure includes a second tunneling layer and a second polar doped layer stacked on the second tunneling layer. The second polar doped layer includes at least one of doped polycrystalline silicon, doped amorphous silicon, and doped microcrystalline silicon. The polarity of the second polar doped layer is opposite to that of the first polar doped layer.

[0027] Furthermore, a trench exists between the first region and the second region, and the first passivated contact structure and the second passivated contact structure are isolated by the trench. The trench does not have a doped layer formed by doping with group III or group V elements; or

[0028] A dielectric film or an intrinsic silicon film layer is provided between the first region and the second region, and the first region and the second region are isolated from each other by the dielectric film or the intrinsic silicon film layer.

[0029] Furthermore, the front side of the silicon wafer does not have a front surface field formed by doping, or the front side of the silicon wafer has a surface doping concentration of less than 5*10. 18 atoms / cm 3 The front surface field.

[0030] This application also provides a double-sided contact battery, comprising a silicon wafer as described in any of the above claims, wherein the silicon wafer has opposing first and second surfaces;

[0031] A third passivated contact structure is stacked on the first surface; and

[0032] The fourth passivated contact structure is stacked on the second surface

[0033] Furthermore, the third passivated contact structure includes a third tunneling layer and a third polar doped layer stacked on the third tunneling layer, wherein the third polar doped layer includes at least one of doped polycrystalline silicon, doped amorphous silicon, and doped microcrystalline silicon.

[0034] The fourth passivation contact structure includes a fourth tunneling layer and a fourth polar doped layer stacked on the fourth tunneling layer. The fourth polar doped layer includes at least one of doped polycrystalline silicon, doped amorphous silicon, and doped microcrystalline silicon, and the polarity of the fourth polar doped layer is opposite to that of the third polar doped layer.

[0035] This application also provides a battery assembly, which includes a back-contact battery or a double-contact battery as described in any of the above claims.

[0036] This application also provides a photovoltaic system, which includes the above-described battery components.

[0037] In the silicon wafer, back-contact cell, bifacial contact cell, cell module, and photovoltaic system of this application embodiment, the sum of the doping concentrations of all doped elements in the silicon wafer is less than 5*10. 14 atoms / cm 3 The resistivity of the silicon wafer after heat donor elimination treatment is greater than 30 ohm·cm. In back-contact cells, a structural design with a first passivation contact structure, a second passivation contact structure, and a back passivation film layer is used to achieve back surface passivation. In double-sided contact cells, a third and fourth passivation contact structure are used to passivate the first and second surfaces. Thus, on the one hand, the silicon wafer has a lower doping concentration and higher resistivity, which can reduce the proportion of crucible residue during the manufacture of single-crystal silicon rods, improve manufacturing efficiency, and thus reduce costs. On the other hand, applying the silicon wafer of this application to back-contact cells using the surface passivation technology of the first passivation contact structure, the second passivation contact structure, and a back passivation film layer, or to double-sided contact cells using the third and fourth passivation contact structures, can significantly reduce surface recombination on the back side of the back-contact cell and surface recombination in the double-sided contact cell. This allows the characteristic lifetime of surface recombination in the back-contact cell and double-sided contact cell to reach or even exceed the bulk lifetime, thus making the effective lifetime of the entire back-contact cell and double-sided contact cell dominated by the bulk region. This ensures that the concentration of non-equilibrium carriers throughout the bulk transport channel remains at a high level, thereby reducing the significant resistance loss caused by excessively low local non-equilibrium carrier concentration and thus guaranteeing the conversion efficiency of both back-contact and double-sided contact cells. In other words, this application achieves the conversion efficiency of both back-contact and double-sided contact cells while using silicon wafers with low doping concentration and high resistivity, thereby reducing the proportion of crucible residue during the fabrication of single-crystal silicon rods and lowering costs.

[0038] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of a photovoltaic system module provided in an embodiment of this application;

[0040] Figure 2 This is a schematic diagram of a battery assembly provided in an embodiment of this application;

[0041] Figure 3 This is a cross-sectional structural diagram of the back contact battery provided in an embodiment of this application;

[0042] Figure 4 This is a cross-sectional structural diagram of a double-sided contact battery provided in an embodiment of this application;

[0043] Figure 5 This is another cross-sectional structural diagram of the back contact battery provided in the embodiments of this application;

[0044] Figure 6 This is a graph showing the relationship between silicon wafer resistivity and efficiency loss in existing battery technologies.

[0045] Figure 7 This diagram shows the relationship between bulk resistance loss, bulk Auger recombination loss and silicon wafer resistivity in existing PERC cells.

[0046] Figure 8 This is the result of the relationship between the conversion efficiency of PERC cells and the resistivity of silicon wafers in existing technologies;

[0047] Figure 9 This is a graph showing the relationship between bulk resistance loss, bulk Auger recombination loss and silicon wafer resistivity for back contact batteries and double-sided contact batteries provided in the embodiments of this application.

[0048] Figure 10 This is a graph showing the relationship between carrier concentration and silicon wafer resistivity for back-contact batteries and double-sided contact batteries provided in the embodiments of this application.

[0049] Figure 11 This application provides the relationship between silicon wafer resistivity and battery conversion efficiency for back-contact batteries and double-sided contact batteries.

[0050] Figure 12 This application provides a graph showing the relationship between silicon wafer resistivity and maximum power point current for back-contact batteries and double-sided contact batteries.

[0051] Figure 13 This is a graph showing the relationship between the concentration of non-equilibrium carriers and the minority carrier lifetime of the back contact battery and the double-sided contact battery provided in the embodiments of this application under different resistivities. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. Furthermore, it should be understood that the specific embodiments described herein are merely for explaining this application and are not intended to limit this application.

[0053] In the description of this application, it should be understood that the terms "upper", "lower", "back", "front", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0054] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0055] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0056] Please see Figure 1 The photovoltaic system 1000 in this application embodiment may include the battery module 200 in this application embodiment.

[0057] The battery assembly 200 in this application embodiment may include a plurality of back-contact batteries 100 (i.e., back-contact solar cells) in this application embodiment or a plurality of double-sided contact batteries 300 (i.e., double-sided solar cells) in this application embodiment.

[0058] Multiple back-contact cells 100 or double-sided contact cells 300 in the battery assembly 200 can be connected in series to form a battery string. These battery strings can be connected in series, in parallel, or in a series-parallel combination to achieve current collection and output. For example, the connection between individual cells can be achieved by welding solder strips, or the connection between battery strings can be achieved by busbars. In this embodiment, the silicon wafer 10 is used for a solar cell, which includes the back-contact cells 100 and double-sided contact cells 300 as described in this embodiment.

[0059] Please see Figure 3 The back contact battery 100 in this application embodiment may include the silicon wafer 10, the first passivation contact structure 20, the second passivation contact structure 30 and the back passivation film layer 40 in this application embodiment.

[0060] The silicon wafer 10 in this embodiment is doped with at least one of phosphorus, boron, and gallium, and the sum of the doping concentrations of all doped elements in the silicon wafer 10 is less than 5*10. 14 atoms / cm 3 The resistivity of silicon wafer 10 after thermal donor elimination treatment is greater than 30 ohm·cm.

[0061] like Figure 3 As shown, the back surface 11 of the silicon wafer 10 has a plurality of first regions 111 and a plurality of second regions 112, which are arranged alternately. A first passivation contact structure 20 is stacked on the first region 111, and a second passivation contact structure 30 is stacked on the second region 112. The polarity of the second passivation contact structure 30 is different from that of the first passivation contact structure 20; one of them is P-type, and the other is N-type. A back passivation film layer 40 is stacked on the first passivation contact structure 20 and the second passivation contact structure 30. Specifically, the back passivation film layer 40 can cover the entire back surface 11 of the silicon wafer 10.

[0062] Of course, it is understood that in this application, the back contact battery 100 may also include a front passivation film (not shown) disposed on the front side 12 of the silicon wafer 10, which can achieve effective passivation of the front surface.

[0063] Please see Figure 4The double-sided contact cell 300 in this embodiment may include the silicon wafer 10, the third passivation structure 301, and the fourth passivation contact structure 302 as described in this embodiment. The silicon wafer 10 has a first surface 101 and a second surface 102, which may be the front and back sides of the silicon wafer 10, respectively. Similarly, in the double-sided contact cell 300, the sum of the doping concentrations of all doped elements in the silicon wafer 10 is less than 5*10⁻⁶. 14 atoms / cm 3 The resistivity of silicon wafer 10 after thermal donor elimination treatment is greater than 30 ohm·cm. A third passivation contact structure 301 is stacked on the first surface 101, and a fourth passivation contact structure 302 is stacked on the second surface 102. Specifically, the polarity of the third passivation structure 301 is different from that of the fourth passivation contact structure 302; one of them is P-type, and the other is N-type.

[0064] In the silicon wafer 10, back contact cell 100, bifacial contact cell 300, cell module 200, and photovoltaic system 1000 of this application embodiment, the silicon wafer 10 is doped with at least one of phosphorus, boron, and gallium, and the sum of the doping concentrations of all doped elements in the silicon wafer 10 is less than 5*10. 14 atoms / cm 3 The resistivity of silicon wafer 10 after heat donor elimination treatment is greater than 30 ohm·cm. In the back contact cell 100, a structural design with a first passivation contact structure 20, a second passivation contact structure 30, and a back passivation film layer 40 is used to achieve back surface passivation. In the double-sided contact cell 300, a third passivation contact structure 301 and a fourth passivation contact structure 302 are used to passivate the first surface 101 and the second surface 102, respectively.

[0065] Thus, on the one hand, the doping concentration of the doped elements in the silicon wafer 10 is low and the resistivity is high, which can reduce the proportion of crucibles left during the manufacture of single-crystal silicon rods, improve manufacturing efficiency, and thus reduce costs. On the other hand, applying the silicon wafer 10 of this application to a back contact cell 100 using surface passivation technology with a first passivation contact structure 20, a second passivation contact structure 30, and a back passivation film layer 40, or to a double-sided contact cell 300 using a third passivation contact structure 301 and a fourth passivation contact structure 302, can significantly reduce surface recombination on the back side 11 of the back contact cell 100 and the surface recombination of the double-sided contact cell 300. This allows the characteristic lifetime of surface recombination in the back contact cell 100 and the double-sided contact cell 300 to reach or even exceed the bulk lifetime, thereby making the effective lifetime of the entire back contact cell 100 and the double-sided contact cell 300 dominated by the bulk region. This ensures that the concentration of non-equilibrium carriers throughout the bulk transport channel remains at a high level, thereby reducing the significant resistance loss caused by excessively low local non-equilibrium carrier concentration and thus guaranteeing the conversion efficiency of the back contact cell 100 and the double-sided contact cell 300. In other words, this application achieves the conversion efficiency of the back contact cell 100 and the double-sided contact cell 300 while using a silicon wafer 10 with low doping concentration and high resistivity, thereby reducing the proportion of crucible residue during the fabrication of single-crystal silicon rods and lowering costs.

[0066] In this application, the silicon wafer 10 is preferably a monocrystalline silicon wafer. Of course, in some embodiments, it may also be a polycrystalline silicon wafer, and there is no specific limitation here.

[0067] In some embodiments, the sum of the doping concentrations of all doped elements in silicon wafer 10 is less than 2*10. 14 atoms / cm 3 Furthermore, in some embodiments, the sum of the doping concentrations of all doped elements in silicon wafer 10 is preferably less than 1*10. 14 atoms / cm 3 .

[0068] Preferably, in some embodiments, the sum of the doping concentrations of all doped elements in the silicon wafer 10 is preferably less than 1*10. 13 atoms / cm 3 Thus, by optimizing the doping concentration of the doping elements in silicon wafer 10, the proportion of crucible residue can be further reduced while ensuring cell efficiency.

[0069] In some embodiments, the resistivity of the silicon wafer 10 after the thermal donor elimination treatment may be greater than 100 ohm·cm. Further, in some embodiments, the resistivity of the silicon wafer 10 after the thermal donor elimination treatment may be greater than 200 ohm·cm.

[0070] Furthermore, in some embodiments, the resistivity of the silicon wafer 10 after thermal donor elimination treatment is greater than 500 ohm·cm or greater than 1000 ohm·cm or even greater than 5000 ohm·cm.

[0071] This can further reduce the sum of bulk resistivity efficiency loss and bulk Auger recombination efficiency loss, improve conversion efficiency, and reduce the proportion of crucible residue.

[0072] In some embodiments, the thickness of the silicon wafer 10 can be 30 μm-300 μm. This avoids the situation where the silicon wafer 10 is too thin, resulting in a low concentration of photogenerated carriers, and also avoids the situation where the silicon wafer 10 is too thick, resulting in excessively high battery costs.

[0073] Specifically, the thickness of the silicon wafer 10 can be, for example, any value between 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 150μm, 200μm, 250μm, 300μm or 30μm-300μm, and is not limited here.

[0074] In some embodiments, the silicon wafer 10 may also be doped with at least one of group III elements and / or group V elements other than phosphorus, boron, and gallium, wherein the sum of the doping concentrations of all doped elements is less than 5*10. 14 atoms / cm 3 This also reduces the sum of efficiency losses caused by bulk resistance loss and bulk Auger recombination, improving conversion efficiency and reducing the proportion of crucible residue.

[0075] Specifically, for example, in some embodiments, the silicon wafer 10 may also be doped with nitrogen. The addition of nitrogen can improve the mechanical strength of the silicon wafer 10 and suppress the generation of micro-defects in the silicon wafer, thereby improving the performance of the back contact battery 100 and the double-sided contact battery 300.

[0076] In some embodiments, the doping element may include phosphorus and boron or gallium. When the silicon wafer is a P-type wafer, the ratio between the phosphorus doping concentration and the boron or gallium doping concentration is less than 0.2. When the silicon wafer is an N-type wafer, the ratio between the phosphorus doping concentration and the boron or gallium doping concentration is greater than 5.

[0077] Please see Figure 3 In some embodiments, in the back contact battery, the first passivation contact structure 20 may include a first tunneling layer 21 and a first polar doped layer 22 stacked on the first tunneling layer 21. The first polar doped layer 22 may include at least one of doped polycrystalline silicon, doped amorphous silicon, and doped microcrystalline silicon.

[0078] The second passivated contact structure 30 includes a second tunneling layer 31 and a second polar doped layer 32 stacked on the second tunneling layer 31. The second polar doped layer 32 may include at least one of doped polycrystalline silicon, doped amorphous silicon, and doped microcrystalline silicon. The polarity of the second polar doped layer 32 is opposite to that of the first polar doped layer 22. For example, when the first polar doped layer 22 is a P-type doped layer, the second polar doped layer 32 may be an N-type doped layer; when the first polar doped layer 22 is an N-type doped layer, the second polar doped layer 32 may be a P-type doped layer.

[0079] Thus, in the back contact battery 100, the first passivation contact structure 20 and the second passivation contact structure 30 adopt the above-described structural design, which can significantly reduce the back recombination of the back contact battery 100, thereby enabling the characteristic lifetime of surface recombination to reach or exceed the bulk lifetime, and thus making the effective lifetime of the back contact battery 100 dominated by the bulk lifetime.

[0080] Specifically, in such embodiments, the first tunneling layer 21 and the second tunneling layer 31 may be thin film oxide layers or thin film intrinsic silicon layers, and no specific limitation is made here.

[0081] In some embodiments, in the back contact battery 100, the front surface 12 of the silicon wafer 10 does not have a front surface field, or the front surface 12 of the silicon wafer 10 may have a surface doping concentration of less than 5*10. 18 atoms / cm 3 The front surface field. In this way, the recombination on the front side 12 of the back contact battery 100 can be greatly reduced, and the effective life of the back contact battery 100 is dominated by the bulk life.

[0082] Please see Figure 5 In some embodiments, a trench 113 is provided between the first region 111 and the second region 112, and the first passivation contact structure 20 and the second passivation contact structure 30 are isolated by the trench 13. The trench 13 does not have a doped layer formed by doping with group III or group V elements. In this way, edge recombination on the surface can be reduced.

[0083] Specifically, such as Figure 5 As shown, the back passivation film layer 40 covers the first passivation contact structure 20, the second passivation contact structure 30, and the trench 13. That is, the back passivation film layer 40 covers the first passivation contact structure 20, the second passivation contact structure 30, and the area between the first region 111 and the second region 112.

[0084] Of course, in some embodiments, a dielectric film or an intrinsic silicon film layer may also be provided between the first region 111 and the second region 112. The first region 111 and the second region 112 can be isolated from each other by the dielectric film or the intrinsic silicon film layer to reduce edge recombination. Specific details are not limited here. Specifically, the dielectric film may include insulating films such as silicon oxide and silicon nitride.

[0085] Please see Figure 4 In some embodiments, in the double-sided contact battery 300, the third passivation contact structure 301 may include a third tunneling layer 3011 and a third polar doped layer 3012 stacked on the third tunneling layer 3011. The third polar doped layer 3012 may include at least one of doped polycrystalline silicon, doped amorphous silicon, and doped microcrystalline silicon.

[0086] The fourth passivation contact structure 302 includes a fourth tunneling layer 3021 and a fourth polar doped layer 3022 stacked on the fourth tunneling layer 3021. The fourth polar doped layer 3022 may include at least one of doped polycrystalline silicon, doped amorphous silicon, and doped microcrystalline silicon. The polarity of the fourth polar doped layer 3022 is opposite to that of the third polar doped layer 3012. For example, when the third polar doped layer 3012 is a P-type doped layer, the fourth polar doped layer 3022 may be an N-type doped layer, and when the third polar doped layer 3012 is an N-type doped layer, the fourth polar doped layer 3022 may be a P-type doped layer.

[0087] Thus, by adopting the above design, the third passivation contact structure 301 and the fourth passivation contact structure 302 can significantly reduce the front and back recombination of the bi-sided contact battery 300, and the characteristic lifetime of surface recombination can reach or exceed the bulk lifetime, so that the effective lifetime of the bi-sided contact battery 300 is dominated by the bulk lifetime.

[0088] Specifically, the third tunneling layer 3011 and the fourth tunneling layer 3021 can also be thin-film oxide layers or thin-film intrinsic silicon layers, and there is no specific limitation here. Of course, it can also be understood that in the double-sided contact cell 300, other passivation film layers, such as silicon nitride film layers, can also be stacked on the third passivation contact structure 301 and the fourth passivation contact structure 302, and there is no specific limitation here.

[0089] In some embodiments, when fabricating the silicon wafer 10 and the back contact cell 100 or the double-sided contact cell 300, phosphorus gettering, surface defect gettering, or other effective gettering methods can be used to reduce impurities in the silicon wafer. At the same time, an efficient cleaning process can be used to effectively remove surface impurities, such as an ozone cleaning process, thereby controlling the defects in the silicon wafer 10 to a low level.

[0090] The following explains the specific background of this application and the technical effects it can achieve:

[0091] In the development of photovoltaic technology, before 2015, the mass production of crystalline silicon solar cells was mainly based on P-type all-Al back-field cells. These cells used boron-doped polycrystalline silicon or silicon wafers as substrates. To ensure cell performance, their resistivity ranged from 1 to 3 ohms·cm. The main reasons were:

[0092] 1. If the resistivity is too low (i.e., the boron doping concentration is too high), the bulk minority carrier lifetime will be greatly reduced, resulting in a rapid decrease in the probability of effective minority carrier collection. At the same time, if the boron doping concentration is too high, the concentration of BO recombination pairs generated by the photovoltaic product in the working environment (under sunlight) will be too high, causing a high light-induced degradation effect.

[0093] 2. Excessive resistivity will lead to excessive resistance loss due to current transmission in the silicon wafer.

[0094] In this situation, since the segregation coefficient of boron in silicon is 0.8, which is not equal to 1, whether the straightening method or the zone melting method is used, the process is a homogeneous transformation. According to the basic theory of binary phase diagrams or in actual production processes, the boron doping concentration from the head to the tail of the silicon rod will be inconsistent. If the resistivity control range is very narrow, the length of the silicon rod needs to be shortened. This will mean an increase in the proportion of material left in the pot (with a fixed amount of material, a shorter drawing length means more material is left in the pot), resulting in a decrease in production capacity and an increase in cost.

[0095] After 2015, the market share of P-type monocrystalline PERC cells rose rapidly and gradually became mainstream. In the early stages of PERC mass production, the silicon wafers used were the same as those for all-Al back cells, namely boron-doped P-type, with a resistivity range of 1-3 ohm·cm. However, technicians quickly discovered the limitations of this silicon wafer specification:

[0096] 1. The structure of localized contact on the back of PERC batteries leads to a significant increase in losses due to bulk resistance. At a resistivity of 1-3 ohm·cm, the resistance loss is too large.

[0097] 2. The bulk lifetime of boron-doped silicon wafers is affected by BO recombination pairs. As resistivity decreases, minority carrier lifetime decreases significantly, resulting in excessive recombination losses.

[0098] Thus, a contradiction arose between production volume and silicon wafer resistivity. Around 2017, the crystalline silicon industry found a way to balance this contradiction: mass production using Ga-doped low-resistivity P-type silicon wafers. Ga doping solved the impact of BO recombination on minority carrier lifetime, resulting in a significant increase in the minority carrier lifetime of low-resistivity silicon wafers. As long as the resistivity is not too low to cause a significant increase in Auger recombination, resistivity and recombination loss are approximately unrelated factors.

[0099] Thus, the industry has come to a realization regarding solar cells: lower resistivity can achieve higher conversion efficiency, and the resistivity of mass-produced silicon wafers has been adjusted to 0.4-1.1 ohm.cm.

[0100] However, under such circumstances, the proportion of crucibles left in the crystal pulling process will rise to 50%. This is because Ga has a smaller segregation coefficient than B, which is 0.008. The resistivity of different positions on the silicon rod changes more, which further amplifies the contradiction between silicon wafer resistivity and yield, and makes it difficult to reconcile. The length of the single crystal pulling is shortened, the proportion of crucibles left in the process rises, and the cost increases significantly.

[0101] Between 2015 and 2021, the efficiency of mass-produced PERC cells increased from 20.5% to 23.0%, and the cost per kilowatt-hour of photovoltaic power decreased rapidly. However, efficiency had already approached the theoretical performance for mass production, and further improvements in efficiency and cost reduction had reached a bottleneck. During the maturation of PERC mass production, engineers were searching for next-generation technologies. Several technologies competed fiercely, and ultimately three cells emerged as leaders: phosphorus-doped N-type Topcon, phosphorus-doped N-type HJT, and gallium-doped P-type HPBC. All three achieved conversion efficiencies exceeding 25% and, after evaluation, have the potential to further lead the reduction in cost per kilowatt-hour after PERC. In these cells, the silicon wafer resistivity is typically low, and the upper and lower limits of silicon wafer resistivity specifications are maintained at a certain ratio. The ingot retention rate during crystal pulling for P-type wafers is maintained at ~50%, and for N-type wafers, it is maintained at ~30-40%.

[0102] As can be seen from the above, in the field of photovoltaic technology, in order to ensure the efficiency of solar cells, there is an inherent understanding: 1. The resistivity of silicon wafers should be as low as possible; 2. Upper and lower limits should be set for resistivity; 3. In order to balance cell conversion efficiency, the proportion of crucible left at the crystal pulling end should be >30%.

[0103] The specific reasons that led to this understanding are explained below:

[0104] First, efficiency loss caused by silicon wafer resistivity.

[0105] The power loss caused by silicon wafer resistance is approximately estimated based on the current at the maximum power point. Specifically, the Jt of polycrystalline silicon cells, Topcon cells, HJT cells, and PERC cells is... mpp The point is approximately at: 34.3 mA / cm 2 39.7 mA / cm 2 37.3 mA / cm 2 39.36 mA / cm 2 Assuming all silicon wafers are 150 μm thick, calculate the volume resistivity loss caused by silicon wafers with different resistivities in the dark state, such as... Figure 6 As shown, Figure 6This is a graph showing the relationship between silicon resistivity (resistivity in the dark state) and efficiency loss for different solar cells in the prior art.

[0106] Depend on Figure 6 As can be seen, the efficiency loss caused by silicon wafer resistance increases with increasing silicon wafer resistivity, with PERC being the most sensitive. This is also the reason why the resistivity of PERC cells is chosen to be lower than that of other cells. Among them, all-Al back-mounted cells, Topcon, and HJT cells have a conversion efficiency loss of approximately 0.05% at ~2.5 ohm·cm and approximately 0.1% at ~5 ohm·cm.

[0107] Based on the current module price of RMB 1 / W and the premium of RMB 0.007 / W brought by the increase in power per W, the conversion efficiency loss of 0.05% and 0.1% will result in a revenue loss of RMB 10 million and RMB 20 million per GW of modules, respectively. The profit loss caused by the efficiency loss has a very large impact on the profit of the module business, and may even affect the company's profitability and losses.

[0108] Second, consideration of the upper and lower limits of silicon wafer resistivity specifications;

[0109] like Figure 7 As shown, Figure 7 The figure shows the simulation results of the relationship between bulk resistance loss, bulk Auger recombination loss and silicon wafer resistivity of PERC cells in the prior art;

[0110] Depend on Figure 7 It is known that the resistance loss caused by bulk resistivity is approximately a linear function; the loss increases with increasing resistivity. Auger recombination is related to the square of the carrier concentration; as resistivity decreases, the bulk Auger recombination loss increases rapidly. The sum of these two losses presents a concave curve, which is the source of the upper and lower limits for resistivity specifications. Figure 7 It can be seen that the minimum value of the sum of volume resistivity loss and volume Auger composite loss occurs in the range of 0.4-0.6 ohm·cm.

[0111] In addition, please see Figure 8 , Figure 8 The simulation results show the relationship between the conversion efficiency of PERC cells and the resistivity of silicon wafers in existing technologies.

[0112] Depend on Figure 8 It is known that the peak of the battery conversion efficiency occurs when the silicon wafer resistivity is about 0.4-0.6 ohm·cm. As the resistivity increases or decreases, the conversion efficiency decreases rapidly. However, the efficiency reduction caused by the decrease in resistivity is more significant. The underlying determining factor is the relationship between the silicon wafer resistivity and resistance loss and Auger recombination loss.

[0113] When the resistivity is <0.3 ohm.cm or >1.5 ohm.cm, an efficiency reduction of >0.1% occurs. Considering that the efficiency loss is more rapid when the resistivity is reduced, and also considering the product reliability issues, the minimum resistivity is generally set to 0.4 ohm.cm, and the upper limit of resistivity can be set to 1.1 ohm.cm, while taking into account the cost of silicon wafers.

[0114] However, after in-depth research and verification by the inventors of this application, it was found that:

[0115] 1. The bulk resistivity of a silicon wafer under illumination is related to the free carrier concentration. Silicon wafer doping affects the carrier concentration, which in turn affects the bulk resistivity of the silicon wafer under illumination. The free carrier concentration is related to the doping concentration and the non-equilibrium carrier concentration.

[0116] 2. During the operation of a solar cell, non-equilibrium charge carriers are generated under light irradiation, which will affect the actual volume resistivity (i.e., the volume resistivity under light irradiation).

[0117] 3. A higher volume resistivity (resistivity in the dark state) results in a longer volume lifetime. Under illumination, when recombination / photogeneration reaches equilibrium, the concentration of non-equilibrium carriers is higher. In other words, the higher the volume lifetime, the higher the concentration of non-equilibrium carriers, and the lower the volume resistivity under illumination.

[0118] 4. There is a strict physical correspondence between non-equilibrium carrier concentration, recombination, and battery voltage. As recombination decreases, battery voltage increases, and non-equilibrium carrier concentration also increases.

[0119] Therefore, if the concentration of non-equilibrium carriers reaches the same level as or even higher than the doping concentration of the silicon wafer, and the increase in non-equilibrium carrier concentration due to the increase in the bulk resistivity (resistivity in the dark state) of the silicon wafer can significantly reduce the bulk resistivity (resistivity under illumination) of the silicon wafer when working under illumination, thereby reducing the bulk resistivity efficiency loss, the resulting bulk resistivity efficiency loss is less than that caused by using low resistivity, highly doped silicon wafers in the prior art. In other words, when the resistivity (resistivity in the dark state) of the silicon wafer increases, the resistance loss will actually decrease under illumination due to the significant increase in the concentration of non-equilibrium carriers. At this time, the sum of the resistance efficiency loss and the Auger recombination efficiency loss (i.e., the overall efficiency loss) shows a monotonically decreasing trend with the increase of resistivity.

[0120] In order to achieve this technical objective, the inventors of this application have discovered through research that:

[0121] A back-contact battery 100 structure is adopted, and a first passivation contact structure 20, a second passivation contact structure 30, and a back passivation film layer 40 are used on the back side 11 of the back-contact battery 100. No additional surface doping is applied to the front side 12 of the back-contact battery 100 (i.e., it does not have a front surface length) or a sufficiently low surface doping is used (i.e., a low-doping-concentration front surface field is formed). Alternatively, a double-sided contact battery 300 structure is adopted, and a third passivation contact structure 301 and a fourth passivation contact structure 302 are used on the two surfaces of the double-sided contact battery 300, respectively. This significantly reduces the front / back surface recombination of the back-contact battery 100 and the double-sided contact battery 300, and the characteristic lifetime of surface recombination reaches or exceeds the bulk lifetime, making the effective battery life dominated by the bulk lifetime.

[0122] At the same time, adopting such a battery structure can ensure that the non-equilibrium carrier concentration at all points in the battery's transport channel is at a high level during operation, thereby reducing or avoiding large resistance losses caused by excessively low local non-equilibrium carrier concentration.

[0123] In other words, the inventors of this application have discovered through research and verification that the contradiction between battery efficiency and silicon wafer 10 can be resolved through the design of the above-mentioned adaptable battery structure, breaking the above-mentioned conventional wisdom. Under the premise of ensuring conversion efficiency, the use of silicon wafer 10 with lower doping concentration and higher resistivity will result in a significant reduction in silicon wafer cost, leading to a substantial decrease in the cost per kilowatt-hour of photovoltaic power.

[0124] Specifically, the test simulation results of the back contact cell 100 and the double-sided contact cell 300 of this application using the silicon wafer 100 are as follows: Figure 9 , Figure 10 and Figure 11 As shown.

[0125] Figure 9 The graph shows the relationship between bulk resistance loss, bulk Auger recombination loss and silicon wafer resistivity (resistivity in the dark) of the back contact cell 100 and double-sided contact cell 300 of this application using silicon wafer 10.

[0126] Depend on Figure 9 As can be seen, by adopting passivation contact technology for the back contact cell 100 and the bifacial cell 300, the overall efficiency loss caused by the sum of bulk resistance loss and bulk Auger recombination loss shows a monotonically decreasing trend as the resistivity of the silicon wafer 10 increases. This achieves a breakthrough in the above contradiction. That is, as the resistivity of the silicon wafer increases, the overall efficiency loss of the back contact cell 100 and the bifacial cell 300 will decrease and eventually converge.

[0127] Figure 10This is a graph showing the relationship between carrier concentration and silicon resistivity for the back contact cell 100 and double-sided contact cell 300 of the present application using the silicon wafer 10 of the present application.

[0128] Depend on Figure 10 As can be seen, when the battery operates under illumination, when the silicon wafer resistivity is >1.3 ohm·cm, the non-equilibrium carrier concentration begins to exceed the bulk doping concentration (i.e., the doping concentration of the dopant element). Ultimately, the increase in non-equilibrium carrier concentration caused by the improved lifetime due to the increase in bulk resistivity can offset the resistivity change caused by the decrease in bulk doping concentration. In other words, the increase in non-equilibrium carrier concentration caused by the increase in the bulk resistivity of the silicon wafer (resistivity in the dark state) can significantly reduce efficiency loss, thus offsetting the efficiency loss caused by the decrease in doping concentration.

[0129] Figure 11 The relationship between silicon wafer resistivity and cell conversion efficiency of the back contact cell 100 and double-sided contact cell 300 of this application using silicon wafer 10.

[0130] Depend on Figure 11 It is understood that by using the silicon wafer 10 of this application and applying it to a back contact cell 100 having a first passivation contact structure 20, a second passivation contact structure 30 and a back passivation film layer 40, or applying it to a double-sided contact cell 300 having a third passivation contact structure 301 and a fourth passivation contact structure 302, the conversion efficiency of the cell increases monotonically with the increase of the resistivity of the silicon wafer 10, and eventually converges.

[0131] In summary, this application uses a doping concentration of less than 5*10. 14 atoms / cm 3 Furthermore, the back contact cell 100 and double-sided contact cell 300 of the low-doped high-resistivity silicon wafer 10 with a resistivity greater than 30 ohm·cm can effectively reduce efficiency loss to ensure the conversion efficiency of the cell, thereby reducing the proportion of crucibles left during the fabrication of the silicon wafer 10 and reducing costs. This breaks with existing conventional wisdom and reduces manufacturing costs.

[0132] In addition, the cells using the silicon wafer 10 of this application also have the following effects:

[0133] 1. Reduced component mismatch

[0134] like Figure 12 As shown, Figure 12 This is a graph showing the relationship between the silicon resistivity and the maximum power point current of the back contact battery 100 and the double-sided contact battery 300 in the embodiments of this application.

[0135] Depend on Figure 12It is known that as resistivity increases, the maximum power point current increases and gradually stabilizes. When using batteries to make modules, the batteries are in series, and their final currents need to be consistent. If J mpp When there are significant differences, mismatch between solar cells is inevitable, leading to insufficient cell performance and a decrease in cell thickness measurement (CTM). Therefore, by appropriately adjusting the cell structure and technology, it is possible to use high-resistivity silicon wafers (i.e., silicon wafer 10 in this application) for production, which will improve the module's CTM.

[0136] 2. Improved ability to resist undesirable factors and increased power generation.

[0137] like Figure 13 As shown, Figure 13 This is a graph showing the relationship between the concentration of non-equilibrium carriers and the SRH minority carrier lifetime of the back contact battery 100 and the double-sided contact battery 300 in the embodiments of this application. The horizontal axis represents the non-equilibrium carrier concentration, and the vertical axis represents the SRH minority carrier lifetime.

[0138] The lifetime performance under different resistivity is influenced by defects with larger minority carrier trapping cross sections. Figure 13 As resistivity increases, the lifetime introduced by defects with larger minority carrier capture cross-sections shows a significant advantage under low injection conditions. This means that efficiency losses caused by silicon wafer halving, surface scratches, and metal ions will be suppressed to some extent, leading to improved product performance. Simultaneously, the increased lifetime under low injection conditions will result in better low-irradiance performance, leading to increased power generation per watt of module and a reduction in the levelized cost of electricity (LCOE).

[0139] 3. The economic value of allowing the use of high resistivity silicon wafers in production

[0140] 1. Silicon wafer cost: After the resistivity of silicon wafer 10 is greater than 30 ohm.cm and there is no upper limit to resistivity, the crystal pulling length of a single silicon rod is longer, and the amount of pot left can be greatly reduced, resulting in a significant increase in output or a significant decrease in material costs. Combined with appropriate adjustments in other aspects, the estimated cost can be reduced by ~0.011 yuan / W.

[0141] 2. Battery efficiency gains: Resistivity increases from 1-7 ohm.cm to >30 ohm.cm, resulting in an average conversion efficiency increase of approximately 0.05%, leading to cost reductions and product premium gains of approximately 0.01 yuan / W.

[0142] 3. Other benefits: The benefits brought by reduced component mismatch and reduced sensitivity to factors affecting low injection life vary depending on the actual technical level. Calculated based on an equivalent average efficiency improvement of 0.1%, the resulting cost reduction and product premium are approximately RMB 0.02 / W.

[0143] In summary, the technical solution proposed in this application is expected to generate a revenue of RMB 0.041 / W. In 2022, the production capacities of major domestic photovoltaic manufacturers were 85GW, 65GW, 65GW, and 50GW, respectively, with corresponding net profits of RMB 14.8 billion, RMB 2.93 billion, RMB 3.68 billion, and RMB 5.53 billion. If the technical effects of this application are adopted, the revenue generated would be RMB 3.485 billion, RMB 2.665 billion, RMB 2.665 billion, and RMB 2.05 billion, respectively, equivalent to increases in net profit of 23.5%, 91.0%, 72.4%, and 37.1%, demonstrating significant economic value.

[0144] In the description of this specification, the references to terms such as "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0145] Furthermore, the above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A back contact battery with a passivated contact structure, characterized in that, The back contact battery includes: The silicon wafer is a monocrystalline silicon wafer, and it is doped with at least one dopant element selected from phosphorus, boron, and gallium, wherein the sum of the doping concentrations of all dopant elements is less than 5*10⁻⁶. 14 atoms / cm 3 The resistivity of the silicon wafer after thermal donor elimination treatment is greater than 30 ohm·cm; the silicon wafer is a silicon wafer that has undergone phosphorus gettering or surface defect gettering treatment; the thickness of the silicon wafer is 30μm-300μm; The back side of the silicon wafer has a plurality of first regions and a plurality of second regions, which are arranged alternately and at intervals in sequence. A first passivated contact structure is stacked on the first region; A second passivated contact structure is stacked on the second region, the polarity of the second passivated contact structure being different from the polarity of the first passivated contact structure; and A back passivation film layer is stacked on the first passivation contact structure and the second passivation contact structure; The first region and the second region are separated by a trench, and the first passivation contact structure and the second passivation contact structure are isolated by the trench. Alternatively, a dielectric film or an intrinsic silicon film layer is provided between the first region and the second region, and the first region and the second region are isolated from each other by the dielectric film or the intrinsic silicon film layer. The front side of the silicon wafer does not have a front surface field formed by doping, or the front side of the silicon wafer has a surface doping concentration of less than 5*10. 18 atoms / cm 3 The front surface field.

2. The back contact battery according to claim 1, characterized in that, The sum of the doping concentrations of all doped elements in the silicon wafer is less than 2*10. 14 atoms / cm 3 .

3. The back contact battery according to claim 2, characterized in that, The sum of the doping concentrations of all doped elements in the silicon wafer is less than 1*10. 14 atoms / cm 3 .

4. The back contact battery according to claim 3, characterized in that, The sum of the doping concentrations of all doped elements in the silicon wafer is less than 1*10. 13 atoms / cm 3 .

5. The back contact battery according to claim 1, characterized in that, The resistivity of the silicon wafer after heat donor elimination treatment is greater than 50 ohm·cm.

6. The back contact battery according to claim 5, characterized in that, The resistivity of the silicon wafer after thermal donor elimination treatment is greater than 100 ohm·cm.

7. The back contact battery according to claim 6, characterized in that, The resistivity of the silicon wafer after thermal donor elimination treatment is greater than 200 ohm·cm.

8. The back contact battery according to claim 7, characterized in that, The resistivity of the silicon wafer after thermal donor elimination treatment is greater than 500 ohm·cm.

9. The back contact battery according to claim 8, characterized in that, The resistivity of the silicon wafer after thermal donor elimination treatment is greater than 1000 ohm·cm.

10. The back contact battery according to claim 9, characterized in that, The resistivity of the silicon wafer after thermal donor elimination treatment is greater than 5000 ohm·cm.

11. The back contact battery according to claim 1, characterized in that, The silicon wafer is also doped with at least one of group III and / or group V elements other than phosphorus, boron, and gallium, and the sum of the doping concentrations of all doped elements is less than 5*10. 14 atoms / cm 3 .

12. The back contact battery according to claim 1, characterized in that, The doping elements include phosphorus and boron or gallium; When the silicon wafer is a P-type silicon wafer, the ratio between the doping concentration of phosphorus and the doping concentration of boron or gallium is less than 0.

2. When the silicon wafer is an N-type silicon wafer, the ratio between the doping concentration of phosphorus and the doping concentration of boron or gallium is greater than 5.

13. The back contact battery according to claim 1, characterized in that, The first passivated contact structure includes a first tunneling layer and a first polar doped layer stacked on the first tunneling layer. The first polar doped layer includes at least one of doped polycrystalline silicon, doped amorphous silicon, and doped microcrystalline silicon. The second passivated contact structure includes a second tunneling layer and a second polar doped layer stacked on the second tunneling layer. The second polar doped layer includes at least one of doped polycrystalline silicon, doped amorphous silicon, and doped microcrystalline silicon. The polarity of the second polar doped layer is opposite to that of the first polar doped layer.

14. The back contact battery according to claim 1, characterized in that, The trench does not have a doped layer formed by doping with group III or group V elements.

15. A battery assembly, characterized in that, Includes the back contact battery as described in any one of claims 1-14.

16. A photovoltaic system, characterized in that, Includes the battery assembly as described in claim 15.

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