A foldback current limiting protection circuit

Abstract

The application provides a foldback current limiting protection circuit, which comprises a working circuit provided with a power tube, a current comparison unit, a foldback current limiting unit, a current limiting control unit and a control unit. The working circuit is used for generating an output voltage lower than an input voltage. The current comparison unit is used for comparing a current sampling signal sampled from a load current of the power tube with a first bias current to generate a current comparison signal. The foldback current limiting unit is used for comparing a divided voltage signal of the output voltage with a preset voltage threshold to generate a foldback current limiting signal. The current limiting control unit is connected with the current comparison unit and the foldback current limiting unit respectively and is used for generating a current limiting control signal under the action of the current comparison signal and the foldback current limiting signal. The control unit is controllably connected between the current limiting control unit and a gate of the power tube under the action of the current limiting control signal to control a gate voltage of the power tube. The application has the advantages of simple structure, small chip area and low power consumption when the circuit is short-circuited or overloaded.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a foldback current limiting protection circuit. Background Technology

[0002] With the rapid development of electronic product technology, power management chips such as LDO (Low Dropout Regulator) linear power supplies and DC-DC converters are increasingly widely used in electronic products. These chips play a crucial role in portable wearable devices such as mobile phones, wireless mice, and laptops. As the performance requirements of electronic products continue to increase, the design of power management chips faces increasingly complex application scenarios. Without increasing chip costs, simplifying circuit design, improving chip load capacity, reducing static power consumption, and enhancing system stability and reliability have become key research and development priorities.

[0003] The foldback current limiting protection circuit is a common protection circuit used in low dropout voltage regulators (LDOs). In an LDO, the function of the foldback current limiting protection circuit is to prevent excessive load current from flowing through the LDO, thereby protecting the LDO and other circuitry from damage. When the load current exceeds the LDO's rated current limit, the foldback current limiting protection circuit automatically activates, restricting current flow.

[0004] However, in existing foldback current limiting protection circuits, when the circuit is short-circuited or overloaded, a larger current needs to be provided to meet the load demand, which leads to an increase in the power consumption inside the LDO. Moreover, when the load current exceeds the limit value, the circuit needs a certain amount of time to detect and respond, which introduces a certain delay time. This will cause the output voltage to drop instantaneously, which may have a negative impact on the stability and performance of the system. Summary of the Invention

[0005] To address the above technical problems, this invention provides a foldback current limiting protection circuit.

[0006] The technical problem solved by this invention can be achieved by the following technical solutions:

[0007] A foldback current limiting protection circuit includes:

[0008] A circuit equipped with a power transistor is used to generate an output voltage that is lower than the input voltage.

[0009] A current comparison unit is used to compare a current sampling signal of a load current sampled from the power transistor with a first bias current to generate a current comparison signal.

[0010] A foldback current limiting unit is used to compare the voltage divider signal of the output voltage with a preset voltage threshold to generate a foldback current limiting signal;

[0011] A current limiting control unit is connected to the current comparison unit and the foldback current limiting unit respectively, and is used to generate a current limiting control signal under the action of the current comparison signal and the foldback current limiting signal;

[0012] A control unit is controllably connected between the current limiting control unit and the gate of the power transistor under the action of the current limiting control signal, so as to control the gate voltage of the power transistor.

[0013] Preferably, the current limiting control unit includes:

[0014] A first processing module is controllably connected between the current sampling signal and a first node under the action of the current comparison signal;

[0015] A second processing module is controllably connected between the first node and the grounding terminal under the action of the current limiting signal; wherein the current limiting control signal is output from the first node.

[0016] Preferably, the first processing module includes:

[0017] A first PMOS transistor, the gate of the first PMOS transistor is connected to the current comparison signal, the source of the first PMOS transistor is connected to the current sampling signal, and the drain of the first PMOS transistor is connected to the first node.

[0018] The second processing module includes:

[0019] A first NMOS transistor, the gate of which is connected to the foldback current limiting signal, the drain of which is connected to the first node, and the source of which is connected to the ground terminal.

[0020] Preferably, the operating circuit includes: a third processing module, which is controllably connected between the gate of the power transistor and a second node under the action of a first bias voltage, wherein a first resistor is connected between the second node and the ground terminal;

[0021] The control unit includes:

[0022] A second NMOS transistor, the gate of which is connected to the current limiting control signal, the source of which is connected to the second node through a second resistor, and the drain of which is connected to a first reference current;

[0023] A first capacitor is connected between the gate of the second NMOS transistor and the ground terminal.

[0024] Preferably, the first reference current is generated by a current generation circuit, the current generation circuit comprising:

[0025] A second PMOS transistor, the gate of which is connected to a first enable signal, the source of which is connected to the input voltage, and the drain of which generates the first reference current.

[0026] Preferably, the foldback current limiting unit includes:

[0027] A fourth processing module is controllably connected between a second bias current and a third node under the action of the voltage divider signal of the output voltage, and generates a third node voltage from the third node;

[0028] A first bias module, controllably connected between the input voltage and the third node under the action of a first bias control signal, is used to provide a fourth bias current to the third processing module;

[0029] A fifth processing module is controllably connected between a fourth node and a fifth node under the action of a preset gate voltage control signal. A third bias current is connected between the fifth node and the ground terminal. A fourth node voltage is generated from the fourth node, and the foldback current limiting signal is generated from the fifth node. The preset voltage threshold is the fourth node voltage.

[0030] A voltage comparison module is connected between the third node and the fourth node to compare the voltage of the third node and the voltage of the fourth node and generate a voltage comparison signal;

[0031] A feedback module is connected between the fourth node and the grounding terminal. The feedback terminal of the feedback module is connected to the fifth node and the current limiting control unit. It is used to generate a feedback signal based on the voltage comparison signal and output it to the fifth node to control the voltage of the foldback current limiting signal.

[0032] Preferably, the fourth processing module includes: a third NMOS transistor, the gate of which is connected to the voltage divider signal of the output voltage, the drain of which is connected to the second bias current, and the source of which is connected to the third node;

[0033] The fifth processing module includes: a third PMOS transistor, the gate of which is connected to the preset gate voltage control signal, the source of which is connected to the fourth node, and the drain of which is connected to the fifth node;

[0034] The voltage comparison module includes: a third resistor connected between the third node and the fourth node;

[0035] The feedback module includes: a fourth NMOS transistor, the gate of which is connected to the fifth node, the drain of which is connected to the fourth node, and the source of which is connected to the ground terminal.

[0036] Preferably, the first bias control signal is provided through a bias control module, the bias control module comprising:

[0037] A fifth NMOS transistor, wherein the gate of the fifth NMOS transistor is connected to a second bias voltage, the source of the fifth NMOS transistor is connected to a second bias current, and the drain of the fifth NMOS transistor outputs the first bias control signal;

[0038] A fourth PMOS transistor, the gate of which is connected to a fifth bias current, the source of which is connected to the input voltage, and the drain of which is connected to the drain of the fifth NMOS transistor.

[0039] Preferably, the preset gate voltage control signal is provided through a gate voltage control module, the gate voltage control module comprising:

[0040] A fifth PMOS transistor, wherein the gate of the fifth PMOS transistor is connected to the preset gate voltage control signal, and the source of the fifth PMOS transistor is connected to the input voltage;

[0041] A sixth NMOS transistor, the gate of which is connected to the drain of the fifth PMOS transistor, the drain of which is connected to the preset gate voltage control signal, and the source of which is grounded;

[0042] A sixth PMOS transistor, wherein the gate and drain of the sixth PMOS transistor are respectively connected to the gate of the sixth NMOS transistor, and the source of the sixth PMOS transistor is connected to the input voltage;

[0043] A seventh PMOS transistor, the gate of which is connected to the gate of the sixth NMOS transistor, and the source and drain of which are respectively connected to the input voltage.

[0044] Preferably, it further includes a protection control module, the protection control module comprising:

[0045] A first enable control branch is controllably connected between the current limiting control signal and the ground terminal under the action of a second enable signal;

[0046] A second enable control branch is controllably connected between the input voltage and the first bias control signal under the action of a third enable signal.

[0047] The advantages or beneficial effects of the technical solution of this invention are as follows:

[0048] This invention provides a novel foldback-type current limiting protection circuit, which greatly reduces the power consumption of the chip under heavy load while achieving current limiting protection. It has the advantages of simple structure, small chip area, and low power consumption when the circuit is short-circuited or overloaded. Attached Figure Description

[0049] Figure 1 This is a block diagram of the foldback current limiting protection circuit in a preferred embodiment of the present invention;

[0050] Figure 2 This is a structural block diagram of the current limiting control unit in a preferred embodiment of the present invention;

[0051] Figure 3 This is a block diagram of the working circuit in a preferred embodiment of the present invention;

[0052] Figure 4 This is a structural block diagram of the foldback current limiting unit in a preferred embodiment of the present invention;

[0053] Figure 5 A circuit diagram of the current comparison unit, the current limiting control unit, and the control unit is shown in a preferred embodiment of the present invention.

[0054] Figure 6 This is a circuit diagram of the foldback current limiting unit in a preferred embodiment of the present invention;

[0055] Figure 7 A circuit diagram of the gate voltage control module is shown in a preferred embodiment of the present invention.

[0056] Figure 8 This is a schematic diagram illustrating the application of the control unit in a preferred embodiment of the present invention;

[0057] Figure 9 This is a schematic diagram of the application of an LDO in a preferred embodiment of the present invention;

[0058] Figure 10 This is a schematic diagram of the application inside the LDO in a preferred embodiment of the present invention. Detailed Implementation

[0059] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0060] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0061] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.

[0062] See Figure 1 In a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, a foldback current limiting protection circuit is provided, comprising:

[0063] A working circuit 1 equipped with a power transistor MP is used to generate an output voltage VOUT that is lower than the input voltage VIN;

[0064] A current comparison unit 2 is used to compare a current sampling signal of the load current of a sampled self-power transistor MP with a first bias current to generate a current comparison signal.

[0065] A foldback current limiting unit 3 is used to compare the output voltage divider signal VFB1 with a preset voltage threshold to generate a foldback current limiting signal.

[0066] A current limiting control unit 4 is connected to a current comparison unit 2 and a foldback current limiting unit 3 respectively, and is used to generate a current limiting control signal under the action of the current comparison signal and the foldback current limiting signal;

[0067] A control unit 5 is controllably connected between the current limiting control unit 4 and the gate of the power transistor MP under the action of a current limiting control signal, so as to control the gate voltage of the power transistor MP.

[0068] Specifically, in this embodiment, firstly, the load current of the power transistor MP is sampled to obtain a current sampling signal; then, the current sampling signal is compared with the first bias current to obtain a current comparison signal; simultaneously, the output voltage is divided and compared with a preset voltage threshold, and a foldback current limiting signal is generated based on the comparison result; next, a current limiting control signal is generated under the action of the current comparison signal and / or the foldback current limiting signal, thereby controlling the gate voltage of the power transistor MP. While achieving current limiting protection, the power consumption of the chip under heavy load is greatly reduced, and it has the advantages of simple structure, small chip area, and low power consumption when the circuit is short-circuited or overloaded.

[0069] As an example, in current comparison unit 2, if the current sampling signal exceeds the first bias current, the current comparison signal output by current comparison unit 2 is low; if the current sampling signal is lower than the first bias current, the current comparison signal output by current comparison unit 2 is high.

[0070] As an example, in the foldback current limiting unit 3, if the voltage divider signal of the output voltage is greater than the preset voltage threshold, the voltage of the foldback current limiting signal increases; if the voltage divider signal of the output voltage is less than the preset voltage threshold, the voltage of the foldback current limiting signal decreases.

[0071] As an example, in the current limiting control unit 4, if the current comparison signal is low, the pull-up capability of the current limiting control unit 4 is increased, making the current limiting control signal high, and the control unit 5 is turned on, thereby controlling the gate voltage of the power transistor MP. Specifically, the gate voltage of the power transistor MP is pulled high to achieve the purpose of current limiting. If the foldback current limiting signal rises, the pull-down capability of the current limiting control unit 4 is increased, making the current limiting control signal low, and the control unit 5 is turned off.

[0072] When the working circuit 1 is lightly loaded, the gate voltage of the power transistor MP is high and the current sampling signal is small, and the working circuit 1 operates normally. When the working circuit 1 is short-circuited or overloaded, the gate voltage of the power transistor MP is low and the current sampling signal is large. Then the output of the current comparison unit 2 starts to flip. The high-level current limiting control signal generated under the action of the current comparison signal forces the output voltage to decrease. Through the feedback loop of the output voltage divider, the output current flowing through the power transistor MP gradually decreases and is clamped to a small value when the output voltage decreases, thus achieving short-circuit current limiting and protecting the chip.

[0073] In a preferred embodiment, such as Figure 2 As shown, the current limiting control unit 4 includes:

[0074] A first processing module 41 is controllably connected between the current sampling signal and a first node C under the action of the current comparison signal.

[0075] Specifically, in this embodiment, when the current comparison signal is high, the first processing module 41 is turned off; when the current comparison signal is low, the first processing module 41 is turned on, increasing the pull-up capability of the first processing module 41, thereby increasing the voltage of the current limiting control signal output by the first node C.

[0076] As an example, such as Figure 5 As shown, the first processing module 41 includes:

[0077] A first PMOS transistor PM1, the gate of the first PMOS transistor PM1 is connected to the current comparison signal, the source of the first PMOS transistor PM1 is connected to the current sampling signal, and the drain of the first PMOS transistor PM1 is connected to the first node C.

[0078] Specifically, in this embodiment, when the current comparison signal is high, the first PMOS transistor PM1 is turned off; when the current comparison signal is low, the first PMOS transistor PM1 is turned on, increasing the pull-up capability of the first PMOS transistor PM1, thereby pulling up the voltage of the first node.

[0079] In a preferred embodiment, such as Figure 2 As shown, a second processing module 42 is controllably connected between the first node C and the grounding terminal under the action of the foldback current limiting signal; wherein, the current limiting control signal is output from the first node C.

[0080] Specifically, in this embodiment, when the return current limiting signal is low, the second processing module 42 is turned off; when the return current limiting signal is high, the second processing module 42 is turned on, increasing the pull-down capability of the second processing module 42, thereby pulling down the voltage of the current limiting control signal output by the first node C.

[0081] As an example, such as Figure 5 As shown, the second processing module 42 includes:

[0082] A first NMOS transistor NM1 is connected to the gate of the first NMOS transistor NM1 via a foldback current limiting signal, the drain of the first NMOS transistor NM1 is connected to the first node C, and the source of the first NMOS transistor NM1 is connected to the ground terminal.

[0083] Specifically, in this embodiment, when the foldback current limiting signal is low, the first NMOS transistor NM1 is turned off; when the foldback current limiting signal is high, the first NMOS transistor NM1 is turned on, increasing the pull-down capability of the first NMOS transistor NM1, thereby pulling down the voltage of the first node C.

[0084] In a preferred embodiment, such as Figure 3 and Figure 8 As shown, the working circuit 1 includes: a third processing module 11, which is controllably connected between the gate of the power transistor MP and a second node G under the action of a first bias voltage VBIAS3, and a first resistor R1 is connected between the second node G and the ground terminal.

[0085] Control unit 5 includes:

[0086] A second NMOS transistor NM2 is connected to a current limiting control signal at its gate, and its source is connected to a second node through a second resistor R2. The drain of the second NMOS transistor NM2 is connected to a first reference current I10.

[0087] A first capacitor C1 is connected between the gate of the second NMOS transistor NM2 and the ground terminal.

[0088] Specifically, in this embodiment, when the current limiting control signal is low, the second NMOS transistor NM2 is turned off; when the current limiting control signal is high, the second NMOS transistor NM2 is turned on, the first reference current I10 flows through the second resistor R2 and the first resistor R1, and the voltage of the second node G increases, thereby controlling the gate voltage of the power transistor MP to rise, thus achieving the purpose of current limiting.

[0089] Furthermore, the voltage increase at the second node G is:

[0090] ΔVG=I10*R1,

[0091] Where I10 represents the first reference current I10; R1 represents the resistance value of the first resistor; ΔVG represents the increase in the second node voltage VG;

[0092] The gate voltage VGP of the power transistor MP is VG + VDS; where VDS represents the drain-source voltage of the third processing module 11.

[0093] Furthermore, the third processing module 11 includes: a twelfth NMOS transistor NM12, the gate of the twelfth NMOS transistor NM12 is connected to the first bias voltage VBIAS3, the drain of the twelfth NMOS transistor NM12 is connected to the gate of the power transistor MP, and the source of the twelfth NMOS transistor NM12 is connected to the second node G.

[0094] The drain-source voltage of the twelfth NMOS transistor is the same as the drain-source voltage of the third processing module 11 mentioned above.

[0095] In a preferred embodiment, the first reference current I10 is generated by a current generation circuit, which includes:

[0096] A second PMOS transistor PM2 is used. The gate of the second PMOS transistor PM2 is connected to a first enable signal, the source of the second PMOS transistor PM2 is connected to the input voltage VIN, and the drain of the second PMOS transistor PM2 generates a first reference current I10.

[0097] Specifically, in this embodiment, when the first enable signal is high, the second PMOS transistor PM2 is turned off; when the first enable signal is low, the second PMOS transistor PM2 is turned on, providing the second NMOS transistor NM2 with a first reference current I10, thereby controlling the gate voltage of the power transistor MP to rise, achieving the purpose of current limiting.

[0098] Furthermore, when the working circuit 1 is working normally, the first enable signal is at a low level; when the working circuit 1 is short-circuited, the first enable signal is at a high level.

[0099] In a preferred embodiment, such as Figure 4 As shown, the turnaround current limiting unit 3 includes:

[0100] A fourth processing module 31 is controllably connected between a second bias current and a third node under the action of the voltage divider signal of the output voltage, and generates a third node voltage from the third node.

[0101] A voltage comparison module 34 is used to compare the voltage of the third node with a preset voltage threshold and generate a voltage comparison signal;

[0102] A feedback module 35 is connected between the fourth node and the ground terminal. The feedback terminal of the feedback module 35 is connected to the fifth node and the current limiting control unit 4. It is used to generate an output to the fifth node based on the voltage comparison signal to control the voltage of the foldback current limiting signal.

[0103] Specifically, in this embodiment, firstly, a third node voltage is generated based on the voltage division of the output voltage. The third node voltage is a voltage that is one gate-source voltage higher than the voltage division signal of the output voltage. Then, the third node voltage is compared with a preset voltage threshold, and the voltage of the foldback current limiting signal is adjusted based on the negative feedback of the voltage comparison signal.

[0104] Furthermore, when the voltage of the third node is greater than the preset voltage threshold, the voltage of the foldback current limiting signal is increased through negative feedback adjustment; when the voltage of the third node is not greater than the preset voltage threshold, the voltage of the foldback current limiting signal is decreased through negative feedback adjustment.

[0105] In a preferred embodiment, the preset voltage threshold is generated by a fifth processing module 33, which is controllably connected between a fourth node and a fifth node under the action of a preset gate voltage control signal. A third bias current is connected between the fifth node and the ground terminal. A fourth node voltage is generated from the fourth node, and a foldback current limiting signal is generated from the fifth node. The preset voltage threshold is the fourth node voltage.

[0106] Furthermore, the preset voltage threshold is a gate-source voltage.

[0107] In a preferred embodiment, the foldback current limiting unit 3 further includes a first bias module 32, which is controllably connected between the input voltage VIN and the third node under the action of a first bias control signal, for providing a fourth bias current to the third processing module 11.

[0108] Specifically, in this embodiment, when the first bias control signal is at a high level, the first bias module 32 does not work; when the first bias control signal is at a low level, the first bias module 32 works to provide bias current to the third processing module 11.

[0109] In some implementations, the first bias module 32 includes: an eighth PMOS transistor PM8, the gate of the eighth PMOS transistor PM8 is connected to a first bias control signal, the source of the eighth PMOS transistor PM8 is connected to the input voltage VIN, and the drain of the eighth PMOS transistor PM8 is connected to a third node.

[0110] Specifically, in this embodiment, when the first bias control signal is high, the eighth PMOS transistor PM8 is turned off; when the first bias control signal is low, the eighth PMOS transistor PM8 is turned on, providing bias current for the third processing module 11.

[0111] In a preferred embodiment, the first bias control signal is provided through a bias control module, which includes:

[0112] A fifth NMOS transistor NM5 is connected to a second bias voltage VBIAS at its gate, and to a second bias current at its source. The drain of the fifth NMOS transistor NM5 outputs a first bias control signal.

[0113] Specifically, in this embodiment, when the second bias voltage VBIAS is low, the fifth NMOS transistor NM5 is turned off; when the second bias voltage VBIAS is high, the fifth NMOS transistor NM5 is turned on, providing the gate voltage for the eighth PMOS transistor.

[0114] In a preferred embodiment, the bias control module further includes: a fourth PMOS transistor PM4, the gate of the fourth PMOS transistor PM4 is connected to a fifth bias current IBIAS2, the source of the fourth PMOS transistor PM4 is connected to the input voltage VIN, and the drain of the fourth PMOS transistor PM4 is connected to the drain of the fifth NMOS transistor NM5.

[0115] Specifically, in this embodiment, when the fifth bias current IBIAS2 is high, the fourth PMOS transistor PM4 is turned off; when the fifth bias current IBIAS2 is low, the fourth PMOS transistor PM4 is turned on, providing bias current for the fifth NMOS transistor NM5.

[0116] Furthermore, the aforementioned second bias current is provided through a seventh NMOS transistor NM7. The gate of the seventh NMOS transistor NM7 is connected to IBIAS1, the source of the seventh NMOS transistor NM7 is grounded, and the drain of the seventh NMOS transistor NM7 is connected to the source of the fifth NMOS transistor NM5 and the source of the third NMOS transistor NM3, respectively, to provide the second bias current for the fifth NMOS transistor NM5 and the third NMOS transistor NM3.

[0117] In a preferred embodiment, the fourth processing module 31 includes: a third NMOS transistor NM3, the gate of the third NMOS transistor NM3 is connected to the voltage divider signal of the output voltage, the drain of the third NMOS transistor NM3 is connected to the second bias current, and the source of the third NMOS transistor NM3 is connected to the third node.

[0118] Furthermore, the third node voltage is a voltage that is higher than the output voltage divider signal by the gate-source voltage of the third NMOS transistor NM3, i.e., VD = VFB1 + VGS,NM3; where VD represents the third node voltage; VFB1 represents the output voltage divider signal; and VGS,NM3 represents the gate-source voltage of the third NMOS transistor.

[0119] In a preferred embodiment, the fifth processing module 33 includes: a third PMOS transistor PM3, the gate of the third PMOS transistor PM3 is connected to a preset gate voltage control signal, the source of the third PMOS transistor PM3 is connected to a fourth node, and the drain of the third PMOS transistor PM3 is connected to a fifth node.

[0120] Furthermore, the aforementioned preset voltage threshold is the gate-source voltage of the third PMOS transistor PM3, i.e., VE = 0 + VGS,PM3; where VE represents the preset voltage threshold and VGS,PM3 represents the gate-source voltage of the third PMOS transistor PM3.

[0121] In a preferred embodiment, the aforementioned preset gate voltage control signal is provided through a gate voltage control module, such as... Figure 7 As shown, the gate voltage control module includes:

[0122] The fifth PMOS transistor PM5 has its gate connected to a preset gate voltage control signal, and its source connected to the input voltage VIN.

[0123] The sixth NMOS transistor NM6 has its gate connected to the drain of the fifth PMOS transistor PM5, its drain connected to a preset gate voltage control signal, and its source grounded.

[0124] The sixth PMOS transistor PM6 has its gate and drain connected to the gate of the sixth NMOS transistor NM6, and its source connected to the input voltage VIN.

[0125] The seventh PMOS transistor PM7 has its gate connected to the gate of the sixth NMOS transistor NM6, and its source and drain are connected to the input voltage VIN.

[0126] Specifically, in this embodiment, a preset gate voltage control signal is provided by the fifth PMOS transistor PM5, the sixth PMOS transistor PM6, the seventh PMOS transistor PM7, and the sixth NMOS transistor NM6, so that the fifth processing module 33 continuously provides a preset voltage threshold that can be compared with the third node voltage.

[0127] In a preferred embodiment, the voltage comparison module 34 is connected between the third node D and the fourth node E; the voltage comparison module 34 includes a third resistor R3, which is connected between the third node D and the fourth node E.

[0128] Furthermore, when the voltage of the third node is greater than the voltage of the fourth node, the current I7 flows from the third node D to the fourth node E, and the voltage of the fifth node (i.e., the foldback current limiting signal) increases through negative feedback regulation; when the voltage of the third node is less than the voltage of the fourth node, the current I7 flows from the fourth node E to the third node D, and the voltage of the fifth node (i.e., the foldback current limiting signal) decreases through negative feedback regulation.

[0129] In a preferred embodiment, the feedback module 35 is connected between the fourth node and the ground terminal. The feedback module 35 includes: a fourth NMOS transistor NM4, the gate of the fourth NMOS transistor NM4 is connected to the fifth node, the drain of the fourth NMOS transistor NM4 is connected to the fourth node, and the source of the fourth NMOS transistor NM4 is connected to the ground terminal.

[0130] Furthermore, when a portion of the current I7 flows from the fourth node E to the third node D, the current I9 flowing through the fourth NMOS transistor NM4 decreases, causing the gate voltage of the fourth NMOS transistor NM4 to decrease, i.e., the voltage of the foldback current limiting signal decreases. When the current I7 flows from the third node D to the fourth node E, the current I9 flowing through the fourth NMOS transistor NM4 increases, causing the gate voltage of the fourth NMOS transistor NM4 to increase, i.e., the voltage of the foldback current limiting signal increases.

[0131] Furthermore, it also includes: a ninth PMOS transistor PM9, the gate of the ninth PMOS transistor PM9 is connected to IBIAS2, the source of the ninth PMOS transistor PM9 is connected to the input voltage VIN, and the drain of the ninth PMOS transistor PM9 is connected to the drain of the fourth NMOS transistor NM4, which is used to provide bias current for the fourth NMOS transistor NM4.

[0132] In a preferred embodiment, the system further includes a protection control module, which comprises:

[0133] A first enable control branch is controllably connected between the current limiting control signal and the ground terminal under the action of a second enable signal.

[0134] As an example, such as Figure 5 As shown, the first enable control branch is implemented using the ninth NMOS transistor NM9. The gate of the ninth NMOS transistor NM9 is connected to the second enable signal, the drain is connected to the current limiting control signal, and the source is connected to the ground terminal.

[0135] When the second enable signal is high, the ninth NMOS transistor NM9 is turned on, which pulls down the gate voltage (i.e., the current limiting control signal) of the second NMOS transistor NM2.

[0136] When the second enable signal is low, the ninth NMOS transistor NM9 is turned off, and the control unit 5 operates normally.

[0137] Furthermore, the second enable signal is an enable low control voltage.

[0138] In a preferred embodiment, a second enable control branch is controllably connected between the input voltage VIN and the first bias control signal under the action of a third enable signal.

[0139] As an example, such as Figure 6 As shown, the second enable control branch is implemented using the tenth PMOS transistor PM10. The gate of the tenth PMOS transistor PM10 is connected to the third enable signal, the drain is connected to the first bias control signal, and the source is connected to the input voltage VIN.

[0140] When the third enable signal is low, the tenth PMOS transistor PM10 is turned on, which pulls up the gate voltage (i.e. the first bias control signal) of the eighth PMOS transistor PM8, and the eighth PMOS transistor PM8 is turned off.

[0141] When the third enable signal is high, the tenth PMOS transistor PM10 is turned off, and the eighth PMOS transistor PM8 normally provides bias for the third NMOS transistor NM3.

[0142] In some implementations, such as Figure 5As shown, the aforementioned current sampling signal is generated through a current sampling circuit, which includes:

[0143] The eleventh PMOS transistor PM11 has its gate connected to the gate of the power transistor MP, its source connected to the input voltage VIN, and its drain output current sampling signal.

[0144] In some implementations, such as Figure 5 As shown, the current comparison unit 2 includes:

[0145] The twelfth PMOS transistor PM12 has its source connected to the current sampling signal, and its gate and drain are connected to the drain of the ninth NMOS transistor NM9.

[0146] The gate of the ninth NMOS transistor NM9 is connected to the first bias current, and the source of the ninth NMOS transistor NM9 is connected to the ground terminal.

[0147] The thirteenth PMOS transistor PM13 has its gate connected to the gate of the twelfth PMOS transistor PM12, its source connected to the output voltage, and its drain output to compare the current signal.

[0148] The tenth NMOS transistor NM10 has its gate connected to the first bias current, its drain connected to the drain of the thirteenth PMOS transistor PM13, and its source connected to ground.

[0149] In the preferred embodiments described above, such as Figures 1-8 As shown, IBIAS1 is the internal bias voltage, providing bias current to the circuit; IBIAS2 is the internal bias voltage, providing bias current to the circuit; VBIAS and VBIAS3 are bias voltages to provide a voltage reference point; VIN is the LDO input PAD; VGP is the gate voltage of the LDO internal power transistor MP; VCP is the signal output by control unit 5; VFB1 is the output voltage divided by the feedback resistor network (VOUT voltage division); VFB is the feedback voltage; and VREF is the reference voltage.

[0150] I1 is the current sampling signal obtained from sampling; I2 is the current flowing through the ninth NMOS transistor NM9; I3 is the current flowing through the tenth NMOS transistor NM10; I4 is the current flowing through the first PMOS transistor PM1; I5 is the current flowing through the first NMOS transistor NM1; I6 is the current flowing through the eighth PMOS transistor PM8; I7 is the current flowing through the third resistor R3; I8 is the current flowing through the ninth PMOS transistor PM9; I9 is ​​the current flowing through the fourth NMOS transistor NM4; I10 is the current flowing through the second PMOS transistor PM2; and I11 is the current flowing through the fourth resistor R4.

[0151] like Figure 5 and Figure 6 As shown, the eleventh PMOS transistor PM11 is the sampling transistor, which samples the load current of the power transistor MP. When the working circuit 1 is working normally, the gate voltage of the power transistor MP is relatively large, the current sampling signal I1 obtained is relatively small, and the current basically flows away through I2.

[0152] As the load on the working circuit 1 increases, the gate voltage of the power transistor MP decreases, the current sampling signal I1 increases, the voltage at point A increases, and I3 also increases accordingly. The gate voltage of the twelfth PMOS transistor PM12 increases, the voltage at point B begins to decrease, and the first PMOS transistor PM1 gradually turns on. At this time, because the voltage of the output voltage divider signal VFB1 is relatively high and its pull-down capability is weak, the potential at point D is relatively high, causing some current in I9 to flow into I8, making the voltage at point F relatively high, increasing the pull-down capability of the first NMOS transistor NM1, making the voltage at point C relatively low, and basically flowing through I5.

[0153] When the circuit begins to overload, the voltage at point C rises, the second NMOS transistor NM2 turns on, and current flows through the second resistor R2. Figure 8 The current through the first resistor R4 is reduced, causing the current through the fourth resistor R4 to decrease. At this time, the gate voltage VGP of the power transistor MP is VIN - R4 * I11, where VIN is the input voltage and I11 is the current flowing through the fourth resistor R4. As a result, the VGP voltage increases, that is, the gate voltage of the power transistor MP increases, thereby achieving the purpose of current limiting.

[0154] When the circuit is overloaded, it remains in a current-limiting state. The voltage of the voltage divider signal VFB1 continues to decrease, and its pull-down capability becomes stronger, causing the potential at point D to decrease. When the potential at point D is lower than that at point E, a portion of the current I7 flows from point E through the third resistor R3 to point D. As a result, the current I9 decreases, the voltage at point F decreases, the pull-down capability of the first NMOS transistor NM1 weakens, the potential at point C continues to increase, the current flowing through the second resistor R2 continues to increase, the voltage VGP continues to increase, and the gate voltage of the control power transistor MP increases, thereby continuously reducing the current-limiting value and achieving the purpose of foldback current limiting.

[0155] The foldback current limiting protection circuit of this invention can be applied to, for example... Figure 9 In the LDO shown, VIN is the LDO input PAD, VOUT is the LDO output voltage, EN is the enable signal, where EN_L is the enable low control voltage, EN_H is the enable high control voltage, and GND is the power ground.

[0156] like Figure 10 The diagram shown is a schematic of the internal structure of an LDO. The LDO includes: a main operational amplifier 6, a foldback current limiting protection circuit 7, a reference circuit 8, a logic control circuit 9, an undervoltage lockout (UVLO) circuit 10, and an overvoltage protection (OCP) circuit 11. The circuit shown in this embodiment includes part of the main operational amplifier 6, the foldback current limiting protection circuit 7, and the power transistor MP within the LDO.

[0157] The advantages or beneficial effects of adopting the above technical solution are as follows: The present invention provides a novel foldback current limiting protection circuit, which greatly reduces the power consumption of the chip under heavy load while realizing current limiting protection. It has the advantages of simple structure, small chip area, and low power consumption when the circuit is short-circuited or overloaded.

[0158] The above are merely preferred embodiments of the present invention and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should recognize that any equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included within the protection scope of the present invention.

Claims

1. A foldback current limit protection circuit, characterized by, include: A circuit equipped with a power transistor is used to generate an output voltage that is lower than the input voltage. A current comparison unit is used to compare a current sampling signal of a load current sampled from the power transistor with a first bias current to generate a current comparison signal. A foldback current limiting unit is used to compare the voltage divider signal of the output voltage with a preset voltage threshold to generate a foldback current limiting signal; A current limiting control unit is connected to the current comparison unit and the foldback current limiting unit respectively, and is used to generate a current limiting control signal under the action of the current comparison signal and the foldback current limiting signal; A control unit is controllably connected between the current limiting control unit and the gate of the power transistor under the action of the current limiting control signal, so as to control the gate voltage of the power transistor; The foldback current limiting unit includes: A fourth processing module is controllably connected between a second bias current and a third node under the action of the voltage divider signal of the output voltage, and generates a third node voltage from the third node; A first bias module, controllably connected between the input voltage and the third node under the action of a first bias control signal, is used to provide a fourth bias current for the fourth processing module; A fifth processing module is controllably connected between a fourth node and a fifth node under the action of a preset gate voltage control signal. A third bias current is connected between the fifth node and the ground terminal. A fourth node voltage is generated from the fourth node, and the foldback current limiting signal is generated from the fifth node. The preset voltage threshold is the fourth node voltage. A voltage comparison module is connected between the third node and the fourth node to compare the voltage of the third node and the voltage of the fourth node and generate a voltage comparison signal; A feedback module is connected between the fourth node and the grounding terminal. The feedback terminal of the feedback module is connected to the fifth node and the current limiting control unit. It is used to generate a feedback signal based on the voltage comparison signal and output it to the fifth node to control the voltage of the foldback current limiting signal.

2. The foldback current limit protection circuit of claim 1, wherein, The current limiting control unit includes: A first processing module is controllably connected between the current sampling signal and a first node under the action of the current comparison signal; A second processing module is controllably connected between the first node and the grounding terminal under the action of the current limiting signal; wherein the current limiting control signal is output from the first node.

3. The foldback current limit protection circuit of claim 2, wherein, The first processing module includes: A first PMOS transistor, the gate of the first PMOS transistor is connected to the current comparison signal, the source of the first PMOS transistor is connected to the current sampling signal, and the drain of the first PMOS transistor is connected to the first node. The second processing module includes: A first NMOS transistor, the gate of which is connected to the foldback current limiting signal, the drain of which is connected to the first node, and the source of which is connected to the ground terminal.

4. The foldback current limit protection circuit of claim 1, wherein, The operating circuit includes: a third processing module, which is controllably connected between the gate of the power transistor and a second node under the action of a first bias voltage, and a first resistor is connected between the second node and the ground terminal; The control unit includes: A second NMOS transistor, the gate of which is connected to the current limiting control signal, the source of which is connected to the second node through a second resistor, and the drain of which is connected to a first reference current; A first capacitor is connected between the gate of the second NMOS transistor and the ground terminal.

5. The foldback current limit protection circuit of claim 4, wherein, The first reference current is generated by a current generation circuit, the current generation circuit comprising: A second PMOS transistor, the gate of which is connected to a first enable signal, the source of which is connected to the input voltage, and the drain of which generates the first reference current.

6. The foldback current limit protection circuit of claim 1, wherein, The fourth processing module includes: a third NMOS transistor, the gate of which is connected to the voltage divider signal of the output voltage, the drain of which is connected to the second bias current, and the source of which is connected to the third node; The fifth processing module includes: a third PMOS transistor, the gate of which is connected to the preset gate voltage control signal, the source of which is connected to the fourth node, and the drain of which is connected to the fifth node; The voltage comparison module includes: a third resistor connected between the third node and the fourth node; The feedback module includes: a fourth NMOS transistor, the gate of which is connected to the fifth node, the drain of which is connected to the fourth node, and the source of which is connected to the ground terminal.

7. The foldback current limiting protection circuit according to claim 1, characterized in that, The first bias control signal is provided through a bias control module, the bias control module comprising: A fifth NMOS transistor, wherein the gate of the fifth NMOS transistor is connected to a second bias voltage, the source of the fifth NMOS transistor is connected to a second bias current, and the drain of the fifth NMOS transistor outputs the first bias control signal; A fourth PMOS transistor, the gate of which is connected to a fifth bias current, the source of which is connected to the input voltage, and the drain of which is connected to the drain of the fifth NMOS transistor.

8. The foldback current limiting protection circuit according to claim 1, characterized in that, The preset gate voltage control signal is provided through a gate voltage control module, which includes: A fifth PMOS transistor, wherein the gate of the fifth PMOS transistor is connected to the preset gate voltage control signal, and the source of the fifth PMOS transistor is connected to the input voltage; A sixth NMOS transistor, the gate of which is connected to the drain of the fifth PMOS transistor, the drain of which is connected to the preset gate voltage control signal, and the source of which is grounded; A sixth PMOS transistor, wherein the gate and drain of the sixth PMOS transistor are respectively connected to the gate of the sixth NMOS transistor, and the source of the sixth PMOS transistor is connected to the input voltage; A seventh PMOS transistor, the gate of which is connected to the gate of the sixth NMOS transistor, and the source and drain of which are respectively connected to the input voltage.

9. The foldback current limiting protection circuit according to claim 1, characterized in that, It also includes a protection control module, which comprises: A first enable control branch is controllably connected between the current limiting control signal and the ground terminal under the action of a second enable signal; A second enable control branch is controllably connected between the input voltage and the first bias control signal under the action of a third enable signal.

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