Electronic device and monitoring method

Abstract

An electronic device includes an oscillator, a controller, and a test circuit. The oscillator generates a clock signal according to an enable signal and determines a period of the clock signal according to an adjustment signal. The controller generates the enable signal and generates a first test signal according to the clock signal. The controller also judges the period according to a first comparison signal and a second comparison signal. The test circuit generates the first comparison signal and the second comparison signal using the first test signal and the period.

Description

Technical Field

[0001] This invention relates to an electronic device and a monitoring method, and more particularly to an electronic device for self-testing the period of a clock signal and a method for monitoring the clock signal. Background Technology

[0002] In digital integrated circuits, the frequency of the internal clock signal is typically maintained using phase-locked loops (PLLs). However, PLLs not only consume circuit area and power but also require an additional clock signal to monitor the accuracy of the internal clock signal. When the circuit area of ​​a digital integrated circuit is small, whether a PLL with a circuit area similar to or even larger than that of the main digital integrated circuit is needed to maintain the accuracy of the internal clock signal frequency becomes a troubling problem.

[0003] However, some small digital integrated circuits require precise clock signal frequencies, necessitating optimization of the method for monitoring the clock signal frequency and the ability to correct frequency deviations when they are detected. Furthermore, the cost required to achieve this should be minimized as much as possible. Summary of the Invention

[0004] This invention proposes an electronic device and its monitoring method, enabling the electronic device to monitor and correct its internal clock signal. Furthermore, due to the simple structure of the test circuit, in addition to effectively monitoring and correcting the period and frequency of the clock signal, the required circuit area and power consumption are much smaller than those of a phase-locked loop, which helps to improve the accuracy of the internal clock signal under limited conditions.

[0005] In view of this, the present invention provides an electronic device comprising an oscillator, a controller, and a test circuit. The oscillator generates a clock signal based on an enable signal and determines a period of the clock signal based on an adjustment signal. The controller generates the enable signal and generates a first test signal based on the clock signal. The controller further determines the period based on a first comparison signal and a second comparison signal. The test circuit uses the first test signal to test the period and generates the first comparison signal and the second comparison signal.

[0006] According to one embodiment of the present invention, the controller further generates the adjustment signal to adjust the period to a target range.

[0007] According to one embodiment of the present invention, the controller generates the enable signal and the adjustment signal according to an external instruction, causing the oscillator to start generating the clock signal. When the controller receives the clock signal, it generates the first test signal and the second test signal. The first test signal includes a first pulse width, and the second test signal includes a second pulse width, wherein the second pulse width is greater than the first pulse width.

[0008] According to an embodiment of the present invention, the test circuit includes a test capacitor. The test capacitor is charged with a first current during the first pulse width to generate a test voltage. The test circuit generates a first comparison signal and a second comparison signal based on the test voltage. The controller determines whether the period is within the target range based on the first comparison signal and the second comparison signal, and generates the adjustment signal accordingly.

[0009] According to an embodiment of the present invention, the test circuit further includes a first current source, a first transistor, a second transistor, a first voltage source, a first comparator, and a second comparator. The first current source generates a first current. The first transistor charges the test capacitor with the first current according to the first test signal to generate the test voltage. The test capacitor is coupled between a first node and a ground terminal. The second transistor couples the first node to the ground terminal according to the second test signal. The first voltage source generates a first reference voltage and a second reference voltage. The first comparator compares the test voltage with the first reference voltage to generate the first comparison signal. The second comparator compares the test voltage with the second reference voltage to generate the second comparison signal.

[0010] According to an embodiment of the present invention, when the test circuit tests the cycle, the first transistor is turned on according to the first test signal, and the second transistor is not turned on according to the second test signal.

[0011] According to an embodiment of the present invention, when the test circuit does not test the cycle, the first transistor does not conduct according to the first test signal, and the second transistor couples the first node to the ground terminal according to the second test signal.

[0012] According to an embodiment of the present invention, when the controller determines that the test voltage is between the first reference voltage and the second reference voltage based on the first comparison signal and the second comparison signal, the controller determines that the period is within the target range and does not adjust the period.

[0013] According to an embodiment of the present invention, when the controller determines that the test voltage exceeds the first reference voltage and the second reference voltage based on the first comparison signal and the second comparison signal, the controller determines that the period exceeds the target range and reduces the period based on the adjustment signal.

[0014] According to an embodiment of the present invention, when the controller determines that the voltage of the first node is less than the first reference voltage and the second reference voltage based on the first comparison signal and the second comparison signal, it determines that the period is lower than the target range, and the controller increases the period based on the adjustment signal.

[0015] According to one embodiment of the present invention, the oscillator includes a second voltage source, a second current source, a current adjustment circuit, a current mirror, an oscillation capacitor, a third transistor, a fourth transistor, and an inverter. The second voltage source and the second current source generate a second current according to the enable signal. The current adjustment circuit receives the second current and generates a third current, and changes the ratio of the third current to the second current according to the adjustment signal. The current mirror maps the third current to a fourth current and a fifth current. The oscillation capacitor is coupled between a second node and a ground terminal and is charged by the fourth current. The third transistor couples the second node to the ground terminal according to the clock signal. The fourth transistor includes a first terminal, a second terminal, and a control terminal, wherein the first terminal receives the fifth current, the second terminal is coupled to the ground terminal, and the control terminal is coupled to the second node. The inverter generates the clock signal according to the voltage at the first terminal of the fourth transistor.

[0016] According to an embodiment of the present invention, one of the first voltage source and the second voltage source is a first bandgap reference voltage circuit, and the other of the first voltage source and the second voltage source is a second bandgap reference voltage circuit. The first bandgap reference voltage circuit includes a plurality of bipolar junction transistors (BJTs), and the second bandgap reference voltage circuit includes an enhancement-mode transistor and a depletion-mode transistor.

[0017] The present invention also proposes a monitoring method applicable to an electronic device, the electronic device including an oscillator. The monitoring method includes: receiving an external command; enabling the oscillator to generate a clock signal according to the external command; generating a charging time using the clock signal; during the charging time, charging a test capacitor using a first current to generate a test voltage; and determining, based on the test voltage, whether a period of the clock signal is within a target range.

[0018] According to an embodiment of the present invention, the step of charging the test capacitor with the first current during the charging time to generate the test voltage includes: generating the first current using a first current source; generating a first test signal using the clock signal, wherein the first test signal includes a first pulse width equal to the charging time; and charging the test capacitor with the first current according to the first test signal.

[0019] According to an embodiment of the present invention, the step of determining whether the period of the clock signal is within the target range based on the test voltage includes: comparing the test voltage with a first reference voltage to generate a first comparison signal; comparing the test voltage with a second reference voltage to generate a second comparison signal; and determining whether the period is within the target range based on the first comparison signal and the second comparison signal. The monitoring method further includes: adjusting the period when the period is not within the target range; and not adjusting the period when the period is within the target range.

[0020] According to an embodiment of the present invention, the step of determining whether the period is within the target range based on the first comparison signal and the second comparison signal further includes: when the test voltage is determined to be between the first reference voltage and the second reference voltage based on the first comparison signal and the second comparison signal, the period is determined to be within the target range.

[0021] According to an embodiment of the present invention, the step of determining whether the period is within the target range based on the first comparison signal and the second comparison signal further includes: when it is determined based on the first comparison signal and the second comparison signal that the test voltage exceeds the first reference voltage and the second reference voltage, determining that the period exceeds the target range.

[0022] According to an embodiment of the present invention, the oscillator further includes an oscillation capacitor, and the clock signal is generated by charging and discharging the oscillation capacitor with a second current. The step of adjusting the period when the period is not within the target range further includes: increasing the second current to reduce the period.

[0023] According to an embodiment of the present invention, the step of determining whether the period is within the target range based on the first comparison signal and the second comparison signal further includes: when the test voltage is determined to be less than the first reference voltage and the second reference voltage based on the first comparison signal and the second comparison signal, the period is determined to be less than the target range.

[0024] According to an embodiment of the present invention, the oscillator further includes an oscillation capacitor, and the clock signal is generated by charging and discharging the oscillation capacitor with a second current. The step of adjusting the period when the period is not within the target range further includes: reducing the second current to increase the period. Attached Figure Description

[0025] Figure 1 A block diagram of an electronic device according to an embodiment of the present invention is shown;

[0026] Figure 2 A circuit diagram of a test circuit according to an embodiment of the present invention is shown;

[0027] Figure 3 The diagram shows a waveform of the test circuit according to an embodiment of the present invention;

[0028] Figure 4 A circuit diagram of an oscillator according to an embodiment of the present invention is shown;

[0029] Figure 5 A circuit diagram of a current adjustment circuit according to an embodiment of the present invention is shown;

[0030] Figure 6 A circuit diagram of a bandgap reference voltage circuit according to an embodiment of the present invention is shown;

[0031] Figure 7 A circuit diagram showing a bandgap reference voltage circuit according to another embodiment of the present invention; and

[0032] Figure 8 A flowchart of a monitoring method according to an embodiment of the present invention is shown.

[0033] Symbol Explanation

[0034] 100: Electronic devices

[0035] 110: Controller

[0036] 120,400: Oscillator

[0037] 130,200: Test Circuit

[0038] 410,500: Current adjustment circuit

[0039] 600, 700: Bandgap reference voltage circuit

[0040] 800: Monitoring Methods

[0041] CMD: External Commands

[0042] EN: Enable signal

[0043] CLK: Clock signal

[0044] ADJ: Adjust signal

[0045] ADJ[0]: First element adjustment signal

[0046] ADJ[1]: Second bit adjustment signal

[0047] ADJ[2]: Third bit adjustment signal

[0048] ADJ[3]: Fourth bit adjustment signal

[0049] ADJ[4]: Fifth bit adjustment signal

[0050] BIST1: First Test Signal

[0051] BIST2: Second Test Signal

[0052] SCP1: First Comparison Signal

[0053] SCP2: Second Comparison Signal

[0054] IS1: First current source

[0055] IS2: Second current source

[0056] T1: First transistor

[0057] T2: Second transistor

[0058] T3: Third transistor

[0059] T4: Fourth transistor

[0060] T5: Fifth transistor

[0061] T6: Sixth transistor

[0062] T7: Seventh Transistor

[0063] T8: Eighth transistor

[0064] T9: Ninth Transistor

[0065] T10: Tenth Transistor

[0066] T11: Eleventh Transistor

[0067] T12: Twelfth transistor

[0068] T13: Thirteenth Transistor

[0069] T14: Fourteenth transistor

[0070] T15: Fifteenth Transistor

[0071] T16: Sixteenth transistor

[0072] T17: The seventeenth transistor

[0073] T18: The eighteenth transistor

[0074] T19: Nineteenth transistor

[0075] T20: Twentieth Transistor

[0076] T21: Twenty-first transistor

[0077] T22: Twenty-second transistor

[0078] T23: Twenty-third transistor

[0079] T24: Twenty-fourth transistor

[0080] T25: Twenty-fifth transistor

[0081] CT: Test Capacitance

[0082] COSC: Oscillating Current

[0083] CP: Filter capacitor

[0084] BG1: First voltage source

[0085] BG2: Second voltage source

[0086] CMP1: First comparator

[0087] CMP2: Second comparator

[0088] VCC: Supply voltage

[0089] VTS: Test Voltage

[0090] VREF1: First reference voltage

[0091] VREF2: Second reference voltage

[0092] PW1: First pulse width

[0093] PW2: Second pulse width

[0094] H: High voltage level

[0095] CM: Current Mirror

[0096] INV: Inverter

[0097] N1: First node

[0098] N2: Second node

[0099] N3: Third node

[0100] N4: Fourth Node

[0101] N5: Fifth Node

[0102] NP1: First positive extreme

[0103] NP2: Second positive extreme

[0104] NP3: Third positive extreme

[0105] NN1: First negative extreme

[0106] NN2: Second negative extreme

[0107] NN3: Third negative extreme

[0108] NO: Output end

[0109] I1: First current

[0110] I2: Second current

[0111] I3: Third Current

[0112] I4: Fourth Current

[0113] I5: Fifth Current

[0114] IB: Bias Current

[0115] R1: First resistor

[0116] R2: Second resistor

[0117] R3: Third resistor

[0118] R4: Fourth resistor

[0119] R5: Fifth resistor

[0120] R6: Sixth resistor

[0121] Q1: First bipolar junction transistor

[0122] Q2: Second bipolar junction transistor

[0123] AMP: Amplifier

[0124] VBG: Bandgap reference voltage

[0125] VEB1, VEB2: Trans-voltage

[0126] S810~S860: Procedure Flow Detailed Implementation

[0127] The following description is an embodiment of the present invention. Its purpose is to illustrate the general principles of the invention and should not be considered as a limitation thereof. The scope of the invention should be defined by the claims.

[0128] It is understood that although terms such as "first," "second," and "third" may be used herein to describe various devices, components, regions, layers, and / or portions, these devices, components, regions, layers, and / or portions should not be limited by these terms, and these terms are only used to distinguish different devices, components, regions, layers, and / or portions. Therefore, a first device, component, region, layer, and / or portion discussed below may be referred to as a second device, component, region, layer, and / or portion without departing from the teachings of some embodiments of the present invention.

[0129] It is worth noting that the following disclosure provides multiple embodiments or examples for practicing different features of the invention. The specific device examples and arrangements described below are merely for briefly illustrating the spirit of the invention and are not intended to limit the scope of the invention. Furthermore, the same device symbols or terms may be repeated in multiple examples in the following description. However, the purpose of repetition is only to provide a simplified and clear description and is not intended to limit the relationship between the various embodiments and / or configurations discussed below. Moreover, descriptions in the following description of a feature being connected to, coupled to, and / or formed on another feature may actually encompass multiple different embodiments, including direct contact between the features, or additional features formed between the features, such that the features are not in direct contact.

[0130] Figure 1 A block diagram of an electronic device according to an embodiment of the present invention is shown. Figure 1 As shown, the electronic device 100 includes a controller 110, an oscillator 120, and a test circuit 130. The controller 110 receives an external command CMD and generates an enable signal EN to enable the oscillator 120 to generate a clock signal CLK. The controller 110 also generates an adjustment signal ADJ to adjust the period (or frequency, hereinafter referred to as period) of the clock signal CLK.

[0131] According to an embodiment of the present invention, when the controller 110 receives the clock signal CLK, the controller 110 generates a first test signal BIST1 and a second test signal BIST2, so that the test circuit 130 generates a first comparison signal SCP1 and a second comparison signal SCP2 based on the period of the clock signal CLK tested by the first test signal BIST1 and the second test signal BIST2.

[0132] The controller 110 determines whether the period of the clock signal CLK is within the target range based on the first comparison signal SCP1 and the second comparison signal SCP2. When the period of the clock signal CLK is not within the target range, the controller 110 adjusts the period of the clock signal CLK generated by the oscillator 120 using the adjustment signal ADJ.

[0133] According to one embodiment of the present invention, when the controller 110 receives an external instruction CMD to generate an enable signal EN and receives a clock signal CLK, the controller 110 generates a first test signal BIST1 and a second test signal BIST2, controlling the test circuit 130 to test the period of the clock signal CLK. In other words, the test circuit 130 only tests the period of the clock signal CLK after the oscillator 120 has finished starting. After the controller 110 has adjusted the period of the clock signal CLK, the controller 110 uses the adjusted clock signal CLK for subsequent operations.

[0134] Figure 2 A circuit diagram of a test circuit according to an embodiment of the present invention is shown. Figure 2 As shown, the test circuit 200 includes a first current source IS1, a first transistor T1, a second transistor T2, a test capacitor CT, a first voltage source BG1, a first comparator CMP1, and a second comparator CMP2.

[0135] The first current source IS1 generates a first current I1 from the supply voltage VCC and flows to the first transistor T1. The first transistor T1, according to the first test signal BIST1, provides the first current I1 to the first node N1 to generate the test voltage VTS. The second transistor T2, according to the second test signal BIST2, couples the first node N1 to ground. The test capacitor CT is coupled between the first node N1 and ground.

[0136] A first voltage source BG1 generates a first reference voltage VREF1 and a second reference voltage VREF2. According to one embodiment of the invention, the first reference voltage VREF1 is greater than the second reference voltage VREF2. According to one embodiment of the invention, a first current source IS1, in conjunction with the first voltage source BG1, generates a first current I1 with a low temperature coefficient. According to one embodiment of the invention, the first voltage source BG1 is a bandgap reference voltage circuit.

[0137] The first comparator CMP1 includes a first positive terminal NP1 and a first negative terminal NN1. The first positive terminal NP1 receives a first reference voltage VREF1, and the first negative terminal NN1 receives a test voltage VTS. The first comparator CMP1 compares the test voltage VTS with the first reference voltage VREF1 to generate a first comparison signal SCP1. The second comparator CMP2 includes a second positive terminal NP2 and a second negative terminal NN2. The second positive terminal NP2 receives the test voltage VTS, and the second negative terminal NN2 receives a second reference voltage VREF2. The second comparator CMP2 compares the test voltage VTS with the second reference voltage VREF2 to generate a second comparison signal SCP2.

[0138] Figure 3 The following description shows a waveform diagram of a test circuit according to an embodiment of the present invention. Figure 2 Circuit diagram and Figure 3 The waveform diagram is provided for detailed explanation.

[0139] like Figure 3 As shown, at the first time T1, the controller 110 switches the first test signal BIST1 and the second test signal BIST2 from a high voltage level to a low voltage level. The first test signal BIST1 includes a first pulse width PW1, and the second test signal BIST2 includes a second pulse width PW2. The first pulse width PW1 is smaller than the second pulse width PW2. According to an embodiment of the present invention, the first pulse width PW1 and the second pulse width PW2 are generated by the period of the clock signal CLK.

[0140] According to other embodiments of the present invention, the controller 110 may also switch the first test signal BIST1 and the second test signal BIST2 from a low voltage level to a high voltage level at a first time T1. Here, the switching from a high voltage level to a low voltage level is used for illustrative purposes and is not limited thereto.

[0141] like Figure 2 As shown, during the first pulse width PW1, since both the first test signal BIST1 and the second test signal BIST2 are at low voltage levels, the first transistor T1 is turned on and the second transistor T2 is not turned on. The test capacitor CT is charged by the first current I1 to generate the test voltage VTS. According to an embodiment of the present invention, since the test capacitor CT is charged within the first pulse width PW1, the first pulse width PW1 can also be regarded as the charging time of the test capacitor CT.

[0142] like Figure 3As shown, the test voltage VTS begins to rise from the first time point T1. At the second time point T2, the test voltage VTS exceeds the second reference voltage VREF2, causing the second comparison signal SCP2 to switch to a high voltage level H at the second time point T2. Furthermore, since the test voltage VTS is always less than the first reference voltage VREF1, the first comparison signal SCP1 always maintains a high voltage level H.

[0143] According to an embodiment of the present invention, the controller 110 can determine that the period of the clock signal CLK is within the target range based on the fact that both the first comparison signal SCP1 and the second comparison signal SCP2 are at high voltage level H, without needing to adjust the period of the clock signal CLK through the adjustment signal ADJ.

[0144] According to another embodiment of the present invention, when the test voltage VTS exceeds the first reference voltage VREF1 and the second reference voltage VREF2 within the first pulse width PW1, the controller 110 can determine that the period of the clock signal CLK exceeds the target range by the first comparison signal SCP1 being at a low voltage level and the second comparison signal SCP2 being at a high voltage level H, and can reduce the period of the clock signal CLK by adjusting the signal ADJ.

[0145] According to another embodiment of the present invention, when the test voltage VTS is less than the first reference voltage VREF1 and the second reference voltage VREF2 within the first pulse width PW1, the controller 110 can determine that the period of the clock signal CLK is lower than the target range by the first comparison signal SCP1 being at a high voltage level H and the second comparison signal SCP2 being at a low voltage level, and can increase the period of the clock signal CLK by adjusting the signal ADJ.

[0146] like Figure 3 As shown, when the test circuit 200 does not test the period of the clock signal CLK, both the first test signal BIST1 and the second test signal BIST2 are at high voltage levels. This prevents the first transistor T1 from being turned on, thus stopping the first current I1 from charging the test capacitor CT, and turns on the second transistor T2 to discharge the test capacitor CT to ground. According to other embodiments of the present invention, when the test circuit 200 does not test the period of the clock signal CLK, the controller 110 can de-energize the first current source IS1, the first voltage source VS1, the first comparator CMP1, and the second comparator CMP2 to reduce overall power loss.

[0147] Figure 4 A circuit diagram of an oscillator according to an embodiment of the present invention is shown, wherein... Figure 4 The oscillator 400 corresponds to Figure 1 , Figure 2 Oscillator 120. For example... Figure 4As shown, the oscillator 400 includes a second voltage source BG2, a second current source IS2, a current adjustment circuit 410, a current mirror CM, an oscillation current COSC, a third transistor T3, a fourth transistor T4, and an inverter INV.

[0148] The second voltage source BG2 and the second current source IS2 generate a second current I2 according to the enable signal EN. According to one embodiment of the invention, the second voltage source BG2 is a bandgap reference voltage circuit. According to another embodiment of the invention, the second current source IS2 and the second voltage source BG2 are used to generate a second current I2 with a low temperature coefficient. The current adjustment circuit 410 receives the second current I2 and generates a third current I3, and changes the ratio of the third current I3 to the second current I2 according to the adjustment signal ADJ.

[0149] The current mirror CM maps the third current I3 to the fourth current I4 and the fifth current I5, where the ratio of the fourth current I4 to the third current I3 is K, and the ratio of the fifth current I5 to the third current I3 is J. The oscillating capacitor COSC is coupled between the second node N2 and the ground terminal, and is charged by the fourth current I4.

[0150] The third transistor T3 couples the second node N2 to ground based on the clock signal CLK. The fourth transistor T4 includes a first terminal, a second terminal, and a control terminal, wherein the first terminal receives the fifth current I5, the second terminal is coupled to ground, and the control terminal is coupled to the second node N2. The inverter INV generates the clock signal CLK based on the voltage at the first terminal of the fourth transistor T4.

[0151] According to one embodiment of the present invention, when the fourth current I4 charges the oscillating capacitor COSC, the voltage of the second node N2 continuously rises from a low voltage level, at which time the clock signal CLK is at a low voltage level. According to another embodiment of the present invention, when the voltage of the second node N2 is sufficient to turn on the fourth transistor T4, the clock signal CLK is at a high voltage level (i.e., the supply voltage VDD), thereby turning on the third transistor T3 and discharging the oscillating capacitor COSC (i.e., the voltage of the second node N2) to the ground terminal.

[0152] Figure 5 This diagram shows a current adjustment circuit according to an embodiment of the present invention, wherein the current adjustment circuit 500 corresponds to... Figure 4 The current adjustment circuit 410 is described below using a 5-bit adjustment signal ADJ, but is not intended to be limited to this in any way.

[0153] like Figure 5As shown, the current adjustment circuit 500 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14.

[0154] The fifth transistor T5 receives the second current I2 and is coupled as a diode. The second current I2 flows through the fifth transistor T5 to generate a bias voltage VB, which is coupled to the control terminals of the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14.

[0155] According to one embodiment of the present invention, the sixth transistor T6 has the same aspect ratio as the fifth transistor T5, therefore the current flowing through the sixth transistor T6 is the same as the current flowing through the fifth transistor. According to other embodiments of the present invention, the aspect ratio of the sixth transistor T6 is Y times that of the fifth transistor T5. The following explanation assumes that the sixth transistor T6 has the same aspect ratio as the fifth transistor T5, but is not intended to limit the scope in any way.

[0156] The aspect ratios of the seventh transistor T7 and the eighth transistor T8 are 1 / 2 and 1 / 4 of those of the fifth transistor T5, respectively. Therefore, the current flowing through the seventh transistor T7 and the eighth transistor T8 is 1 / 2 and 1 / 4 of that flowing through the fifth transistor T5, respectively. The aspect ratios of the ninth transistor T9 and the tenth transistor T10 are the same as those of the eighth transistor T8. Since the ninth transistor T9 and the tenth transistor T10 are connected in series, the current flowing through the ninth transistor T9 and the tenth transistor T10 can be considered as 1 / 2 of that flowing through the eighth transistor T8.

[0157] Furthermore, the aspect ratios of the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 are the same as those of the eighth transistor T8. In addition, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 are connected in series. Therefore, the current flowing through the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, and the fourteenth transistor T14 can be regarded as 1 / 4 of the current flowing through the eighth transistor T8.

[0158] like Figure 5As shown, the current adjustment circuit 500 also includes a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, and a nineteenth transistor T19, which are controlled by the first bit adjustment signal ADJ[0], the second bit adjustment signal ADJ[1], the third bit adjustment signal ADJ[2], the fourth bit adjustment signal ADJ[3], and the fifth bit adjustment signal ADJ[4], respectively.

[0159] For example, when the seventeenth transistor T17 and the nineteenth transistor T19 are turned on by adjusting the signal ADJ[4:0], the ratio of the third current I3 to the second current I2 is 9 / 8. In other words, the controller 110 selects at least one of the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17, the eighteenth transistor T18, and the nineteenth transistor T19 to be turned on by adjusting the signal ADJ, thereby adjusting the magnitude of the third current I3.

[0160] Back Figure 4 The oscillation capacitor COSC is charged by the fourth current I4, which is K times the third current I3. When the controller 110 increases or decreases the magnitude of the third current I3 by adjusting the signal ADJ, the period of the clock signal CLK also decreases or increases accordingly, thereby achieving the purpose of adjusting the period (or frequency) of the clock signal CLK.

[0161] Figure 6 A circuit diagram of a bandgap reference voltage circuit according to an embodiment of the present invention is shown. Figure 6 As shown, the bandgap reference voltage circuit 600 includes a first resistor R1, a second resistor R2, a third resistor R3, a first bipolar junction transistor Q1, a second bipolar junction transistor Q2, and an amplifier AMP.

[0162] The first resistor R1 is connected in series with the first bipolar junction transistor Q1, and the third resistor R3 is coupled between the second resistor R2 and the second bipolar junction transistor Q2. The amplifier AMP includes a third negative terminal NN3, a third positive terminal NP3, and an output terminal NO. The third negative terminal NN3 is coupled between the first resistor R1 and the first bipolar junction transistor Q1, the third positive terminal NP3 is coupled between the second resistor R2 and the third resistor R3, and the output terminal NO is coupled between the first resistor R1 and the second resistor R2 and outputs the bandgap reference voltage VBG.

[0163] The bandgap reference voltage VBG is shown in Equation 1:

[0164]

[0165] Where VEB1 is the voltage across the first bipolar junction transistor Q1, VEB2 is the voltage across the second bipolar junction transistor Q2, and ΔVEB is as shown in Formula 2:

[0166] ΔVEB=VEB1-VEB2 (Formula 2)

[0167] Since VEB1 has a positive temperature coefficient and ΔVEB has a negative temperature coefficient, adjusting the ratio of the second resistor R2 and the third resistor R3 can minimize the temperature coefficient of the bandgap reference voltage VBG. According to one embodiment of the present invention, since the bandgap reference voltage VBG has a low temperature coefficient, combining resistors with zero or low temperature coefficients can generate a current with a low temperature coefficient.

[0168] Figure 7 A circuit diagram of a bandgap reference voltage circuit according to another embodiment of the present invention is shown. Figure 7 As shown, the bandgap reference voltage circuit 700 includes a twentieth transistor T20, a twenty-first transistor T21, a twenty-second transistor T22, a twenty-third transistor T23, a twenty-fourth transistor T24, a twenty-fifth transistor T25, a fourth resistor R4, a fifth resistor R5, a filter capacitor CP, and a sixth resistor R6. According to one embodiment of the present invention, the twentieth transistor T20 and the twenty-first transistor T21 are enhancement-mode P-type transistors, the twenty-second transistor T22 and the twenty-third transistor T23 are enhancement-mode N-type transistors, and the twenty-fourth transistor T24 and the twenty-fifth transistor T25 are depletion-mode transistors.

[0169] The twentieth transistor T20 is coupled as a diode and is coupled between the supply voltage VCC and the third node N3. The control terminal of the twenty-first transistor T21 is coupled to the third node N3, the first terminal of the twenty-first transistor T21 is coupled to the supply voltage VCC, and the second terminal of the twenty-first transistor T21 is coupled to the fifth node N5.

[0170] The control terminal of transistor T22 is coupled to the bandgap reference voltage VBG. The first terminal of transistor T22 is coupled to the fourth resistor R4. The second terminal of transistor T22 is coupled to the third node N3. The fourth resistor R4 is coupled to ground. The control terminal of transistor T23 is coupled to the bandgap reference voltage VBG. The first terminal of transistor T23 is coupled to ground. The second terminal of transistor T23 is coupled to the fourth node N4.

[0171] The control terminal and first terminal of the twenty-fourth transistor T24 are coupled to the fourth node N4, and the second terminal of the twenty-fourth transistor T24 is coupled to the fifth node N5. The control terminal of the twenty-fifth transistor T25 is coupled to the fourth node N4, the first terminal of the twenty-fifth transistor T25 is coupled to the bandgap reference voltage VBG, and the second terminal of the twenty-fifth transistor T25 is coupled to the fifth node N5. The fifth resistor R5 and the filter capacitor CP are connected in series between the fourth node N4 and the ground terminal for frequency response compensation.

[0172] Transistor T22, with resistor R4 as the fourth resistor, generates a bias current IB. Transistors T20 and T21 map the bias current IB to transistors T23 and T24, respectively. The current I flowing through transistor T23... T23 And the current I flowing through the twenty-fourth transistor T24 T24 Since they are equal, we can obtain Formula 3.

[0173] I T23 =K T23 (VBG-VT T23 ) 2 =K T24 (-VT T24 ) 2 =I T24 (Formula 3)

[0174] Where K T23 and K T24 The current constants of transistors T23 and T24, respectively, are VT. T23 VT is the threshold voltage of the twenty-third transistor T23. T24 This is the threshold voltage of the twenty-fourth transistor, T24. Therefore, after rearranging Equation 3, the bandgap reference voltage VBG is as shown in Equation 4.

[0175]

[0176] Since the threshold voltage of the 24th transistor T24 has a positive temperature coefficient, and the threshold voltage of the 23rd transistor T23 has a negative temperature coefficient, adjusting the aspect ratio of the 23rd transistor T23 to that of the 24th transistor T24 can minimize the temperature coefficient of the bandgap reference voltage VBG. Furthermore, minimizing the temperature coefficient of the sixth resistor R6 can also generate a current with a low temperature coefficient.

[0177] According to one embodiment of the present invention, the first voltage source BG1 is implemented by a bandgap reference voltage circuit 600, and the second voltage source BG2 is implemented by a bandgap reference voltage circuit 700. According to another embodiment of the present invention, the first voltage source BG1 is implemented by a bandgap reference voltage circuit 700, and the second voltage source BG2 is implemented by a bandgap reference voltage circuit 600. In other words, one of the first voltage source BG1 and the second voltage source BG2 is implemented by a plurality of bipolar junction transistors, and the other is implemented by an enhancement-mode transistor and a depletion-mode transistor, to avoid the possibility of simultaneous failure of both voltage sources.

[0178] According to another embodiment of the present invention, Figure 2 The first current source IS1 and Figure 3 The second current source IS2 is generated independently, which avoids common-mode failure. Common-mode failure refers to the simultaneous failure of devices in two or more independent channels of the system due to interdependence, which causes the system to fail to perform its intended function.

[0179] when Figure 2 When the oscillator 120 and the test circuit 200 use independent voltage and current sources respectively, a failure of either voltage or current source will cause an abnormal period in the clock signal CLK, and reduces the probability of simultaneous failures of the voltage and / or current sources of the oscillator 120 and the test circuit 200. The controller 110 can determine, through the first comparison signal SCP1 and the second comparison signal SCP2, whether an abnormality in the voltage and / or current sources of the oscillator 120 and the test circuit 200 has caused a shift in the period of the clock signal CLK. Furthermore, because... Figure 2 The oscillator 120 and the test circuit 200 use voltage sources with different architectures, which can further reduce... Figure 2 This reduces the probability of simultaneous malfunctions in the oscillator 120 and the voltage source of the test circuit 200, thereby preventing common-mode failure.

[0180] Figure 8 A flowchart of a monitoring method according to an embodiment of the present invention is shown. The following description of the monitoring method 800 will be accompanied by… Figure 2 The circuit diagram is provided for detailed explanation.

[0181] First, the controller 110 receives an external instruction CMD (step S810) and generates an enable signal EN according to the external instruction CMD, causing the oscillator 120 to generate a clock signal CLK (step S820). Next, the controller 110 uses the clock signal CLK to generate a charging time (step S830), wherein the charging time is equal to the first pulse width PW1 of the first test signal BIST1.

[0182] During the charging time, a test voltage VTS is generated by charging the test capacitor CT with a fixed current (step S840). The controller 110 determines whether the period of the clock signal CLK is within the target range based on the test voltage VTS (step S850). If the period of the clock signal CLK is within the target range, the monitoring method 800 ends. If the period of the clock signal CLK is not within the target range, the controller 110 adjusts the period of the clock signal CLK using the adjustment signal ADJ (step S860), and re-executes steps S830 to S850 until the period of the clock signal CLK is within the target range.

[0183] This invention proposes an electronic device and its monitoring method, enabling the electronic device to monitor and correct its internal clock signal. Furthermore, due to the simple structure of the test circuit, in addition to effectively monitoring and correcting the period and frequency of the clock signal, the required circuit area and power consumption are much smaller than those of a phase-locked loop, which helps to improve the accuracy of the internal clock signal under limited conditions.

[0184] While the embodiments and advantages of the present invention have been disclosed above, it should be understood that those skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of the invention. Furthermore, the scope of protection of the present invention is not limited to the processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps described in the specific embodiments of the specification. Anyone skilled in the art can understand, from the disclosure of some embodiments of the present invention, current or future developed processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps, as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein, and can be used according to some embodiments of the present invention. Therefore, the scope of protection of the present invention includes the above-described processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of the present invention also includes combinations of various claims and embodiments.

Claims

1. An electronic device, characterized in that, include: An oscillator generates a clock signal according to an enable signal, wherein the oscillator determines a period of the clock signal according to an adjustment signal. A controller generates the enable signal and, based on the clock signal, generates a first test signal, wherein the controller determines the period based on a first comparison signal and a second comparison signal; and A test circuit uses the first test signal to test the period and generate the first comparison signal and the second comparison signal; When the controller receives the clock signal, the controller generates the first test signal and a second test signal, wherein the first test signal includes a first pulse width, the second test signal includes a second pulse width, and the second pulse width is greater than the first pulse width. The test circuit includes: A test capacitor is charged with a first current during the first pulse width to generate a test voltage. The test circuit generates a first comparison signal and a second comparison signal based on the test voltage. The controller determines whether the period is within the target range based on the first comparison signal and the second comparison signal, and generates the adjustment signal accordingly. A first current source generates a first current; A first transistor charges the test capacitor with the first current according to the first test signal to generate the test voltage, wherein the test capacitor is coupled between a first node and a ground terminal. A second transistor, based on the second test signal, couples the first node to the ground terminal; A first voltage source generates a first reference voltage and a second reference voltage; A first comparator compares the test voltage with the first reference voltage to generate the first comparison signal; and A second comparator compares the test voltage with the second reference voltage to generate the second comparison signal.

2. The electronic device according to claim 1, characterized in that, The controller also generates the adjustment signal to adjust the period to a target range.

3. The electronic device according to claim 2, characterized in that, The controller generates the enable signal and the adjustment signal according to an external instruction, causing the oscillator to start generating the clock signal.

4. The electronic device according to claim 1, characterized in that, When the test circuit tests the cycle, the first transistor turns on according to the first test signal, and the second transistor does not turn on according to the second test signal.

5. The electronic device according to claim 1, characterized in that, When the test circuit does not test the cycle, the first transistor does not conduct according to the first test signal, and the second transistor couples the first node to the ground terminal according to the second test signal.

6. The electronic device according to claim 1, characterized in that, When the controller determines that the test voltage is between the first reference voltage and the second reference voltage based on the first comparison signal and the second comparison signal, the controller determines that the period is within the target range and does not adjust the period.

7. The electronic device according to claim 1, characterized in that, When the controller determines that the test voltage exceeds the first reference voltage and the second reference voltage based on the first comparison signal and the second comparison signal, the controller determines that the period exceeds the target range and reduces the period based on the adjustment signal.

8. The electronic device according to claim 1, characterized in that, When the controller determines that the voltage of the first node is less than the first reference voltage and the second reference voltage based on the first comparison signal and the second comparison signal, it determines that the period is lower than the upper target range, and the controller increases the period based on the adjustment signal.

9. The electronic device according to claim 1, characterized in that, The oscillator includes: A second voltage source and a second current source, which generate a second current according to the enable signal; A current adjustment circuit receives the second current and generates a third current, and changes the ratio of the third current to the second current according to the adjustment signal; A current mirror maps the third current to a fourth current and a fifth current; An oscillating capacitor is coupled between a second node and the ground terminal, and is charged by the fourth current; A third transistor, according to the clock signal, couples the second node to the ground terminal; A fourth transistor includes a first terminal, a second terminal, and a control terminal, wherein the first terminal receives the fifth current, the second terminal is coupled to the ground terminal, and the control terminal is coupled to the second node; and An inverter generates the clock signal based on the voltage at the first terminal of the fourth transistor.

10. The electronic device according to claim 9, characterized in that, One of the first voltage source and the second voltage source is a first bandgap reference voltage circuit, and the other of the first voltage source and the second voltage source is a second bandgap reference voltage circuit. The first bandgap reference voltage circuit includes a plurality of bipolar junction transistors, and the second bandgap reference voltage circuit includes an enhancement-mode transistor and a depletion-mode transistor.

11. A monitoring method applicable to an electronic device, characterized in that, The electronic device includes an oscillator, and the monitoring method includes: Receive an external command; According to the external command, the oscillator is enabled to generate a clock signal; A charging time is generated using the clock signal; During the charging time, a test capacitor is charged using a first current to generate a test voltage; and Based on the test voltage, determine whether one cycle of the clock signal is within a target range; The step of determining whether the period of the clock signal is within the target range based on the test voltage includes: The test voltage is compared with a first reference voltage to generate a first comparison signal; The test voltage is compared with a second reference voltage to generate a second comparison signal; and Based on the first comparison signal and the second comparison signal, it is determined whether the period is within the target range; The monitoring method further includes: When the period is not within the target range, adjust the period; and When the period is within the target range, the period is not adjusted.

12. The monitoring method according to claim 11, characterized in that, The step of charging the test capacitor with the first current during the charging time to generate the test voltage includes: The first current is generated using a first current source; Using the clock signal, a first test signal is generated, wherein the first test signal includes a first pulse width, the first pulse width being equal to the charging time; and The test capacitor is charged using the first current based on a first test signal.

13. The monitoring method according to claim 11, characterized in that, The step of determining whether the period is within the target range based on the first comparison signal and the second comparison signal includes: When the test voltage is determined to be between the first reference voltage and the second reference voltage based on the first comparison signal and the second comparison signal, the period is determined to be within the target range.

14. The monitoring method according to claim 11, characterized in that, The step of determining whether the period is within the target range based on the first comparison signal and the second comparison signal further includes: When it is determined from the first comparison signal and the second comparison signal that the test voltage exceeds the first reference voltage and the second reference voltage, it is determined that the period exceeds the target range.

15. The monitoring method according to claim 14, characterized in that, The oscillator further includes an oscillation capacitor, and the clock signal is generated by charging and discharging the oscillation capacitor with a second current. The step of adjusting the period when the period is not within the target range further includes: Increase the second current to reduce the cycle.

16. The monitoring method according to claim 11, characterized in that, The step of determining whether the period is within the target range based on the first comparison signal and the second comparison signal further includes: When the test voltage is determined to be less than the first reference voltage and the second reference voltage based on the first comparison signal and the second comparison signal, the period is determined to be lower than the target range.

17. The monitoring method according to claim 16, characterized in that, The oscillator further includes an oscillation capacitor, and the clock signal is generated by charging and discharging the oscillation capacitor with a second current. The step of adjusting the period when the period is not within the target range further includes: Reduce the second current to increase the cycle.

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