Digital-to-analog converter and method of operation thereof

Abstract

A digital-to-analog converter and an operating method thereof are provided. The digital-to-analog converter includes a current source module, a decoder, a change indicator, and a random number generator. The decoder is coupled to the current source module and receives a digital input signal. The change indicator is coupled to the decoder and provides an indication signal to the decoder. The random number generator is coupled to the change indicator and provides a random number signal to the change indicator. The change indicator generates the indication signal according to the random number signal, and the decoder generates a control signal to the current source module according to the digital input signal and the indication signal, so that the current source module generates an analog output signal corresponding to the digital input signal according to the control signal.

Description

Technical Field

[0001] This invention relates to a converter, and more particularly to a digital-to-analog converter and its operation method. Background Technology

[0002] A common problem with traditional digital-to-analog converters (DACs) is that the inconsistent current values ​​generated by the multiple internal current sources inevitably lead to spurious interference in the analog signal output by the DAC. For example, if at least one of the multiple internal current sources of the DAC provides a significantly higher or lower current value, some of the multiple analog signals sequentially output by the DAC in consecutive (operating) cycles may exhibit obvious numerical anomalies. This will result in poor performance in the DAC's integral non-linearity (INL) and spurious-free dynamic range (SFDR). Summary of the Invention

[0003] This invention provides a digital-to-analog converter and its operation method, which can achieve good digital-to-analog conversion function.

[0004] The digital-to-analog converter of this invention includes a current source module, a decoder, a change indicator, and a random number generator. The decoder is coupled to the current source module and receives a digital input signal. The change indicator is coupled to the decoder and provides an indicator signal to the decoder. The random number generator is coupled to the change indicator and provides a random number signal to the change indicator. The change indicator generates an indicator signal based on the random number signal, and the decoder generates a control signal to the current source module based on the digital input signal and the indicator signal, causing the current source module to generate an analog output signal corresponding to the digital input signal based on the control signal.

[0005] The operation method of the digital-to-analog converter in this embodiment of the invention includes the following steps: providing a random number signal through a random number generator; generating an indication signal based on the random number signal through a change indicator; receiving a digital input signal and the indication signal through a decoder; generating a control signal to a current source module based on the digital input signal and the indication signal through the decoder; and generating an analog output signal corresponding to the digital input signal through the current source module based on the control signal.

[0006] The digital-to-analog converter and its operation method of the present invention can generate an indication signal using a random number signal, and generate a control signal based on the digital input signal and the indication signal through a decoder, so that the analog output signal generated by the current source module according to the control signal can have a lower spurious component interference. Attached Figure Description

[0007] Figure 1 This is a circuit diagram of a digital-to-analog converter according to an embodiment of the present invention;

[0008] Figure 2 This is a flowchart of an operation method of a digital-to-analog converter according to an embodiment of the present invention;

[0009] Figure 3 This is a circuit diagram of a random number generator according to an embodiment of the present invention;

[0010] Figure 4 This is a circuit diagram of a change indicator according to an embodiment of the present invention;

[0011] Figure 5 yes Figure 4 A waveform diagram of the random number signal and the output signal generated by the change indicator;

[0012] Figure 6 This is a circuit diagram of a decoder and a current source module according to an embodiment of the present invention;

[0013] Figure 7A This is an example diagram of the operation of a digital-to-analog converter according to an embodiment of the present invention;

[0014] Figure 7B This is an example diagram of the operation of a digital-to-analog converter according to another embodiment of the present invention;

[0015] Figures 8A to 8D This is an example diagram illustrating the operation of control signals according to an embodiment of the present invention.

[0016] Explanation of reference numerals in the attached figures

[0017] 100: Digital-to-Analog Converter

[0018] 110: Decoder

[0019] 111: Decoding Circuit

[0020] 112: Control Circuit

[0021] 120: Random Number Generator

[0022] 130: Change indicator

[0023] 131_1~131_P: D-type flip-flops

[0024] 140: Current source module

[0025] 310-1~310-8: Displacement Buffer

[0026] 320: Logic Gates

[0027] 510, 520: Arrows

[0028] 601~603: Encoding array

[0029] 610: Logic Circuits

[0030] 810: Virtual bit

[0031] Din: Digital input signal

[0032] D1~D7: Output terminals of the displacement buffer

[0033] CS: Control signal

[0034] CLK: Frequency signal

[0035] RNS: Random Number Signal

[0036] SP: Indicator signal

[0037] Aout: Analog output signal

[0038] S210~S250: Steps

[0039] CK: Frequency input terminal

[0040] RE: Reset End

[0041] IN: Input terminal

[0042] OUT: Output terminal

[0043] RS: Reset signal

[0044] EN_1~EN_P, EN_1~EN_8: output signal

[0045] T11~T14: Time period

[0046] T1~T6: Period

[0047] D1, D1-1, D1-2, D1', D1”, D2, D2', D2”, F1, F1', F1”, F2, F2', F2”: Bit positions C1_1~C1_N, C2_1~C2_N, CM_1~CM_N: Current sources Detailed Implementation

[0048] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0049] Figure 1 This is a circuit diagram of a digital-to-analog converter according to an embodiment of the present invention. (Reference) Figure 1The digital-to-analog converter (DAC) 100 includes a decoder 110, a random number generator 120, a change indicator 130, and a current source module 140. In this embodiment, the decoder 110 is coupled to the change indicator 130 and the current source module 140. The random number generator 120 is coupled to the change indicator 130. In this embodiment, the random number generator 120 can provide a random number signal RNS to the change indicator 130, so that the change indicator 130 can generate an indicator signal SP based on the random number signal RNS. It should be noted that the change indicator 130 in this embodiment can directly transmit the random number signal or provide multiple simplified indicator signals SP through logical operations, and the present invention does not limit the signal implementation method of the indicator signal SP. The decoder 110 can receive a digital input signal Din and the indicator signal SP provided by the change indicator 130 to generate a corresponding control signal CS to the current source module 140. The current source module 140 can generate a corresponding analog output signal Aout based on the control signal CS. In this embodiment, the digital input signal Din may include, for example, an encoding corresponding to at least one of thermal code and binary code, but the invention is not limited thereto. The digital-to-analog converter 100 of this embodiment can implement a digital-to-analog converter with randomly-shifted dynamic element matching (RS-DEM) functionality.

[0050] In this embodiment, decoder 110 may be a Dynamic Element Matching (DEM) decoder. In this embodiment, random number generator 120 may be a pseudo-random number generator (PRNG) or other type of random number generator, and the generated random number signal may, for example, include a pseudo-random binary sequence (PRBS). In this embodiment, current source module 140 may further include multiple current sources arranged sequentially, and these current sources may form a current source array, for example, a 1×M current source array, an N×M current source array, or a multi-dimensional current source array, where M and N are positive integers. Furthermore, in this embodiment, digital-to-analog converter 100 may be implemented, for example, by a binary-weighted digital-to-analog converter (controlled by binary code), a segmented digital-to-analog converter (controlled by thermal code), or a combination of both. In one embodiment, if the digital-to-analog converter 100 is implemented by a segmented digital-to-analog converter circuit architecture, the current values ​​of the multiple output currents provided by these current sources can be approximately the same.

[0051] In this embodiment, the decoder 110 can determine the number of current sources to be enabled in the current source module 140 based on the digital input signal Din, and can determine the current source objects to be enabled based on the indication signal SP. It should be noted that the indication signal SP can cyclically indicate different current source objects to provide current output based on a periodic change. Furthermore, since the indication signal SP is generated based on the random number signal RNS, the indication signal SP can indicate changes randomly. For example, in the first cycle, the indication signal SP can indicate the first current source, the second current source, and the third current source to provide current output. Then, in the second cycle, the indication signal SP can indicate the second current source, the third current source, and the fourth current source to provide current output. Then, in the third cycle, the indication signal SP can still indicate the second current source, the third current source, and the fourth current source to provide current output. In other words, the current source objects it indicates to be enabled have a non-fixed variation (not always sequentially selecting from the next current source, and its specific operation will be described in detail in the following embodiments). In this way, the current source module 140 of this embodiment can effectively output an analog output signal Aout corresponding to the digital value of the digital input signal Din, and can have a lower influence of spurious component interference, and can have better performance in integral non-linearity (INL) and spurious free dynamic range (SFDR).

[0052] Figure 2 This is a flowchart illustrating the operation method of a digital-to-analog converter according to an embodiment of the present invention. (See reference) Figure 1 as well as Figure 2 The digital-to-analog converter 100 may, for example, perform the following steps S210 to S250. In this embodiment, the digital-to-analog converter 100 may receive a digital input signal Din in one (operation) cycle. In step S210, the digital-to-analog converter 100 may provide a random number signal RNS through a random number generator 120. In this embodiment, the random number signal RNS may, for example, consist of randomly occurring pulse waveforms corresponding to different cycles, wherein, for example, the occurrence of a pulse waveform represents the value "1", and the absence of a pulse waveform represents the value "0".

[0053] In step S220, the digital-to-analog converter 100 can generate an indication signal SP based on the random number signal RNS through the change indicator 130. In this embodiment, the change indicator 130 can determine whether the selection start value of the indication signal SP remains the same as or different from the selection start value of the previous cycle based on the random number signal RNS. In this embodiment, the random number signal RNS can be a 1-bit signal. When the change indicator 130 determines that the selection start value of the indication signal SP is different from the selection start value of the previous cycle (for example, the random number signal RNS has a value of "1" in this cycle), the change indicator 130 selects the selection start value as the result of the selection start value of the previous cycle plus 1. When the change indicator 130 determines that the selection start value of the indication signal SP is the same as the selection start keep value of the previous cycle (for example, the random number signal RNS has a value of "0" in this cycle), the change indicator 130 selects the selection start value as the selection start value of the previous cycle. It should be noted that the change indicator 130 can directly implement the above process, or it can be combined with an inverter, a delay circuit or other related circuits to simultaneously generate multiple sets of different random number change indicator signals SP.

[0054] In step S230, the digital-to-analog converter 100 can receive the digital input signal Din and the indication signal SP through the decoder 110. In step S240, the digital-to-analog converter 100 can generate a control signal CS to the current source module 140 based on the digital input signal Din and the indication signal SP through the decoder 110. In this embodiment, the decoder 110 can determine the number of current sources enabled based on the value corresponding to the encoding of the digital input signal Din (e.g., a decimal value, but the present invention is not limited to this value type). On the other hand, in addition to selecting multiple current sources based on a fixed current source as the starting selection target, the decoder 110 can also determine one of the multiple current sources in the current source module 140 as the starting selection target based on the selection starting value of the indication signal SP. For example, the user of this embodiment can select one of the multiple current sources in the current source module 140 as the initial selection target by using the selection start value of the indicator signal SP, and sequentially select other current sources based on the current source of the initial selection target according to the number of current sources enabled, so that these selected current sources are enabled to provide current output. Therefore, the decoder 110 can generate a control signal CS according to the number of current sources enabled and the selection start value. In this embodiment, the control signal CS may, for example, include multiple enable signals (or switch signals) to enable (or turn on) at least one of the corresponding multiple current sources in the current source module 140.

[0055] In step S250, the digital-to-analog converter 100 can generate an analog output signal Aout corresponding to the digital input signal Din according to the control signal CS via the current source module 140. In this embodiment, at least one of the multiple enabled current sources in the current source module 140 can provide a current output, and the current source module 140 can combine (add current values) the current outputs of these randomly enabled current sources to generate the analog output signal Aout (i.e., the sum of the current values ​​corresponding to the current outputs of these enabled current sources). In this way, the operation method of this embodiment and the digital-to-analog converter 100 can generate an analog output signal Aout with better integral nonlinearity and spurious dynamic range.

[0056] Figure 3 This is a circuit diagram of a random number generator according to an embodiment of the present invention. Figure 3 An example of a random number generator 120 provided in this embodiment of the invention is a 7-bit pseudo-random number generator, which has 1 output bit as a random number signal RNS. In detail, Figure 3 The random number generator 120 includes multiple shift buffers 310-1 to 310-8 and a logic gate 320. Shift buffers 310-1 to 310-8 are implemented using D-flip flip-flops, and each has outputs D1 to F7, timing inputs, and inputs. The timing inputs of shift buffers 310-1 to 310-8 are coupled to a frequency signal CLK. The output of shift buffer 310-8 generates a random number signal RNS. Shift buffers 310-1 to 310-7 are arranged in series. The logic gate 320 can be an XOR gate or an XNOR gate, and is used to convert the outputs of some of the shift buffers 310-1 to 310-7... Figure 3 For example, the signal feedback from the output terminals D6 and D7 of shift buffers 310-6 to 310-7 is returned to the input terminal of the first stage (i.e., shift buffer 310-1) of shift buffers 310-1 to 310-7. A "7-bit" pseudo-random number generator refers to a random number generator 120 that uses seven 1-bit shift buffers to generate a random number signal RNS. For a 7-bit pseudo-random number generator, the signal pattern of the output random number signal RNS will repeat after 127 cycles. Users of this embodiment can adjust it according to their needs. Figure 3 The number of shift buffers in the random number generator 120 can be used to adjust the number of bits inside it, for example, the random number generator 120 can be adjusted to 8 bits, 16 bits, etc. It should be noted that the random number signal RNS provided by the last stage (i.e., shift buffer 310-8) of the shift buffers 310-1 to 310-7 in the random number generator 120 in this embodiment is a 1-bit signal.

[0057] Figure 4 This is a circuit diagram of a change indicator 130 according to an embodiment of the present invention. (See reference) Figure 4 This embodiment is an exemplary embodiment of the change indicator of the present invention. In this embodiment, the change indicator 130 may include a plurality of D-type flip-flops 131_P, 131_1 to 131_(P-1) arranged in sequence, where P is a positive integer. In this embodiment, the input terminal IN of each of the D-type flip-flops 131_1 to 131_P is coupled to the output terminal OUT of the corresponding preceding D-type flip-flop. The frequency input terminal CK of each of the D-type flip-flops 131_1 to 131_P receives a random number signal RNS. The reset terminal RE of each of the D-type flip-flops 131_2 to 131_P receives a reset signal RS, and the setting terminal SET of the D-type flip-flop 131_1 (first stage) receives the reset signal RS. In this embodiment, the output terminal OUT of the D-type flip-flop 131_1 (first stage) outputs an output signal EN_1 with a corresponding pulse waveform (which can be represented by the value "1"). In this embodiment, the indicator signal SP is composed of the output signals EN_1 to EN_P on the respective output terminals OUT of the D-type flip-flops 131_2 to 131_P, and will be described below.

[0058] The output signals EN_1 to EN_P of the D-type flip-flops 131_1 to 131_P can be arranged sequentially to form the indicator signal SP. The starting value of the indicator signal SP is determined by the level corresponding to the output signal with the corresponding pulse waveform (which can be represented by the value "1"). In other words, the indicator signal SP in this embodiment is composed of the output signals EN_1 to EN_P, that is, the indicator signal SP = [EN_P, EN_(P-1), ..., EN_1].

[0059] In this embodiment, the number of D-type flip-flops 131_1 to 131_P can correspond to the number of current sources. For example, for a 1×M current source array, P equals M. As another example, for an N×M current source array, the N×M current source array can be divided into two groups for two-dimensional control. One group has P equal to N and uses internal circuitry to control the shift behavior of N rows, while the other group has P equal to M and uses internal circuitry to control the shift behavior of M columns. Furthermore, D-type flip-flops 131_1 to 131_P can also be applied to current source arrays with more dimensions (e.g., 3 dimensions or more).

[0060] For example, when the change indicator 130 starts operating, in the first cycle, the reset signal RS may have a start pulse (which can be represented by the value "1"), and the output of the D-type flip-flop 131_1 may output an output signal EN_1 with a corresponding pulse waveform (which can be represented by the value "1"), while the output signals EN_2 to EN_P of the D-type flip-flops 131_2 to 131_P have no pulse waveform (which can be represented by the value "0"). In other words, in the first cycle, which is the reset phase or the initial phase, the output signal EN_1 is set to the value "1", and the output signals EN_2 to EN_P are set to the value "0". Therefore, in the first cycle, the indicator signal SP may have a signal waveform corresponding to the value "000000…001", and the corresponding decimal value is "1" (the value type of the indicator signal SP in this invention is not limited to this).

[0061] In the second cycle, if the output of D-type flip-flop 131_2 receives the output signal EN_1 (which can be represented by the value "1") from the previous stage D-type flip-flop 131_1, and the random number signal RNS can, for example, have a pulse waveform (which can be represented by the value "1"), then the output of D-type flip-flop 131_2 can output an output signal EN_2 with a corresponding pulse waveform (which can be represented by the value "1"). The output signals EN_1, EN_3, and EN_P of D-type flip-flops 131_1, 131_3 to 131_P have no pulse waveform (which can be represented by the value "0"). Therefore, in the second cycle, the indicator signal SP can have a signal waveform corresponding to the value "000000…010", and the corresponding decimal value is "2".

[0062] Conversely, in the second cycle, if the output of D-type flip-flop 131_2 receives the output signal EN_1 (which can be represented by the value "1") of the previous stage D-type flip-flop 131_1, and the random number signal RNS may, for example, not have a pulse waveform (which can be represented by the value "0"), then the output of D-type flip-flop 131_1 can maintain the output signal EN_1 with the corresponding pulse waveform (which can be represented by the value "1"), while the output signals EN_2 to EN_P of D-type flip-flops 131_2 to 131_P have no pulse waveform (which can be represented by the value "0"). Therefore, in the second cycle, the indicator signal SP can maintain the signal waveform corresponding to the value "000000…001" of the previous cycle, and the corresponding decimal value is "1". Similarly, if the output signal EN_3 has the corresponding pulse waveform (which can be represented by the value "1"), then the selection start value indicated by the current indicator signal SP is "3" (decimal).

[0063] Figure 5 yes Figure 4A schematic diagram of the waveforms of the random number signal RNS and the output signals EN_1 to EN_8 generated by the change indicator 130. Here, it is assumed... Figure 4 P in the text is "8". Figure 4 The change indicator 130 includes a plurality of D-type flip-flops 131_1 to 131_8 arranged in sequence, and Figure 5 To more clearly illustrate this embodiment, the random number signal RNS and the output signals EN_1 to EN_8 of the D-type flip-flops 131_1 to 131_8 are presented. When the value of the random number signal RNS is "0", one of the output signals EN_1 to EN_8 that were in the enabled state of the previous stage will continue to be in the enabled state in the next time period. For example, please refer to... Figure 5 The time periods are T11 and T12, or T13 and T14. In time period T11, the output signal EN_7 is in the enabled state and the value of the random number signal RNS is "1". Then, because the value of the random number signal RNS changes to "0" in time period T12, the output signal EN_7, which was in the enabled state in time period T11, will continue to be in the enabled state in time period T12, as shown by arrow 510. Similarly, in time periods T13 and T14, because the value of the random number signal RNS changes from "1" to "0" in time period T13, the output signal EN_4, which was in the enabled state in time period T13, will continue to be in the enabled state in time period T14, as shown by arrow 520.

[0064] Figure 6 This is a circuit diagram of a decoder and a current source module according to an embodiment of the present invention. (Reference) Figure 1 as well as Figure 6 , Figure 1 The decoder 110 and current source module 140 can achieve the following: Figure 6 The circuit architecture shown is not limited to this. In this embodiment, the decoder 110 may include a decoding circuit 111 and a control circuit 112. The current source module 140 may include a plurality of current sources C1_1 to CM_N (i.e., an N×M current source array) in a two-dimensional architecture. The current sources C1_1 to CM_N are coupled to the same voltage VDD. The decoding circuit 111 can be used to receive a digital input signal Din and decode the digital input signal Din. For example, the digital input signal Din may be, for example, a binary code, and after being decoded by the decoding circuit 111, it may generate, for example, a plurality of decoded signals corresponding to a plurality of values ​​of a uni-ary code, and provide them to the control circuit 112. The control circuit 112 may receive the plurality of decoded signals and an indication signal SP to determine the generation of a control signal CS. It should be noted that the control signal CS may, for example, include a plurality of enable signals, and these enable signals are used to respectively operate the current sources C1_1 to CM_N to turn on to provide current, and the currents of the current sources that are turned on are summed to generate an analog output signal Aout.

[0065] It should be noted that the current source module 140 in this embodiment is an example of a segmented digital-to-analog converter controlled by thermal code, so each group of current sources has the same number N current values. That is, the number and total current value of current sources C1_1 to C1_N are the same as the number and total current value of current sources C2_1 to C2_N. However, in one embodiment, the current source module 140 can also be implemented by a binary weighted digital-to-analog converter controlled by binary code, so each group of current sources can have different current values, or, if each current source produces the same current value, each group of current sources can have different numbers. For example, if each current source produces the same current value, the first group of current sources may include 8 current sources C1_1 to C1_8. The second group of current sources may include 4 current sources C2_1 to C2_4 (since 8 × (1 / 2) = 4). The third group of current sources may include 2 current sources C3_1 to C3_2 (since 8 × (1 / 2)^2 = 2). The fourth group of current sources may include one current source C4_1 (since 8×(1 / 2)^3=1). The difference between each group of current sources is that the user of this embodiment controls the current source through other codes, thereby adaptively adjusting the current value generated by each group of current sources. For example, in addition to the control by unary codes mentioned above, binary codes can also be used for control.

[0066] Figure 7A This is an example diagram illustrating the operation of a digital-to-analog converter according to an embodiment of the present invention. (See reference) Figure 1 , Figure 6 as well as Figure 7A This embodiment uses a 1×8 current source array where N is "1" and M is "8" as an example. The current source module 140 may include, for example, a... Figure 6 The current sources C1_1, C2_1 to CM_1 shown are (i.e., Figure 6 In this context, N is the current source corresponding to "1" and M is "8", and each of the current sources C1_1, C2_1 to C8_1 can, for example, be used to provide a current output of current value I. In other words, Figure 6 In the case of M=8, CM_1 is C8_1. It should be noted that the current value I in this embodiment is only used to illustrate the result of current summation, and not the actual output result of the current source. The current values ​​provided by each current source may have slight differences.

[0067] like Figure 7AAs shown, during period T1, assuming the random number generator 120 provides a random number signal RNS with a value of "0" to the change indicator 130, and the change indicator 130 can generate an indicator signal SP corresponding to a value (selection start value) of "3" (decimal). When the decoder 110 receives a digital input signal Din with a value of "011" (taking binary code encoding as an example), the decoding circuit 111 of the decoder 110 can decode the digital input signal Din to generate a corresponding decoded signal. Since the decimal value corresponding to the encoding of the digital input signal Din is "3", the number of current sources enabled is 3. Furthermore, since the value of the indicator signal SP is "3", the control circuit 112 of the decoder 110 can decide to select 3 current sources (e.g., current sources C3_1, C4_1, C5_1) to enable starting from the 3rd current source (e.g., current source C3_1), and generate the signal as shown in the diagram. Figure 7A The control signal CS, encoded as "00111000", is shown during period T1. Since the values ​​of bits 3 to 5 of the control signal CS are "1", this means that current sources 3 to 5 (e.g., current sources C3_1, C4_1, C5_1) will be enabled to provide current output. Therefore, the analog output signal Aout can have a current value of, for example, 3 × I during period T1.

[0068] During period T2, assuming the random number generator 120 provides a random number signal RNS with a value of "1" to the change indicator 130, and the change indicator 130 can generate an indicator signal SP corresponding to a value (selection start value) of "4" (decimal) (the selection start value is the result of the selection start value of the previous period plus 1). When the decoder 110 still receives the encoded digital input signal Din with a value of "011", the decoding circuit 111 of the decoder 110 can decode the digital input signal Din to generate a corresponding decoded signal. However, the decimal value corresponding to the encoding of the digital input signal Din is still "3", so the number of current sources enabled is 3. And, since the value of the indicator signal SP is "4" (shifted from "3" to "4"), the control circuit 112 of the decoder 110 can decide to select 3 current sources (e.g., current sources C4_1, C5_1, C6_1) to enable starting from the 4th current source (e.g., current source C4_1), and generate a signal as shown in the figure. Figure 7A The control signal CS, encoded as "00011100", is shown during period T2. The values ​​of bits 4 through 6 of this control signal CS are "1", thus enabling current sources 4 through 6 (e.g., current sources C4_1, C5_1, C6_1) to provide current output. Therefore, the analog output signal Aout may have a current value of, for example, 3 × I during period T2.

[0069] During period T3, assume that random number generator 120 provides a random number signal RNS with a value of "0" to change indicator 130, and change indicator 130 can generate an indicator signal SP corresponding to a value (selection start value) of "4" (decimal) (the selection start value is the same as the selection start keep value of the previous period). When decoder 110 still receives a digital input signal Din encoded with a value of "011", decoder circuit 111 of decoder 110 can decode digital input signal Din to generate a corresponding decoded signal. However, the decimal value corresponding to the encoding of digital input signal Din is still "3", so the number of current sources enabled is 3. Since the value of indicator signal SP is "4" (unshifted), control circuit 112 of decoder 110 maintains the selection of 3 current sources (e.g., current sources C4_1, C5_1, C6_1) to enable starting from the 4th current source (e.g., current source C4_1), and generates a signal such as Figure 7A The control signal CS, encoded as "00011100", is shown during period T3. The values ​​of bits 4 through 6 of this control signal CS are "1", thus enabling current sources 4 through 6 (e.g., current sources C4_1, C5_1, C6_1) to provide current output. Therefore, the analog output signal Aout during period T3 may have a current value of, for example, 3 × I.

[0070] Similarly, during period T4, the value of the indicator signal SP is "4" (unshifted). The control circuit 112 of the decoder 110 can determine to select three current sources (e.g., current sources C4_1, C5_1, C6_1) to enable, starting from the fourth current source (e.g., current source C4_1), thereby generating... Figure 7A The control signal CS, encoded as "00011100", is shown during period T4. The values ​​at bits 4 through 6 of the control signal CS are "1", thus enabling current sources 4 through 6 (e.g., current sources C4_1, C5_1, C6_1) to provide current output. Therefore, the analog output signal Aout can have a current value of, for example, 3 × I during period T4.

[0071] Similarly, during period T5, the value of the indicator signal SP is "5" (shifted from "4" to "5"). The control circuit 112 of the decoder 110 can determine to select three current sources (e.g., current sources C5_1, C6_1, C7_1) to enable, starting from the fifth current source (e.g., current source C5_1), and generate... Figure 7AThe control signal CS, encoded as "00001110", is shown during period T5. The values ​​of bits 5 through 7 of the control signal CS are "1", thus enabling current sources 5 through 7 (e.g., current sources C5_1, C6_1, C7_1) to provide current output. Therefore, the analog output signal Aout may have a current value of, for example, 3 × I during period T5.

[0072] Similarly, during period T6, the value of the indicator signal SP is "6" (shifted from "5" to "6"). The control circuit 112 of the decoder 110 can determine to select three current sources (e.g., current sources C6_1, C7_1, C8_1) to enable, starting from the sixth current source (e.g., current source C6_1), and generate... Figure 7A The control signal CS, encoded as "00000111", is shown during period T6. The values ​​of bits 6 through 8 of this control signal CS are "1", thus enabling current sources 6 through 8 (e.g., current sources C6_1, C7_1, C8_1) to provide current output. Therefore, the analog output signal Aout during period T6 may have a current value of, for example, 3 × I.

[0073] Figure 7B This is an example diagram illustrating the operation of a digital-to-analog converter according to another embodiment of the present invention. (See reference) Figure 1 , Figure 6 as well as Figure 7B This embodiment uses a 1×8 current source array as an example. The current source module 140 may include, for example, a 1×8 current source array. Figure 6 The current sources C1_1, C2_1 to C8_1 are shown, and each of the current sources C1_1, C2_1 to C8_1 can be used, for example, to provide a current output of current value I.

[0074] like Figure 7BAs shown, during period T1, assuming the random number generator 120 provides a random number signal RNS with a value of "0" to the change indicator 130, and the change indicator 130 can generate an indicator signal SP corresponding to a value (selection start value) of "3" (decimal). When the decoder 110 receives a digital input signal Din with a value of "011" (taking binary code encoding as an example), the decoding circuit 111 of the decoder 110 can decode the digital input signal Din to generate a corresponding decoded signal. Since the decimal value corresponding to the encoding of the digital input signal Din is "3", the number of current sources enabled is 3. Furthermore, since the value of the indicator signal SP is "3", the control circuit 112 of the decoder 110 can decide to select 3 current sources (e.g., current sources C3_1, C4_1, C5_1) to enable starting from the 3rd current source (e.g., current source C3_1), and generate the signal as shown in the diagram. Figure 7B The control signal CS, encoded as "00111000", is shown during period T1. The values ​​of bits 3 through 5 of the control signal CS are "1", thus enabling current sources 3 through 5 (e.g., current sources C3_1, C4_1, C5_1) to provide current output. Therefore, the analog output signal Aout can have a current value of, for example, 3 × I during period T1.

[0075] During period T2, assume that random number generator 120 provides a random number signal RNS with the value "1" to change indicator 130, and change indicator 130 can generate an indicator signal SP corresponding to a value (selection start value) of "4" (decimal) (the selection start value is the result of the selection start value of the previous period plus 1). When decoder 110 receives a digital input signal Din encoded with the value "101", decoder circuit 111 of decoder 110 can decode the digital input signal Din to generate a corresponding decoded signal. However, the decimal value corresponding to the encoding of digital input signal Din is "5", therefore the number of current sources enabled is 5. Furthermore, since the value of the indicator signal SP is "4" (shifted from "3" to "4"), the control circuit 112 of the decoder 110 can determine to select five current sources (e.g., current sources C4_1, C5_1, C6_1, C7_1, C8_1) to enable, starting from the fourth current source (e.g., current source C4_1), thereby generating... Figure 7BThe control signal CS, encoded as "00011111", is shown during period T2. The values ​​of bits 4 through 8 of this control signal CS are "1", thus enabling current sources 4 through 8 (e.g., current sources C4_1, C5_1, C6_1, C7_1, C8_1) to provide current output. Therefore, the analog output signal Aout can have a current value of, for example, 5 × 1 during period T2.

[0076] During period T3, it is assumed that random number generator 120 provides a random number signal RNS with a value of "0" to change indicator 130, and change indicator 130 can generate an indicator signal SP corresponding to a value (selection start value) of "4" (decimal) (the selection start value is the same as the selection start keep value of the previous period). When decoder 110 receives a digital input signal Din encoded with a value of "010", decoder circuit 111 of decoder 110 can decode digital input signal Din to generate a corresponding decoded signal. However, the decimal value corresponding to the encoding of digital input signal Din is "2", so the number of current sources enabled is 2. And, since the value of indicator signal SP is "4" (unshifted), control circuit 112 of decoder 110 can decide to select 2 current sources (e.g., current sources C4_1, C5_1) to enable starting from the 4th current source (e.g., current source C4_1), and generate a signal such as Figure 7B The control signal CS, encoded as "00011000", is shown during period T3. The values ​​of the 4th and 5th bits of the control signal CS are "1", thus enabling the 4th and 5th current sources (e.g., current sources C4_1 and C5_1) to provide current output. Therefore, the analog output signal Aout can have a current value of, for example, 2×1 during period T3.

[0077] Similarly, during period T4, the value of the indicator signal SP is "4" (unshifted). The control circuit 112 of the decoder 110 can determine to select seven current sources (e.g., current sources C4_1, C5_1, C6_1, C7_1, C8_1, C1_1, C2_1) to enable, starting from the fourth current source (e.g., current source C4_1), thereby generating... Figure 7B The control signal CS, encoded as "11011111", is shown during period T4. The values ​​of bits 1-2 and 4-8 corresponding to the control signal CS are "1", thus enabling current sources 1-2 and 4-8 (e.g., current sources C1_1, C2_1, C4_1, C5_1, C6_1, C7_1, C8_1) to provide current output. Therefore, the analog output signal Aout can have a current value of, for example, 7×1 during period T3.

[0078] Similarly, during period T5, the value of the indicator signal SP is "5" (shifted from "4" to "5"). The control circuit 112 of the decoder 110 can determine to select seven current sources (e.g., current sources C5_1, C6_1, C7_1, C8_1, C1_1, C2_1, C3_1) to enable, starting from the fifth current source (e.g., current source C5_1), thereby generating... Figure 7B The control signal CS, encoded as "11101111", is shown during period T5. The values ​​of bits 1-3 and 5-8 corresponding to the control signal CS are "1", thus enabling current sources 1-3 and 5-8 (e.g., current sources C1_1, C2_1, C3_1, C5_1, C6_1, C7_1, C8_1) to provide current output. Therefore, the analog output signal Aout can have a current value of, for example, 7×I during period T5.

[0079] Similarly, during period T6, the value of the indicator signal SP is "6" (shifted from "5" to "6"). The control circuit 112 of the decoder 110 can determine to select seven current sources (e.g., current sources C6_1, C7_1, C8_1, C1_1, C2_1, C3_1, C4_1) to enable, starting from the sixth current source (e.g., current source C6_1), thereby generating... Figure 7B The control signal CS, encoded as "11110111", is shown during period T6. The values ​​at bits 1-4 and 6-8 of the control signal CS are "1", thus enabling current sources 1-4 and 6-8 (e.g., current sources C1_1, C2_1, C3_1, C4_1, C6_1, C7_1, C8_1) to provide current output. Therefore, the analog output signal Aout during period T6 can have, for example, a current value of 7×1.

[0080] This embodiment of the invention further employs Virtual Dynamic Component Matching (Pseudo DEM; PDEM) under the aforementioned random shift method. A virtual bit 810 is added to the encoding of the control signal CS. This virtual bit is located one bit before the bit position pointed to by the encoding of the digital input signal Din, and the value of this virtual bit 810 is maintained at "0". Specifically, from... Figure 7BAs can be seen from periods T5 and T6, even if the binary (decimal) value corresponding to the encoding of the digital input signal Din is "111(7)", the encoding of the control signal CS is "11101111" and "1110111", respectively. That is, the encoding of the control signal CS is not all "1" because it has a virtual bit 810 with the value "0". In this way, the control signal CS of the present invention is still different from the control signal CS of the previous stage when randomly shifted, so that the same input value will not appear continuously in the present invention, and the present invention can still change the position of the current source by changing the random number through the dynamic component matching method, thereby avoiding the dynamic component matching method from losing its effectiveness.

[0081] Back Figure 1 The current source module 140 of the present invention can be implemented by a single-dimensional to multi-dimensional current source array, wherein each dimension may include multiple current sources. The random number signal RNS may include multiple values. The indicator signal SP may include multiple selection start values. The change indicator 130 can determine, based on these values, whether these selection start values ​​of the indicator signal SP remain the same as or different from the selection start values ​​of the previous cycle. The decoder 110 can determine, based on these selection start values, one of the multiple dimensions of the current source array as the starting selection object. The digital input signal Din may include multiple sets of codes. The decoder 110 can determine the current-enabled quantity of each dimension of the current source array based on the values ​​(e.g., decimal values) corresponding to the multiple sets of codes of the digital input signal Din. For example, Figure 7A and Figure 7B In one embodiment of the present invention, it is implemented using a single-dimensional 1×8 current source array. Figures 8A to 8D This is an example diagram illustrating the operation of control signals according to an embodiment of the present invention. It uses a two-dimensional 8×8 current source array to implement a digital-to-analog converter with only unary encoding (thermometer code) functionality. Unary encoding can also be called unary code. Users of this embodiment can expand the current source array to more dimensions as needed, for example, a current source array with 3, 4, or even 5 dimensions.

[0082] exist Figures 8A to 8D In this embodiment, reference can also be made to Figure 1 as well as Figure 6This embodiment uses a current source module 140 with a two-dimensional current source array as an example (i.e., an N×M (8×8) current source array where N is 8 and M is 8). Furthermore, it should be noted that the random number signal RNS may include a first value and a second value. The indicator signal SP may include a first selection start value and a second selection start value. The change indicator 130 can determine, based on the first value, whether the first selection start value of the indicator signal SP remains the same as or different from the first selection start value of the previous cycle. The change indicator 130 can determine, based on the second value, whether the second selection start value of the indicator signal SP remains the same as or different from the second selection start value of the previous cycle.

[0083] In this embodiment, the decoder 110 can determine the starting selection object of these current sources in the first dimension according to the first selection start value, that is, for example, selecting one of the rows as the starting selection object of a row, and the decoder 110 can determine the starting selection object of these current sources in the second dimension according to the second selection start value, that is, for example, selecting one of the columns as the starting selection object of a column.

[0084] In this embodiment, the digital input signal Din may include a first set of codes and a second set of codes. The decoder 110 can determine the current-enabled quantity of these current sources based on the values ​​(e.g., decimal values) corresponding to the first set of codes and the values ​​(e.g., decimal values) corresponding to the second set of codes. In some embodiments, the values ​​(e.g., decimal values) corresponding to the first set of codes can be used to control the current-enabled quantity of these current sources in a first dimension, while the values ​​(e.g., decimal values) corresponding to the second set of codes are used to control the current-enabled quantity of these current sources in a second dimension. In one embodiment of the invention, other logical methods can also be used to determine the current-enabled quantity of these current sources, for example... Figures 8A to 8D Examples of implementations.

[0085] This embodiment uses an 8×8 current source array, and can also add a fixed-enabled current source to adjust the intermediate code near the current balance point. For example, when 32 current sources are enabled and the other 32 are disabled, this embodiment will have an additional normally enabled current source to avoid the generated current being exactly the middle value, thus allowing the decimal encoding to be closer to the center point. That is, when using an 8×8 current source array, this embodiment will also add an additional fixed-enabled current source, thus using 65 current sources to implement the 8×8 current source array, instead of 64 current sources.

[0086] refer to Figure 1 , Figure 6as well as Figure 8A This embodiment uses an 8×8 current source array as an example. The current source module 140 may include, for example, an 8×8 current source array. Figure 6 The current sources C1_1 to C8_8 are shown, and each of the current sources C1_1 to C8_8 can be used, for example, to provide a current output of current value I. The control signal CS may include the encoding information of the encoding array 601. In this embodiment of the invention, the corresponding current source can be selected using the encoding of the bit positions converted by the digital input signal Din, as described below. As mentioned above, the digital input signal Din in this embodiment includes a first set of codes and a second set of codes. The first set of codes and the second set of codes can be presented using binary encoding. For ease of explanation of this embodiment... Figures 8A to 8D Here, the first group of codes and the second group of codes are converted into decimal codes for the upper position of the row (e.g., positions D1 to F1) and the upper position of the column (e.g., positions D2 to F2), respectively.

[0087] Here Figure 8A As the initial case of this embodiment, both the first and second sets of codes are binary codes "000". Therefore, the decimal codes for both the top positions in the horizontal column (e.g., positions D1 to F1) and the top positions in the vertical column (e.g., positions D2 to F2) are "00000000". In the first set of codes, the top position D1 in the horizontal column is "0" for the least significant bit (LSB), and the top position F1 in the horizontal column is "0" for the most significant bit (MSB). In the second set of codes, the first bit of the top position D2 in the vertical column is the least significant bit (LSB), and the top position F2 in the vertical column represents the most significant bit (MSB).

[0088] Figure 8B The first group of codes (binary code "001") is converted to decimal "1", so the decimal code of the upper position of the row (e.g., positions D1, D1-1, D1-2 to F1) is "10000000", where position D1 is "1" of the least significant bit (LSB) and position F1 is "0" of the most significant bit (MSB).

[0089] on the other hand, Figure 8B The second group of codes (binary code "011") is converted to decimal "3", so the decimal code of the uppermost position in the row (e.g., positions D2 to F2) is "11100000". The three bits of position D2 are "111", and the first bit of position D2 is the least significant bit (LSB). Position F2 represents the most significant bit (MSB), and it is "0".

[0090] The encoding array 601 uses the code for the upper position of each horizontal column and the code for the upper position of each vertical column to correspond to the selected current source. Figure 8A For example, in this embodiment, the encoding of the upper position in the row is first confirmed, for example, the bit positions D1, D1-1, D1-2 to F1 are confirmed sequentially. When the encoding of the upper position in the row (e.g., bit position D1) is "1", it means that all current sources on the row corresponding to bit position D1 are enabled (turned on). For example, Figure 8A The bits D1 to F1 are all "0", therefore Figure 8A The encoded array 601 does not have a case where the entire row is "1". Figure 8B In the encoding array 601, the first row of the encoding array 601 corresponding to the bit position D1 is all "1".

[0091] On the other hand, when the code of the upper position of a row (e.g., bit position D1-1) is the first occurrence of "0", it indicates that all current sources in the corresponding row will be enabled (turned on) according to the code of the upper position of the row (e.g., bit positions D2 to F2), while the other part of the current sources will not be enabled (turned off). Please see Figure 8A The row corresponding to bit position D1 in the encoded array 601 has all its codes and the bits above it (bit positions D2 to F2) set to "0". See also... Figure 8B The row corresponding to bit position D1-1 in the encoding array 601 has the first three codes as "1" and the rest as "0". Therefore, the encoding of this row is exactly the same as that of bit positions D2 to F2. When the encoding of the upper bit position (e.g., bit position D1-2) is a "0" that appears multiple times before, the encoding of multiple rows corresponding to bit position D1-2 is all "0", indicating that the corresponding current source is not enabled (not turned on). Therefore, Figure 8A Encoding array 601 shows that all current sources are off, which means... Figure 4 All medium current sources are energy-disabled; Figure 8B The encoding array 601 presents 8+3=11 current sources that need to be turned on, thus turning on a total of 11 sets of current sources.

[0092] This embodiment of the invention utilizes the aforementioned logic to select the corresponding current source by using the encoding of the bit position converted from the digital input signal Din. Applying this embodiment, it can selectively determine whether the encoding of the upper bit position (e.g., bit positions D1, D1-1, D1-2) is the first, second, or Xth occurrence of a "0", and whether the corresponding row encoding is completely identical to the encoding of bit positions D2 to F2, thereby realizing this embodiment of the invention, but not limited to the aforementioned logic.

[0093] Returning to this embodiment, as Figure 8B As shown, in the first cycle, assuming the random number generator 120 provides a random number signal RNS with a first value of "0" and a second value of "0" to the change indicator 130, and the change indicator 130 can generate an indicator signal SP corresponding to a value (first selection start value) of "1" (decimal) and a value (second selection start value) of "1" (decimal). As previously mentioned, when the decoder 110 receives a digital input signal Din with a first set of codes (taking binary code as an example) having a value of "001" and a second set of codes (taking binary code as an example) having a value of "011", the decoding circuit 111 of the decoder 110 can decode the digital input signal Din to generate a corresponding decoded signal. Since the total number of current sources to be enabled is 8 + 3 = 11, the decimal value corresponding to the first group of codes in the digital input signal Din is "1" to indicate the activation of a group of 8 current sources per row, and the decimal value corresponding to the second group of codes in the digital input signal Din is "3" to indicate the activation of 3 groups of current sources. Furthermore, since the values ​​of the indicator signal SP are "1" (first selection start value) and "1" (second selection start value), the decoder 110 can decide to enable all 8 groups of current sources (e.g., current sources C1_1 to C1_8) in columns 1-8 of the first row, and decide to enable the current sources in columns 1-3 of the second row. That is, starting from the first current source in the second row, 3 current sources (e.g., current sources C2_1 to C2_3) are selected to be enabled, resulting in... Figure 8B The control signal CS shown corresponds to the encoded array 601 during the first cycle.

[0094] In this embodiment, the value corresponding to the upper position D1 of the first group of codes is "1", indicating that the 1st to 8th current sources in the first row (e.g., current sources C1_1 to C1_8) will be enabled to provide current output. Furthermore, the value corresponding to the upper position D2 of the second group of codes is "111", indicating that the 1st to 3rd current sources in the second row (e.g., current sources C2_1 to C2_3) will be enabled to provide current output. Thus, the analog output signal Aout can have a current value of, for example, 11×I during the first cycle, and if the 65th group of fixed-on current sources is included, the total current value is 11×I + I = 12×I.

[0095] Next, refer to Figure 1 as well as Figure 8C .like Figure 8CAs shown, in the second cycle, assuming the random number generator 120 provides a random number signal RNS with a first value of "0" and a second value of "1" to the change indicator 130, the change indicator 130 will generate an indicator signal SP corresponding to a value (first selection start value) of "1" (decimal) and a value (second selection start value) of "2" (decimal). When the decoder 110 receives a digital input signal Din with a first group code of "001" and a second group code of "011", the decoding circuit 111 of the decoder 110 can decode the digital input signal Din to generate a corresponding decoded signal. In this embodiment, the decimal value corresponding to the first group code of the digital input signal Din is "1" to indicate the activation of a group of 8 current sources in a row, and the decimal value corresponding to the second group code of the digital input signal Din is "3" to indicate the activation of 3 current sources. Furthermore, since the values ​​of the indicator signal SP are "1" (first selection start value) and "2" (second selection start value), the decoder 110 can determine that all current sources in the first row (e.g., current sources C1_1 to C1_8) are enabled, and select three current sources (e.g., current sources C2_2 to C2_4) starting from the current source in the second row and second column to enable them (e.g., the corresponding current sources marked by the next bit position of the horizontal upper position D1' in the first group of codes and the vertical upper position D2' in the second group of codes, as indicated by the aforementioned segment mechanism), thereby generating... Figure 8C The control signal CS shown corresponds to the encoded array 602 during the second cycle.

[0096] In this embodiment, the value corresponding to the upper position D1' in the first group of codes is "1", and the value corresponding to the upper position F1' in the first group of codes is "0", which remains in the same position (because the first value of the random number signal RNS is "0"). Therefore, the 1st to 8th current sources in the first row (e.g., current sources C1_1 to C1_8) will be enabled to provide current output. In this embodiment, the value corresponding to the 2nd to 4th column positions D2' in the second group of codes is "1", and the default value of the 8th column position in the second group of codes (e.g., "0") is "0". Figure 8B Position F2) Cyclic displacement to Figure 8C In the second group of encoding, the bit position is F2' in the first column of the row (because the second value of the random number signal RNS is "1"). Therefore, the 2nd to 4th current sources in the 2nd row (e.g., current sources C2_2 to C2_4) will be enabled to provide current output. In this way, the analog output signal Aout can have a current value of, for example, 11×I during the second cycle, but due to... Figure 8BCompared to the current sources provided at different locations, and if the 65th group of fixed-on current sources is included in the calculation, the total current value is 11×I+I=12×I.

[0097] Or, refer to Figure 1 as well as Figure 8D .like Figure 8D As shown, in the second cycle, assuming the random number generator 120 provides a random number signal RNS with a first value of "1" and a second value of "0" to the change indicator 130, and the change indicator 130 can generate an indicator signal SP corresponding to a value (first selection start value) of "2" (decimal) and a value (second selection start value) of "1" (decimal). When the decoder 110 receives a digital input signal Din with a first group code of "001" and a second group code of "011", the decoding circuit 111 of the decoder 110 can decode the digital input signal Din to generate a corresponding decoded signal. In this embodiment, the decimal value corresponding to the first group code of the digital input signal Din is "1" to indicate that a whole row of 8 current sources will be turned on, and the decimal value corresponding to the second group code of the digital input signal Din is "3" to indicate that 3 current sources will be turned on. Furthermore, since the values ​​of the indicator signal SP are "2" (first selection start value) and "1" (second selection start value), the decoder 110 can determine that all current sources in the second row (e.g., current sources C2_1 to C2_8) are enabled, and the current elements in columns 1 to 3 of the third row are controlled to be enabled. That is, starting from the first current source in the third row, three current sources (e.g., current sources C3_1 to C3_3) are selected to be enabled, thus generating... Figure 8D The control signal CS shown corresponds to the encoding array 603 during the second cycle.

[0098] In this embodiment, the value corresponding to position D1 in the second row of the first group of codes is "1", while the default value of position D1 in the eighth row of the first group of codes is "0" (e.g., ...). Figure 8A Position F1) Cyclic displacement to Figure 8DIn the first group of codes, the bit position F1 in the first row of the horizontal column is set (because the first value of the random number signal RNS is "1"). Therefore, the first to eighth current sources in the second row (e.g., current sources C2_1 to C2_8) will be enabled to provide current output. Furthermore, the bit position D2 in the first to third columns of the vertical column in the second group of codes is set to "1", and the bit position F2 in the vertical column of the second group of codes, which is "0", remains in the same position (because the second value of the random number signal RNS is "0"). Therefore, the first to third current sources in the third row (e.g., current sources C3_1 to C3_3) will be enabled to provide current output. In this way, the analog output signal Aout can have a current value of, for example, 11I during the second period, but due to... Figure 8B , Figure 8C Compared to the current sources provided at different locations, and if the 65th group of fixed-on current sources is included in the calculation, the total current value is 11×I+I=12×I.

[0099] In summary, the digital-to-analog converter and its operating method of the present invention can generate an indication signal using a random number signal by changing the indicator, and can generate a corresponding control signal based on the digital input signal and the indication signal by a decoder, thereby enabling at least one of multiple current sources in a random displacement selection mode that varies with time (operation cycle). Therefore, the analog output signal generated by the digital-to-analog converter of the present invention can have better integral nonlinearity and spurious-free dynamic range performance.

[0100] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A digital-to-analog converter, characterized in that, include: Current source module; The decoder is coupled to the current source module and receives digital input signals; The indicator is changed, coupled to the decoder, and an indication signal is provided to the decoder; as well as A random number generator, coupled to the change indicator, provides a random number signal to the change indicator. The change indicator generates the indication signal based on the random number signal, and the decoder generates a control signal to the current source module based on the digital input signal and the indication signal, so that the current source module generates an analog output signal corresponding to the digital input signal based on the control signal. The change indicator further adds a virtual bit to the indicator signal, the virtual bit being located one bit before the bit position indicated by the encoding of the digital input signal, and the virtual bit being set to the value 0.

2. The digital-to-analog converter according to claim 1, wherein the current source module comprises a plurality of current sources, and the plurality of current sources are arranged sequentially. The decoder determines the number of current sources to be enabled based on the numerical value corresponding to the encoding of the digital input signal, and determines one of the plurality of current sources as the initial selection target based on the selection start value of the indication signal, and determines whether to sequentially select other current sources from the initial selection target based on the number of current sources to be enabled, so that at least one of the plurality of current sources is enabled to provide current output.

3. The digital-to-analog converter according to claim 2, wherein the change indicator determines, based on the random number signal, whether the selection start value of the indicator signal remains the same as or different from the selection start value of the previous period.

4. The digital-to-analog converter according to claim 3, wherein when the change indicator determines that the selection start value of the indicator signal is different from the selection start value of the previous period based on the random number signal, the selection start value is the result of adding 1 to the selection start value of the previous period.

5. The digital-to-analog converter according to claim 2, wherein the plurality of current sources form a 1×M current source array, where M is a positive integer.

6. The digital-to-analog converter according to claim 2, wherein the plurality of current sources form an N×M current source array, where M and N are positive integers.

7. The digital-to-analog converter according to claim 2, wherein the digital input signal comprises multiple sets of codes. The decoder determines the current-enabled quantity of each dimension of the current source array based on the values ​​corresponding to the multiple sets of codes of the digital input signal.

8. The digital-to-analog converter of claim 2, wherein the indication signal includes a plurality of selection start values, The decoder determines one of the multiple dimensions of the current source array as the starting selection object based on the multiple selection start values.

9. The digital-to-analog converter according to claim 8, wherein the random number signal comprises a plurality of values. The change indicator determines, based on the plurality of values, whether the plurality of selection start values ​​of the indicator signal remain the same as or different from the selection start values ​​of the previous cycle.

10. The digital-to-analog converter of claim 1, wherein the random number generator comprises: Multiple displacement buffers; as well as Logic gates The plurality of displacement buffers are arranged in series with each other. The logic gate feeds back the output of a portion of the multiple displacement buffers to the multiple displacement buffers as the input of the first stage of the multiple displacement buffers. The output of the last stage of the plurality of displacement buffers provides the random number signal, which is a 1-bit signal.

11. The digital-to-analog converter of claim 1, wherein the change indicator comprises a plurality of D-type flip-flops arranged in sequence. The input terminals of each of the plurality of D-type flip-flops are coupled to the output terminals of the corresponding preceding D-type flip-flops. The frequency input terminals of each of the plurality of D-type flip-flops receive the random number signal. The setting terminal of the first stage of the plurality of D-type flip-flops receives a reset signal, and the reset terminals of the other stages of the plurality of D-type flip-flops receive the reset signal.

12. A method for operating a digital-to-analog converter, comprising: Random number signals are provided through a random number generator; The indicator is modified to generate an indication signal based on the random number signal; The digital input signal and the indication signal are received by the decoder; The decoder generates a control signal to the current source module based on the digital input signal and the indication signal. as well as The current source module generates an analog output signal corresponding to the digital input signal based on the control signal. The step of generating the control signal to the current source module by the decoder based on the digital input signal and the indication signal includes: A virtual bit is added to the indication signal. The virtual bit is located one bit before the bit position indicated by the encoding of the digital input signal, and the virtual bit is set to the value 0.

13. The operating method according to claim 12, wherein the current source module comprises a plurality of current sources, and the plurality of current sources are arranged sequentially, wherein the step of generating the control signal comprises: The decoder determines the number of current sources enabled based on the numerical value corresponding to the encoding of the digital input signal. The decoder determines one of the plurality of current sources as the initial selection target based on the selection start value of the indication signal; and The decoder determines whether to sequentially select other current sources from the initial selection object based on the number of current sources enabled, so that at least one of the plurality of current sources is enabled to provide current output.

14. The operating method according to claim 13, wherein the change indicator determines, based on the random number signal, whether the selection start value of the indicator signal remains the same as or different from the selection start value of the previous period.

15. The operating method according to claim 14, wherein when the change indicator determines that the selection start value of the indicator signal is different from the selection start value of the previous period based on the random number signal, the selection start value is the result of adding 1 to the selection start value of the previous period.

16. The operating method according to claim 13, wherein the plurality of current sources form a 1×M current source array, where M is a positive integer.

17. The operating method according to claim 13, wherein the plurality of current sources form an N×M current source array, where M and N are positive integers.

18. The operating method of claim 13, wherein the digital input signal comprises multiple sets of codes, and the step of generating the control signal further comprises: The decoder determines the current-enabled quantity of each dimension of the current source array based on the values ​​corresponding to the multiple sets of codes of the digital input signal.

19. The operating method of claim 13, wherein the indication signal includes a plurality of selection start values, and the step of generating the control signal further includes: The decoder determines one of the multiple dimensions of the current source array as the starting selection object based on the multiple selection start values.

20. The operating method according to claim 19, wherein the random number signal comprises a plurality of values. The change indicator determines, based on the plurality of values, whether the plurality of selection start values ​​of the indicator signal remain the same as or different from the selection start values ​​of the previous cycle.

21. The method of operation according to claim 12, wherein the random number generator comprises: Multiple displacement buffers; as well as Logic gates The plurality of displacement buffers are arranged in series with each other. The logic gate feeds back the output of a portion of the multiple displacement buffers to the multiple displacement buffers as the input of the first stage of the multiple displacement buffers. The output of the last stage of the plurality of displacement buffers provides the random number signal, which is a 1-bit signal.

22. The method of operation according to claim 12, wherein the change indicator comprises a plurality of D-type triggers arranged in sequence, and the step of generating the indicator signal comprises: The input terminals of each of the plurality of D-type flip-flops are coupled to the output terminals of the corresponding preceding D-type flip-flops; The random number signal is received through the frequency input terminals of the plurality of D-type flip-flops; as well as The reset signal is received through the setting terminal of the first stage of the plurality of D-type flip-flops, and the reset signal is received through the individual reset terminals of the other stages of the plurality of D-type flip-flops.

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