A transmitter circuit structure and a transceiver

Abstract

The application discloses a transmitter circuit structure and a transceiver, and the transmitter circuit structure comprises a capacitor and a first resistor connected with the capacitor, and further comprises a fixed current module and a dynamic current offset module. One end of the fixed current module is connected with the first resistor, and the other end is grounded, and the fixed current module is used for providing a fixed current for the capacitor; the dynamic current offset module is connected with the first resistor and the fixed current module respectively, and is used for offsetting a dynamic current of a LIN node. The application completely offsets or approximately offsets the dynamic current of the LIN node through the dynamic current offset module, and provides a stable current for the capacitor through the fixed current module, so that the current in the transmitter circuit structure basically does not change with time, electromagnetic interference and radiation in the transmitter circuit structure are avoided, and the problem that electromagnetic interference or electromagnetic radiation occurs in the transmitter circuit in the process that the voltage of the LIN bus rises or falls in the prior art is solved.

Description

Technical Field

[0001] This invention relates to the field of LIN transceiver technology, specifically to a transmitter circuit structure and a transceiver. Background Technology

[0002] like Figure 1 As shown, Figure 1 This is a traditional LIN transmitter circuit, in which the first resistor and capacitor are external components of the transmitter circuit chip, while the rest are internal components of the transmitter circuit chip. Figure 1 When switch K1 in the circuit opens from closed to open, the LIN bus voltage rises, and the current I that charges the capacitor increases. charge for:

[0003]

[0004] Among them, V D1 The voltage drop across diode D1 is given by the formula above. It can be seen that as the LIN bus voltage increases from low to high, I... charge The current gradually decreases until it eventually reaches zero, therefore Figure 1 The charging current of the LIN transmitter circuit changes gradually.

[0005] When switch K1 changes from open to closed, the LIN bus voltage drops, and the current I discharged from the capacitor increases. discharge for:

[0006]

[0007] Where N is the ratio of the number of NMOS transistors NM2 to the number of NMOS transistors NM1, this formula shows that as the LIN bus voltage decreases from high to low, I... discharge The current gradually decreases until it approaches a certain value, therefore... Figure 1 The discharge current of the LIN transmitter circuit also changes gradually.

[0008] In summary, during the rise or fall of the LIN bus voltage, the charging and discharging current of the capacitor in the LIN transmitter circuit changes. In other words, the capacitor current changes continuously over time, resulting in electromagnetic interference and electromagnetic radiation in the circuit. This will undoubtedly affect the normal operation of other electronic devices.

[0009] Therefore, a new technological solution is needed. Summary of the Invention

[0010] In view of this, embodiments of the present invention provide a transmitter circuit structure and transceiver to solve the problem of electromagnetic interference or electromagnetic radiation generated in the transmitter circuit during the rise or fall of the LIN bus voltage in the prior art.

[0011] The embodiments of the present invention provide the following technical solutions:

[0012] This invention provides a transmitter circuit structure, including a capacitor and a first resistor connected to the capacitor. The transmitter circuit structure further includes:

[0013] A fixed current module, one end of which is connected to a first resistor and the other end is grounded, is used to provide a fixed current to the capacitor;

[0014] A dynamic current cancellation module is connected to the first resistor and the fixed current module respectively, and is used to cancel the dynamic current of the LIN node.

[0015] Furthermore, the fixed current module includes:

[0016] A first current source, the input terminal of which is connected to the first resistor;

[0017] A first switch, the first end of which is connected to the output end of the first current source, and the second end of which is connected to the capacitor through the dynamic current cancellation module;

[0018] The second switch, the first end of which is connected to the dynamic current cancellation module;

[0019] The second current source has its input terminal connected to the second terminal of the second switch and its output terminal connected to the capacitor.

[0020] Furthermore, the dynamic current cancellation module includes:

[0021] A current mirror reference generation unit, wherein the first end of the current mirror reference generation unit is connected to the first resistor;

[0022] Multiple first PMOS transistors are connected to the current mirror reference generation unit to replicate the dynamic reference current generated by the current mirror reference generation unit.

[0023] A compensation current control unit, wherein the compensation current control unit is connected to the plurality of first PMOS transistors respectively;

[0024] A current mirror unit, wherein the first end of the current mirror unit is connected to the compensation current control unit and the first PMOS transistor respectively, and the second end of the current mirror unit is connected to the fixed current module;

[0025] The compensation current control unit can control the connection or disconnection between the first PMOS transistor and the first terminal of the current mirror unit.

[0026] Furthermore, the current mirror reference generation unit includes:

[0027] The second PMOS transistor has its gate connected to the gates of the plurality of first PMOS transistors and the drain of the second PMOS transistor, and its source connected to the sources of the plurality of first PMOS transistors and the first resistor.

[0028] The second resistor has its input terminal connected to the drain of the second PMOS transistor and its output terminal connected to the fixed current module.

[0029] The first diode has its anode connected to the output terminal of the second resistor, and its cathode connected to the capacitor.

[0030] Furthermore, the cathode of the first diode is connected to the LIN node.

[0031] Furthermore, the compensation current control unit includes:

[0032] The plurality of third switches, the first terminals of which are connected to the drains of the plurality of first PMOS transistors, and the second terminals of which are connected to the first terminals of the current mirror unit;

[0033] A control element, wherein the control element is connected to the third terminal of the plurality of third switches respectively.

[0034] Furthermore, the third switch is a single-pole double-throw switch.

[0035] Furthermore, the current mirror unit includes:

[0036] The first NMOS transistor has its drain connected to its gate, and its drain can be connected to the drains of the plurality of first PMOS transistors through the compensation current control unit. The source of the first NMOS transistor is grounded.

[0037] The second NMOS transistor has its gate connected to the gate of the first NMOS transistor, the drain of the first NMOS transistor is connected to the fixed current module, and the source of the first NMOS transistor is grounded.

[0038] Furthermore, the dynamic current cancellation module includes:

[0039] The second diode has its anode connected to the current mirror reference generation unit and its cathode connected to the current mirror unit.

[0040] A transceiver according to an embodiment of the present invention includes the transmitter circuit structure as described above.

[0041] Compared with the prior art, the beneficial effects that the at least one technical solution adopted in the embodiments of the present invention can achieve include at least:

[0042] The present invention discloses a transmitter circuit structure that completely or approximately cancels the dynamic current of the LIN node through a dynamic current cancellation module and provides a stable current to the capacitor through a fixed current module. This ensures that the current in the transmitter circuit structure remains essentially unchanged over time, thereby avoiding electromagnetic interference and radiation in the transmitter circuit structure. This solves the problem of electromagnetic interference or electromagnetic radiation generated in the transmitter circuit during the rise or fall of the LIN bus voltage in the prior art. Attached Figure Description

[0043] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a schematic diagram of the transmitter circuit in the prior art;

[0045] Figure 2 This is a structural block diagram of the transmitter circuit structure according to an embodiment of the present invention;

[0046] Figure 3 This is a schematic diagram of a specific embodiment of the transmitter circuit of the present invention;

[0047] The attached figures are labeled as follows:

[0048] 10. Capacitors;

[0049] 20. First resistor;

[0050] 30. Fixed current module; 31. First current source; 32. First switch; 33. Second switch; 34. Second current source;

[0051] 40. Dynamic current cancellation module; 41. Current mirror reference generation unit; 411. Second PMOS transistor; 412. Second resistor; 413. First diode; 42. First PMOS transistor; 43. Compensation current control unit; 431. Third switch; 432. Control element; 44. Current mirror unit; 441. First NMOS transistor; 442. Second NMOS transistor; 45. Second diode. Detailed Implementation

[0052] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0053] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0054] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0055] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0056] Additionally, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that practice can be carried out without these specific details.

[0057] In the existing technology, the charging current or discharging current of capacitor 10 changes during the rise or fall of the LIN bus voltage, that is, di / dt changes. Therefore, there are more frequency components in the transmitter circuit, resulting in greater external EME (electromagnetic environment) radiation.

[0058] Based on this, the embodiments of the present invention propose a processing solution: such as Figure 2As shown, the present invention completely or approximately cancels the dynamic current of the LIN node through the dynamic current cancellation module 40, and provides a stable current to the capacitor 10 through the fixed current module 30, so that the current in the transmitter circuit structure does not change with time, thereby avoiding electromagnetic interference and radiation. Therefore, when the transmitter of the LIN transceiver is working, whether the LIN bus voltage rises from low to high or from high to low, its rising slope and falling slope are fixed or approximately constant, and can be done relatively slowly, thereby minimizing EME.

[0059] The technical solutions provided by the various embodiments of this application are described below with reference to the accompanying drawings.

[0060] like Figures 2-3 As shown, an embodiment of the present invention provides a transmitter circuit structure, including a capacitor 10 and a first resistor 20 connected to the capacitor 10.

[0061] Both capacitor 10 and first resistor 20 are located outside the transmitter circuit structure.

[0062] The transmitter circuit structure also includes a fixed current module 30 and a dynamic current cancellation module 40. One end of the fixed current module 30 is connected to the first resistor 20, and the other end is grounded. The fixed current module 30 provides a fixed current to the capacitor 10. The dynamic current cancellation module 40 is connected to both the first resistor 20 and the fixed current module 30, and is used to cancel the dynamic current of the LIN node.

[0063] The dynamic current cancellation module 40 completely or approximately cancels the dynamic current of the LIN node, and the charging current of capacitor 10 and the discharging current of capacitor 10 are fixed by the fixed current module 30. This makes the rise or fall slope of the LIN bus voltage fixed, that is, di / dt = 0 or close to zero. Therefore, the magnitude of the rise or fall slope of LIN can be controlled by adjusting the magnitude of the charging current and discharging current of capacitor 10.

[0064] This invention does not limit the specific structure of the fixed current module 30 and the dynamic current cancellation module 40. Any circuit structure that can provide a fixed current to the capacitor 10 and cancel the dynamic current of the LIN node is within the scope of protection of this application.

[0065] In a preferred embodiment of this application, the fixed current module 30 includes a first current source 31, a first switch 32, a second switch 33, and a second current source 34. The input terminal of the first current source 31 is connected to the first resistor 20; the first terminal of the first switch 32 is connected to the output terminal of the first current source 31, and the second terminal is connected to the capacitor 10 through a dynamic current cancellation module 40; the first terminal of the second switch 33 is connected to the dynamic current cancellation module 40; the input terminal of the second current source 34 is connected to the second terminal of the second switch 33, and the output terminal is connected to the capacitor 10.

[0066] The first current source 31 and the second current source 34 are used to provide a stable current.

[0067] The first switch 32 and the second switch 33 are used to control the closing or opening of the fixed current module 30, so as to provide a fixed current to the capacitor 10 or stop providing a fixed current to the capacitor 10.

[0068] In a preferred embodiment of this application, the dynamic current cancellation module 40 includes a current mirror reference generation unit 41, a plurality of first PMOS transistors 42, a compensation current control unit 43, and a current mirror unit 44. The first terminal of the current mirror reference generation unit 41 is connected to a first resistor 20; the plurality of first PMOS transistors 42 are respectively connected to the current mirror reference generation unit 41 to replicate the dynamic reference current generated by the current mirror reference generation unit 41; the compensation current control unit 43 is respectively connected to the plurality of first PMOS transistors 42; the first terminal of the current mirror unit 44 is respectively connected to the compensation current control unit 43 and the first PMOS transistors 42, and the second terminal of the current mirror unit 44 is connected to the fixed current module 30.

[0069] One end of the current mirror reference generation unit 41 is connected to the first current source 31, and the other end is connected to the first switch 32.

[0070] The compensation current control unit 43 can control the connection or disconnection of the first PMOS transistor 42 and the first end of the current mirror unit 44.

[0071] Among them, the current mirror reference generation unit 41 is used to generate a dynamic reference current.

[0072] Among them, multiple first PMOS transistors 42 are used to replicate the dynamic reference current generated by the current mirror reference generation unit 41.

[0073] Among them, at least one of the multiple first PMOS transistors 42 is directly connected to the current mirror unit 44, and multiple first PMOS transistors 42 can be connected to the current mirror unit 44 under the control of the compensation current control unit 43.

[0074] The compensation current control unit 43 can control multiple first PMOS transistors 42 to connect with the compensation current control unit 43 itself or control multiple first PMOS transistors 42 to connect with the current mirror unit 44.

[0075] In a preferred embodiment of this application, the current mirror reference generation unit 41 includes a second PMOS transistor 411, a second resistor 412, and a first diode 413. The gate of the second PMOS transistor 411 is connected to the gates of a plurality of first PMOS transistors 42 and the drain of the second PMOS transistor 411, respectively. The source of the second PMOS transistor 411 is connected to the sources of the plurality of first PMOS transistors 42 and the first resistor 20, respectively. The input terminal of the second resistor 412 is connected to the drain of the second PMOS transistor 411, and its output terminal is connected to the fixed current module 30. The anode of the first diode 413 is connected to the output terminal of the second resistor 412, and the cathode of the first diode 413 is connected to the capacitor 10.

[0076] The source of the second POS transistor is connected to the input terminal of the first current source 31.

[0077] The second PMOS transistor 411, the second resistor 412, and the first diode 413 work together to generate a dynamic reference current.

[0078] like Figure 3 As shown, the source of the first PMOS transistor 42 is also connected to the VBAT node.

[0079] Furthermore, the cathode of the first diode 413 is connected to the LIN node.

[0080] In a preferred embodiment of this application, the compensation current control unit 43 includes a plurality of third switches 431 and a control element 432. The first terminals of the plurality of third switches 431 are connected to the drains of a plurality of first PMOS transistors 42, and the second terminals of the plurality of third switches 431 are connected to the first terminal of the current mirror unit 44; the control element 432 is connected to the third terminals of the plurality of third switches 431 respectively.

[0081] When the first and second ends of the third switch 431 are connected, the first PMOS transistor 42 is connected to the current mirror unit 44; when the first and third ends of the third switch 431 are connected, the first PMOS transistor 42 is connected to the control element 432.

[0082] The third switch 431 is a single-pole double-throw switch, which allows the control element 432 to control whether the first PMOS transistor 42 is connected to the current mirror unit 44.

[0083] The control element 432 includes, but is not limited to, digital algorithm modules, eFuse (electronic fuse), OTP (one-time programmable), and MTP (multiple-time programmable) methods.

[0084] In a preferred embodiment of this application, the current mirror unit 44 includes a first NMOS transistor 441 and a second NMOS transistor 442. The drain of the first NMOS transistor 441 is connected to its gate and can be connected to the drains of multiple first PMOS transistors 42 via a compensation current control unit 43. The source of the first NMOS transistor 441 is grounded. The gate of the second NMOS transistor 442 is connected to the gate of the first NMOS transistor 441. The drain of the first NMOS transistor 441 is connected to the fixed current module 30. The source of the first NMOS transistor 441 is grounded.

[0085] The first NMOS transistor 441 is connected to the second terminal of the third switch 431, and the first NMOS transistor 441 is connected to the drain of at least one first PMOS transistor 42; the drain of the second NMOS transistor 442 is connected to the second switch 33.

[0086] In some embodiments, the dynamic current cancellation module 40 includes a second diode 45, the anode of which is connected to the current mirror reference generation unit 41, and the cathode of which is connected to the current mirror unit 44.

[0087] Specifically, the anode of the second diode 45 is connected to the cathode of the first diode 413, and the cathode of the second diode 45 is connected to the drain of the second NMOS transistor 442.

[0088] The following is a specific implementation of an embodiment of the present invention:

[0089] like Figure 3As shown, PMOS transistors PM1 (second PMOS transistor 411), PM2 (first PMOS transistor 42), PM3 (first PMOS transistor 42), and PM4 (first PMOS transistor 42) form a current mirror unit 44, enabling PMOS transistors PM2, PM3, and PM4 to replicate the current of PMOS transistor PM1. PMOS transistor PM1, resistor R1, and diode D1 (first diode 413) constitute a current mirror reference generation unit 41, used to generate a dynamic reference current. NMOS transistors NM1 (first NMOS transistor 441) and NMOS transistor NM2 (second NMOS transistor 442) form the current mirror unit 44, enabling NMOS transistor NM2 to replicate the current of NMOS transistor NM1. Cell (control element 432), switch K3 (third switch 431), switch K4 (third switch 431), etc. constitute the compensation current control unit 43, which can adjust the current flowing into NM1 tube according to the different resistor R2; current source I1 (first current source 31) and current source I2 (second current source 34), switch K1 (first switch 32), switch K2 (second switch 33) constitute the fixed current module 30, which is used to generate a fixed charging and discharging current for capacitor 10; resistor R2 and capacitor 10 are external application devices of the chip.

[0090] The dynamic current cancellation module 40 consists of PMOS transistors PM1, PM2, PM3, and PM4, NMOS transistors NM1 and NM2, resistors R1 and R2, diodes D1 and D2 (second diode 45), and switches K3 and K4. The charging current of the dynamic current cancellation module 40 to the LIN bus during the LIN bus transition from high to low or from low to high is:

[0091]

[0092] Among them, V D1 V is the voltage drop across diode D1. GSI This represents the gate-source voltage difference of PMOS transistor PM1.

[0093] The discharge current of the dynamic current cancellation module 40 to the LIN bus is:

[0094]

[0095] Where M is the ratio of the number of PMOS transistors PM2, PM3, and PM4 to the number of PM1 transistor, which is also the ratio of the number of the first PMOS transistor 42 to the number of the second PMOS transistor 411, and N is the ratio of the number of MOS transistors NM2 to the number of NMOS transistors NM1.

[0096] Ultimately, this is achieved dynamically by controlling the number of closed switches such as K3 and K4 through the Control Cell:

[0097] i charge =I discharge

[0098] That is, the dynamic current cancellation module 40 dynamically cancels the charging and discharging of the LIN node.

[0099] Among them, current source I1, current source I2 and switch K1, switch K2 form a fixed current module 30. Since the dynamic current cancellation module 40 completely or approximately cancels the dynamic current of the LIN node, the charging current of capacitor 10 is now a fixed current I1, and the discharging current of capacitor 10 is I2. Therefore, the rising and falling slopes of the LIN bus are fixed, that is, di / dt = 0 or approximately zero, and the magnitude of the rising and falling slopes of LIN can be controlled by adjusting the magnitude of current I1 and current I2.

[0100] The transmitter circuit structure of this invention features a small size, simple circuit structure, high integration, and high reliability.

[0101] The transmitter circuit structure of the present invention uses a dynamic current cancellation module 40 to cancel the dynamic current during the rise and fall of the LIN bus, and then gives the charging and discharging current of the capacitor 10 a fixed value, thereby realizing that the current during the rise or fall of the LIN bus is a fixed value or approximately a fixed value, and finally the di / dt (current change with time) is zero or approximately zero.

[0102] The present invention also provides a transceiver, characterized in that it includes any of the transmitter circuit structures described above.

[0103] The transceiver also includes a receiver circuit to receive signals.

[0104] In this specification, the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the product embodiments described later, since they correspond to the methods, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions in the system embodiments.

[0105] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A transmitter circuit structure, comprising a capacitor and a first resistor connected to the capacitor, characterized in that, The transmitter circuit structure also includes: A fixed current module, one end of which is connected to a first resistor and the other end is grounded, is used to provide a fixed current to the capacitor; A dynamic current cancellation module is connected to the first resistor and the fixed current module respectively, and is used to cancel the dynamic current of the LIN node. The fixed current module includes: A first current source, the input terminal of which is connected to the first resistor; A first switch, the first end of which is connected to the output end of the first current source, and the second end of which is connected to the capacitor through the dynamic current cancellation module; The second switch, the first end of which is connected to the dynamic current cancellation module; The second current source has its input terminal connected to the second terminal of the second switch and its output terminal connected to the capacitor. The dynamic current cancellation module includes: A current mirror reference generation unit, wherein the first end of the current mirror reference generation unit is connected to the first resistor; Multiple first PMOS transistors are connected to the current mirror reference generation unit to replicate the dynamic reference current generated by the current mirror reference generation unit. A compensation current control unit, wherein the compensation current control unit is connected to the plurality of first PMOS transistors respectively; A current mirror unit, wherein the first end of the current mirror unit is connected to the compensation current control unit and the first PMOS transistor respectively, and the second end of the current mirror unit is connected to the fixed current module; The compensation current control unit can control the connection or disconnection between the first PMOS transistor and the first end of the current mirror unit. The dynamic current cancellation module is used to cancel the dynamic current of the LIN node so that the current in the transmitter circuit structure remains essentially unchanged over time.

2. The transmitter circuit structure according to claim 1, characterized in that, The current mirror reference generation unit includes: The second PMOS transistor has its gate connected to the gates of the plurality of first PMOS transistors and the drain of the second PMOS transistor, and its source connected to the sources of the plurality of first PMOS transistors and the first resistor. The second resistor has its input terminal connected to the drain of the second PMOS transistor and its output terminal connected to the fixed current module. The first diode has its anode connected to the output terminal of the second resistor, and its cathode connected to the capacitor.

3. The transmitter circuit structure according to claim 2, characterized in that, The cathode of the first diode is connected to the LIN node.

4. The transmitter circuit structure according to claim 1, characterized in that, The compensation current control unit includes: Multiple third switches, the first terminals of which are connected to the drains of the multiple first PMOS transistors, and the second terminals of which are connected to the first terminals of the current mirror unit; A control element, wherein the control element is connected to the third terminal of the plurality of third switches respectively.

5. The transmitter circuit structure according to claim 4, characterized in that, The third switch is a single-pole double-throw switch.

6. The transmitter circuit structure according to claim 1, characterized in that, The current mirror unit includes: The first NMOS transistor has its drain connected to its gate, and its drain can be connected to the drains of the plurality of first PMOS transistors through the compensation current control unit. The source of the first NMOS transistor is grounded. The second NMOS transistor has its gate connected to the gate of the first NMOS transistor, the drain of the first NMOS transistor is connected to the fixed current module, and the source of the first NMOS transistor is grounded.

7. The transmitter circuit structure according to claim 1, characterized in that, The dynamic current cancellation module includes: The second diode has its anode connected to the current mirror reference generation unit and its cathode connected to the current mirror unit.

8. A transceiver, characterized in that, Includes the transmitter circuit structure as described in any one of claims 1 to 7.

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