A method for synthesizing phased array transposed cascaded digital beams

Abstract

The application provides a phased array transposed cascade digital beam synthesis method, belonging to the technical field of digital beam forming (DBF), and solves the problem of increased hardware resource consumption caused by large array scale; the method comprises the following steps: constructing a transposed cascade architecture, setting a data connection interface on a board card of the transposed cascade architecture, and connecting the inter-subarray beam synthesis signals corresponding to each board card through the data connection interface; presetting a data buffer area with a certain depth in the board card, and synchronizing the inter-board data of each board card using a synchronization signal, and then performing beam synthesis or array element synthesis operation; for a receiving signal, a first board card connects the signal data to a second board card through the data connection interface for synthesis; for a transmitting signal, a second board card connects the signal data to a first board card through the data connection interface for synthesis; the application successfully reduces the demand for secondary board cards, optimizes hardware resources, and has good flexibility.

Description

Technical Field

[0001] This invention belongs to the field of digital beamforming (DBF) technology, specifically a method for synthesizing phased array transposed cascaded digital beams. Background Technology

[0002] Beamforming is an important branch of array signal processing. By forming directional beams, it attenuates signals arriving from other directions while receiving signals from a specific direction. The principle of beamforming is as follows: for the received signal, multiple array elements are delayed according to their beam directions, compensated until the wavefronts are aligned, and then summed.

[0003] When the array size is small, the number of array elements is small, and the hardware resource requirements for signal synthesis are low. Beamforming can be completed in one synthesis. However, as the array size increases and the number of array elements increases, single-level hardware resources can no longer meet the needs of multi-element synthesis. In this case, a hierarchical synthesis processing architecture can be adopted. Taking a 256-element array as an example, the existing synthesis scheme is as follows: each 16 array elements are treated as a subarray. First, the signals of each subarray are synthesized, which is called primary synthesis. Then, the subarray-level signals are synthesized a second time, which is called secondary synthesis. The signal after secondary synthesis is the final beamforming signal.

[0004] However, the above solution is only applicable to arrays with a scale of hundreds or at most thousands of array elements that require multi-beam synthesis. When the number of array elements increases to tens of thousands, the number of primary boards increases dramatically, the number of signals that the secondary boards need to carry increases, hardware resources are consumed, system wiring becomes complex, and portability is poor. Therefore, it is necessary to improve the digital beam synthesis method to solve these problems caused by the dramatic increase in the number of array elements. Summary of the Invention

[0005] The purpose of this invention is to solve the problems of increased hardware resource consumption and complex wiring caused by the large array size of existing digital beamforming methods. Therefore, a transposed cascaded phased array digital beamforming method is proposed. This invention performs data transmission between chips through a transposed cascaded data interface, and simultaneously uses a synchronization signal and a preset data buffer to achieve data synchronization between chips, and performs inter-chip beamforming on the synchronized data. Compared with existing beamforming methods, this invention successfully reduces the number of secondary boards required, optimizes hardware resources, and has good flexibility.

[0006] The present invention employs the following technical solutions to achieve its objective:

[0007] A method for synthesizing phased array transposed cascaded digital beams, the method comprising the following steps:

[0008] S1. Construct a transposed cascaded phased array architecture, and set up a data connection interface for transposed cascade on each board of the transposed cascaded architecture.

[0009] S2. A data cache area is preset in each board;

[0010] S3. Use synchronization signals to perform inter-chip data synchronization for each board in the transposed cascaded architecture;

[0011] S4. After completing the inter-chip data synchronization, perform beamforming or array element combining operations; beamforming is performed during the signal data reception and processing stage, and array element combining is performed during the signal data transmission and processing stage.

[0012] Furthermore, in step S1, each board in the transposed cascade architecture serially connects its corresponding inter-array beamforming signals through a data connection interface; for received signals, the first board connects the signal data to the second board through a data connection interface for synthesis; for transmitted signals, the second board connects the signal data to the first board through a data connection interface for synthesis.

[0013] Specifically, the data connection interface in each board includes: a receive beam data input port, a receive data beam output port, a transmit beam data input port, and a transmit beam data output port.

[0014] In summary, due to the adoption of this technical solution, the beneficial effects of this invention are as follows:

[0015] This invention successfully solves the problems of increased hardware resources and complex system routing caused by the large array size in existing methods; the transposed cascaded beamforming technology of this invention adopts a serial routing method, which simplifies the corresponding hardware structure and reduces the complexity of interconnection.

[0016] When dealing with large array sizes, the method of this invention reduces the number of secondary boards required compared to existing digital beamforming technologies, thus successfully optimizing hardware resources. In the method of this invention, the number of cascaded chips can be expanded or reduced as needed, achieving excellent flexibility. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the overall process of the method of the present invention;

[0018] Figure 2 This is a schematic diagram illustrating the connection principle of the transposed cascade architecture in this invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0020] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0021] Example

[0022] like Figure 1 As shown, a method for synthesizing phased array transposed cascaded digital beams can be summarized as follows:

[0023] S1. Construct a transposed cascaded phased array architecture, and set up a data connection interface for transposed cascade on each board of the transposed cascaded architecture.

[0024] S2. A data cache area is preset in each board;

[0025] S3. Use synchronization signals to perform inter-chip data synchronization for each board in the transposed cascaded architecture;

[0026] S4. After completing the inter-chip data synchronization, perform beamforming or array element combining operations; beamforming is performed during the signal data reception and processing stage, and array element combining is performed during the signal data transmission and processing stage.

[0027] This embodiment describes the details of each step in the order of method execution.

[0028] First, in step S1, each board in the transposed cascaded architecture serially connects its corresponding inter-array beamforming signals via a data connection interface. For received signals, the first board connects the signal data to the second board via the data connection interface for beamforming. For transmitted signals, the second board connects the signal data to the first board via the data connection interface for beamforming. The data flow between the first and second boards can be viewed synchronously. Figure 2 The illustration.

[0029] In this embodiment, as Figure 2As shown, each board includes the following data connection interfaces: receive beam data input port, receive beam data output port, transmit beam data input port, and transmit beam data output port; each interface corresponds to the data input or output of that interface.

[0030] This embodiment uses two subarrays as an example, applying the transposed cascaded architecture to the two subarrays, which correspond to the first board and the second board, respectively. For received signals, the first board transmits the signal data from its receive beam data input port to the receive beam data input port of the second board through its receive data beam output port, thereby completing the synthesis of the received signal within the second board. For transmitted signals, the second board transmits the signal data from its transmit beam data input port to the transmit beam data input port of the first board through its transmit beam data output port, thereby completing the synthesis of the transmitted signal within the first board.

[0031] In step S2, a data buffer with a preset depth is set in each board to buffer signal data that has not been synchronized or synthesized. The depth of the data buffer is preset according to the inter-board data delay. When the inter-board data delay is greater, the corresponding data buffer depth is preset to be deeper.

[0032] In step S3, the synchronization signal includes a transmit beam synchronization signal and a receive beam synchronization signal; the transmit beam synchronization signal is sent uniformly from the outside and arrives at each board simultaneously. In this embodiment, the time delay error here is preferably no more than 1ms.

[0033] The received beam synchronization signal is sent to the board along with the array element received signal. After being processed by the digital beamforming of the current board to form beam data, it is sent to the next board connected to it along with the beam data.

[0034] In step S4, beamforming combines the received array data into beam data; array element combining combines the beam data to be transmitted into array data. The following is a detailed processing procedure for each corresponding stage.

[0035] In the signal data reception and processing stage, with Figure 2 Taking the two boards shown as an example, the first board and the second board respectively perform weighted synthesis on the received array data to form first beam data located in the first board and second beam data located in the second board. The second beam data is sent to a preset data buffer in the second board, and the initial address of the second beam data in the data buffer is recorded. The first beam data and the synchronization signal are sent to the second board through the data connection interface. After the second board detects the synchronization signal, it retrieves the second beam data according to the recorded initial address and adds it to the received first beam data to complete the inter-board beam synthesis process.

[0036] As a preferred embodiment, for possible expansions during the actual beamforming process, if the second board is also connected to a third board through a data connection interface, the third board is used as the new second board, and the original second board is used as the new first board. Based on the beamforming method between the first board and the second board, a new round of inter-board beamforming process is continued. Through the cycle of the inter-board beamforming process, until each board in the transposed cascaded architecture has completed the beamforming process, the last board outputs the beamforming data result.

[0037] In the signal data transmission processing stage, the overall process is the reverse of the reception processing stage. The last board of the transposed cascade architecture forwards the beam data to be transmitted step by step through the data connection interface until the first board of the transposed cascade architecture receives the beam data to be transmitted. When each board receives the beam data to be transmitted currently sent to it, it stores it in its own data buffer and records its initial address in the data buffer. When all boards receive the synchronization signal from the outside at the same time, they retrieve the data from their respective data buffers in sequence according to the recorded initial address, perform weighted synthesis of array data, form array data for transmission, and transmit it to the outside.

Claims

1. A method for synthesizing phased array transposed cascaded digital beams, characterized in that, The synthesis method includes the following steps: S1. Construct a transposed cascaded phased array architecture, and set up a data connection interface for transposed cascade on each board of the transposed cascaded architecture. S2. A data cache area is preset in each board; S3. Use synchronization signals to perform inter-chip data synchronization for each board in the transposed cascaded architecture; S4. After completing the inter-chip data synchronization, perform beamforming or array element combining operations; beamforming is performed during the signal data reception and processing stage, and array element combining is performed during the signal data transmission and processing stage. In step S1, each board in the transposed cascade architecture serially connects its corresponding inter-array beamforming signals through a data connection interface; for received signals, the first board connects the signal data to the second board through a data connection interface for combining; for transmitted signals, the second board connects the signal data to the first board through a data connection interface for combining.

2. The method for synthesizing a phased array transposed cascaded digital beam according to claim 1, characterized in that: The data connection interface in each board includes: a receive beam data input port, a receive data beam output port, a transmit beam data input port, and a transmit beam data output port.

3. The method for synthesizing phased array transposed cascaded digital beams according to claim 2, characterized in that: The transposed cascaded architecture is applied to two subarrays, corresponding to the first board and the second board, respectively. For received signals, the first board transmits the signal data from its receive beam data input port to the receive beam data input port of the second board through its receive data beam output port, thereby completing the synthesis of the received signal within the second board. For transmitted signals, the second board transmits the signal data from its transmit beam data input port to the transmit beam data input port of the first board through its transmit beam data output port, thereby completing the synthesis of the transmitted signal within the first board.

4. The method for synthesizing a phased array transposed cascaded digital beam according to claim 1, characterized in that: In step S2, a data buffer area with depth is preset in each board to buffer signal data that has not been synchronized or synthesized. The depth of the data buffer is preset based on the inter-chip data latency of the board. The greater the inter-chip data latency, the deeper the corresponding data buffer is preset.

5. The method for synthesizing a phased array transposed cascaded digital beam according to claim 1, characterized in that: In step S3, the synchronization signal includes a transmit beam synchronization signal and a receive beam synchronization signal. The transmit beam synchronization signal is sent uniformly from the outside and arrives at each board simultaneously, with a time delay error of no more than 1ms. The receive beam synchronization signal is sent into the board along with the array element receive signal. After being processed by the digital beamforming of the current board to form beam data, it is sent into the next board connected to it along with the beam data.

6. The method for synthesizing a phased array transposed cascaded digital beam according to claim 1, characterized in that: In step S4, beamforming combines the received array data into beam data; array element combining combines the beam data to be transmitted into array data.

7. The method for synthesizing phased array transposed cascaded digital beams according to claim 6, characterized in that: During the signal data reception and processing stage, the first board and the second board respectively perform weighted synthesis on the received array data to form the first beam data located in the first board and the second beam data located in the second board; the second beam data is sent into the preset data buffer in the second board, and the initial address of the second beam data in the data buffer is recorded. The first beam data and the synchronization signal are sent to the second board through the data connection interface. After the second board detects the synchronization signal, it retrieves the second beam data according to the recorded initial address and adds it to the received first beam data to complete the inter-chip beamforming process.

8. The method for synthesizing phased array transposed cascaded digital beams according to claim 7, characterized in that: When the second board is also connected to the third board through the data connection interface, the third board is used as the new second board, and the original second board is used as the new first board. Based on the beamforming method between the first board and the second board, a new round of inter-board beamforming process continues. The beamforming process is repeated until each board in the transposed cascaded architecture has completed the beamforming process, and the last board outputs the beamforming data result.

9. The method for synthesizing a phased array transposed cascaded digital beam according to claim 6, characterized in that: During the signal data transmission and processing stage, the last board of the transposed cascade architecture forwards the beam data to be transmitted step by step through the data connection interface until the first board of the transposed cascade architecture receives the beam data to be transmitted. When each board receives the beam data to be transmitted, it stores it in its own data buffer and records its initial address in the data buffer. When all boards receive the synchronization signal from the outside at the same time, they retrieve the data from their respective data buffers in sequence according to the recorded initial address, perform weighted synthesis of array data, form array data for transmission, and transmit it to the outside.

Images