Semiconductor structure and method of manufacturing a semiconductor structure

Abstract

Embodiments of the present disclosure relate to a semiconductor structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes a plurality of word lines and a plurality of bit lines, the extension direction of the word lines is different from the extension direction of the bit lines; a stepped structure, the stepped structure includes a plurality of steps, each step includes at least a first part and a second part, the first part extends along a first direction, the second part extends along a second direction, the first direction is different from the second direction; and a plurality of electrical contact structures, the electrical contact structures cover the top surface of the steps of the first part and the second part, and the electrical contact structures are in contact with the word lines or the bit lines. Embodiments of the present disclosure are beneficial to reduce the arrangement difficulty of the lead in the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the semiconductor structure. Background Technology

[0002] As the integration density of dynamic memory continues to increase, higher requirements are being placed on the arrangement of transistors in the dynamic memory array structure.

[0003] To further improve the integration density of semiconductor structures, three-dimensional semiconductor structures are being researched. A three-dimensional semiconductor structure refers to a three-dimensional stacked semiconductor structure, where the transistors are arranged in a stacked configuration. Three-dimensional stacked semiconductor structures are characterized by high density, large capacity, and high speed.

[0004] However, for three-dimensional semiconductor structures, how to design the interconnection of each functional device to reduce the difficulty of lead arrangement in the semiconductor structure is an urgent problem to be solved. Summary of the Invention

[0005] This disclosure provides a semiconductor structure and a method for fabricating the semiconductor structure, which at least helps to reduce the difficulty of arranging leads in the semiconductor structure.

[0006] This disclosure provides a semiconductor structure including: multiple word lines and multiple bit lines, wherein the extension directions of the word lines are different from the extension directions of the bit lines; a stepped structure including multiple steps, each step including at least a first portion and a second portion that are in contact, the first portion extending along a first direction and the second portion extending along a second direction, wherein the first direction and the second direction are different; and multiple electrical contact structures covering the top surface of the steps of the first portion and the second portion, wherein the electrical contact structures are in contact with the word lines or the bit lines.

[0007] Accordingly, this disclosure also provides a method for fabricating a semiconductor structure, comprising: forming a plurality of word lines and a plurality of bit lines, wherein the extension direction of the word lines is different from the extension direction of the bit lines; forming a stepped structure, wherein the stepped structure includes multiple steps, wherein each step includes at least a first part and a second part that are in contact, the first part extending along a first direction and the second part extending along a second direction, wherein the first direction is different from the second direction; and forming a plurality of electrical contact structures, wherein the electrical contact structures cover the top surface of the steps of the first part and the second part, and the electrical contact structures are in contact with the word lines or bit lines.

[0008] The technical solutions provided in this disclosure have at least the following advantages:

[0009] In the semiconductor structure technical solution provided in this disclosure, each step in the stepped structure includes at least a first part and a second part that are connected, and the extension directions of the first part and the second part are different. Thus, when the electrical contact structure covers the top surface of the first and second parts of the step, the electrical contact structure located on the step surface also extends in two different directions. This is equivalent to forming at least two sets of electrical contact structures with different directions in one stepped structure, increasing the flexibility of connecting the electrical contact structure to word lines or bit lines. Furthermore, the electrical contact structure can be led out in different directions, increasing the ways to arrange the leads, thereby reducing the difficulty of lead arrangement and reducing parasitic capacitance. Attached Figure Description

[0010] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a top view of a partial structure of a semiconductor structure provided in an embodiment of the present disclosure;

[0012] Figure 2 for Figure 1 A schematic diagram of a cross-sectional view of section aa';

[0013] Figure 3 A partial top view of another semiconductor structure provided in an embodiment of this disclosure;

[0014] Figure 4 A partial top view of another semiconductor structure provided in an embodiment of the present disclosure;

[0015] Figure 5 for Figure 4 A schematic diagram of a cross-sectional view of section aa';

[0016] Figure 6 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0017] Figure 7 This is a top view schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure;

[0018] Figures 8 to 22A schematic diagram of the structure corresponding to each step in the method for preparing a semiconductor structure according to another embodiment of this disclosure;

[0019] Figure 23 A schematic diagram of a sub-step structure formed in a method for fabricating a semiconductor structure according to another embodiment of this disclosure;

[0020] Figure 24 This is a schematic diagram of another structure corresponding to the sub-step structure formed in the preparation method of a semiconductor structure provided in another embodiment of the present disclosure;

[0021] Figure 25 This is another schematic diagram of a sub-step structure formed in a method for preparing a semiconductor structure according to another embodiment of the present disclosure. Detailed Implementation

[0022] As the background technology shows, how to reduce the difficulty of lead arrangement in semiconductor structures is an urgent problem to be solved.

[0023] This disclosure provides a semiconductor structure with a stepped structure. Each step includes at least a first part and a second part that are connected. The first part extends in a first direction, and the second part extends in a second direction, with the first and second directions being different. Thus, the electrical contact structures disposed on the top surfaces of the steps in the first and second parts also extend in two different directions, effectively forming two sets of steps in different directions within a single stepped structure. Therefore, word lines or bit lines can be made in contact with the stepped structure in at least two directions, enabling signal transmission between external circuits and word lines or bit lines. In other words, this increases the number of lead arrangement methods and reduces the difficulty of lead arrangement. Furthermore, since the electrical contact structures can be led out from different directions, the spacing between the leads is larger, thereby reducing parasitic capacitance.

[0024] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0025] Figure 1 This is a top view of a partial structure of a semiconductor structure provided in an embodiment of the present disclosure; Figure 2 for Figure 1 A schematic diagram of a cross-sectional view of section aa'; Figure 3 A partial top view of another semiconductor structure provided in an embodiment of this disclosure; Figure 4This is a partial top view of another semiconductor structure provided in an embodiment of the present disclosure.

[0026] refer to Figures 1 to 4 The semiconductor structure includes: multiple word lines and multiple bit lines, wherein the extension direction of the word lines is different from that of the bit lines; a step structure 1, which includes multiple steps 101, each step 101 including at least a first part and a second part that are in contact, the first part extending along a first direction X and the second part extending along a second direction Y, wherein the first direction X and the second direction Y are different; and multiple electrical contact structures 102, which cover the top surface of the steps 101 of the first part and the second part, and the electrical contact structures 102 are in contact with the word lines or bit lines.

[0027] Since the steps 101 extend in different directions, when the electrical contact structure 102 is located on the top surface of the steps 101 in the first and second parts, the electrical contact structure 102 also extends in the first direction X or the second direction Y, thus extending in two different directions. This is equivalent to forming at least two sets of steps in the stepped structure 1, allowing word lines or bit lines to contact the electrical contact structure 102 in the first direction X or the second direction Y to transmit signals with external circuits. In other words, by setting the steps 101 to extend in different directions, the electrical contact structure 102 can be led out in different directions, thereby increasing the ways to lead out the wires and reducing the difficulty of wire arrangement.

[0028] Step 101 can serve as a load-bearing structure for electrical contact structure 102. The previous step 101 is located on part of the top surface of the current step 101. Specifically, multiple steps 101 are stacked vertically. Specifically, the top step 101 is the first step 101, the bottom step 101 is the Nth step 101, N is greater than 1, the nth step 101 overlaps with part of the (n+1)th step 101, and 1≤n≤N.

[0029] In some embodiments, assuming that step 101 includes a middle region 20 and a first side region 21 and a second side region 22 located on both sides of the middle region 20, then the nth step 101 covers the top surface of the first side region 21 of the (n+1)th step 101 and the top surface of the middle region 20, exposing the top surface of the second side region 22 of the (n+1)th step 101, and the end face of the first side region 21 away from the middle region 20 in each step 101 is flush. Since the top surface of the second side region 22 of each step 101 is not covered by another step 101, when the electrical contact structure 102 is located on the top surface of the first part and the second part of the step 101, the electrical contact structure 102 on the top surface of the second side region 22 of each step 101 can be led out, so that each contact structure will not contact each other, preventing the problem of electrical interference.

[0030] In some embodiments, the material of step 101 may include a dielectric material, such as silicon oxide.

[0031] In some embodiments, the electrical contact structure 102 includes: a contact layer 111 covering a portion of the top surface of the step 101; and a connecting post 112 in contact with the contact layer 111. The top surfaces of the connecting posts 112 corresponding to the plurality of steps 101 are flush, and the stepped structure 1 exposes the end face of the contact layer 111 away from the connecting post 112, with the exposed end face contacting either a bit line or a word line. In some embodiments, the connecting post 112 may be perpendicular to the contact layer 111; in other embodiments, the connecting post 112 may not be perpendicular to the contact layer 111, for example, the angle between the connecting post 112 and the top surface of the contact layer 111 may be acute or obtuse, i.e., the connecting post 112 is inclined relative to the contact layer 111. It is understood that the positional relationship between the connecting post 112 and the contact layer can be selected according to the actual manufacturing process. Specifically, in some embodiments, the materials of the contact layer 111 and the connecting post 112 can be metals, such as at least one of tantalum, tungsten, titanium, copper, aluminum, silver, and gold; in other embodiments, the material of the contact layer 111 can also be polycrystalline silicon or at least one of doped silicon, doped germanium, titanium nitride, tantalum nitride, tungsten silicide, cobalt silicide, or titanium silicide.

[0032] Specifically, the contact layer 111 covers the top surface of the step 101 of the first side region 21, the middle region 20, and a portion of the second side region 22, with the contact layer 111 exposing the portion of the top surface of the step 101 in the second side region 22 that is away from the middle region 20. Since the top surface of the step 101 in the second side region 22 is not covered by the previous step 101, the contact layer 111 is positioned on the top surface of the step 101 in a portion of the second side region 22, facilitating contact between the connecting post 112 and the top surface of the contact layer 111 to extract the signal from the contact layer 111.

[0033] The stepped structure 1 exposes the end face of the contact layer 111 away from the connecting post 112. Specifically, the stepped structure 1 exposes one end face of the contact layer 111 located in the first side region 21, and the exposed end face portion of the contact layer 111 contacts the word line or bit line. In other words, one end of the contact layer 111 contacts the word line or bit line, making the contact layer 111 electrically connected to the word line or bit line, and the other end of the contact layer 111 contacts the connecting post 112, through which the electrical signal of the contact layer 111 is led out, thereby realizing the signal transmission between the word line or bit line and the external circuit.

[0034] Electrical contact structures 102 are disposed on the top surface of each step 101. Therefore, contact layers 111 are located on the top surface of each step 101, and each contact layer 111 contacts a connecting post 112. That is, each step 101 corresponds to a connecting post 112. The connecting post 112 is set perpendicular to the contact layer 111, i.e., the connecting post 112 is perpendicular to the top surface of the step 101, while the contact layer 111 is parallel to the top surface of the step 101. This allows the electrical contact structure 102 to lead out the electrical signals of word lines or bit lines in the horizontal direction, and to lead out the electrical signals of the contact layer 111 to the external circuit in the vertical direction. Setting the top surface of each connecting post 112 to be flush facilitates the batch fabrication of multiple leads, allowing the leads to contact the connecting post 112 and lead out the electrical signals of the connecting post 112. In addition, since the top surface of each connecting post 112 is flush, it also helps to reduce the difficulty of lead arrangement.

[0035] It is understood that the contact layer 111 is located on the top surface of the step 101 of the first part and the second part, and the connecting post 112 is correspondingly provided with the contact layer 111, that is, the connecting post 112 is located on the top surface of the step 101 of the first part and the second part.

[0036] In some embodiments, the system further includes a plurality of lead-out structures 103, which are electrically connected to the top surface of the connecting post 112. Specifically, the lead-out structure 103 contacts the top surface of the connecting post 112, thereby achieving an electrical connection between the lead-out structure 103 and the connecting post 112. Specifically, in some embodiments, the electrical contact structure 102 contacts the word line. For example, the contact layer 111 located on the top surface of the first part of the step 101 contacts the word line. Since the contact layer 111 on the top surface of the first part of the step 101 is in contact with the contact layer 111 on the top surface of the second part of the step 101, the connecting post 112 corresponding to the first part of the step 101 can be connected to the lead-out structure 103, or the connecting post 112 corresponding to the second part of the step 101 can be connected to the lead-out structure 103, thereby achieving the lead-out of the electrical signal of the word line. Therefore, it can be seen that the lead-out structure 103 can be connected to the connecting post 112 in different directions. This greatly improves the flexibility of the lead-out structure 103 in transmitting signals between word lines or bit lines and external circuits, thereby reducing the difficulty of arranging the lead-out structure 103. Furthermore, since the lead-out structure 103 can be arranged in different directions, the spacing between the lead-out structures 103 can be larger, thereby reducing parasitic capacitance.

[0037] In some embodiments, the angle between the first direction X and the second direction Y can be 90°, or close to 90°, such as 80°, 85°, 95°, or 100°. This ensures that, on the one hand, the angle between the first direction X and the second direction Y is not too small. Therefore, when the lead-out structure 103 is designed to lead the electrical contact structure 102 out from the first direction X or the second direction Y, the larger angle between the first direction X and the second direction Y results in a larger distance between the first portion of the electrical contact structure 102 and the second portion of the electrical contact structure 102. This, in turn, allows for a larger distance between the lead-out structure 103 corresponding to the first portion and the lead-out structure 103 corresponding to the second portion, thereby reducing parasitic capacitance. On the other hand, it prevents the angle between the first direction X and the second direction Y from being too large, thus preventing the overall size of the stepped structure 1 from becoming too large due to an excessively large distance between the first and second portions, and consequently reducing the overall size of the stepped structure 1.

[0038] It is understood that in other embodiments, the angle between the first direction X and the second direction Y may be less than 90° or greater than 90°.

[0039] In some embodiments, the system further includes an isolation structure 104 located between adjacent electrical contact structures 102 for isolating adjacent electrical contact structures 102. Specifically, in some embodiments, the electrical contact structure 102 includes a contact layer 111 and connecting posts 112. The contact layer 111 is located on the top surface of each step 101, such that each step 101 isolates the contact layer 111. To isolate adjacent connecting posts 112, the isolation structure 104 can be located between adjacent connecting posts 112 to prevent electrical interference between adjacent connecting posts 112. In some embodiments, the material of the isolation structure 104 can be a dielectric material, such as silicon oxide.

[0040] In some embodiments, the electrical contact structure 102 is exposed above the top surface of the end of the step 101, and the isolation structure 104 is located on the top surface of the exposed portion of the step 101. That is, the step 101 also serves to support the isolation structure 104, and the isolation structure 104 is located on one side of the electrical contact structure 102, allowing the isolation structure 104 to effectively isolate the electrical contact structure 102. Specifically, in some embodiments, the contact layer 111 is exposed above the top surface of the step 101 in a portion of the second side region 22, and the isolation structure 104 is located on the top surface of the step 101 in a portion of the second side region 22. One side of the isolation structure 104 is connected to the end face of the contact layer 111, and the other side of the isolation structure 104 is flush with the end face of the step 101. Since the connecting post 112 is located on the top surface of the contact layer 111 corresponding to the step 101 in the remaining portion of the first side region 21, and one side of the connecting post 112 is flush with the end face of the step 101, and the other side of the connecting post 112 is flush with the end face of the contact layer 111. Therefore, one side of the isolation structure 104 is connected to the end face of the contact layer 111, and the other side of the isolation structure 104 is flush with the end face of the step 101, so that the isolation structure 104 can be tightly connected to the side of the connecting column 112 located on the top surface of the contact layer 111, thereby giving the isolation structure 104 a good isolation effect on the connecting columns 112 on both sides.

[0041] In some embodiments, at least a portion of the step 101 further includes a third portion connected to the second portion, the third portion extending along a third direction different from the second direction Y, and the electrical contact structure 102 also covering the top surface of the step 101 of the third portion. That is, the step 101 of the third portion and the electrical contact structure 102 located on the top surface of the step 101 of the third portion can also serve as a set of steps, thereby allowing the lead-out structure 103 to lead out the electrical contact structure 102 in three different orientations. Specifically, in some embodiments, when the electrical contact structure 102 of the first part contacts the word line, that is, when the contact layer 111 of the first part contacts the word line, a portion of the lead-out structure 103 can be connected to the connecting post 112 of the first part, thereby leading out the word line signal in the first direction X. A portion of the lead-out structure 103 can also be connected to the electrical contact structure 102 of the second part, thereby leading out the word line signal in the second direction Y. The remaining portion of the lead-out structure 103 can also be connected to the electrical contact structure 102 of the third part, thereby leading out the word line signal in the third direction, further improving the placement flexibility of the lead-out structure 103. It is understood that regardless of which of the first, second, or third part's electrical contact structures 102 the lead-out structure 103 is connected to, each lead-out structure 103 corresponds to a step 101, that is, each lead-out structure 103 is connected to the electrical contact structure 102 located on the top surface of a step 101, thereby leading out the electrical signal of the word line corresponding to each step 101.

[0042] It is understood that in other embodiments, the second part of the electrical contact structure 102 may be configured to contact the word line or the bit line, or the third part of the electrical contact structure 102 may be configured to contact the word line or the bit line.

[0043] In some embodiments, the third direction is parallel to the first direction X. Setting the third direction parallel to the first direction X ensures that the relative distance between the third part and the first part is equal at every point, resulting in a larger distance between the third part and the first part. This prevents the problem of large parasitic capacitance caused by an excessively small distance between the lead-out structures 103 corresponding to the third part and the first part. It also prevents the lines from intersecting between the lead-out structures 103 of the third part and the first part, reducing the difficulty of arranging the lead-out structures 103. On the other hand, setting the third direction parallel to the first direction X also prevents the distance between the third part and the first part from becoming too large, thus keeping the overall size of the stepped structure 1 relatively small.

[0044] It is worth noting that in some embodiments, some steps 101 may include a third part, while the remaining steps 101 may only include the first and second parts.

[0045] refer to Figure 3 In other embodiments, each step 101 may include a third portion, with the first, second, and third portions sequentially joined to form a U-shaped step 101. This allows the signals from the electrical contact structures 102 corresponding to each step 101 to be led out from three different locations. Specifically, the lead-out structures 103 can be connected to the electrical contact structures 102 corresponding to any one of the first, second, or third portions of the step 101, further increasing the arrangement options for the lead-out structures 103. In some embodiments, each step 101 may include a third portion.

[0046] refer to Figure 4 In some embodiments, the steps 101 form a closed ring. In this way, the lead-out structure 103 can be connected to the electrical contact structure 102 in all directions, which greatly improves the arrangement flexibility of the lead-out structure 103 and greatly reduces the difficulty of arranging the lead-out structure 103 compared with the current steps 101 that extend in a single direction.

[0047] In some embodiments, the closed ring is a closed rectangle, and the step 101 includes a first part, a second part, a third part, and a fourth part connected in sequence. The third part extends along a first direction X, and the fourth part extends along a second direction Y. The electrical contact structure 102 is also located on the top surface of the step 101 corresponding to the third and fourth parts. That is, a step structure 1 is equivalent to containing four sets of steps. When the electrical contact structure 102 is connected to either a word line or a bit line, the lead-out structure 103 can be set to be connected to any one of the electrical contact structures 102 corresponding to the first, second, third, or fourth parts. The available space can be fully utilized to design the lead-out structure 103, which greatly reduces the difficulty of arranging the lead-out structure 103 while preventing electrical interference between different lead-out structures 103. Furthermore, since the lead-out structures 103 are located in different orientations, the distance between the lead-out structures 103 is greatly increased, thereby significantly improving the problem of large parasitic capacitance caused by the dense arrangement of the lead-out structures 103.

[0048] refer to Figure 6 as well as Figure 7 In some embodiments, bit lines 12 or word lines 11 are electrically connected to either the electrical contact structure 102 corresponding to the first or second portion. In some embodiments, multiple word lines 11 are spaced apart along the same direction, and multiple bit lines 12 are spaced apart along the same direction, with the bit lines 12 perpendicular to the extending direction of the word lines 11. Specifically, in some embodiments, the semiconductor structure may further include an array of semiconductor pillars, each semiconductor pillar including a channel region and source / drain regions located on both sides of the channel region. Word lines 11 may be electrically connected to each channel region in a row of semiconductor pillars, and bit lines 12 may be electrically connected to a source / drain region in a column of semiconductor pillars. In some embodiments, a gate dielectric layer may also be included, located between the word lines 11 and the semiconductor pillars of the channel region, for isolating the word lines 11 from the channel regions. The word line 11 and bit line 12 can be made of metal, such as at least one of tantalum, tungsten, titanium, copper, aluminum, silver, and gold; or they can be made of polycrystalline silicon or at least one of doped silicon, doped germanium, titanium nitride, tantalum nitride, tungsten silicide, cobalt silicide, or titanium silicide. The gate dielectric layer can be made of silicon oxide.

[0049] In the stepped structure 1, multiple steps 101 are stacked in the same direction. Therefore, the electrical contact structures 102 located on the top surface of the steps 101 are also stacked in the same direction. Based on this, each electrical contact structure 102 can be connected one-to-one with the word lines 11 arranged in the same direction, or one-to-one with the bit lines 12 arranged in the same direction.

[0050] Since the electrical contact structure 102 is located on the top surface of the steps 101 in both the first and second parts, any one of the electrical contact structures 102 corresponding to the steps 101 in either the first or second part can be connected to the word line 11 or the bit line 12. Thus, the placement of the step structure 1 can be determined based on the specific structure of the word line 11 or the bit line 12, for example, by referring to... Figure 6 as well as Figure 7 , Figure 6 as well as Figure 7 Taking the electrical connection between the stepped structure 1 and the word line as an example, the connection method between the stepped structure 1 and the word line can be flexibly set based on the placement of the word line in the semiconductor structure. For example, refer to... Figure 6 The stepped structure 1 can be electrically connected to the end of the word line 11; see reference. Figure 7 The stepped structure 1 allows it to be electrically connected to the side of the word line, thus making the placement of the stepped structure 1 more flexible. This allows for full utilization of the space in the semiconductor structure, improving space utilization and thus increasing the integration of the semiconductor structure.

[0051] It is understood that in some embodiments, when step 101 further includes a third portion, bit line 12 or word line 11 may be connected to any one of the first portion, the second portion, or the third portion.

[0052] In some other embodiments, when step 101 further includes a fourth part, bit line 12 or word line 11 can also be connected to the fourth part. This further increases the number of ways the step structure 1 can be arranged.

[0053] In the semiconductor structure provided in the above embodiments, the step 101 includes a first part and a second part, and the first part and the second part extend in different directions. Therefore, when the electrical contact structure 102 is located on the top surface of the step 101 of the first part and the second part, the electrical contact structure 102 also extends in the first direction X or the second direction Y, thereby extending in two different directions. This is equivalent to forming at least two sets of steps in the stepped structure 1, so that the word line 11 or the bit line 12 can contact the electrical contact structure 102 in the first direction X or the second direction Y to realize signal transmission with the external circuit. In other words, by setting the step 101 to extend in different directions, the electrical contact structure 102 can be led out in different directions, thereby increasing the lead-out methods and reducing the difficulty of lead arrangement.

[0054] Accordingly, this disclosure also provides a method for preparing a semiconductor structure, which can be used to prepare the semiconductor structure provided in the above embodiments. The semiconductor structure provided in an embodiment of this disclosure will be described in detail below with reference to the accompanying drawings.

[0055] Methods for fabricating semiconductor structures include:

[0056] Multiple word lines and multiple bit lines are formed, with the word lines extending in different directions than the bit lines. In some embodiments, the multiple word lines are arranged at intervals along the same direction, and the multiple bit lines are arranged at intervals along the same direction, with the bit lines perpendicular to the extension direction of the word lines.

[0057] Specifically, in some embodiments, it may further include: forming an array of semiconductor pillars, each semiconductor pillar including a channel region and source / drain regions located on both sides of the channel region. Word lines are electrically connected to each channel region in a row of semiconductor pillars, and bit lines are electrically connected to a source / drain region in a column of semiconductor pillars.

[0058] In some embodiments, the method of forming word lines may include: forming a gate dielectric layer on the surface of a semiconductor pillar in the channel region using a deposition process, wherein the material of the gate dielectric layer may be silicon oxide; forming word lines on the surface of the gate dielectric layer using a deposition process, wherein the material of the word lines may be a metal, such as at least one of tantalum, tungsten, titanium, copper, aluminum, silver, and gold, or polysilicon or at least one of doped silicon, doped germanium, titanium nitride, tantalum nitride, tungsten silicide, cobalt silicide, or titanium silicide.

[0059] In some embodiments, the method of forming a bit line may include: forming a bit line on the end face of one of the source / drain regions in a semiconductor pillar using a deposition process. The material of the bit line may be a metal, such as at least one of tantalum, tungsten, titanium, copper, aluminum, silver, and gold. The deposition process may be an atomic layer deposition process.

[0060] refer to Figures 8 to 22 This forms a stepped structure, which includes multiple steps 101. Each step 101 includes at least a first part and a second part that are connected. The first part extends along a first direction X, and the second part extends along a second direction Y. The first direction X and the second direction Y are different. The previous step 101 is located on part of the top surface of the current step 101. Specifically, the multiple steps 101 are stacked up and down along the same direction.

[0061] Multiple electrical contact structures are formed, covering the top surface of the step 101 in the first and second parts, and contacting the word line 11 or bit line 12. The step 101 can serve as a supporting structure for the electrical contact structures. When the electrical contact structures are located on the top surface of the step 101 in the first and second parts, they extend in either the first direction X or the second direction Y, thus extending in two different directions. This is equivalent to forming at least two sets of steps in the stepped structure 1, allowing the word line 11 or bit line 12 to contact the electrical contact structures in either the first direction X or the second direction Y, enabling signal transmission with external circuits. In other words, by setting the step 101 to extend in different directions, the electrical contact structures are led out in different directions, thereby increasing the lead-out methods and reducing the difficulty of lead arrangement.

[0062] In some embodiments, the exposed top surface of the step 101 of the electrical contact structure further includes: forming an isolation structure 104 on the surface of the exposed top surface of the step 101, and the isolation structure 104 is located between adjacent electrical contact structures. The step 101 also serves to support the isolation structure 104, and the isolation structure 104 is located on one side of the electrical contact structure, so that the isolation structure 104 can effectively isolate the electrical contact structure.

[0063] Specifically, in some embodiments, the method for forming the stepped structure 1 and the electrical contact structure includes:

[0064] refer to Figures 11 to 10 A substrate 100 is provided, on which sequentially stacked isolation layers 31 and initial contact layers 41 are formed. The top isolation layer 31 serves as the first isolation layer 31, and the top initial contact layer 41 serves as the first initial contact layer 41. The bottom isolation layer 31 serves as the Nth isolation layer 31, and the bottom initial contact layer 41 serves as the Nth initial contact layer 41. The isolation layers 31 and initial contact layers 41 are spaced apart. Each isolation layer 31 serves as the basis for forming the step 101, and each initial contact layer 41 can serve as a support layer, supporting the isolation layers 31. Furthermore, the initial contact layer 41 can also serve as the basis for subsequently formed contact layers.

[0065] In some embodiments, the material of the substrate 100 is silicon. In other embodiments, the substrate 100 may also be a germanium substrate 100, a germanium-silicon substrate, a silicon carbide substrate, or a silicon substrate on an insulator.

[0066] In some embodiments, when the substrate 100 is a silicon substrate and the material of the initial contact layer 41 is silicon, the method for forming the sequentially stacked isolation layer 31 and the initial contact layer 41 may include:

[0067] A first sacrificial layer and an initial contact layer 41 are sequentially formed on a substrate 100 using an epitaxial process, with the first sacrificial layer and the initial contact layer 41 spaced apart. In some embodiments, the material of the first sacrificial layer may be silicon germanide, so that the first sacrificial layer, the initial contact layer 41, and the substrate 100 have the same elemental silicon. This makes it easier to sequentially form the first sacrificial layer and the initial contact layer 41 on the top surface of the substrate 100 using an epitaxial process. The formed first sacrificial layer and the initial contact layer 41 have a clear boundary and a relatively flat morphology. After the first sacrificial layer is removed, on the one hand, the initial contact layer 41 has a flat morphology, and on the other hand, the first sacrificial layer can be removed relatively cleanly.

[0068] Next, the first sacrificial layer is removed to form a gap layer, exposing the surfaces of the two adjacent initial contact layers 41. In some embodiments, either a dry etching process or a wet etching process can be used to remove the first sacrificial layer.

[0069] An isolation layer 31 is formed in the gap layer, located between and in contact with the two initial contact layers 41. In some embodiments, the material of the isolation layer 31 can be a dielectric material, such as silicon oxide. Silicon oxide has high hardness, which allows the formed step 101 to provide good load-bearing capacity for the electrical contact structure 102. In some embodiments, the isolation layer 31 can be formed in the gap layer using a deposition process, specifically either atomic layer deposition or thermal oxidation.

[0070] refer to Figures 11 to 22 The first process is performed sequentially on the first isolation layer 31 and the first initial contact layer 41 to the Nth isolation layer 31 and the Nth initial contact layer 41. Specifically, the first process is performed on the nth isolation layer 31 and the nth initial contact layer 41 to form the nth step 101 and the corresponding electrical contact structure 102 and isolation structure 104, where 1 ≤ n ≤ N. If the nth isolation layer 31 and the nth initial contact layer 41 are considered as a group of initial structures, the same first process is performed sequentially on each group of initial structures to form the step 101 corresponding to the number of layers in each group and the corresponding electrical contact structure 102 and isolation structure 104. In this way, it is unnecessary to perform etching or other processes on the stacked multiple isolation layers 31 and initial contact layers 41 in one step. Since each first process only targets one initial contact layer 41 and one isolation layer 31, the depth-to-width ratio of the etched holes in each first process step is small, which is beneficial to improving the yield of the formed semiconductor structure.

[0071] Specifically, refer to Figure 5In some embodiments, the formed electrical contact structure 102 includes: a contact layer 111 covering the top surface of the step 101, with the upper step 101 exposing a portion of the top surface of the contact layer 111 located on the top surface of the current step 101; and a connecting post 112 contacting the exposed portion of the contact layer 111, with the connecting post 112 perpendicular to the contact layer 111. The top surface of the connecting post 112 corresponding to each step 101 is flush with the top surface of the step structure 1, and the exposed end face of the contact layer 111 away from the connecting post 112 contacts one of the bit line 12 or the word line 11. One end of the contact layer 111 contacts the word line 11 or the bit line 12, making the contact layer 111 electrically connected to the word line 11 or the bit line 12. The other end of the contact layer 111 contacts the connecting post 112, through which the electrical signal of the contact layer 111 is led out, thereby realizing signal transmission between the word line 11 or the bit line 12 and the external circuit.

[0072] refer to Figures 11 to 22 In some embodiments, the formed steps 101 form a closed ring, and the first process includes:

[0073] A connecting post 112 is formed on the top surface of a portion of the nth initial contact layer 41. The connecting post 112 forms a closed ring, and the connecting post 112 is exposed on the top surface of the nth initial contact layer 41. The exposed top surface of the nth initial contact layer 41 is also in a closed ring shape. Thus, the shapes of the subsequently formed first groove and second groove are correspondingly closed ring shapes, thereby making the formed step 101 and the electrical contact structure 102 corresponding to the step 101 both ring-shaped.

[0074] An etching process is performed on the exposed top surface of the nth initial contact layer 41 to form a first groove 14. The first groove exposes a portion of the top surface of the nth isolation layer 31. An isolation structure 104 is formed on the sidewall of the first groove and the sidewall of the connecting post 112, and the isolation structure 104 is also located on a portion of the top surface of the nth isolation layer 31. The top surface of the formed isolation structure 104 is flush with the top surface of the connecting post 112. Specifically, the sidewall of the first groove is the initial contact layer 41, and the sidewall of the formed first groove is flush with the sidewall of the connecting post 112. In this way, the isolation structure 104 subsequently formed on the sidewall of the connecting post 112 and the first groove can be in close contact with the connecting post 112 and the initial contact layer 41, so that the isolation structure 104 can effectively isolate and protect the connecting post 112 and the isolation structure 104. Furthermore, the top surface of each isolation structure 104 is set to be flush with the top surface of the connecting post 112, and the isolation structure 104 can completely cover the sidewall of the connecting post 112, thereby isolating the connecting post 112. It is worth noting that the connecting post 112 formed by the first process of the (n+1)th initial contact layer 41 and the (n+1)th isolation layer 31 is flush with the top surface of the isolation structure 104 formed by the first process of the nth initial contact layer 41 and the nth isolation layer 31. Thus, when the first process is repeated, the top surfaces of the multiple connecting posts 112 and the multiple isolation structures 104 are all flush, thereby achieving a better isolation effect of the isolation structure 104.

[0075] The nth isolation layer 31 exposed on the top surface is etched to form a second groove. The second groove exposes the (n+1)th initial contact layer 41, and the remaining nth isolation layer 31 forms the nth step 101. Since the connecting post 112 and the isolation structure 104 are located on the top surface of the step 101, and the first process proceeds from the first layer to the Nth layer, that is, starting from the top layer, in the actual fabrication process, the connecting post 112 and the isolation structure 104 are formed first, and the step 101 is formed subsequently.

[0076] The nth isolation layer 31 exposed above refers to the top surface of the nth isolation layer 31 that is not covered by the formed isolation structure 104. The second groove exposes the (n+1)th initial contact layer 41. Thus, in the (n+1)th first process, a connecting post 112 can be formed on the exposed (n+1)th top surface.

[0077] The sidewall of the formed second groove is an isolation layer 31, and the sidewall of the second groove is flush with the sidewall of the isolation structure 104. In this way, when the connecting post 112 corresponding to the (n+1)th step 101 is formed on the sidewall of the second groove, the formed connecting post 112 can be in close contact with the isolation structure 104.

[0078] In some embodiments, the projection shapes of the first and second grooves onto the surface of the substrate 100 are rectangular. This results in the formed steps 101, the corresponding contact layers 111, and the connecting posts 112 being closed rectangles. In other words, a stepped structure 1 is equivalent to containing four sets of steps. When the electrical contact structure 102 is connected to either the word line 11 or the bit line 12, the lead-out structures 103 can be connected to the electrical contact structures 102 located in different directions. This allows for full utilization of available space in the design of the lead-out structures 103, preventing electrical interference between different lead-out structures 103 while significantly reducing the difficulty of arranging them. Furthermore, because the lead-out structures 103 are located in different orientations, the distance between them is greatly increased, thereby significantly improving the problem of large parasitic capacitance caused by overly dense arrangement of the lead-out structures 103.

[0079] Specifically, the first process will be explained below with N being 4, that is, with the formation of 4 steps 101 as an example.

[0080] Perform the first process, refer to Figure 11 as well as Figure 12 A connecting post 112 is formed on the top surface of the first initial contact layer 42. (Reference) Figure 10 In some embodiments, a mask layer 13 can be formed on the top surface of the initial contact layer 41. The mask layer 13 serves both as a patterning element and as a support for the formed connecting pillars 112, preventing the connecting pillars 112 of the first layer from collapsing due to the lack of lateral support.

[0081] In some embodiments, the material of the mask layer 13 may be silicon oxide, and the mask layer 13 may be formed on the top surface of the first initial contact layer 42 by atomic layer deposition or thermal oxidation.

[0082] The mask layer 13 is patterned. In some embodiments, self-aligned quadruple patterning (SAQP) or self-aligned double patterning (SADP) can be used for etching. The patterned mask layer 13 is etched to form an initial groove. The sidewalls of the initial groove expose the remaining part of the mask layer 13, and the top of the initial groove exposes part of the top surface of the first initial contact layer 42. A first initial connection layer 51 is formed on the sidewalls of the initial groove and the top surface of the first initial contact layer 42. Part of the first initial connection layer 51 located on the sidewalls of the initial groove is removed, and part of the first initial connection layer 51 located on the top surface of the first initial contact layer 42 is also removed to form a connecting post 112 with a preset thickness. The formed connecting post 112 is a closed ring and exposes part of the top surface of the first initial contact layer 42.

[0083] refer to Figure 12 The first initial contact layer 42 exposed on the top surface is etched to form a first groove 14. The sidewall of the first groove 14 is flush with the sidewall of the connecting post 112, and the sidewall of the first groove 14 exposes the first initial contact layer 42. The bottom of the first groove 14 exposes the first isolation layer 31.

[0084] A first initial isolation structure 61 is formed on the sidewall of the first groove, the sidewall of the connecting post 112, and the top surface of the first isolation layer 32 using a deposition process. The first initial isolation structure 61 is also located on the top surface of the mask layer and the top surface of the connecting post 112.

[0085] refer to Figure 13 The removed portion is located in the first groove 14 (reference). Figure 12 The first initial isolation structure 61 on the sidewall is removed, and a portion of the first initial isolation structure 61 located on the top surface of the first isolation layer 32 is also removed to form an isolation structure 104 with a preset thickness, exposing a portion of the top surface of the first isolation layer 32. It is worth noting that the first initial isolation structure 61 located on the top surface of the mask layer and the top surface of the connecting pillar 112 may not be removed, and may be used as a mask for the subsequently formed second initial connecting layer.

[0086] The first isolation layer 32 exposed on the top surface is etched to form a second groove 15. The sidewall of the second groove 15 exposes the first isolation layer 32, and the remaining part of the first isolation layer 32 serves as the first step 101. The bottom of the second groove 15 exposes part of the top surface of the second initial contact layer 43, and the sidewall of the second groove 15 is flush with the sidewall of the isolation structure 104.

[0087] Perform the second first process, refer to Figure 14A second initial connection layer 52 is formed on the sidewall of the second groove, the sidewall of the isolation layer 31, and the top surface of the second initial contact layer 43. It is understood that, since the first initial isolation structure 61 located on the top surface of the mask layer and the top surface of the connecting pillar 112 was not removed in the first process, the second initial connection layer 52 is still located on the first initial isolation structure 61 (see reference). Figure 13 The top surface of the first initial isolation structure 61 separates the connecting pillar 112 formed in the first process from the second initial connecting layer 52, which is beneficial for subsequent removal of the connecting pillar 112 located in the first initial isolation structure 61 (see reference). Figure 13 When the second initial connecting layer 52 is applied to the top surface, it will not cause process damage to the connecting pillar 112 formed in the first process.

[0088] The second initial connecting layer 52 located on the side wall of the second groove and the side wall of the isolation structure 104 is removed. At the same time, the second initial connecting layer 52 located on the top surface of the second initial contact layer 43 and the second initial connecting layer 52 located on the top surface of the first initial isolation structure 61 are also removed to form a connecting post 112 with a preset thickness, and expose part of the top surface of the second initial contact layer 43.

[0089] refer to Figure 15 The second initial contact layer 43 exposed on the top surface is etched to form a first groove, and a second initial isolation structure 62 is formed in the first groove.

[0090] refer to Figure 16 The second initial isolation structure 62 is etched to form the isolation structure 104 corresponding to the second step 101. The method for etching the second initial isolation structure 62 is the same as the method for etching the first initial isolation structure 61 in the first process. It is worth noting that the second initial isolation structure 62 located on the top surface of the connecting post 112 and the top surface of the isolation structure 104 corresponding to the first step 101 may not be removed.

[0091] The second isolation layer 33 exposed on the top surface is etched to form a second groove. The sidewall of the second groove exposes the second isolation layer 33, and the remaining part of the second isolation layer 33 serves as a second step 101. The bottom of the second groove exposes the top surface of the third initial contact layer 44, and the sidewall of the second groove is flush with the sidewall of the isolation structure 104.

[0092] The third and fourth first processes are understood to be the same as the first two first processes, which will be briefly described below. For specific steps, please refer to the above description of the first process.

[0093] Perform the third first process, refer to Figure 17This forms the third initial connection layer 53.

[0094] refer to Figure 18 The third initial connection layer 53 is etched to form the connection pillar 112.

[0095] The third initial contact layer 44 is etched to form a first groove, and a third initial isolation structure 63 is formed on the side wall of the first groove, the side wall of the connecting post 112, and the top surface of the third isolation layer 34.

[0096] refer to Figure 19 The third initial isolation structure 63 is etched to form the isolation structure 104.

[0097] The exposed top surface of the third isolation layer 34 is etched to form a second groove. The sidewall of the second groove exposes the third isolation layer 34, and the remaining part of the third isolation layer 34 serves as the third step 101. The bottom of the second groove exposes the top surface of the fourth initial contact layer 41, and the sidewall of the second groove is flush with the sidewall of the isolation structure 104.

[0098] Perform the fourth first process, refer to Figure 20 This forms the fourth initial connection layer.

[0099] refer to Figure 21 The fourth initial connection layer is etched to form the connection pillar 112.

[0100] The fourth initial contact layer 45 is etched to form the first groove. It can be understood that since the fourth initial contact layer 45 is the last initial contact layer, after the connecting post 112 is formed, the top surface of the fourth isolation layer 35 exposed in the first groove can be etched directly until part of the top surface of the substrate 100 is exposed.

[0101] refer to Figure 22 Next, a fourth initial isolation structure 64 is formed on the sidewall of the first groove, the sidewall of the connecting post 112, the sidewall of the fourth isolation layer 35, and the top surface of the base 100. The fourth initial isolation structure 64 fills the gaps between the closed rings formed by the connecting post 112, the gaps in the first groove, and the gaps between the closed rings formed by the fourth isolation layer 35. Furthermore, the fourth initial isolation structure 64 is also located on the top surface of the connecting post 112 and the isolation structure formed by the previous first process.

[0102] refer to Figure 22 Remove the remaining portion of the initial contact layer 41 (reference) Figure 10A contact layer 111 is formed, which is connected to the connecting post 112 to form an electrical contact structure. The remaining initial contact layer refers to the initial contact layer that was not etched away in the first process. As can be seen from the steps of forming the isolation structure 104 and the connecting post 112 described above, each connecting post 112 is located on the top surface of a portion of the initial contact layer, and each isolation structure 104 is in contact with the sidewall of the remaining initial contact layer. Therefore, after removing the remaining initial contact layer and forming the contact layer 111 at the original location of the remaining initial contact layer 41, each connecting post 112 is located on the top surface of a portion of the contact layer 111, and each isolation structure 104 is in contact with the sidewall of the contact layer 111. This allows the connecting post 112 to lead out the electrical signal from the contact layer 111, and the isolation structure 104 to isolate adjacent contact layers 111.

[0103] In some embodiments, the method of forming the contact layer 111 includes:

[0104] The initial contact layer is removed to form a third groove. In some embodiments, a wet etching process or a dry etching process can be used to remove the initial contact layer, and the third groove exposes the bottom surface of the previous step 101 and the top surface of the current step 101.

[0105] A contact layer 111 is formed in the third groove using a deposition process. In some embodiments, the contact layer 111 can be a metal, such as at least one of tantalum, tungsten, titanium, copper, aluminum, silver, and gold. The deposition process can be atomic layer deposition. Metals have good conductivity, and connecting the metal to the bit line 12 or word line 11 speeds up signal transmission through the contact layer 111.

[0106] In other embodiments, the initial contact layer is made of silicon, and the method for forming the contact layer 111 includes:

[0107] The initial contact layer is doped with dopant ions to transform it into contact layer 111. This means that an etching process is unnecessary for etching the initial contact layer, thus eliminating the need for an etching step.

[0108] Specifically, in some embodiments, the material of the initial contact layer can be a silicon-based material, such as polycrystalline silicon or silicon, and the dopant ions can be either N-type or P-type ions. The doping process can be either ion implantation or thermal diffusion.

[0109] refer to Figure 5 After forming the contact layer 111, it also includes: a fourth initial isolation structure 64 (reference) located on the top surface of the connecting post 112 and the isolation structure 104. Figure 22The planarization process is performed to remove the four initial isolation structures 104 (reference). Figure 22 ), exposing the top surface of each connecting post 112.

[0110] A second sacrificial layer is formed on the top surface of the connecting pillar 112 and the top surface of the isolation structure 104 using a deposition process. The material of the second sacrificial layer can be silicon nitride.

[0111] The second sacrificial layer is patterned; the patterned second sacrificial layer is etched, and the second sacrificial layer 71 located on the top surface of the isolation structure 104 is retained. The remaining second sacrificial layer forms a plurality of first through holes, wherein each through hole exposes the top surface of the connecting post 112.

[0112] A lead-out structure 103 is formed in the second through hole (reference). Figure 4 Each lead-out structure 103 contacts the top surface of the connecting post 112. The lead-out structures 103 can be configured to connect to the connecting post 112 in different directions. This greatly improves the flexibility of the lead-out structure 103 configuration when transmitting signals between the word line 11 or bit line 12 and external circuits, thereby reducing the difficulty of arranging the lead-out structures 103. Furthermore, since the lead-out structures 103 can be configured in different directions, the spacing between the lead-out structures 103 can be larger, thereby reducing parasitic capacitance. In some embodiments, the material of the lead-out structure 103 can be a metal, such as at least one of tantalum, tungsten, titanium, copper, aluminum, silver, and gold.

[0113] In some embodiments, it also includes:

[0114] The top surface of the stepped structure 1 is patterned. Specifically, the top surface of the connecting column 112 and the top surface of the isolation structure 104 can be patterned to define the subsequent etching openings.

[0115] The patterned stepped structure 1 is etched until it penetrates the substrate 100 to form two sub-stepped structures 2. The steps 101 in the sub-stepped structures 2 include a first portion and a second portion. In some embodiments, when forming the stepped structure 1, each step 101, each electrical contact structure 102, and each isolation structure 104 are all closed rings. In this way, the stepped structure 1 can be formed in different directions in one first process step, which is equivalent to forming multiple sets of steps. This can greatly improve the fabrication efficiency.

[0116] Based on this, an etching process can be performed on the stepped structure 1, which has a closed ring structure, to divide the stepped structure 1 into two or more parts. This results in each sub-step 2 having only one step 101: a first part and a second part that are in contact, with the first and second parts extending in different directions, and also including an electrical contact structure 102 corresponding to the first and second parts. Alternatively, in other embodiments, each step 101 may include a first part, a second part, and a third part that are in contact, and also includes an electrical contact structure 102 corresponding to the first, second, and third parts. Furthermore, the step 101 may also include a fourth part, with the electrical contact structure 102 located on the top surface of the fourth step 101. In other words, the etching process of the stepped structure 1 can be performed based on the available space in the semiconductor structure and the arrangement of the word lines 11 and bit lines 12, so that the shape of the sub-step structures 2 meets the requirements, greatly improving the versatility of the stepped structure 1.

[0117] Specifically, refer to Figure 23 as well as Figure 24 In some embodiments, etching can be performed along the centerline in different directions on the top surface of the stepped structure 1 to divide the stepped structure 1 into two sub-stepped structures 2. In the two sub-stepped structures 2 thus formed, each step 101 forms a U-shape, and the electrical contact structure 102 and the isolation structure 104 also correspond to the shape of the step 101.

[0118] In other embodiments, reference is made to Figure 25 Alternatively, etching can be performed along the diagonal of the top surface of the stepped structure 1 to form two sub-stepped structures 2. In one part of the step 101, only the first part and the second part are included, while the remaining part of the step 101 also includes a third part connected to the second part. The extension direction of the third part is different from that of the second part, and the electrical contact structure 102 and the isolation structure 104 also correspond to the shape of the step 101.

[0119] In the semiconductor structure fabrication method provided in the above embodiments, the formed electrical contact structure 102 is located on the top surface of the steps 101 in the first and second parts, thereby causing the electrical contact structure 102 to extend in two different directions. This is equivalent to forming at least two sets of steps in the stepped structure 1, allowing the word line 11 or bit line 12 to contact the electrical contact structure 102 in the first direction X or the second direction Y, thus enabling signal transmission with external circuits. In other words, by setting the steps 101 to extend in different directions, the electrical contact structure 102 is led out in different directions, thereby increasing the lead-out methods and reducing the difficulty of lead arrangement.

[0120] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Multiple word lines and multiple bit lines, wherein the extension direction of the word lines is different from the extension direction of the bit lines; A stepped structure, the stepped structure including multiple steps, each step including at least a first part and a second part that are connected, the first part extending along a first direction, the second part extending along a second direction, the first direction and the second direction being different; Multiple electrical contact structures, wherein the electrical contact structures cover the stepped top surface of the first portion and the second portion, and the electrical contact structures are in contact with the word line or the bit line; The steps form a closed ring.

2. The semiconductor structure according to claim 1, characterized in that, At least part of the step also includes: a third part connected to the second part, the third part extending along a third direction different from the second direction, and the electrical contact structure also covering part of the top surface of the step of the third part.

3. The semiconductor structure according to claim 2, characterized in that, The third direction is parallel to the first direction.

4. The semiconductor structure according to claim 2 or 3, characterized in that, Each step includes the third part, and the first part, the second part and the third part are sequentially joined together to form a U-shaped step.

5. The semiconductor structure according to claim 1, characterized in that, The closed ring is a closed rectangle, and the step includes a first part, a second part, a third part and a fourth part connected in sequence. The third part extends along the first direction, the fourth part extends along the second direction, and the electrical contact structure is also located on the top surface of the step corresponding to the third part and the fourth part.

6. The semiconductor structure according to claim 1 or 2, characterized in that, The electrical contact structure includes: A contact layer that covers a portion of the top surface of the step; A connecting post is in contact with the contact layer. The top surfaces of the connecting posts corresponding to the plurality of steps are flush. The stepped structure exposes the end face of the contact layer away from the connecting post, and the exposed end face is in contact with one of the bit line or the word line.

7. The semiconductor structure according to claim 6, characterized in that, Also includes: Multiple lead-out structures are provided, and the lead-out structures are electrically connected to the top surface of the connecting post.

8. The semiconductor structure according to claim 1, characterized in that, Also includes: An isolation structure is located between adjacent electrical contact structures for isolating the adjacent electrical contact structures.

9. The semiconductor structure according to claim 1, characterized in that, The bit line or the word line is electrically connected to either the electrical contact structure corresponding to the first portion or the second portion.

10. A method for fabricating a semiconductor structure, characterized in that, include: Multiple word lines and multiple bit lines are formed, wherein the extension direction of the word lines is different from the extension direction of the bit lines; A stepped structure is formed, the stepped structure includes multiple steps, the steps form a closed ring, and each step includes at least a first part and a second part that are connected. The first part extends along a first direction, and the second part extends along a second direction. The first direction and the second direction are different. Multiple electrical contact structures are formed, wherein the electrical contact structures cover the top surface of the steps of the first part and the second part, and the electrical contact structures are in contact with word lines or bit lines.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that, The exposed portion of the top surface of the step in the electrical contact structure further includes: forming an isolation structure on the exposed top surface of the step, and the isolation structure being located between adjacent electrical contact structures.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that, The method of forming the stepped structure and the electrical contact structure includes: Provide a base: An isolation layer and an initial contact layer are formed on the substrate in sequence, with the top isolation layer as the first isolation layer, the top initial contact layer as the first initial contact layer, the bottom isolation layer as the Nth isolation layer, and the bottom initial contact layer as the Nth initial contact layer. The first process is performed sequentially on the first isolation layer and the first initial contact layer to the Nth isolation layer and the Nth initial contact layer, wherein the first process is performed on the nth isolation layer and the nth initial contact layer to form the nth step and the electrical contact structure and the isolation structure corresponding to the nth step, where 1≤n≤N.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that, The first process includes: A connecting post is formed on the top surface of a portion of the nth initial contact layer, the connecting post forming a closed ring, and the connecting post protruding from the top surface of a portion of the nth initial contact layer; An etching process is performed on the nth initial contact layer exposed on the top surface to form a first groove, and the first groove exposes part of the top surface of the nth isolation layer. The isolation structure is formed on the sidewall of the first groove and the sidewall of the connecting column, and the isolation structure is also located on the top surface of a portion of the nth isolation layer, wherein the top surface of the formed isolation structure is flush with the top surface of the connecting column; The nth isolation layer exposed on the top surface is etched to form a second groove, the second groove exposes the (n+1)th initial contact layer, and the remaining nth isolation layer forms the nth step; The remaining portion of the initial contact layer is removed to form a contact layer, which is connected to the connecting post to form the electrical contact structure.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that, The method of forming the contact layer includes: Remove the initial contact layer to form a third groove; The contact layer is formed in the third groove using a deposition process.

15. The method for preparing a semiconductor structure according to claim 13, characterized in that, The initial contact layer is made of silicon, and the method for forming the contact layer includes: The initial contact layer is doped with dopant ions to transform it into the contact layer.

16. The method for preparing a semiconductor structure according to claim 13, characterized in that, The projection shape of the first groove and the second groove on the substrate surface is rectangular.

17. The method for preparing a semiconductor structure according to claim 13, characterized in that, Also includes: The top surface of the stepped structure is patterned. The patterned stepped structure is etched until it penetrates the substrate to form two sub-stepped structures, wherein the steps in the sub-stepped structures include the first portion and the second portion.

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