Semiconductor structure and method of forming the same

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a forming method thereof. The method comprises: providing a substrate, the substrate comprising a stack structure and a first isolation structure arranged alternately along a first direction; forming a grid-shaped etching groove extending along the first direction in the stack structure and the first isolation structure; the grid-shaped etching groove divides the substrate into a first region and a second region arranged sequentially along a second direction; the first direction and the second direction are any two directions in a plane in which the substrate lies; forming a second isolation structure in the grid-shaped etching groove; forming a transistor structure and a capacitor structure in the first region and the second region respectively, the transistor structure and the capacitor structure being isolated by the second isolation structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor structure and a method for forming the same. Background Technology

[0002] Currently, the integration level of semiconductor devices is constantly improving. For example, Dynamic Random Access Memory (DRAM) has changed from a vertical structure to a horizontal structure, which enables three-dimensional stacking and forms a multi-layer stacked structure, further improving the storage density of DRAM.

[0003] However, in the multi-layer stacked structure of related technologies, a support structure must be formed to isolate the capacitor structure and the transistor structure; otherwise, the lengths of the capacitor structure and the transistor structure in the multi-layer stacked structure will be inconsistent. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same.

[0005] In a first aspect, embodiments of this disclosure provide a method for forming a semiconductor structure, the method comprising:

[0006] A substrate is provided, the substrate comprising a stacked structure and a first isolation structure alternately arranged along a first direction;

[0007] A grid-like etched groove extending along the first direction is formed in the stacked structure and the first isolation structure; the grid-like etched groove divides the substrate into a first region and a second region arranged sequentially along a second direction; the first direction and the second direction are any two directions in the plane in which the substrate is located;

[0008] A second isolation structure is formed in the grid-like etched grooves;

[0009] A transistor structure and a capacitor structure are formed in the first region and the second region, respectively, and the transistor structure and the capacitor structure are isolated by the second isolation structure.

[0010] In some embodiments, the stacked structure includes sacrificial layers and isolation layers stacked alternately along a third direction; the third direction intersects the plane containing the substrate; the sacrificial layers include a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer stacked sequentially along the third direction;

[0011] The grid-like etched grooves are formed through the following steps:

[0012] The stacked structure and the first isolation structure are etched to form a sub-etched groove extending along the first direction; the sub-etched groove has a first preset size along the second direction;

[0013] Using the surfaces of the first and third sacrificial layers exposed by the sub-etched grooves as the etching starting point, along the second direction, the first sacrificial layer with a second preset size and the third sacrificial layer with a second preset size are removed to form a first space;

[0014] Using the surface of the first isolation structure exposed by the sub-etched groove as the etching starting point, the first isolation structure with a third preset size is removed along the second direction to form a second space;

[0015] The sub-etched grooves, the first space, and the second space together constitute the mesh-like etched grooves.

[0016] In some embodiments, the first sacrificial layer and the third sacrificial layer have a fourth preset size along the third direction; the fourth preset size is greater than 1.5 times the first preset size, and the second preset size is greater than 0.5 times the first preset size.

[0017] In some embodiments, the first isolation structure has a fifth preset dimension along the first direction;

[0018] The fifth preset size is greater than or equal to 1.5 times the first preset size.

[0019] In some embodiments, the second isolation structure includes a first isolation layer and a second isolation layer; wherein the second isolation layer is formed by the following steps:

[0020] A first initial isolation layer is formed in the grid-like etched grooves; wherein, the first initial isolation layer has grid-like gaps located between the first isolation structures and between the stacked structures;

[0021] Etching removes the first initial isolation layer located in the projection region of the first isolation structure along the second direction, and the first isolation structure located in the second region, exposing the gaps between the stacked structures and forming etching trenches;

[0022] A first insulating material is filled in the gaps between the etched trenches and the exposed stacked structure; wherein the first insulating material located in the gaps constitutes the second insulating layer.

[0023] In some embodiments, the transistor structure is formed by the following steps:

[0024] Remove the second sacrificial layer in the first region to form a first etched groove;

[0025] The channel structure of the transistor structure is formed in the first etched groove;

[0026] Remove the first sacrificial layer, the third sacrificial layer, and the first isolation structure in the first region to expose the channel structure;

[0027] A gate structure is formed on the surface of the channel structure.

[0028] In some embodiments, forming a channel structure for the transistor structure in the first etched groove includes:

[0029] The first etched groove is filled with a metal oxide material to form the channel structure; the metal oxide material includes indium gallium zinc oxide.

[0030] In some embodiments, a gate structure is formed on the surface of the channel structure, including:

[0031] A gate dielectric layer and an initial gate conductive layer are sequentially formed on the surface of the channel structure;

[0032] A third isolation structure is formed in the gaps between the initial gate conductive layers and in the gaps between the stacked structures;

[0033] The initial gate conductive layer is etched back along the second direction to form a gate conductive layer and a third space; the gate dielectric layer and the gate conductive layer together constitute the gate structure.

[0034] In some embodiments, the method further includes:

[0035] A plurality of bit line structures are formed, arranged sequentially along the first direction and extending along the third direction; wherein the bit line structures are connected to the channel structure.

[0036] In some embodiments, the capacitor structure and the first isolation layer are formed by the following steps:

[0037] Remove the second sacrificial layer in the second region to form a second etched groove;

[0038] The first initial isolation layer exposed by the second etched groove is etched away until the second isolation layer and the channel structure are exposed, forming a fourth space, and the remaining first initial isolation layer constitutes the first isolation layer;

[0039] The first sacrificial layer and the third sacrificial layer in the second region are removed to form a third etched groove; wherein the third etched groove includes the second etched groove and the fourth space;

[0040] A capacitor structure is formed in the third etched groove.

[0041] In some embodiments, a capacitor structure is formed in the third etched groove, including:

[0042] A first electrode layer, a dielectric layer, and a second electrode layer are sequentially formed on the sidewall of the third etched groove to form the capacitor structure;

[0043] The first electrode layer is connected to the channel structure, and the second electrode layer fills the third etched groove.

[0044] In some embodiments, the substrate further includes a substrate; the stacked structure and the first isolation structure are formed on the surface of the substrate; the first isolation structure and the stacked structure are formed by the following steps:

[0045] An initial stacked structure is formed on the surface of the substrate, the initial stacked structure comprising the sacrificial layer and the isolation layer stacked sequentially along the third direction;

[0046] A photoresist layer with a preset pattern is formed on the surface of the initial stacked structure, the preset pattern including sub-patterns spaced apart along the first direction; the sub-patterns expose the initial stacked structure;

[0047] The initial stacked structure is removed by the photoresist layer to form isolation grooves and the stacked structure spaced apart along the first direction;

[0048] The first isolation structure is formed in the isolation groove.

[0049] In some embodiments, the etching selectivity between the first initial isolation layer and the substrate is greater than the etching selectivity between the second isolation layer and the substrate.

[0050] In a second aspect, embodiments of this disclosure provide a semiconductor structure, the semiconductor structure comprising:

[0051] Base;

[0052] A second isolation structure located in the substrate, the second isolation structure including a second isolation layer and a first isolation layer surrounding a portion of the second isolation layer; the second isolation structure divides the substrate into a first region and a second region arranged sequentially along a second direction;

[0053] The transistor structure is located in the first region and arranged in an array along a first direction and a third direction, and the capacitor structure is located in the second region and arranged in an array along the first direction and the third direction; wherein the transistor structure and the capacitor structure are isolated by the first isolation layer and the second isolation layer; the first direction and the second direction are any two directions in the plane where the substrate is located; the third direction intersects the plane where the substrate is located.

[0054] In some embodiments, the substrate includes a substrate; the transistor structure and the capacitor structure are located on the surface of the substrate;

[0055] The etching selectivity between the first isolation layer and the substrate is greater than that between the second isolation layer and the substrate.

[0056] In some embodiments, the transistor structure includes a gate structure;

[0057] The gate structure includes a channel structure, a gate dielectric layer located on the surface of the channel structure, and a gate conductive layer located on the surface of the gate dielectric layer; wherein the channel structure is made of a metal oxide material, and the metal oxide material includes indium gallium zinc oxide.

[0058] In some embodiments, the channel structure includes a first end and a second end along the second direction; the semiconductor structure further includes a bit line structure connected to the first end and a capacitor structure connected to the second end;

[0059] The bit line structures are arranged sequentially along the first direction and extend along the third direction;

[0060] The capacitor structure includes a first electrode layer, a dielectric layer, and a second electrode layer.

[0061] In some embodiments, the semiconductor structure further includes: an isolation layer;

[0062] The isolation layer is located between adjacent gate structures along the third direction, and the isolation layer is located between adjacent capacitor structures along the third direction.

[0063] The semiconductor structure and its formation method provided in this disclosure, by forming a second isolation structure as an isolation structure between the transistor structure and the capacitor structure in the semiconductor structure, can make the length of each layer of transistor structure and the length of each layer of capacitor structure in the semiconductor structure consistent. In addition, in this disclosure, the above effects can be achieved without forming a support structure, which simplifies the semiconductor structure fabrication process. Attached Figure Description

[0064] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0065] Figure 1 A schematic flowchart illustrating a semiconductor structure formation method provided in an embodiment of this disclosure;

[0066] Figures 2a-2u This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this disclosure;

[0067] The annotations in the attached figures are explained as follows:

[0068] 10—Substrate; 11a—Initial stacked structure; 12—Sacrificial layer; 13—Isolation layer; 121—First sacrificial layer; 122—Second sacrificial layer; 123—Third sacrificial layer; 11—Stacked structure; 14—Isolation trench; 15—First isolation structure; 16—Sub-etched trench; 17—Mesh-shaped etched trench; 18a—First initial isolation layer; 18b—Void; 19—Etching trench; 20a—First isolation material; 20—Second isolation layer; 21a—First etched trench; 21—Trench structure; 22 1—Gate dielectric layer; 222a—Initial gate conductive layer; 222—Gate conductive layer; 23—Third isolation structure; 23a—Fourth isolation structure; 24—Bit line structure; 26—Second etched groove; 18—First isolation layer; 27—Third etched groove; 22—Gate structure; 251—First electrode layer; 252—Dielectric layer; 253—Second electrode layer; 25—Capacitor structure; H—First space; I—Second space; J—Third space; K—Fourth space; A—First region; B—Second region. Detailed Implementation

[0069] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0070] In the following description, numerous details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0071] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0072] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0073] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0074] Before introducing the embodiments of this disclosure, let's define three directions that may be used in the following embodiments to describe the three-dimensional structure. Taking a Cartesian coordinate system as an example, the three directions may include the X-axis, Y-axis, and Z-axis. The substrate may include a top surface on the front side and a bottom surface on the back side opposite the front side. Ignoring the flatness of the top and bottom surfaces, the direction intersecting (e.g., perpendicular) with the top and bottom surfaces of the substrate is defined as the third direction. In the direction of the top and bottom surfaces of the substrate (i.e., the plane in which the substrate lies), two intersecting (e.g., perpendicular) directions are defined. For example, the direction in which the stacked structure and the first isolation structure are alternately arranged can be defined as the first direction, and the extension direction of the first isolation structure can be defined as the second direction. The planar orientation of the substrate can be determined based on the first and second directions. In the embodiments of this disclosure, the first direction, the second direction, and the third direction may be mutually perpendicular. In other embodiments, the first direction, the second direction, and the third direction may not be perpendicular. In the embodiments of this disclosure, the first direction is defined as the X-axis, the second direction as the Y-axis, and the third direction as the Z-axis.

[0075] This disclosure provides a method for forming a semiconductor structure. Figure 1 This is a schematic flowchart of a semiconductor structure formation method provided in an embodiment of the present disclosure, such as... Figure 1 As shown, the method for forming a semiconductor structure includes the following steps:

[0076] Step S101: Provide a substrate, the substrate including a stacked structure and a first isolation structure arranged alternately along a first direction.

[0077] In this embodiment of the disclosure, the substrate includes at least a substrate; the substrate may be a silicon substrate, or may include other semiconductor elements, such as germanium (Ge), or include semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb), or include other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or combinations thereof.

[0078] In this embodiment of the disclosure, the stacked structure includes sacrificial layers and isolation layers that are alternately stacked from bottom to top along a third direction; the sacrificial layers include a first sacrificial layer, a second sacrificial layer and a third sacrificial layer that are stacked sequentially along a third direction.

[0079] In some embodiments, because it is necessary to subsequently remove a portion of the first sacrificial layer and a portion of the third sacrificial layer while retaining the second sacrificial layer, the etching selectivity ratio between the first sacrificial layer and the substrate is equal to that between the third sacrificial layer and the substrate during the process of removing a portion of the first sacrificial layer and the substrate. Furthermore, the etching selectivity ratio between the first sacrificial layer and the substrate is greater than that between the second sacrificial layer and the substrate, or the etching selectivity ratio between the third sacrificial layer and the substrate is greater than that between the second sacrificial layer and the substrate. This allows for the simultaneous removal of a portion of the first and third sacrificial layers during the etching process, while also ensuring that the second sacrificial layer is not damaged during the removal of the first and third sacrificial layers.

[0080] In this embodiment, the first sacrificial layer and the third sacrificial layer can be made of the same material, such as a silicon nitride layer, the second sacrificial layer can be a polysilicon layer, and the isolation layer can be silicon oxide or a silicon oxynitride layer. The material of the first isolation structure can be a Low K (low dielectric constant) material or other suitable materials.

[0081] In step S102, a grid-like etched groove extending along a first direction is formed in the stacked structure and the first isolation structure; the grid-like etched groove divides the substrate into a first region and a second region arranged sequentially along a second direction.

[0082] In this embodiment of the disclosure, the first region and the second region can be used to form different functional structures, for example, the first region can be used to form a gate structure, a word line structure, or a bit line structure, and the second region can be used to form a capacitor structure.

[0083] The mesh-like etched grooves in this embodiment are mesh-like on both sides along the second direction and have a certain thickness in the second direction.

[0084] Step S103: A second isolation structure is formed in the grid-like etched grooves.

[0085] In this embodiment of the disclosure, the second isolation structure includes a second isolation layer and a first isolation layer surrounding a portion of the second isolation layer. Furthermore, in this embodiment, the etching selectivity between the first isolation layer and the substrate is greater than the etching selectivity between the second isolation layer and the substrate. For example, the material of the first isolation layer may be a low-K material, and the material of the second isolation layer may be silicon oxide.

[0086] In step S104, a transistor structure and a capacitor structure are formed in the first region and the second region, respectively, and the transistor structure and the capacitor structure are isolated by a second isolation structure.

[0087] In this embodiment of the disclosure, the transistor structure includes a gate structure, a source, and a drain; the gate structure can be a dual-gate structure or a full-ring gate structure.

[0088] In this embodiment, the stacked structure formed by stacking multiple transistor structures and capacitor structures in a third-order upward direction can form a three-dimensional semiconductor structure, thereby improving the integration density of the semiconductor structure and achieving miniaturization. Furthermore, in this embodiment, the distance between the gate structure and the capacitor structure is increased by using a second isolation structure (i.e., a first isolation layer and a second isolation layer), and Low K and silicon oxide are used as the first and second isolation layers respectively, which can reduce the parasitic capacitance of the semiconductor structure, thereby reducing capacitor resistance delay and improving the response time of the semiconductor structure.

[0089] In this embodiment of the disclosure, by forming a second isolation structure as an isolation structure between the transistor structure and the capacitor structure in the semiconductor structure, the length of each layer of transistor structure and the length of each layer of capacitor structure in the semiconductor structure can be made consistent. In addition, in this embodiment of the disclosure, the above effects can be achieved without forming a support structure, which simplifies the semiconductor structure fabrication process.

[0090] Figures 2a-2u This is a schematic diagram of the semiconductor structure formation process provided in the embodiments of this disclosure. The following is in conjunction with... Figures 2a-2u The formation process of the semiconductor structure provided in the embodiments of this disclosure will be described in detail. Figure 2a and 2b For 3D views, Figures 2c-2u A top view and a cross-sectional view along a-a' are shown during the semiconductor structure formation process.

[0091] First, step S101 is performed, providing a substrate, the substrate including a stacked structure and a first isolation structure arranged alternately along a first direction.

[0092] In some embodiments, the substrate further includes a substrate; the stacked structure and the first isolation structure are located on the substrate surface.

[0093] In this embodiment of the disclosure, the substrate may be a silicon substrate, or the substrate may include other semiconductor elements, such as germanium, or include semiconductor compounds, such as silicon carbide or gallium arsenide.

[0094] In some embodiments, the stacked structure and the first isolation structure are formed by the following steps: forming an initial stacked structure on the surface of a substrate, the initial stacked structure including a sacrificial layer and an isolation layer stacked sequentially along a third direction; forming a photoresist layer with a preset pattern on the surface of the initial stacked structure, the preset pattern including sub-patterns spaced apart along a first direction; exposing the initial stacked structure through the sub-patterns; removing the exposed initial stacked structure through the photoresist layer to form isolation grooves spaced apart along the first direction; and forming the first isolation structure in the isolation grooves.

[0095] In this embodiment of the disclosure, the number of sacrificial layers and isolation layers in the initial stacked structure can be set according to the required storage density. The more sacrificial layers and isolation layers there are, the higher the integration of the final semiconductor structure.

[0096] like Figure 2a As shown, an initial stacked structure 11a is formed on the surface of the substrate 10. The initial stacked structure 11a includes a sacrificial layer 12 and an isolation layer 13 that are alternately stacked from bottom to top along the Z-axis direction. The sacrificial layer 12 includes a first sacrificial layer 121, a second sacrificial layer 122 and a third sacrificial layer 123 that are stacked sequentially along the Z-axis direction.

[0097] In this embodiment of the disclosure, the materials of the first sacrificial layer 121 and the third sacrificial layer 123 may be silicon nitride, the material of the second sacrificial layer 122 may be polycrystalline silicon, and the material of the isolation layer may be silicon oxide.

[0098] In this embodiment of the present disclosure, the first sacrificial layer 121 and the third sacrificial layer 123 have a fourth preset size L4 along the Z-axis direction, and the fourth preset size L4 is 30 to 60 nanometers (nm). The second sacrificial layer 122 has a size of 20 to 40 nm along the Z-axis direction, and the isolation layer 123 has a size of 20 to 50 nm along the Z-axis direction.

[0099] In this embodiment of the disclosure, the first sacrificial layer 121, the second sacrificial layer 122, the third sacrificial layer 123 and the isolation layer 13 can be formed by any of the following deposition processes: chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, coating process or thin film process.

[0100] like Figures 2a-2c As shown, a photoresist layer (not shown) with a preset pattern is formed on the surface of the initial stacked structure 11a. The preset pattern includes sub-patterns F arranged at intervals along the X-axis direction. The sub-patterns F expose the initial stacked structure 11a. The exposed initial stacked structure 11a is removed by the photoresist layer to form a stacked structure 11 and an isolation groove 14 arranged alternately along the X-axis direction.

[0101] In this embodiment of the present disclosure, the isolation groove 14 has a fifth preset size L5 along the X-axis direction, and the fifth preset size L5 is 30 to 60 nm.

[0102] In this embodiment of the disclosure, the exposed initial stacked structure 11a can be removed by etching using a high aspect ratio (HAR) technique to form the stacked structure 11 and the isolation groove 14.

[0103] In this embodiment of the disclosure, after forming the stacked structure 11 and the isolation groove 14, the method for forming the semiconductor structure further includes: removing the photoresist layer with a preset pattern to expose the upper surface of the stacked structure 11 (e.g., ...). Figure 2b and 2c (As shown).

[0104] like Figure 2d As shown, the first isolation structure can be formed by the following steps: filling the isolation groove 14 with a second isolation material to form the first isolation structure 15. The second isolation material can be a Low K material or other suitable material.

[0105] Next, step S102 is performed to form a grid-like etched groove extending along a first direction in the stacked structure and the first isolation structure.

[0106] In some embodiments, the mesh-like etched grooves can be formed by the following steps: etching the stacked structure and the first isolation structure to form sub-etched grooves extending along a first direction; the sub-etched grooves have a first preset size along a second direction; taking the surfaces of the first and third sacrificial layers exposed by the sub-etched grooves as etching starting points, along the second direction, removing the first sacrificial layer and the third sacrificial layer having a second preset size to form a first space; taking the surface of the first isolation structure exposed by the sub-etched grooves as etching starting points, along the second direction, removing the first isolation structure having a second preset size to form a second space; the sub-etched grooves, the first space, and the second space together constitute the mesh-like etched grooves.

[0107] like Figure 2e As shown, the etched stacked structure 11 and the first isolation structure 15 form a sub-etched groove 16 extending along the X-axis direction; the sub-etched groove 16 has a first preset size L1 along the Y-axis direction. In this embodiment of the present disclosure, a portion of the stacked structure 11 and a portion of the first isolation structure 15 can be removed by using dry etching techniques (such as plasma etching, reactive ion etching, or ion milling).

[0108] In this embodiment of the disclosure, the sub-etched groove is used to define the position of the transistor and the length of the channel structure. Compared with wet etching technology, the sub-etched groove formed by dry etching has higher process stability.

[0109] In some embodiments, the fifth preset size L5 is greater than or equal to 1.5 times the first preset size L1, and the first preset size L1 is 20 to 40 nm.

[0110] like Figure 2fAs shown, taking the surfaces of the first sacrificial layer 121 and the third sacrificial layer 123 exposed by the sub-etching groove 16 as the etching starting point, along the Y-axis direction, the first sacrificial layer 121 with a second preset size L2 and the third sacrificial layer 123 with a second preset size L2 are removed to form a first space H.

[0111] In this embodiment of the present disclosure, a first sacrificial layer 121 having a second preset size L2 and a third sacrificial layer 123 having a second preset size L2 can be removed by a selective etching process. In this etching process, the etching selectivity ratio between the first sacrificial layer 121 and the substrate 10 is equal to the etching selectivity ratio between the third sacrificial layer 123 and the substrate 10. The etching selectivity ratio between the first sacrificial layer 121 and the substrate 10 is greater than the etching selectivity ratio between the second sacrificial layer 122 and the substrate 10, and the etching selectivity ratio between the third sacrificial layer 123 and the substrate 10 is greater than the etching selectivity ratio between the second sacrificial layer 122 and the substrate 10.

[0112] like Figure 2f and 2g As shown, taking the surface of the first isolation structure 15 exposed by the sub-etching groove 16 as the etching starting point, the first isolation structure 15 with a third preset size L3 is removed along the Y-axis direction to form the second space I; the sub-etching groove 16, the first space H and the second space I together constitute the mesh-like etching groove 17.

[0113] In this embodiment of the present disclosure, the mesh-like etched groove 17 divides the substrate into a first region A and a second region B. Since the size of the first region A along the Y-axis determines the size of the channel in the subsequent gate structure, the size of the channel in the gate structure can be adjusted by adjusting the position of the mesh-like etched groove, thereby achieving the control capability of adjusting the gate structure and improving the performance of the formed semiconductor structure.

[0114] In some embodiments, the fourth preset size L4 is greater than 1.5 times the first preset size L1, and the second preset size L2 is greater than 0.5 times the first preset size L1. For example, the second preset size L2 is 10 to 20 nm.

[0115] In this embodiment of the disclosure, the third preset size L3 and the second preset size L2 may be equal or unequal. For example, the third preset size L3 is 10 to 20 nm.

[0116] Next, steps S103 and S104 are performed to form a second isolation structure in the grid-shaped etched grooves; a transistor structure and a capacitor structure are formed in the first region and the second region respectively, and the transistor structure and the capacitor structure are isolated by the second isolation structure.

[0117] In some embodiments, the second isolation structure includes a first isolation layer and a second isolation layer; wherein the second isolation layer can be formed by the following steps: forming a first initial isolation layer in a grid-like etched groove; wherein the first initial isolation layer has grid-like gaps located between the first isolation structures and between the stacked structures; etching away the first initial isolation layer located in the projection region of the first isolation structure along a second direction, and the first isolation structure located in the second region, exposing the gaps located between the stacked structures, forming etched trenches; filling the gaps between the etched trenches and the exposed stacked structures with a first isolation material; wherein the first isolation material located in the gaps constitutes the second isolation layer.

[0118] like Figure 2h As shown, a first initial isolation layer 18a is formed in the grid-shaped etched grooves 17; wherein, the first initial isolation layer 18a has grid-shaped gaps 18b located between the first isolation structures 15 and between the stacked structures 11.

[0119] In this embodiment of the present disclosure, the first initial isolation layer 18a can be formed by an atomic layer deposition process to improve the film quality of the formed first initial isolation layer 18a.

[0120] In this embodiment of the disclosure, since the fourth preset size L4 is greater than 1.5 times the first preset size L1, and the second preset size L2 is greater than 0.5 times the first preset size L1, after the first initial isolation layer 18a is formed, a grid-like gap 18b is formed in the first initial isolation layer 18a, which is located between the first isolation structures 15 and between the stacked structures 11. The grid-like gap 18b reserves space for the subsequent formation of the second isolation layer.

[0121] like Figure 2i and 2j As shown, etching removes the first initial isolation layer 18a located in the projection region of the first isolation structure 15 along the Y-axis and the first isolation structure 15 located in the second region B, exposing the gaps between the stacked structures 11 and forming an etching trench 19; the gap 18b between the etching trench 19 and the exposed stacked structures 11 is filled with a first isolation material 20a; wherein, the first isolation material 20a located in the gap 18b constitutes the second isolation layer 20. The first isolation material 20a can be silicon oxide or other suitable materials.

[0122] In this embodiment of the disclosure, the first initial isolation layer 18a in the projection region of the first isolation structure 15 along the Y-axis and the first isolation structure 15 located in the second region B can be removed by dry etching technology. Compared with wet etching technology, dry etching technology has higher process stability.

[0123] In some embodiments, the transistor structure includes a gate structure, a source, and a drain.

[0124] In some embodiments, the gate structure, source, and drain can be formed by the following steps: removing the second sacrificial layer in the first region to form a first etched groove; forming a channel structure of the transistor structure in the first etched groove; removing the first and third sacrificial layers in the first region to expose the channel structure; and forming a gate structure on the surface of the channel structure.

[0125] Please continue reading Figure 2i and 2j The second sacrificial layer 122 in the first region A is removed to form the first etched groove 21a. In this embodiment, the second sacrificial layer 122 in the first region A can be removed by a wet etching process with lateral etching. The etching solution can be a diluted hydrofluoric acid solution or a mixed solution of diluted hydrofluoric acid and ammonia.

[0126] It should be noted that during the lateral etching process to form the first etched groove 21a, the etching selectivity between the second sacrificial layer 122 and the substrate 10 is greater than that between the first sacrificial layer 121 and the substrate 10, and the etching selectivity between the second sacrificial layer 122 and the substrate 10 is greater than that between the third sacrificial layer 123 and the substrate 10. For example, the etching selectivity between the second sacrificial layer 122 and the substrate 10 is more than 10 times that between the first sacrificial layer 121 and the substrate 10.

[0127] In some embodiments, such as Figure 2k As shown, a metal oxide material is filled in the first etched groove 21a to form a channel structure 21; the metal oxide material includes indium gallium zinc oxide (IGZO).

[0128] like Figure 2l As shown, after forming the channel structure 21, the semiconductor structure formation method further includes: removing the first sacrificial layer 121, the third sacrificial layer 123, and the first isolation structure 15 located in the first region A, forming a gap J2 located between adjacent stacked structures, and a gap J1 located between the isolation layer 13 and the channel structure 21. For example, the first sacrificial layer 121, the third sacrificial layer 123, and the first isolation structure 15 in the first region A can be removed by lateral etching using a wet etching process.

[0129] In some embodiments, after removing the first sacrificial layer 121, the third sacrificial layer 123 and the first isolation structure 15 located in the first region A, the semiconductor formation method further includes ion implantation of the first end C of the channel structure 21 along the Y-axis direction to form a source or drain.

[0130] In some embodiments, the gate structure can be formed by the following steps: sequentially forming a gate dielectric layer and an initial gate conductive layer on the surface of the channel structure; forming a third isolation structure in the gaps between the initial gate conductive layers and in the gaps between the stacked structures; etching back the initial gate conductive layer along a second direction to form a gate conductive layer and a third space; the gate dielectric layer and the gate conductive layer together constitute the gate structure.

[0131] like Figure 2m As shown, a gate dielectric material and a gate conductive material are sequentially deposited on the surface of the channel structure 21 to form a gate dielectric layer 221 and an initial gate conductive layer 222a. In this embodiment, the gate dielectric material can be silicon oxide or other suitable materials; the gate conductive material can be any material with good conductivity, such as titanium, titanium nitride, tungsten, cobalt, platinum, palladium, ruthenium, or copper.

[0132] In this embodiment of the present disclosure, the gate dielectric layer 221 and the initial gate conductive layer 222a can be formed by any suitable deposition process, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0133] Please continue reading Figure 2l and 2m A third isolation material is deposited in the gaps between the initial gate conductive layers 222a and in the gaps J2 between the stacked structures to form a third isolation structure 23. The third isolation material can be silicon oxide or any other suitable material.

[0134] like Figure 2m and 2n As shown, the initial gate conductive layer 222a is etched back along the Y-axis to form the gate conductive layer 222 and the third space J; the gate dielectric layer 221 and the gate conductive layer 222 constitute the gate structure 22.

[0135] In this embodiment of the disclosure, the stacked structure formed by stacking multiple gate structures in the Z-axis direction can form a three-dimensional semiconductor structure, thereby improving the integration of the semiconductor structure and achieving miniaturization.

[0136] In some embodiments, such as Figure 2n and 2o As shown, the method for forming a semiconductor structure further includes: depositing a third isolation material in the third space J to form a fourth isolation structure 23a, wherein the fourth isolation structure 23a and the third isolation structure 23 together constitute an isolation structure of adjacent gate structures along the Z-axis direction.

[0137] In some embodiments, the method for forming a semiconductor structure further includes: forming a plurality of bit line structures arranged sequentially along a first direction and extending along a third direction; wherein the bit line structures are connected to the channel structure.

[0138] like Figure 2p As shown, the bit line structures 24 are arranged sequentially along the X-axis and extend along the Z-axis, and each bit line structure 24 is connected to the first end C of the channel post arranged along the Z-axis.

[0139] In this embodiment of the disclosure, the material of the bit line structure 24 includes: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), titanium-containing metal layer, polycrystalline silicon, or any combination thereof.

[0140] In this embodiment of the disclosure, after forming the bit line structure, the method for forming the semiconductor structure further includes: forming a capacitor structure in the second region.

[0141] In some embodiments, the capacitor structure and the first isolation layer can be formed by the following steps: removing the second sacrificial layer in the second region to form a second etched groove; etching away the first initial isolation layer exposed by the second etched groove until the second isolation layer and the channel structure are exposed to form a fourth space, the remaining first initial isolation layer constituting the first isolation layer; removing the first sacrificial layer and the third sacrificial layer in the second region to form a third etched groove; wherein the third etched groove includes the second etched groove and the fourth space; and forming the capacitor structure in the third etched groove.

[0142] like Figure 2p and 2q As shown, the second sacrificial layer 122 in the second region B is removed to form the second etched groove 26.

[0143] like Figure 2q~2s As shown, etching removes the first initial isolation layer 18a exposed by the second etched groove 26 until the second isolation layer 20 and the second end D of the channel structure 21 are exposed, forming the fourth space K. The remaining first initial isolation layer 18a constitutes the first isolation layer 18. In this embodiment, the first isolation layer 18 can contact the first sacrificial layer 121 and the third sacrificial layer 123 in the second region B (e.g., Figure 2r As shown), the first isolation layer 18 may also not contact the first sacrificial layer 121 and the third sacrificial layer 123 in the second region B (e.g., Figure 2s (As shown).

[0144] In some embodiments, the etching selectivity between the first initial isolation layer 18a and the substrate 10 is greater than the etching selectivity between the second isolation layer 20 and the substrate 10. In this way, the second isolation layer can be removed by etching without damaging the first initial isolation layer, that is, the second isolation layer can be used as an etching stop layer in the etching process.

[0145] like Figure 2s~2uAs shown, the first sacrificial layer 121 and the third sacrificial layer 123 in the second region B are removed to form a third etched groove 27; wherein, the third etched groove 27 includes a second etched groove 26 and a fourth space K; a first electrode material, a dielectric material and a second electrode material are deposited sequentially on the sidewall of the third etched groove 27 to form a first electrode layer 251, a dielectric layer 252 and a second electrode layer 253 to form a capacitor structure 25; wherein, the first electrode layer 251 is connected to the second end D of the channel structure 21, and the second electrode layer 253 fills the third etched groove 27.

[0146] In this embodiment, the first electrode material and the second electrode material may include metal nitrides or metal silicides, such as titanium nitride. The dielectric material may include high-k dielectric materials, such as lanthanum oxide (La₂O₃), aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), hafnium oxynitride (HfON), or hafnium silicate (HfSiO₂). x The first electrode material may be one or any combination of zirconium oxide (ZrO2) or zirconium oxide (ZrO2). In other embodiments, the first electrode material and the second electrode material may also be polycrystalline silicon.

[0147] In this embodiment of the disclosure, the first electrode layer 251, the dielectric layer 252, and the second electrode layer 253 can be formed by any of the following deposition processes: chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

[0148] In some embodiments, please continue to see Figure 2r Before forming the capacitor structure, the method for forming the semiconductor structure also includes: ion implantation of the second end D of the exposed channel structure 21 to form a drain or source.

[0149] Since the capacitor structure formed in this embodiment extends along the second direction, that is, the capacitor structure in this embodiment is horizontal, compared with the vertical capacitor structure with a high aspect ratio, the horizontal capacitor structure can reduce the possibility of tipping or breaking, thereby improving the stability of the capacitor structure. In addition, the stacked structure formed by stacking multiple capacitor structures in the third direction can form a three-dimensional semiconductor structure, thereby improving the integration of the semiconductor structure and realizing miniaturization.

[0150] In this embodiment of the disclosure, by forming a second isolation structure (including a first isolation layer and a second isolation layer) as an isolation structure between the transistor structure and the capacitor structure in the semiconductor structure, the length of each transistor structure and the length of each capacitor structure in the semiconductor structure can be made consistent. Moreover, in this embodiment of the disclosure, the above-mentioned effects can be achieved without forming a support structure, which simplifies the semiconductor structure fabrication process.

[0151] In addition, in this embodiment of the present disclosure, Low K and silicon oxide are used as the first isolation layer and the second isolation layer, respectively, which can reduce the parasitic capacitance of the semiconductor structure, thereby reducing the capacitance resistance delay and improving the response time of the semiconductor structure.

[0152] In addition, embodiments of this disclosure also provide a semiconductor structure, such as... Figure 2u As shown, the semiconductor structure includes: a substrate; a second isolation structure located in the substrate, the second isolation structure including a second isolation layer 20 and a first isolation layer 18 surrounding a portion of the second isolation layer 20; the second isolation structure divides the substrate into a first region A and a second region B arranged sequentially along the Y-axis direction; a transistor structure located in the first region A and arranged in an array along the X-axis and Z-axis directions, and a capacitor structure located in the second region B and arranged in an array along the X-axis and Z-axis directions; wherein the transistor structure and the capacitor structure are isolated by the first isolation layer 18 and the second isolation layer 20.

[0153] In this embodiment of the disclosure, the stacked structure formed by stacking multiple transistor structures and capacitor structures in a third-order upward direction can form a three-dimensional semiconductor structure, thereby improving the integration of the semiconductor structure and achieving miniaturization.

[0154] In some embodiments, please continue to see Figure 2u The substrate includes a substrate 10, and the transistor structure and capacitor structure are located on the surface of the substrate 10. The etching selectivity between the first isolation layer 18 and the substrate 10 is greater than the etching selectivity between the second isolation layer 20 and the substrate 10.

[0155] In some embodiments, please continue to see Figure 2u The transistor structure includes a channel structure 21 and a gate structure 22; the gate structure 22 has a gate dielectric layer 221 on the surface of the channel structure 21 and a gate conductive layer 222 on the surface of the gate dielectric layer 221; wherein, the channel structure 21 is made of a metal oxide material, including indium gallium zinc oxide.

[0156] In some embodiments, please continue to see Figure 2u The channel structure 21 includes a first end and a second end along the Y-axis direction; the semiconductor structure also includes a capacitor structure 25 connected to the second end; the capacitor structure 25 includes a first electrode layer 251, a dielectric layer 252 and a second electrode layer 253.

[0157] In some embodiments, the semiconductor structure further includes: an isolation layer 13; the isolation layer 13 is located between adjacent gate structures 22 along the Z-axis direction, and the isolation layer 13 is located between adjacent capacitor structures 25 along the Z-axis direction.

[0158] In some embodiments, please continue to see Figure 2uThe semiconductor structure also includes: a bit line structure 24 connected to the first end; the bit line structures 24 are arranged sequentially along the X-axis and extend along the Z-axis.

[0159] In some embodiments, please continue to see Figure 2u The semiconductor structure also includes a third isolation structure 23 located between adjacent gate structures 22.

[0160] In some embodiments, please continue to see Figure 2u The semiconductor structure also includes a first insulating material 20a located between adjacent capacitor structures 25 along the X-axis direction.

[0161] The semiconductor structure provided in this disclosure is similar to the semiconductor structure formation method in the above embodiments. For technical features not disclosed in detail in this disclosure, please refer to the above embodiments for understanding. Here, they will not be repeated.

[0162] The semiconductor structure provided in this disclosure includes a second isolation structure. Since the second isolation structure can serve as an isolation structure between the transistor structure and the capacitor structure in the semiconductor structure, it ensures that the lengths of each transistor layer and each capacitor layer in the semiconductor structure are consistent. Furthermore, since the second isolation structure includes a first isolation layer and a second isolation layer, using Low K and silicon oxide as the first and second isolation layers respectively can reduce the parasitic capacitance of the semiconductor structure, thereby reducing capacitor resistance delay and improving the response time of the semiconductor structure.

[0163] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the various components shown or discussed are coupled to each other or directly coupled.

[0164] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0165] The above are merely some embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, The method includes: A substrate is provided, the substrate comprising a stacked structure and a first isolation structure alternately arranged along a first direction; A grid-like etched groove extending along the first direction is formed in the stacked structure and the first isolation structure; the grid-like etched groove divides the substrate into a first region and a second region arranged sequentially along a second direction; the first direction and the second direction are any two directions in the plane in which the substrate is located; A second isolation structure is formed in the grid-like etched grooves; A transistor structure and a capacitor structure are formed in the first region and the second region, respectively, and the transistor structure and the capacitor structure are isolated by the second isolation structure.

2. The method according to claim 1, characterized in that, The stacked structure includes sacrificial layers and isolation layers stacked alternately along a third direction; the third direction intersects the plane containing the substrate; the sacrificial layers include a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer stacked sequentially along the third direction; The grid-like etched grooves are formed through the following steps: The stacked structure and the first isolation structure are etched to form a sub-etched groove extending along the first direction; the sub-etched groove has a first preset size along the second direction; Using the surfaces of the first and third sacrificial layers exposed by the sub-etched grooves as the etching starting point, along the second direction, the first sacrificial layer with a second preset size and the third sacrificial layer with a second preset size are removed to form a first space; Using the surface of the first isolation structure exposed by the sub-etched groove as the etching starting point, the first isolation structure with a third preset size is removed along the second direction to form a second space; The sub-etched grooves, the first space, and the second space together constitute the mesh-like etched grooves.

3. The method according to claim 2, characterized in that, The first sacrificial layer and the third sacrificial layer have a fourth preset size along the third direction; the fourth preset size is greater than 1.5 times the first preset size, and the second preset size is greater than 0.5 times the first preset size.

4. The method according to claim 3, characterized in that, The first isolation structure has a fifth preset dimension along the first direction; The fifth preset size is greater than or equal to 1.5 times the first preset size.

5. The method according to claim 4, characterized in that, The second isolation structure includes a first isolation layer and a second isolation layer; wherein the second isolation layer is formed by the following steps: A first initial isolation layer is formed in the grid-like etched grooves; wherein, the first initial isolation layer has grid-like gaps located between the first isolation structures and between the stacked structures; Etching removes the first initial isolation layer located in the projection region of the first isolation structure along the second direction, and the first isolation structure located in the second region, exposing the gaps between the stacked structures and forming etching trenches; A first insulating material is filled in the gaps between the etched trenches and the exposed stacked structure; wherein the first insulating material located in the gaps constitutes the second insulating layer.

6. The method according to claim 5, characterized in that, The transistor structure is formed through the following steps: Remove the second sacrificial layer in the first region to form a first etched groove; The channel structure of the transistor structure is formed in the first etched groove; Remove the first sacrificial layer, the third sacrificial layer, and the first isolation structure in the first region to expose the channel structure; A gate structure is formed on the surface of the channel structure.

7. The method according to claim 6, characterized in that, Forming the channel structure of the transistor structure in the first etched groove includes: The first etched groove is filled with a metal oxide material to form the channel structure; the metal oxide material includes indium gallium zinc oxide.

8. The method according to claim 7, characterized in that, A gate structure is formed on the surface of the channel structure, including: A gate dielectric layer and an initial gate conductive layer are sequentially formed on the surface of the channel structure; A third isolation structure is formed in the gaps between the initial gate conductive layers and in the gaps between the stacked structures; The initial gate conductive layer is etched back along the second direction to form a gate conductive layer and a third space; the gate dielectric layer and the gate conductive layer together constitute the gate structure.

9. The method according to claim 8, characterized in that, The method further includes: A plurality of bit line structures are formed, arranged sequentially along the first direction and extending along the third direction; wherein the bit line structures are connected to the channel structure.

10. The method according to claim 9, characterized in that, The capacitor structure and the first isolation layer are formed through the following steps: Remove the second sacrificial layer in the second region to form a second etched groove; The first initial isolation layer exposed by the second etched groove is etched away until the second isolation layer and the channel structure are exposed, forming a fourth space, and the remaining first initial isolation layer constitutes the first isolation layer; The first sacrificial layer and the third sacrificial layer in the second region are removed to form a third etched groove; wherein the third etched groove includes the second etched groove and the fourth space; A capacitor structure is formed in the third etched groove.

11. The method according to claim 10, characterized in that, A capacitor structure is formed in the third etched groove, including: A first electrode layer, a dielectric layer, and a second electrode layer are sequentially formed on the sidewall of the third etched groove to form the capacitor structure; The first electrode layer is connected to the channel structure, and the second electrode layer fills the third etched groove.

12. The method according to any one of claims 5 to 11, characterized in that, The substrate further includes a substrate; the stacked structure and the first isolation structure are formed on the surface of the substrate; the first isolation structure and the stacked structure are formed by the following steps: An initial stacked structure is formed on the surface of the substrate, the initial stacked structure comprising the sacrificial layer and the isolation layer stacked sequentially along the third direction; A photoresist layer with a preset pattern is formed on the surface of the initial stacked structure, the preset pattern including sub-patterns spaced apart along the first direction; The sub-pattern exposes the initial stacked structure; The initial stacked structure is removed by the photoresist layer to form isolation grooves and the stacked structure spaced apart along the first direction; The first isolation structure is formed in the isolation groove.

13. The method according to claim 12, characterized in that, The etching selectivity between the first initial isolation layer and the substrate is greater than that between the second isolation layer and the substrate.

14. A semiconductor structure, characterized in that, include: Base; A second isolation structure located in the substrate, the second isolation structure comprising a second isolation layer and a first isolation layer surrounding a portion of the second isolation layer; The second isolation structure divides the substrate into a first region and a second region arranged sequentially along a second direction; A transistor structure located in the first region and arranged in an array along a first direction and a third direction, and a capacitor structure located in the second region and arranged in an array along the first direction and the third direction; wherein the transistor structure and the capacitor structure are isolated by the first isolation layer and the second isolation layer; The first direction and the second direction are any two directions within the plane containing the base; the third direction intersects the plane containing the base. Wherein, the substrate includes a substrate; the transistor structure and the capacitor structure are located on the surface of the substrate; The etching selectivity between the first isolation layer and the substrate is greater than that between the second isolation layer and the substrate.

15. The structure according to claim 14, characterized in that, The transistor structure includes a gate structure; The gate structure includes a channel structure, a gate dielectric layer located on the surface of the channel structure, and a gate conductive layer located on the surface of the gate dielectric layer; wherein the channel structure is made of a metal oxide material, and the metal oxide material includes indium gallium zinc oxide.

16. The structure according to claim 15, characterized in that, The channel structure includes a first end and a second end along the second direction; the semiconductor structure further includes a bit line structure connected to the first end and a capacitor structure connected to the second end; The bit line structures are arranged sequentially along the first direction and extend along the third direction; The capacitor structure includes a first electrode layer, a dielectric layer, and a second electrode layer.

17. The structure according to claim 16, characterized in that, The semiconductor structure further includes: an isolation layer; The isolation layer is located between adjacent gate structures along the third direction, and the isolation layer is located between adjacent capacitor structures along the third direction.

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