Magnetic storage structure, magnetic storage array structure and control method thereof, and memory

Abstract

This disclosure relates to the field of semiconductor technology, providing a magnetic storage structure, a magnetic storage array structure, a control method thereof, and a memory. The magnetic storage structure includes: two magnetic tunnel junctions, each including a fixed layer and a free layer; spin-orbit coupling layers corresponding to the magnetic tunnel junctions, located on the side of the free layer away from the fixed layer; a first transistor and a second transistor, one spin-orbit coupling layer electrically connected to the source or drain of the first transistor, and the other spin-orbit coupling layer electrically connected to the source or drain of the second transistor; and a third transistor, the source or drain of the first transistor being electrically connected to the fixed layer in both magnetic tunnel junctions. This disclosure at least helps to increase the layout density of the magnetic tunnel junctions and transistors in the magnetic storage structure, thereby increasing the amount of data stored in a unit space.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a magnetic storage structure, a magnetic storage array structure, a control method thereof, and a memory. Background Technology

[0002] Magnetic Random Access Memory (MRAM) is a novel type of solid-state non-volatile memory characterized by high-speed read and write capabilities. It is formed using the properties of a magnetic tunnel junction (MTJ). MRAM stores data using magnetic field polarization rather than electric charge. An MTJ consists of a free layer, a tunneling layer, and a fixed layer. The direction of the magnetic field in the free layer can change, while the direction of the magnetic field in the fixed layer remains constant. When the magnetic field directions of the free and fixed layers are the same, the MTJ exhibits a low resistance state; when the magnetic field directions of the free and fixed layers are opposite, the MTJ exhibits a high resistance state. By detecting the resistance of the MTJ, the stored data ("0" or "1") can be determined.

[0003] Traditional spin-transfer torque magnetic random access memory (STT-MRAM) utilizes the spin angular momentum transfer of electrons, i.e., the transfer of angular momentum of spin-polarized electrons to the magnetic material in the free layer. With the discovery of the spin-orbit moment effect, a new type of magnetic random access memory (SOT-MRAM) has been proposed. SOT-MRAM is based on spin-orbit coupling, using charge-induced spin current to generate spin-transfer torque, thereby achieving the control of magnetic memory cells. However, how to increase the placement density of MTJs in MRAM remains a pressing problem. Summary of the Invention

[0004] This disclosure provides a magnetic storage structure, a magnetic storage array structure, a control method thereof, and a memory, which at least helps to increase the layout density of magnetic tunnel junctions and transistors in the magnetic storage structure, thereby increasing the amount of data stored in a unit space by the magnetic storage structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a magnetic storage structure, including: two magnetic tunnel junctions, each magnetic tunnel junction including a fixed layer and a free layer; a spin-orbit coupling layer corresponding to each magnetic tunnel junction, the spin-orbit coupling layer being located on the side of the free layer away from the fixed layer; a first transistor and a second transistor, one of the spin-orbit coupling layers being electrically connected to the source or drain of the first transistor, and the other spin-orbit coupling layer being electrically connected to the source or drain of the second transistor; and a third transistor, the source or drain of the third transistor being electrically connected to the fixed layer of both magnetic tunnel junctions.

[0006] In some embodiments, the first transistor, the second transistor, and the third transistor are all vertical all-around gate transistor structures.

[0007] In some embodiments, the arrangement directions of the first transistor and the second transistor, the arrangement directions of the first transistor and the third transistor, and the arrangement directions of the second transistor and the third transistor intersect each other.

[0008] In some embodiments, the first transistor and the third transistor are arranged along a first direction, and the first transistor and the second transistor are arranged along a second direction, wherein the first direction and the second direction are perpendicular.

[0009] In some embodiments, the magnetic tunnel junction electrically connected to the first transistor is arranged at a distance from the first transistor along a first direction, and the magnetic tunnel junction electrically connected to the second transistor is arranged at a distance from the second transistor along the first direction.

[0010] In some embodiments, the magnetic tunnel junction is located between the first transistor and the third transistor.

[0011] In some embodiments, the material of the spin-orbit coupling layer is at least one selected from platinum, tantalum, tungsten, iridium, gold, and titanium.

[0012] In some embodiments, the materials of the free layer and the fixed layer both include at least one of cobalt iron boron, cobalt, or nickel iron.

[0013] According to some embodiments of this disclosure, another aspect of this disclosure provides a magnetic storage array structure, including a plurality of magnetic storage structures as described in any of the preceding claims, characterized in that at least two of the magnetic storage structures are arranged at intervals along a first direction; at least two of the magnetic storage structures are arranged at intervals along a second direction, wherein two adjacent magnetic storage structures along the second direction are centrally symmetrical, and the third transistor of one of the two magnetic storage structures is arranged at intervals with the first transistor of the other along the second direction; or, two adjacent magnetic storage structures along the first direction are centrally symmetrical, and the third transistor of one of the two magnetic storage structures is arranged at intervals with the third transistor of the other along the second direction; the magnetic storage array structure further includes: a first signal line and a second signal line extending along the first direction, wherein the magnetic storage structures arranged along the first direction are electrically connected to the same first signal line and to the same second signal line; a first control line and a second control line extending along the second direction, wherein the magnetic storage structures arranged along the second direction are electrically connected to the same first control line and to the same second control line.

[0014] In some embodiments, the magnetic tunnel junction electrically connected to the first transistor is a first magnetic tunnel junction, and the magnetic tunnel junction electrically connected to the second transistor is a second magnetic tunnel junction; the first magnetic tunnel junction in the magnetic storage structure arranged along the first direction is electrically connected to the same first signal line; the second magnetic tunnel junction in the magnetic storage structure arranged along the first direction is electrically connected to the same second signal line.

[0015] In some embodiments, two adjacent magnetic storage structures along the second direction are respectively a first magnetic storage structure and a second magnetic storage structure; the same first control line electrically connects the first transistor and the second transistor in the first magnetic storage structure and the third transistor in the second magnetic storage structure; the same second control line electrically connects the first transistor and the second transistor in the second magnetic storage structure and the third transistor in the first magnetic storage structure.

[0016] In some embodiments, the same first control line electrically connects the first transistor and the second transistor in the magnetic storage structure arranged along the second direction; two adjacent magnetic storage structures along the first direction are respectively a first magnetic storage structure and a second magnetic storage structure; the same second control line electrically connects the third transistor in the first magnetic storage structure and the third transistor in the second magnetic storage structure.

[0017] In some embodiments, the magnetic storage array structure further includes: a first electrical connection layer, which is in contact with the fixing layer of the plurality of magnetic tunnel junctions arranged along the second direction; and a second electrical connection layer, one end of which is in contact with the first electrical connection layer and the other end of which is in contact with the source or drain of the third transistor.

[0018] In some embodiments, the magnetization structure direction of the magnetic tunnel junction is perpendicular to the surface of the spin-orbit coupling layer, and the free layer is located on the surface of the spin-orbit coupling layer.

[0019] In some embodiments, the magnetization structure of the magnetic tunnel junction is parallel to the surface of the spin-orbit coupling layer, and the free layer is located on the surface of the spin-orbit coupling layer.

[0020] According to some embodiments of this disclosure, another aspect of this disclosure also provides a memory whose array structure is based on the magnetic storage array structure described in any of the foregoing claims.

[0021] According to some embodiments of this disclosure, another aspect of this disclosure provides a read / write control method for a magnetic storage array structure, comprising: controlling one of a first transistor and a second transistor to be in a conducting state; controlling the current flowing through a spin-orbit coupling layer to set the state of one of the two magnetic tunnel junctions to a high-resistance state or a low-resistance state, thereby realizing a write operation on the magnetic tunnel junction, wherein the magnetic tunnel junction realizing the write operation corresponds to the first transistor in a conducting state or the second transistor in a conducting state; controlling a third transistor to be in a conducting state; and reading the magnitude of the current flowing through one of the two magnetic tunnel junctions to determine whether the magnetic tunnel junction is in a high-resistance state or a low-resistance state, thereby realizing a read operation on the magnetic tunnel junction.

[0022] In some embodiments, the magnetic tunnel junction electrically connected to the first transistor is a first magnetic tunnel junction, the spin-orbit coupling layer corresponding to the first magnetic tunnel junction is a first spin-orbit coupling layer, the magnetic tunnel junction electrically connected to the second transistor is a second magnetic tunnel junction, and the spin-orbit coupling layer corresponding to the second magnetic tunnel junction is a second spin-orbit coupling layer; the steps of implementing the read operation and the write operation include: controlling the current flowing through the first spin-orbit coupling layer through a first signal line to set the state of the first magnetic tunnel junction to a high-resistance state or a low-resistance state; controlling the current flowing through the second spin-orbit coupling layer through a second signal line to set the state of the second magnetic tunnel junction to a high-resistance state or a low-resistance state; and controlling the conduction or shutdown of the first transistor, the second transistor, and the third transistor through a first control line and a second control line.

[0023] In some embodiments, the step of controlling the magnetic storage structure to perform the write operation includes: selecting the first signal line and the first control line to turn on the first transistor, and controlling the current flowing through the first spin-orbit coupling layer to set the state of the first magnetic tunnel junction to a high-resistance state or a low-resistance state, so as to realize the write operation on the first magnetic tunnel junction; or, selecting the second signal line and the first control line to turn on the second transistor, and controlling the current flowing through the second spin-orbit coupling layer to set the state of the second magnetic tunnel junction to a high-resistance state or a low-resistance state, so as to realize the write operation on the second magnetic tunnel junction.

[0024] In some embodiments, the step of controlling the magnetic storage structure to perform the read operation includes: selecting the first signal line and the second control line to turn on the third transistor, and reading the magnitude of the current flowing through the first magnetic tunnel junction to determine whether the first magnetic tunnel junction is in a high-resistance state or a low-resistance state, so as to realize the read operation on the first magnetic tunnel junction; or, selecting the second signal line and the second control line to turn on the third transistor, and reading the magnitude of the current flowing through the second magnetic tunnel junction to determine whether the second magnetic tunnel junction is in a high-resistance state or a low-resistance state, so as to realize the read operation on the second magnetic tunnel junction.

[0025] The technical solutions provided in this disclosure have at least the following advantages:

[0026] In the magnetic storage structure, three transistors share two magnetic tunnel junctions (MTJs): the first, second, and third transistors share two MMTs. Specifically, the first transistor is electrically connected to a spin-orbit coupling layer (SOL). When the first transistor is turned on, current flows through the SOL to change the direction of the magnetic field in the free layer of the MMT corresponding to that SOL, thereby adjusting the resistance of the MMT to enable a write operation. The second transistor is electrically connected to another SOL. When the second transistor is turned on, current flows through this other SOL to change the direction of the magnetic field in the free layer of the MMT corresponding to that SOL, thereby adjusting the resistance of the MMT to enable a write operation. The third transistor is electrically connected to the fixed layers of both MMTs. When the third transistor is turned on, the resistance of one of the MMTs is detected to enable a read operation on that MMT. Thus, by using the same transistor to perform read operations on two magnetic tunnel junctions, and by using three transistors to perform write and read operations on two magnetic tunnel junctions, it is possible to store and read 2 bytes of data using three transistors and two magnetic tunnel junctions. This helps to reduce the number of transistors required to store and read 2 bytes of data, thereby increasing the layout density of magnetic tunnel junctions and transistors in the magnetic storage structure, and thus increasing the amount of data stored in a unit space. Attached Figure Description

[0027] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A three-dimensional structural schematic diagram of a magnetic storage structure provided in an embodiment of the present disclosure;

[0029] Figure 2 Another three-dimensional structural schematic diagram of a magnetic storage structure provided in an embodiment of this disclosure;

[0030] Figure 3 To and Figure 1 A top view schematic diagram of a corresponding magnetic storage structure;

[0031] Figure 4 To and Figure 2 Another top view diagram of the corresponding magnetic storage structure;

[0032] Figure 5 A flowchart illustrating a read / write control method for a magnetic storage array structure provided in another embodiment of this disclosure. Detailed Implementation

[0033] As can be seen from the background technology, the layout density of magnetic tunnel junctions and transistors in magnetic storage structures needs to be improved, and the amount of data stored in a unit space by magnetic storage structures needs to be improved.

[0034] Analysis revealed that SOT-MRAM outperforms STT-MRAM, offering faster write speeds, longer breakdown resistance, and better device reliability, along with numerous advantages such as non-volatility. However, in SOT-MRAM, the current paths for write and read operations are separate, requiring two transistors per magnetic storage cell to control the read and write operations respectively. This means SOT-MRAM typically employs a 2T-1R cell structure to store and retrieve one byte of data. This results in a larger layout area for individual magnetic storage cells, hindering the improvement of integration density and data storage capacity.

[0035] This disclosure provides a magnetic storage structure, a magnetic storage array structure, a control method thereof, and a memory. In the magnetic storage structure, a first transistor, a second transistor, and a third transistor share two magnetic tunnel junctions. The third transistor is used to perform read operations on the two magnetic tunnel junctions, while the first and second transistors are used to perform write operations on the two magnetic tunnel junctions respectively. Overall, three transistors are used to perform write and read operations on the two magnetic tunnel junctions. That is, three transistors and two magnetic tunnel junctions are used to store and read 2 bytes of data. This helps to reduce the number of transistors required to store and read 2 bytes of data, thereby improving the layout density of magnetic tunnel junctions and transistors in the magnetic storage structure, and thus increasing the amount of data stored in a unit space by the magnetic storage structure.

[0036] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0037] This disclosure provides a magnetic storage structure according to an embodiment. The magnetic storage structure provided by this disclosure will be described in detail below with reference to the accompanying drawings. Figure 1 A three-dimensional structural schematic diagram of a magnetic storage structure provided in an embodiment of the present disclosure;

[0038] Figure 2 Another three-dimensional structural schematic diagram of a magnetic storage structure provided in an embodiment of this disclosure; Figure 3 To and Figure 1 A top view schematic diagram of a corresponding magnetic storage structure; Figure 4 To and Figure 2 Another top view diagram of the corresponding magnetic storage structure. It should be noted that... Figures 1 to 4 The diagram illustrates multiple magnetic storage structures.

[0039] refer to Figures 1 to 4 The magnetic storage structure 100 includes: two magnetic tunnel junctions 110, each including a fixed layer 120 and a free layer 130; a spin-orbit coupling layer 140 corresponding to each magnetic tunnel junction 110, the spin-orbit coupling layer 140 being located on the side of the free layer 130 away from the fixed layer 120; a first transistor 101 and a second transistor 102, one spin-orbit coupling layer 140 being electrically connected to the source or drain of the first transistor 101, and the other spin-orbit coupling layer 140 being electrically connected to the source or drain of the second transistor 102; and a third transistor 103, the source or drain of the first transistor 101 being electrically connected to the fixed layer 120 in both magnetic tunnel junctions 110.

[0040] For a single magnetic storage structure 100, the first transistor 101, the second transistor 102, and the third transistor 103 share two magnetic tunnel junctions 110. The third transistor 103 is used to perform read operations on the two magnetic tunnel junctions 110, while the first transistor 101 and the second transistor 102 are used to perform write operations on the two magnetic tunnel junctions 110 respectively. In total, three transistors are used to perform both write and read operations on the two magnetic tunnel junctions 110. This means that three transistors and two magnetic tunnel junctions 110 are used to store and retrieve 2 bytes of data. This reduces the number of transistors required to store and retrieve 2 bytes of data, thereby increasing the layout density of the magnetic tunnel junctions 110 and transistors in the magnetic storage structure 100, and thus increasing the amount of data stored per unit space.

[0041] In some embodiments, continue to refer to Figure 1 and Figure 2The first transistor 101, the second transistor 102, and the third transistor 103 are all vertical gate-all-around (VGAA) transistor structures. This helps to reduce the layout area of ​​the transistors in the horizontal direction, i.e., the plane perpendicular to the Z direction, so that the word lines used to control the transistor channel region and the bit lines connected to the source or drain of the transistor are arranged in the Z direction. This is beneficial for forming a 3D stacked magnetic memory structure 100, thereby improving the integration density of the magnetic memory structure 100.

[0042] The magnetic tunnel junction 110, the first transistor 101, the second transistor 102 and the third transistor 103 are described in detail below.

[0043] In some embodiments, reference Figure 1 and Figure 2 Along the direction of the magnetic tunnel junction 110 towards the spin-orbit coupling layer 140, i.e., in the Z direction, the magnetic tunnel junction 110 includes a fixed layer 120, a tunneling layer 150, and a free layer 130 stacked sequentially. The fixed layer 120 and the free layer 130 are ferromagnetic layers, and the coercivity of the free layer 130 is less than that of the fixed layer 120. The tunneling layer 150 is a non-magnetic insulating layer. It can be understood that when the magnetic tunnel junction 110 is saturated magnetized, the magnetization directions of the fixed layer 120 and the free layer 130 are parallel to each other. When the magnetic tunnel junction 110 is reverse magnetized, the coercivity of the free layer 130 is less than that of the fixed layer 120. Therefore, the magnetization vector of the free layer 130, with its lower coercivity, flips first, causing the magnetization directions of the fixed layer 120 and the free layer 130 to become antiparallel. Furthermore, the probability of an electron tunneling from one ferromagnetic layer to another is related to the magnetization directions of the two ferromagnetic layers. If the magnetization directions of the fixed layer 120 and the free layer 130 are parallel to each other, the probability of electrons tunneling through the fixed layer 120 and the free layer 130 is high, resulting in a low-resistance state for the magnetic tunnel junction 110. If the magnetization directions of the fixed layer 120 and the free layer 130 are opposite, the probability of electrons tunneling through the fixed layer 120 and the free layer 130 is low, resulting in a high-resistance state for the magnetic tunnel junction 110.

[0044] In some embodiments, the materials of the free layer 130 and the fixed layer 120 both include at least one of cobalt iron boron, cobalt, or nickel iron, and the material of the tunneling layer 150 can be magnesium oxide.

[0045] In some embodiments, the material of the spin-orbit coupling layer 140 may be at least one of platinum, tantalum, tungsten, iridium, gold, and titanium. Understandably, the spin-orbit coupling layer 140 is located on the side of the free layer 130 away from the fixed layer 120. The spin-orbit coupling layer 140 generates an exchange coupling field in the free layer 130 using the interlayer exchange coupling (IEC) effect. Through the spin-orbit interaction generated by the current flowing through the spin-orbit coupling layer 140, a spin current is injected into the free layer 130 to cause the magnetic moment in the free layer 130 to flip rapidly, thus not damaging the free layer 130 and the tunneling layer 150. When the magnetic field direction in the free layer 130 is the same as the magnetic field direction in the fixed layer 120, the magnetic tunnel junction 110 exhibits a low resistance state; when the magnetic field direction in the free layer 130 is opposite to the magnetic field direction in the fixed layer 120, the magnetic tunnel junction 110 exhibits a high resistance state. By detecting the resistance of the magnetic tunnel junction 110, it can be determined whether the data stored in the magnetic tunnel junction 110 is "0" or "1".

[0046] In some embodiments, reference Figure 1 and Figure 2 The first transistor 101 includes a first semiconductor channel 111 extending in the Z direction. The first semiconductor channel 111 is divided into three segments in the Z direction. The middle segment of the first semiconductor channel 111 serves as the first channel region of the first transistor 101, and the two segments of the first semiconductor channel 111 located on both sides of the first channel region serve as the source and drain terminals of the first transistor 101, respectively. The first transistor 101 also includes a first gate dielectric layer 121 and a first gate 131 that sequentially surround the sidewalls extending in the Z direction of the first channel region.

[0047] Similarly, the second transistor 102 includes a second semiconductor channel 112 extending in the Z direction. The second semiconductor channel 112 is divided into three segments in the Z direction. The middle segment of the second semiconductor channel 112 serves as the second channel region of the second transistor 102, and the two segments of the second semiconductor channel 112 located on both sides of the second channel region serve as the source and drain terminals of the second transistor 102, respectively. The second transistor 102 also includes a second gate dielectric layer 122 and a second gate 132 that sequentially surround the sidewalls extending in the Z direction of the second channel region.

[0048] Similarly, the third transistor 103 includes a third semiconductor channel 113 extending in the Z direction. The third semiconductor channel 113 is divided into three segments in the Z direction. The middle segment of the third semiconductor channel 113 serves as the third channel region of the third transistor 103, and the two segments of the third semiconductor channel 113 located on both sides of the third channel region serve as the source and drain terminals of the third transistor 103, respectively. The third transistor 103 also includes a third gate dielectric layer 123 and a third gate 133 that sequentially surround the sidewalls extending in the Z direction of the third channel region.

[0049] It should be noted that, for the sake of simplicity, Figure 3 and Figure 4 The gate dielectric layers of the first transistor 101, the second transistor 102, and the third transistor 103 are not shown in the diagram; that is, the first gate dielectric layer 121, the second gate dielectric layer 122, and the third gate dielectric layer 123 are not shown. This is understandable. Figure 3 and Figure 4 The first transistor 101 is illustrated by the first semiconductor channel 111 and the first gate 131, the second transistor 102 is illustrated by the second semiconductor channel 112 and the second gate 132, and the third transistor 103 is illustrated by the third semiconductor channel 113 and the third gate 133.

[0050] also, Figures 1 to 4 The first semiconductor channel 111, the second semiconductor channel 112, and the third semiconductor channel 113 are illustrated using three different filling methods to distinguish the first transistor 101, the second transistor 102, and the third transistor 103. In practical applications, the first transistor 101, the second transistor 102, and the third transistor 103 have the same structure and can be formed simultaneously; they only perform different functions in the magnetic storage structure 100. Furthermore, to show the positional relationships between the various structures in the magnetic storage structure 100, Figures 1 to 4 The text uses perspective drawing for some structures.

[0051] In some embodiments, reference Figure 3 and Figure 4 The arrangement directions of the first transistor 101 and the second transistor 102, the arrangement directions of the first transistor 101 and the third transistor 103, and the arrangement directions of the second transistor 102 and the third transistor 103 intersect each other.

[0052] In one example, refer to Figure 3For a single magnetic storage structure 100, the lines connecting the first transistor 101 and the second transistor 102, the first transistor 101 and the third transistor 103, and the second transistor 102 and the third transistor 103 intersect each other, and the three lines form an acute triangle. It is understood that when the first transistor 101, the second transistor 102, and the third transistor 103 are each considered as an individual transistor, and multiple magnetic storage structures 100 are arranged according to a preset rule, the multiple individual transistors are arranged in a parallelogram array. The arrangement of the multiple individual transistors will be described in detail later in the second embodiment of this disclosure.

[0053] In another example, refer to Figure 4 The first transistor 101 and the third transistor 103 are arranged along the first direction X, and the first transistor 101 and the second transistor 102 are arranged along the second direction Y, with the first direction X and the second direction Y being perpendicular. Thus, for a single magnetic storage structure 100, the lines connecting the first transistor 101 and the second transistor 102, the lines connecting the first transistor 101 and the third transistor 103, and the lines connecting the second transistor 102 and the third transistor 103 intersect each other, and the three lines form a right-angled triangle. It can be understood that when the first transistor 101, the second transistor 102, and the third transistor 103 are each considered as an individual transistor, and multiple magnetic storage structures 100 are included according to a preset rule, the multiple individual transistors are arranged in a rectangular array. The arrangement of the multiple individual transistors will be described in detail later in the second embodiment of this disclosure.

[0054] In some embodiments, reference Figures 1 to 4 The magnetic tunnel junction 110, electrically connected to the first transistor 101, is arranged at intervals along the first direction X. The magnetic tunnel junction 110, electrically connected to the second transistor 102, is also arranged at intervals along the first direction X. In one example, the spin-orbit coupling layer 140 also extends along the first direction X and corresponds one-to-one with the magnetic tunnel junction 110. The spin-orbit coupling layer 140 is simultaneously electrically connected to a free layer 130 and a first semiconductor channel 111 of the first transistor 101 to achieve electrical connection between the first transistor 101 and the magnetic tunnel junction 110; or the spin-orbit coupling layer 140 is simultaneously electrically connected to a free layer 130 and a second semiconductor channel 112 of the second transistor 102 to achieve electrical connection between the second transistor 102 and the magnetic tunnel junction 110.

[0055] In some embodiments, reference Figures 1 to 4The magnetic tunnel junction 110 is located between the first transistor 101 and the third transistor 103. In one example, the first transistor 101 and the second transistor 102 are arranged in an array along the second direction Y, and along the first direction X, the first transistor 101, the magnetic tunnel junction 110 and the third transistor 103 are arranged in sequence at intervals, such that the magnetic tunnel junction 110 is located between the first transistor 101 and the third transistor 103. Understandably, when the two free layers 130 of the two magnetic tunnel junctions 110 are required to be electrically connected to the first transistor 101 and the second transistor 102 respectively, and the two fixed layers 120 of the two magnetic tunnel junctions 110 are both electrically connected to the third transistor 103, the location of the magnetic tunnel junction 110 between the first transistor 101 and the third transistor 103 is beneficial to reducing the wiring length of the wiring layers provided in the magnetic storage structure 100. Specifically, making the distance between the magnetic tunnel junction 110 and the first transistor 101, the second transistor 102, and the third transistor 103 shorter is beneficial to reducing the wiring length of the wiring layer that realizes the electrical connection between the magnetic tunnel junction 110 and the first transistor 101 and the second transistor 102, i.e., the spin-orbit coupling layer 140, and also reducing the wiring length of the wiring layer that realizes the electrical connection between the magnetic tunnel junction 110 and the third transistor 103. In one example, the two magnetic tunnel junctions can be arranged at intervals along the second direction Y.

[0056] In some embodiments, reference Figure 1 and Figure 2 The magnetic storage structure may further include: a first conductive post 117, located between the first transistor 101 and the spin-orbit coupling layer 140, and contacted and connected to the first semiconductor channel 111 in the first transistor 101 and the spin-orbit coupling layer 140, respectively; and a second conductive post 127, located between the second transistor 102 and the spin-orbit coupling layer 140, and contacted and connected to the second semiconductor channel 112 in the second transistor 102 and the spin-orbit coupling layer 140, respectively. It should be noted that in practical applications, the first semiconductor channel 111 in the first transistor 101 can be directly contacted and connected to the spin-orbit coupling layer 140, and the second semiconductor channel 112 in the second transistor 102 can also be directly contacted and connected to the spin-orbit coupling layer 140.

[0057] In some embodiments, the electrical connection between the two magnetic tunnel junctions 110 and the third transistor 103 is achieved as follows: (Refer to...) Figures 1 to 4 The magnetic storage structure may further include: a first electrical connection layer 116, which is in contact with the fixing layers 120 of the two magnetic tunnel junctions 110; and a second electrical connection layer 126, one end of which is in contact with the first electrical connection layer 116, and the other end of which is electrically connected to the source or drain of the third transistor 103.

[0058] In some embodiments, the magnetic storage structure may further include a third conductive post 137, located between the third transistor 103 and the second electrical connection layer 126, and respectively contacting and connecting to the third semiconductor channel 113 in the third transistor 103 and the second electrical connection layer 126. It should be noted that in practical applications, the third semiconductor channel 113 in the third transistor 103 may be directly contacted and connected to the second electrical connection layer 126.

[0059] In summary, for a single magnetic storage structure 100, the first transistor 101, the second transistor 102, and the third transistor 103 share two magnetic tunnel junctions 110. The third transistor 103 is used to perform read operations on the two magnetic tunnel junctions 110, while the first transistor 101 and the second transistor 102 are used to perform write operations on the two magnetic tunnel junctions 110 respectively. Overall, three transistors are used to perform both write and read operations on the two magnetic tunnel junctions 110. That is, three transistors and two magnetic tunnel junctions 110 are used to store and read 2 bytes of data. This helps to reduce the number of transistors required to store and read 2 bytes of data, thereby increasing the layout density of the magnetic tunnel junctions 110 and transistors in the magnetic storage structure 100, and thus increasing the amount of data stored in a unit space by the magnetic storage structure 100.

[0060] Another embodiment of this disclosure also provides a magnetic storage array structure, including a plurality of magnetic storage structures 100 as described in one embodiment of this disclosure. The following will be combined with... Figures 1 to 4 A magnetic storage array structure according to another embodiment of this disclosure will be described in detail. It should be noted that the parts that are the same as or corresponding to those in the foregoing embodiments will not be repeated here.

[0061] refer to Figure 3 and Figure 4 The magnetic storage array structure includes a magnetic storage structure 100, wherein at least two magnetic storage structures 100 are arranged at intervals along a first direction X; and at least two magnetic storage structures 100 are arranged at intervals along a second direction Y.

[0062] The following describes in detail the arrangement of multiple magnetic storage structures 100 through two embodiments.

[0063] In some embodiments, reference Figure 1 and Figure 3Two adjacent magnetic storage structures 100 along the second direction Y are centrally symmetrical, and the third transistor 103 of one magnetic storage structure 100 is spaced apart from the first transistor 101 of the other along the second direction Y. It can be understood that for the two adjacent magnetic storage structures 100 along the second direction Y, all four magnetic tunnel junctions 110 are spaced apart along the second direction Y. The third transistor 103 of one structure faces the first transistor 101 of the other along the second direction Y, and the second transistor 102 of one structure faces the third transistor 103 of the other along the second direction Y. This facilitates the placement of three transistors on each side of the magnetic tunnel junction 110 along the first direction X, namely the first transistor 101, the second transistor 102, and the third transistor 103. This reduces the layout space of the two adjacent magnetic storage structures 100 along the second direction Y in the magnetic storage array structure, thereby increasing the integration density of the magnetic storage structures 100 in the magnetic storage array structure.

[0064] In addition, Figure 1 and Figure 3 In the magnetic storage array structure shown, the first transistor 101, the second transistor 102, and the third transistor 103 are each treated as individual transistors, arranged in a parallelogram array. This ensures a regular arrangement of the magnetic storage structures 100, facilitating the fabrication of the magnetic storage array structure and enabling unified control of multiple magnetic storage structures 100, while also achieving a hexagonal close-packed configuration. Furthermore, two adjacent magnetic storage structures 100 along the second direction Y can be considered as a single unit. Figure 1 The partial structure shown above, in the magnetic storage array structure, arranges the above whole along the first direction X and the second direction Y at intervals, which is beneficial to further improve the integration density of the magnetic storage structure 100 in the magnetic storage array structure.

[0065] In other embodiments, reference is made to Figure 2 and Figure 4Two adjacent magnetic storage structures 100 along the first direction X are centrally symmetrical, and the third transistor 103 of one of the two magnetic storage structures 100 is arranged at intervals along the second direction Y. It can be understood that for the two adjacent magnetic storage structures 100 along the first direction X, the two third transistors 103 are arranged at intervals along the second direction Y, the first transistor 101 of one structure is directly opposite the second transistor 102 of the other structure along the first direction X, and the second transistor 102 of one structure is directly opposite the first transistor 101 of the other structure along the first direction X. Their magnetic tunnel junctions 110 are also directly opposite each other along the first direction X. This facilitates the placement of two transistors on each side of the magnetic tunnel junction 110 along the first direction X, thereby reducing the layout space of the two adjacent magnetic storage structures 100 along the first direction X in the magnetic storage array structure and increasing the integration density of the magnetic storage structures 100 in the magnetic storage array structure.

[0066] In addition, Figure 2 and Figure 4 In the magnetic storage array structure shown, the first transistor 101, the second transistor 102, and the third transistor 103 are each treated as individual transistors, resulting in a rectangular array arrangement. This ensures a regular arrangement of the magnetic storage structures 100, facilitating the fabrication of the magnetic storage array structure and enabling unified control of multiple magnetic storage structures 100. It also achieves a densely packed, four-sided stacking configuration. Furthermore, two adjacent magnetic storage structures 100 along the first direction X can be considered as a single unit. Figure 2 The partial structure shown above, in the magnetic storage array structure, arranges the above whole along the first direction X and the second direction Y at intervals, which is beneficial to further improve the integration density of the magnetic storage structure 100 in the magnetic storage array structure.

[0067] In the above embodiments, reference is made to Figures 1 to 4 The magnetic storage array structure may further include: a first signal line 114 and a second signal line 124 extending along the first direction X. The magnetic storage structure 100 arranged along the first direction X is electrically connected to the same first signal line 114 and to the same second signal line 124.

[0068] In one example, refer to Figure 3 The spin-orbit coupling layers 140 corresponding to the first transistors 101 arranged along the first direction X are all electrically connected to the same first signal line 114, and the spin-orbit coupling layers 140 corresponding to the second transistors 102 arranged along the first direction X are all electrically connected to the same second signal line 124. In another example, refer to... Figure 4The first transistor 101 and the second transistor 102 are arranged alternately along the first direction X, and the first transistor 101 and the second transistor 102 arranged alternately along the first direction X are electrically connected to the same first signal line 114 or the same second signal line 124.

[0069] It is understandable that multiple magnetic storage structures 100 arranged along the first direction X can share a first signal line 114 and a second signal line 124, which helps to reduce the control ports of the first signal line 114 and the second signal line 124 and improve the control capability of the magnetic storage array.

[0070] It should be noted that the reference Figure 1 and Figure 2 The magnetic storage array structure further includes a fourth conductive post 147, wherein the fourth conductive post 147 is located between the spin-orbit coupling layer 140 and the first signal line 114 to achieve an electrical connection between the spin-orbit coupling layer 140 and the first signal line 114; or, the fourth conductive post 147 is located between the spin-orbit coupling layer 140 and the second signal line 124 to achieve an electrical connection between the spin-orbit coupling layer 140 and the second signal line 124.

[0071] refer to Figure 3 and Figure 4 The magnetic storage array structure may further include: a first control line 115 and a second control line 125 extending along the second direction Y. The magnetic storage structure 100 arranged along the second direction Y is electrically connected to the same first control line 115 and to the same second control line 125.

[0072] In one example, refer to Figure 3 The transistors located on one side of the magnetic tunnel junction 110 are arranged in the order of first transistor 101, second transistor 102, and third transistor 103, and so on, alternating in the second direction Y. The transistors located on the other side of the magnetic tunnel junction 110 are arranged in the order of third transistor 103, second transistor 102, and first transistor 101, and so on, alternating in the second direction Y. The gates of the transistors arranged in the order of first transistor 101, second transistor 102, and third transistor 103, alternating in the second direction Y, are all electrically connected to the first control line 115. The gates of the transistors arranged in the order of third transistor 103, second transistor 102, and first transistor 101, alternating in the second direction Y, are all electrically connected to the second control line 125.

[0073] In another example, refer to Figure 4The first transistor 101 and the second transistor 102, which are alternately arranged along the second direction Y, are both electrically connected to the same first control line 115, and the third transistors 103, which are spaced apart along the second direction Y, are all electrically connected to the same second control line 125. Thus, the two third transistors 103 of the two adjacent and centrally symmetrical magnetic storage structures 100 in the first direction X can share the second control line 125, which helps to further reduce the number of control ports on the second control line 125 and improves the control capability of the magnetic storage array.

[0074] also, Figure 3 and Figure 4 In the example shown, multiple magnetic storage structures 100 arranged along the second direction Y can share a first control line 115 and a second control line 125, which helps to reduce the number of control ports of the first control line 115 and the second control line 125 and improve the control capability of the magnetic storage array.

[0075] It should be noted that, for the sake of clarity of the illustration, Figure 1 and Figure 2 The first control line 115 and the second control line 125 are not shown in the diagram. (Reference) Figure 3 and Figure 4 The first control line 115 is connected to a plurality of gates arranged along the second direction Y, and the second control line 125 is also connected to a plurality of gates arranged along the second direction Y.

[0076] In some embodiments, reference Figures 1 to 4 The magnetic tunnel junction 110 electrically connected to the first transistor 101 is called the first magnetic tunnel junction 110a, and the magnetic tunnel junction 110 electrically connected to the second transistor 102 is called the second magnetic tunnel junction 110b. The first magnetic tunnel junction 110a in the magnetic storage structure 100 arranged along the first direction X is electrically connected to the same first signal line 114; the second magnetic tunnel junction 110b in the magnetic storage structure 100 arranged along the first direction X is electrically connected to the same second signal line 124. It can be understood that the first signal line 114 is used for write or read operations on the first magnetic tunnel junction 110a, and the second signal line 124 is used for write or read operations on the second magnetic tunnel junction 110b.

[0077] In some embodiments, reference Figure 1 and Figure 3Two adjacent magnetic storage structures 100 along the second direction Y are respectively a first magnetic storage structure 100a and a second magnetic storage structure 100b; the same first control line 115 is electrically connected to the first transistor 101 and the second transistor 102 in the first magnetic storage structure 100a and the third transistor 103 in the second magnetic storage structure 100b, so as to control the above three transistors to be in the on state or the off state; the same second control line 125 is electrically connected to the first transistor 101 and the second transistor 102 in the second magnetic storage structure 100b and the third transistor 103 in the first magnetic storage structure 100a, so as to control the above three transistors to be in the on state or the off state.

[0078] In other embodiments, reference is made to Figure 2 and Figure 4 The first control line 115 is electrically connected to the first transistor 101 and the second transistor 102 in the magnetic storage structure 100 arranged along the second direction Y, so as to control the first transistor 101 and the second transistor 102 to be in the on state or the off state; the two adjacent magnetic storage structures 100 along the first direction X are the first magnetic storage structure 100a and the second magnetic storage structure 100b, respectively; the second control line 125 is electrically connected to the third transistor 103 in the first magnetic storage structure 100a and the third transistor 103 in the second magnetic storage structure 100b, so as to control the third transistor 103 to be in the on state or the off state.

[0079] In some embodiments, the magnetic storage array structure may further include: a first electrical connection layer 116, which is in contact with a fixing layer 120 of a plurality of magnetic tunnel junctions 110 arranged along the second direction Y; and a second electrical connection layer 126, one end of which is in contact with the first electrical connection layer 116, and the other end of which is in contact with the source or drain of the third transistor 103.

[0080] It should be noted that, Figures 1 to 4 The example in which the first electrical connection layer 116 corresponds one-to-one with the magnetic storage structure 100 is used. In practical applications, the first electrical connection layer 116 can extend along the second direction Y, and one first electrical connection layer 116 can correspond to multiple magnetic storage structures 100 arranged along the second direction Y. That is, multiple magnetic storage structures 100 arranged along the second direction Y can share one first electrical connection layer 116.

[0081] The following structure Figures 1 to 4 The principles of reading and writing operations on the magnetic storage structure 100 are explained in detail.

[0082] For the first magnetic storage structure 100a, the first gate 131 of the first transistor 101 and the second gate 132 of the second transistor 102 are connected to the first control line 115, so that the first control line 115 controls the conduction or cutoff of the first transistor 101 and the second transistor 102. The third gate 133 of the third transistor 103 is connected to the second control line 125, so that the second control line 125 controls the conduction or cutoff of the third transistor 103. The source or drain of the first transistor 101 is electrically connected to the spin-orbit coupling layer 140 corresponding to the first magnetic tunnel junction 110a, and the first magnetic tunnel junction 110a corresponds to the first signal line 114. The source or drain of the second transistor 102 is electrically connected to the spin-orbit coupling layer 140 corresponding to the second magnetic tunnel junction 110b, and the second magnetic tunnel junction 110b corresponds to the second signal line 124. Thus, writing to the first magnetic tunnel junction 110a can be controlled by the first transistor 101 and the first signal line 114, writing to the second magnetic tunnel junction 110b can be controlled by the second transistor 102 and the second signal line 124, reading from the first magnetic tunnel junction 110a can be controlled by the third transistor 103 and the first signal line 114, and reading from the second magnetic tunnel junction 110b can be controlled by the third transistor 103 and the second signal line 124, thereby distinguishing the read and write paths so as to optimize reading and writing separately.

[0083] In some embodiments, the magnetization direction of the magnetic tunnel junction 110 is perpendicular to the surface of the spin-orbit coupling layer 140, and the free layer 130 is located on the surface of the spin-orbit coupling layer 140. In other embodiments, the magnetization direction of the magnetic tunnel junction 110 is parallel to the surface of the spin-orbit coupling layer 140, and the free layer 130 is located on the surface of the spin-orbit coupling layer 140.

[0084] For example, when the magnetization direction of the magnetic tunnel junction 110 is perpendicular to the surface of the spin-orbit coupling layer 140, the magnetic field direction in the free layer 130 can be transformed into a direction perpendicular to and towards the surface of the spin-orbit coupling layer 140, or into a direction perpendicular to and away from the surface of the spin-orbit coupling layer 140; the magnetic field direction in the fixed layer 120 can be fixed as a direction perpendicular to and away from the surface of the spin-orbit coupling layer 140, or fixed as a direction perpendicular to and towards the surface of the spin-orbit coupling layer 140. When the free layer 130 undergoes a magnetic field direction transformation due to the spin-orbit interaction in the spin-orbit coupling layer 140, and the magnetic field direction in the free layer 130 becomes the same as the magnetic field direction in the fixed layer 120, then the magnetic tunnel junction 110 exhibits a low-resistance state; when the magnetic field direction in the free layer 130 becomes opposite to the magnetic field direction in the fixed layer 120, then the magnetic tunnel junction 110 exhibits a high-resistance state. Furthermore, the magnetization structure direction of the magnetic tunnel junction 110 can also be parallel to the surface of the spin-orbit coupling layer 140. That is, the magnetic field direction within the fixed layer 120 of the magnetic tunnel junction 110 is parallel to the surface of the spin-orbit coupling layer 140, and the magnetic field direction within the free layer 130 can be the same as or opposite to the magnetic field direction of the fixed layer 120. Correspondingly, the magnetic field directions of the free layer 130 and the fixed layer 120 determine the magnitude of the resistive state of the magnetic tunnel junction 110. It is understood that the magnetization structure direction of the magnetic tunnel junction 110 can be selected and determined according to actual conditions, and this embodiment does not excessively limit the magnetization structure direction of the magnetic tunnel junction 110.

[0085] In summary, the magnetic storage structure 100 in the magnetic storage array structure stores a high amount of data per unit space and reduces the number of transistors required to store and read 2 bytes of data. This benefits the magnetic storage array structure by increasing the amount of data stored per unit space and reducing the number of transistors required to store and read a certain size of data. Furthermore, using… Figure 3 or Figure 4 The arrangement of the magnetic storage structure 100 in the magnetic storage array structure shown is beneficial to increasing the integration density of the magnetic storage structure 100 in the magnetic storage array structure, and reducing the number of the first signal line 114, the second signal line 124, the first control line 115 and the second control line 125 required, so as to reduce the control ports of the first signal line 114, the second signal line 124, the first control line 115 and the second control line 125, and improve the control capability of the magnetic storage array.

[0086] Another embodiment of this disclosure also provides a memory, the array structure of which is based on the magnetic storage array structure described in another embodiment of this disclosure. It should be noted that parts that are the same as or corresponding to those in the foregoing embodiments will not be repeated here.

[0087] It is understood that if the array structure of the memory is set based on the magnetic storage array structure described in another embodiment of this disclosure, it is beneficial to increase the amount of data stored in the memory per unit space, improve the memory's control over the magnetic storage array, and increase the integration density of the magnetic storage array structure in the memory.

[0088] Specifically, memory can be a storage cell or device based on a semiconductor device or component. For example, memory can be volatile memory, such as dynamic random access memory (DRAM), or it can be non-volatile memory, such as phase-change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), etc.

[0089] In another embodiment of this disclosure, a read / write control method for a magnetic storage array structure is provided for controlling the magnetic storage array structure or the magnetic storage structure within the magnetic storage array structure provided in the foregoing embodiments. The following will be combined with... Figures 1 to 5 A detailed description of the read / write control method for a magnetic storage array structure provided in another embodiment of this disclosure will be given. It should be noted that parts that are the same as or corresponding to those in the foregoing embodiments will not be repeated here.

[0090] Figure 5 A flowchart illustrating a read / write control method for a magnetic storage array structure provided in another embodiment of this disclosure.

[0091] refer to Figure 5 The read / write control method for a magnetic storage array structure includes the following steps:

[0092] S101: Control one of the first transistor 101 and the second transistor 102 to be in the on state; control the current flowing through the spin-orbit coupling layer 140 to set the state of one of the two magnetic tunnel junctions 110 to a high-resistance state or a low-resistance state, so as to realize the write operation of the magnetic tunnel junction 110, wherein the magnetic tunnel junction 110 that realizes the write operation corresponds to the first transistor 101 in the on state or the second transistor 102 in the on state.

[0093] S102: Control the third transistor 103 to be in the on state; read the magnitude of the current flowing through one of the two magnetic tunnel junctions 110 to determine whether the magnetic tunnel junction 110 is in a high-resistance state or a low-resistance state, so as to realize the read operation of the magnetic tunnel junction 110.

[0094] In some embodiments, the magnetic tunnel junction 110 electrically connected to the first transistor 101 is a first magnetic tunnel junction 110a, the spin-orbit coupling layer 140 corresponding to the first magnetic tunnel junction 110a is a first spin-orbit coupling layer 140a, the magnetic tunnel junction 110 electrically connected to the second transistor 102 is a second magnetic tunnel junction 110b, and the spin-orbit coupling layer 140 corresponding to the second magnetic tunnel junction 110b is a second spin-orbit coupling layer 140b.

[0095] Therefore, the steps to implement read and write operations can include: referring to... Figures 1 to 4 The first signal line 114 controls the current flowing through the first spin-orbit coupling layer 140a to set the state of the first magnetic tunnel junction 110a to a high-resistance state or a low-resistance state; the second signal line 124 controls the current flowing through the second spin-orbit coupling layer 140b to set the state of the second magnetic tunnel junction 110b to a high-resistance state or a low-resistance state; the first control line 115 and the second control line 125 control the conduction or shutdown of the first transistor 101, the second transistor 102 and the third transistor 103.

[0096] In some embodiments, in conjunction with reference Figure 1 and Figure 3 The steps for controlling the magnetic storage structure 100 to perform write operations can include the following two methods:

[0097] In some embodiments, the first signal line 114 and the first control line 115 are selected to turn on the first transistor 101 and control the current flowing through the first spin-orbit coupling layer 140a to set the state of the first magnetic tunnel junction 110a to a high-resistance state or a low-resistance state, so as to realize the write operation of the first magnetic tunnel junction 110a.

[0098] In one example, when a write operation is required on the first magnetic tunnel junction 110a in the first magnetic storage structure 100a, a conduction voltage is applied to the first control line 115 corresponding to the first magnetic storage structure 100a, i.e., the first control line 115 is turned on, making the first transistor 101 conduct. Then, a voltage is applied to the first signal line 114, i.e., the first signal line 114 is turned on. At this time, the current flows through the first signal line 114, the first spin-orbit coupling layer 140a, and the first transistor 101. It can be understood that when a positive write voltage or a negative write voltage is applied to the first signal line 114, the current flowing through the first spin-orbit coupling layer 140a generates spin-orbit interaction, thereby injecting spin current into the free layer 130 and causing the magnetic moment in the free layer 130 to flip rapidly, making the state of the first magnetic tunnel junction 110a a high-resistance state or a low-resistance state.

[0099] In other embodiments, the second signal line 124 and the first control line 115 are selected to turn on the second transistor 102 and control the current flowing through the second spin-orbit coupling layer 140b to set the state of the second magnetic tunnel junction 110b to a high-resistance state or a low-resistance state, so as to realize the write operation of the second magnetic tunnel junction 110b.

[0100] In one example, when a write operation is required on the second magnetic tunnel junction 110b in the first magnetic storage structure 100a, a conduction voltage is applied to the first control line 115 corresponding to the second magnetic tunnel junction 110b, i.e., the first control line 115 is turned on, causing the second transistor 102 to conduct. Then, a voltage is applied to the second signal line 124, i.e., the second signal line 124 is turned on. At this time, current flows through the second signal line 124, the second spin-orbit coupling layer 140b, and the second transistor 102. It can be understood that applying a positive or negative write voltage to the second signal line 124 causes the current flowing through the second spin-orbit coupling layer 140b to generate spin-orbit interaction, thereby injecting spin current into the free layer 130 and causing the magnetic moment within the free layer 130 to rapidly flip, resulting in the second magnetic tunnel junction 110b being in a high-resistance state or a low-resistance state.

[0101] In some embodiments, the step of controlling a portion of the magnetic storage structure 100 to perform a read operation may include the following two methods:

[0102] In some embodiments, the first signal line 114 and the second control line 125 are selected to turn on the third transistor 103, and the magnitude of the current flowing through the first magnetic tunnel junction 110a is read to determine whether the first magnetic tunnel junction 110a is in a high-resistance state or a low-resistance state, so as to realize the read operation of the first magnetic tunnel junction 110a.

[0103] In one example, when it is necessary to read data stored in the first magnetic tunnel junction 110a in the first magnetic storage structure 100a, a conduction voltage is applied to the second control line 125 corresponding to the first magnetic storage structure 100a, that is, the second control line 125 is turned on, causing the third transistor 103 to conduct, and then the first signal line 114 is turned on, so that current can pass through the first signal line 114, the first magnetic tunnel junction 110a, the first electrical connection layer 116, the second electrical connection layer 126, and the third transistor 103. In this way, the resistance of the first magnetic tunnel junction 110a can be detected through the first signal line 114 and the end of the third transistor 103 away from the second electrical connection layer 126. If the first magnetic tunnel junction 110a is in a high resistance state, the stored data is "1"; if the first magnetic tunnel junction 110a is in a low resistance state, the stored data is "0".

[0104] In other embodiments, the steps of controlling the magnetic storage structure 100 to perform a read operation may include: selecting the second signal line 124 and the second control line 125 to turn on the third transistor 103, and reading the magnitude of the current flowing through the second magnetic tunnel junction 110b to determine whether the second magnetic tunnel junction 110b is in a high-resistance state or a low-resistance state, so as to realize the read operation on the second magnetic tunnel junction 110b.

[0105] In one example, when it is necessary to read data stored in the second magnetic tunnel junction 110b in the second magnetic storage structure 100b, a conduction voltage is applied to the second control line 125 corresponding to the second magnetic storage structure 100b, that is, the second control line 125 is turned on, causing the third transistor 103 to conduct, and then the second signal line 124 is turned on, so that current can pass through the second signal line 124, the second magnetic tunnel junction 110b, the first electrical connection layer 116, the second electrical connection layer 126, and the third transistor 103. In this way, the resistance of the second magnetic tunnel junction 110b can be detected through the second signal line 124 and the end of the third transistor 103 away from the second electrical connection layer 126. If the second magnetic tunnel junction 110b is in a high resistance state, the stored data is "1"; if the second magnetic tunnel junction 110b is in a low resistance state, the stored data is "0".

[0106] In summary, the read / write control method for the magnetic storage array structure provided in another embodiment of this disclosure can utilize three transistors and two magnetic tunnel junctions 110 to store and read 2 bytes of data. This is beneficial for increasing the amount of data stored in a unit space by the magnetic storage structure 100 and / or the magnetic storage array structure, and for reducing the number of transistors required to store and read a certain size of data. In addition, it is beneficial for reducing the number of first signal lines 114, second signal lines 124, first control lines 115, and second control lines 125 required, thereby reducing the number of control ports for the first signal lines 114, second signal lines 124, first control lines 115, and second control lines 125, and reducing the complexity of read / write control for the magnetic storage array structure.

[0107] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A magnetic storage structure, characterized by, include: Two magnetic tunnel junctions, each comprising a fixed layer and a free layer; A spin-orbit coupling layer corresponding to each of the magnetic tunnel junctions is located on the side of the free layer away from the fixed layer. The first transistor and the second transistor, one of the spin-orbit coupling layers is electrically connected to the source or drain of the first transistor, and the other spin-orbit coupling layer is electrically connected to the source or drain of the second transistor. The third transistor, the source or drain of which is electrically connected to the fixed layer in both of the magnetic tunnel junctions; The arrangement directions of the first transistor and the second transistor, the arrangement directions of the first transistor and the third transistor, and the arrangement directions of the second transistor and the third transistor intersect each other.

2. The magnetic storage structure of claim 1, wherein, The first transistor, the second transistor, and the third transistor are all vertical all-around gate transistor structures.

3. The magnetic storage structure of claim 1, wherein, The first transistor and the third transistor are arranged along a first direction, and the first transistor and the second transistor are arranged along a second direction, wherein the first direction and the second direction are perpendicular.

4. The magnetic storage structure of claim 1 or 2, wherein, The magnetic tunnel junction electrically connected to the first transistor is arranged at a distance from the first transistor along a first direction, and the magnetic tunnel junction electrically connected to the second transistor is arranged at a distance from the second transistor along the first direction.

5. The magnetic storage structure of claim 1 or 2, wherein, The magnetic tunnel junction is located between the first transistor and the third transistor.

6. The magnetic storage structure of claim 1 or 2, wherein, The material of the spin-orbit coupling layer is at least one of platinum, tantalum, tungsten, iridium, gold, and titanium.

7. The magnetic storage structure as described in claim 1 or 2, characterized in that, The materials of the free layer and the fixed layer both include at least one of cobalt iron boron, cobalt, or nickel iron.

8. A magnetic storage array structure, characterized in that, It includes a plurality of magnetic storage structures as described in any one of claims 1 to 7, characterized in that, At least two of the magnetic storage structures are arranged at intervals along a first direction; At least two of the magnetic storage structures are arranged at intervals along a second direction, wherein two adjacent magnetic storage structures along the second direction are centrally symmetrical, and the third transistor of one of the two magnetic storage structures is arranged at intervals with the first transistor of the other along the second direction; or, two adjacent magnetic storage structures along the first direction are centrally symmetrical, and the third transistor of one of the two magnetic storage structures is arranged at intervals with the third transistor of the other along the second direction. The magnetic storage array structure also includes: The first signal line and the second signal line extending along the first direction, the magnetic storage structure arranged along the first direction are electrically connected to the same first signal line and to the same second signal line; The first control line and the second control line extending along the second direction, the magnetic storage structure arranged along the second direction are electrically connected to the same first control line and to the same second control line.

9. The magnetic storage array structure as described in claim 8, characterized in that, The magnetic tunnel junction electrically connected to the first transistor is a first magnetic tunnel junction, and the magnetic tunnel junction electrically connected to the second transistor is a second magnetic tunnel junction; The first magnetic tunnel junction in the magnetic storage structure arranged along the first direction is electrically connected to the same first signal line; The second magnetic tunnel junction in the magnetic storage structure arranged along the first direction is electrically connected to the same second signal line.

10. The magnetic storage array structure of claim 8, wherein, The two adjacent magnetic storage structures along the second direction are respectively the first magnetic storage structure and the second magnetic storage structure; The same first control line electrically connects the first transistor and the second transistor in the first magnetic storage structure, as well as the third transistor in the second magnetic storage structure; The same second control line electrically connects the first transistor and the second transistor in the second magnetic storage structure, as well as the third transistor in the first magnetic storage structure.

11. The magnetic storage array structure as described in claim 8, characterized in that, The first control line is electrically connected to the first transistor and the second transistor in the magnetic storage structure arranged along the second direction; The two adjacent magnetic storage structures along the first direction are respectively the first magnetic storage structure and the second magnetic storage structure; The same second control line is electrically connected to the third transistor in the first magnetic storage structure and the third transistor in the second magnetic storage structure.

12. The magnetic storage array structure of claim 8, wherein, Also includes: The first electrical connection layer is in contact with the fixing layer of the plurality of magnetic tunnel junctions arranged along the second direction; The second electrical connection layer has one end in contact with the first electrical connection layer and the other end in contact with the source or drain of the third transistor.

13. The magnetic storage array structure of claim 8, wherein, The magnetization structure of the magnetic tunnel junction is perpendicular to the surface of the spin-orbit coupling layer, and the free layer is located on the surface of the spin-orbit coupling layer.

14. The magnetic storage array structure as described in claim 8, characterized in that, The magnetization structure of the magnetic tunnel junction is parallel to the surface of the spin-orbit coupling layer, and the free layer is located on the surface of the spin-orbit coupling layer.

15. A memory, the array structure of which is based on the magnetic storage array structure of any one of claims 8 to 14.

16. A read / write control method for a magnetic storage array structure, wherein the magnetic storage array structure comprises a plurality of magnetic storage structures as described in any one of claims 1 to 7, characterized in that, include: Control one of the first transistor and the second transistor to be in the on state; The current flowing through the spin-orbit coupling layer is controlled to set one of the two magnetic tunnel junctions to a high-resistance state or a low-resistance state, so as to realize the write operation of the magnetic tunnel junction, wherein the magnetic tunnel junction that realizes the write operation corresponds to the first transistor in the on state or the second transistor in the on state. Control the third transistor to be in the on state; The magnitude of the current flowing through one of the two magnetic tunnel junctions is read to determine whether the magnetic tunnel junction is in a high-resistance state or a low-resistance state, thereby enabling a read operation on the magnetic tunnel junction.

17. The read / write control method of claim 16, wherein, The magnetic tunnel junction electrically connected to the first transistor is a first magnetic tunnel junction, the spin-orbit coupling layer corresponding to the first magnetic tunnel junction is a first spin-orbit coupling layer, the magnetic tunnel junction electrically connected to the second transistor is a second magnetic tunnel junction, and the spin-orbit coupling layer corresponding to the second magnetic tunnel junction is a second spin-orbit coupling layer. The steps to implement the read operation and the write operation include: The current flowing through the first spin-orbit coupling layer is controlled by the first signal line to set the state of the first magnetic tunnel junction to a high-resistance state or a low-resistance state. The current flowing through the second spin-orbit coupling layer is controlled by the second signal line to set the state of the second magnetic tunnel junction to a high-resistance state or a low-resistance state. The first control line and the second control line control the conduction or shutdown of the first transistor, the second transistor, and the third transistor.

18. The read / write control method of claim 17, wherein, The steps for the magnetic storage structure in the control section to perform the write operation include: The first signal line and the first control line are selected to turn on the first transistor, and the current flowing through the first spin-orbit coupling layer is controlled to set the state of the first magnetic tunnel junction to a high-resistance state or a low-resistance state, so as to realize the write operation on the first magnetic tunnel junction. Alternatively, the second signal line and the first control line can be selected to turn on the second transistor and control the current flowing through the second spin-orbit coupling layer to set the state of the second magnetic tunnel junction to a high-resistance state or a low-resistance state, so as to realize the write operation on the second magnetic tunnel junction.

19. The read / write control method of claim 17, wherein, The steps for the magnetic storage structure in the control section to perform the read operation include: The first signal line and the second control line are selected to turn on the third transistor, and the magnitude of the current flowing through the first magnetic tunnel junction is read to determine whether the first magnetic tunnel junction is in a high-resistance state or a low-resistance state, so as to realize the read operation on the first magnetic tunnel junction. Alternatively, the second signal line and the second control line can be selected to turn on the third transistor and to read the magnitude of the current flowing through the second magnetic tunnel junction to determine whether the second magnetic tunnel junction is in a high-resistance state or a low-resistance state, so as to realize the read operation on the second magnetic tunnel junction.

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