Semiconductor structure, semiconductor structure manufacturing method and semiconductor device

Abstract

This disclosure relates to the semiconductor field, providing a semiconductor structure, a method for manufacturing the semiconductor structure, and a semiconductor device. The semiconductor structure includes: a logic chip having a first wireless communication unit; a plurality of memory modules stacked on the upper surface of the logic chip along a first direction parallel to the upper surface of the logic chip; a first adhesive film located between adjacent memory modules and bonded to the memory modules; each memory module including a plurality of memory chips stacked in the first direction, each memory chip having a second wireless communication unit that wirelessly communicates with the first wireless communication unit; at least one of the plurality of memory chips having a power supply wiring layer extending along the active surface of the memory chip to the logic chip. This disclosure can at least increase the number of stacked layers of memory chips and improve the performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure pertains to the field of semiconductors, specifically relating to a semiconductor structure, a method for manufacturing the semiconductor structure, and a semiconductor device. Background Technology

[0002] To improve the integration of semiconductor structures, more than one memory chip can be placed within the same package. HBM (High Bandwidth Memory) is a new type of memory. Memory chip stacking technology, represented by HBM, extends the original one-dimensional memory layout to three dimensions, that is, stacking many memory chips together and packaging them, thereby significantly increasing the density of memory chips and achieving large capacity and high bit width.

[0003] However, it is difficult to further increase the number of stacked layers of memory chips within HBM, and increasing the number of stacked layers will also affect the performance of HBM. Summary of the Invention

[0004] This disclosure provides a semiconductor structure, a method for manufacturing the semiconductor structure, and a semiconductor device, which at least facilitates increasing the number of stacked layers in memory chips and improving the performance of the semiconductor structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, wherein the semiconductor structure includes: a logic chip having a first wireless communication unit; a plurality of memory modules stacked on the upper surface of the logic chip along a first direction parallel to the upper surface of the logic chip; a first adhesive film located between adjacent memory modules and bonded to the memory modules; each memory module includes a plurality of memory chips stacked in the first direction, each memory chip having a second wireless communication unit that wirelessly communicates with the first wireless communication unit; at least one of the plurality of memory chips has a power supply wiring layer that extends along the active surface of the memory chip to the logic chip.

[0006] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for manufacturing a semiconductor structure. The method includes: providing a logic chip having a first wireless communication unit; providing a plurality of memory modules, each memory module including a plurality of memory chips stacked in a first direction, each memory chip having a second wireless communication unit that wirelessly communicates with the first wireless communication unit; at least one of the plurality of memory chips having a power supply wiring layer extending along the active surface of the memory chip to the logic chip; stacking and bonding the plurality of memory modules along the first direction using a first adhesive film, the first adhesive film being located between adjacent memory modules; and connecting the plurality of memory modules to the logic chip, with the first direction parallel to the upper surface of the logic chip.

[0007] According to some embodiments of this disclosure, another aspect of this disclosure also provides a semiconductor device, the semiconductor device comprising: a substrate; a logic chip disposed on the substrate and having a first wireless communication unit; a plurality of memory modules stacked on the upper surface of the logic chip along a first direction parallel to the upper surface of the logic chip; a first adhesive film located between adjacent memory modules and bonded to the memory modules; each memory module comprising a plurality of memory chips stacked in the first direction, each memory chip having a second wireless communication unit that wirelessly communicates with the first wireless communication unit; at least one of the plurality of memory chips having a power supply wiring layer that extends along the active surface of the memory chip to the logic chip.

[0008] The technical solution provided in this disclosure has at least the following advantages: Multiple memory modules are bonded together using a first adhesive film to increase the capacity density of the memory chips and improve structural strength; the power supply wiring layer extends on the active surface of the memory chips, allowing the power supply wiring layer to be manufactured using existing back-end processes of the memory chips, simplifying the process. Furthermore, the stacking direction of the multiple memory chips is parallel to the upper surface of the logic chip, ensuring that the communication distance between each memory chip and the logic chip is the same, thereby reducing differences in communication latency. Additionally, wireless communication between the memory chips and the logic chip eliminates the need to manufacture wired communication sections on the sides of the memory chips, reducing process complexity. Attached Figure Description

[0009] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0010] Figure 1 A schematic diagram of a semiconductor structure is shown;

[0011] Figures 2-5 Cross-sectional views of four semiconductor structures provided in one embodiment of this disclosure are shown respectively;

[0012] Figure 6 , Figure 9 , Figure 13 , Figure 15 , Figure 17 The following are bottom views of different storage modules provided in an embodiment of the present disclosure;

[0013] Figures 7-8 , Figures 10-11 Schematic diagrams of different active surfaces of a memory chip provided in an embodiment of this disclosure are shown respectively;

[0014] Figure 12 , Figure 14 , Figure 16 Partial cross-sectional views of different semiconductor structures provided in an embodiment of this disclosure are shown respectively;

[0015] Figures 18-19 The following are schematic diagrams showing the structural steps corresponding to each step in the manufacturing method of the semiconductor structure provided in another embodiment of this disclosure;

[0016] Figure 20 A schematic diagram of a semiconductor device provided in yet another embodiment of this disclosure is shown. Detailed Implementation

[0017] As is known from the background technology, it is difficult to further increase the number of stacked layers of memory chips within HBM, and increasing the number of stacked layers will also affect the performance of HBM. (Reference) Figure 1 Analysis revealed that the main reason is that the current hybrid bonding technology used to stack and bond multiple memory chips 200 is limited by process technology, with a single memory module typically having no more than eight stacked layers, resulting in a low capacity density of the memory chips 200. Furthermore, the arrangement direction of the multiple memory chips 200 in HBM is perpendicular to the upper surface of the logic chip 300. The conductive vias 400 and bonding portions 500 within the multiple memory chips 200 are electrically connected, forming a wired communication path. When the number of stacked layers is large, the communication distance between the topmost and bottommost memory chips 200 and the logic chip 300 differs significantly, leading to substantial differences in communication latency between different memory chips 200 and the logic chip 300, thus affecting the product's operating speed.

[0018] This disclosure provides a semiconductor structure in which multiple memory modules are bonded together using a first adhesive film to increase the capacity density of the memory chips. Furthermore, the stacking direction of the multiple memory chips is parallel to the upper surface of the logic chip, ensuring that each memory chip has the same communication distance to the logic chip, thereby reducing differences in communication latency. Moreover, wireless communication between the memory chips and the logic chip eliminates the need to fabricate wired communication sections on the sides of the memory chips, reducing process complexity. Additionally, the power supply wiring layer extends on the active surface of the memory chips, allowing the power supply wiring layer to be fabricated using existing back-end processes of the memory chips, simplifying the process.

[0019] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0020] like Figures 2-17 As shown, one embodiment of this disclosure provides a semiconductor structure, including: a logic chip 3 having a first wireless communication unit 31; a plurality of memory modules 100 stacked on the upper surface of the logic chip 3 along a first direction X, the first direction X being parallel to the upper surface of the logic chip 3; a first adhesive film 74 located between adjacent memory modules 100 and bonded to the memory modules 100; each memory module 100 includes a plurality of memory chips 1 stacked in the first direction X, each memory chip 1 having a second wireless communication unit 11, the second wireless communication unit 11 communicating wirelessly with the first wireless communication unit 31; at least one of the plurality of memory chips 1 has a power supply wiring layer 2, the power supply wiring layer 2 extending along the active surface of the memory chip 1 towards the logic chip 3. This design has the following advantages:

[0021] First, the memory chips 1 are stacked in a direction parallel to the upper surface of the logic chip 3, meaning the arrangement of multiple memory chips 1 is parallel to the upper surface of the logic chip 3. Therefore, each memory chip 1 is equidistant from the logic chip 3, which helps reduce the differences in communication latency between different memory chips 1 and the logic chip 3. Furthermore, compared to vertical stacking, parallel stacking helps reduce the distance between multiple memory chips 1 and the logic chip 3, thereby improving communication speed. Simultaneously, more memory chips 1 can be stacked on top of the logic chip 3.

[0022] Secondly, the power supply wiring layer 2 allows the power supply signal line 12 to be led out from the edge of the memory chip 1, which facilitates wired power supply to the memory chip 1 and improves power supply stability. The power supply wiring layer 2 extends along the active surface of the memory chip 1, meaning it is located on the front side of the memory chip 1. Therefore, after the components within the memory chip 1 are manufactured, the power supply wiring layer 2 can be manufactured using existing back-end processes, simplifying the process. Furthermore, the power supply wiring layer 2 can extend only near the upper or lower edge of the memory chip 1 without covering the entire active surface of the memory chip 1. Therefore, the contact area between the power supply wiring layer 2 and the memory chip 1 is small, and the heat from the power supply wiring layer 2 has a smaller impact on the memory chip 1.

[0023] Third, since the side area of ​​a single memory chip 1 facing the logic chip 3 is relatively small, after multiple memory modules 100 are bonded together by the first adhesive film 74, the total side area of ​​the multiple memory chips 1 facing the logic chip 3 increases, which helps to improve structural strength. In addition, the capacity density of the memory chips 1 is also increased.

[0024] The semiconductor structure will be explained in detail below.

[0025] The storage chip 1 can be a DRAM (Dynamic Random Access Memory) or SRAM (Static Random-Access Memory) chip.

[0026] The memory chip 1 has a front and a back side facing each other, as well as a side connecting the front and the back side. Two adjacent memory chips 1 can be stacked face-to-face, face-to-back, or back-to-back. The front side of the memory chip 1 can also be understood as the active surface 13. The back side of the memory chip 1 can also be understood as the non-active surface.

[0027] refer to Figures 2-5 The memory chip 1 and the logic chip 3 communicate wirelessly through the first wireless communication unit 31 and the second wireless communication unit 11. It should be noted that the side of the memory chip 1 faces the logic chip 3, and the side area is relatively small; by using wireless communication to achieve communication between the memory chip 1 and the logic chip 3, there is no need to set up a wired communication unit between the memory chip 1 and the logic chip 3, thereby reducing the manufacturing process difficulty.

[0028] In some embodiments, the second wireless communication unit 11 is located on the side of the memory chip 1 facing the logic chip 3. This reduces the distance between the first wireless communication unit 31 and the second wireless communication unit 11, thereby improving the quality of wireless communication.

[0029] The first adhesive film 74 will be described in detail below.

[0030] refer to Figure 2 and Figures 4-5 In some embodiments, the first adhesive film 74 covers the entire opposite side surface of adjacent storage modules 100. This simplifies the manufacturing process and improves the bonding strength between adjacent storage modules 100.

[0031] refer to Figure 3 In other embodiments, the first adhesive film 74 includes a plurality of spaced adhesive portions 740; the adhesive portions 740 cover opposite sides of adjacent storage modules 100. That is, the adhesive portions 740 also expose parts of the sides of the storage modules 100, thereby improving the heat dissipation of the storage modules 100. Since there are air gaps between the storage modules 100, the thermal impact between adjacent storage modules 100 can also be reduced.

[0032] For example, the adhesive portion 740 covers the side edge and the center of the side of the storage module 100. This helps to improve the uniformity of the distribution of the adhesive portion 740, thereby ensuring the bonding strength.

[0033] refer to Figures 2-5 In the first direction X, the thickness ratio of the first adhesive film 74 to the thickness of the storage module 100 is 1:75 to 1:95, for example, 1:87. When the thickness ratio of the two is kept within the above range, it is beneficial to improve the bonding strength of adjacent storage modules 100 and avoid the first adhesive film 74 occupying too much surface area of ​​the logic chip 3.

[0034] For example, the thickness of the first adhesive film 74 in the first direction X is 4μm to 6μm, such as 5μm. This helps to improve structural strength and avoids wasting space.

[0035] refer to Figures 4-5 The semiconductor structure may also include a second adhesive film 75, which is located on the side of the memory module 100 away from or close to the logic chip 3. The second adhesive film 75 spans multiple memory modules 100 and is bonded to multiple memory modules 100. The second adhesive film 75 helps to further increase the structural strength.

[0036] For example, refer to Figure 4 When the power supply wiring layer 2 is led out from the lower side of the storage module 100, the second adhesive film 75 is located on the side of the storage module 100 away from the logic chip 3. In this way, the second adhesive film 75 can avoid occupying the space of the conductive structure of the power supply wiring 20.

[0037] refer to Figure 5When the power supply wiring layer 2 is led out from the upper side of the storage module 100, the second adhesive film 75 is located on the side of the storage module 100 closer to the logic chip 3. Therefore, the second adhesive film 75 can also be bonded to the logic chip 3, thereby fixing the storage module 100 onto the logic chip 3.

[0038] Continue to refer to Figures 4-5 In some embodiments, the second adhesive film 75 is bonded to the first adhesive film 74, which facilitates the fixation of the first adhesive film 74 and the second adhesive film 75, thereby improving structural strength.

[0039] The first adhesive film 74 and the second adhesive film 75 can be made of the same material, such as die attach film (DAF). In some other embodiments, the heat dissipation coefficient of the second adhesive film 75 can be greater than that of the first adhesive film 74. For example, the second adhesive film 75 may be doped with metal ions to achieve faster heat dissipation and improve the overall heat dissipation effect.

[0040] The following will provide a detailed explanation of the lead-out method for power supply cabling layer 2.

[0041] refer to Figures 2-4 The end face of the power supply wiring layer 2 facing the logic chip 3 is exposed by the memory chip 1. The memory chip 1 also has solder bumps 5, which are connected to the exposed end face of the power supply wiring layer 2. The logic chip 3 has a power supply port 3a, which is electrically connected to the solder bumps 5. That is, the power supply wiring 20 can be led out from the bottom of the memory module 100, and the solder bumps 5 are used to form a wired power supply path. This helps to shorten the length of the power supply path and reduce power consumption.

[0042] In other embodiments, reference is made to... Figure 5 The end face of the power supply wiring layer 2 away from the logic chip 3 is exposed by the memory chip 1, and the exposed end face of the power supply wiring layer 2 can be connected to the power supply port 3a through structures such as leads and lead frames. That is, the wired power supply path and the wireless communication path are located on the upper and lower sides of the memory module 100, respectively, thereby reducing electromagnetic interference from the wired power supply path to wireless communication and improving communication quality. It should be noted that when the end face of the power supply wiring layer 2 away from the logic chip 3 is exposed by the memory chip 1, the power supply port 3a may not be located on the logic chip 3, but on the substrate 8 (see reference). Figure 20 )superior.

[0043] refer to Figures 7-8 and Figures 10-11 , Figures 7-8 and Figures 10-11Different active surfaces 13 of the memory chip 1 are shown. Each memory chip 1 has multiple power supply signal lines 12 extending on the active surface 13, and the power supply wiring layer 2 is electrically connected to the power supply signal lines 12. In other words, the power supply wiring layer 2 supplies power to the components within the memory chip 1 through the power supply signal lines 12. The connection relationship between the power supply signal lines 12 and the power supply wiring layer 2 will be described in detail below.

[0044] Different power supply signal lines 12 can provide different voltage signals, such as digital or analog signals, to the components within the memory chip 1. The power supply signal line 12 can be a ground signal line 12G or a power signal line 12P. Different ground signal lines 12G have different voltage signals, and different power signal lines 12P have different voltage signals.

[0045] refer to Figure 6 , Figure 9 , Figure 13 , Figure 15 , Figure 17 The power supply cabling layer 2 can be a power cabling layer 2P, a ground cabling layer 2G, or a hybrid cabling layer 2PG. That is, a power supply cabling layer 2 includes multiple isolated power supply cablings 20. Based on the type of power supply cablings 20 in each power supply cabling layer 2, the power supply cabling layer 2 can be divided into the three categories mentioned above. When all the power supply cablings 20 in the power supply cabling layer 2 are power supply cablings 20P, this power supply cabling layer 2 is called a power supply cabling layer 2P; when all the power supply cablings 20 in the power supply cabling layer 2 are ground cablings 20G, this power supply cabling layer 2 is called a ground cabling layer 2G; when the power supply cabling layer 2 includes both ground cablings 20G and power cablings 20P, this power supply cabling layer 2 is called a hybrid cabling layer 2PG.

[0046] Grounding wiring 20G is electrically connected to grounding signal line 12G, and power wiring 20P is electrically connected to power signal line 12P. It should be noted that the multiple power wirings 20 within power wiring layer 2 are all mutually insulated, thus enabling the power signal lines 12 with different voltage signals to be led out separately.

[0047] If a memory chip 1 has its own power supply wiring layer 2, then at least some of the power supply signal lines 12 of this memory chip 1 can be directly connected to its own power supply wiring layer 2, that is, led out through its own power supply wiring layer 2. If a memory chip 1 does not have its own power supply wiring layer 2, then the power supply signal lines 12 of this memory chip 1 can be led out through the power supply wiring layers 2 of other memory chips 1. In other words, this memory chip 1 can establish an electrical connection with other memory chips 1 through conductive vias 41 and bonding portions 42, thereby electrically connecting its own power supply signal lines 12 to the power supply signal lines 12 of other memory chips 1, and further electrically connecting to the power supply wiring layers 2 of other memory chips 1. This will be explained in detail later.

[0048] Within the storage module 100, multiple storage chips 1 can be stacked and bonded using a hybrid bonding method. For example, the surface of each storage chip 1 also has a dielectric layer 43, and the dielectric layers 43 of adjacent storage chips 1 can be connected together by forces such as molecular forces. Furthermore, the surface of each storage chip 1 may also have bonding portions 42, which bond together when heated. In other words, the dielectric layer 43 is an insulating material, providing isolation; the bonding portions 42 are conductive materials, providing electrical connection. Additionally, the dielectric layer 43 exposes the end face of the power supply wiring layer 2 facing or away from the logic chip 3, and covers the sides of the power supply wiring layer 2 except for the end face.

[0049] The following will provide a detailed description of the position and quantity relationship between the memory chip 1 and the power supply wiring layer 2.

[0050] Example 1, for reference Figures 2-13 Each memory chip 1 has a power supply wiring layer 2, meaning the number of memory chips 1 is the same as the number of power supply wiring layers 2. Because there are many power supply wiring layers 2, sufficient lead-out locations can be provided for multiple power supply signal lines 12, simplifying the process of leading out the power supply signal lines 12. Furthermore, more power supply wiring layers 2 also help improve power supply stability, thereby improving the performance of the semiconductor structure. In addition, the power supply wiring layers 2 are uniformly arranged within multiple memory chips 1, thus facilitating the standardization of manufacturing processes for different memory chips 1 and reducing production costs.

[0051] In some embodiments, reference Figures 2-11 Two adjacent memory chips 1 constitute a chipset 10, and two power supply wiring layers 2 of the same chipset 10 are located between the two memory chips 1. That is, the two memory chips 1 of the chipset 10 are bonded face to face, i.e., active surface 13 to active surface 13. The two memory chips 1 of the same chipset 10 share the two power supply wiring layers 2 located between them.

[0052] Specifically, refer to Figures 2-5Each memory chip 1 has conductive vias 41, which are, for example, through-silicon vias (TSVs). Two memory chips 1 in the same chipset 10 are connected by a bonding portion 42, which connects to the conductive vias 41 of the two memory chips 1, thus electrically connecting the two memory chips 1. For example, each memory chip 1 has multiple spaced conductive vias 41, and each conductive via 41 is connected to a corresponding power supply signal line 12 within the memory chip 1. The voltage signals on the power supply signal lines 12 within the same memory chip 1 are different, and correspondingly, the voltage signals on the conductive vias 41 within the same memory chip 1 are also different. In the two memory chips 1 in the same chipset 10, conductive vias 41 with the same voltage signal are electrically connected through the bonding portion 42, thereby electrically connecting the power supply signal lines 12 with the same voltage signal in the two memory chips 1 together.

[0053] For example, the conductive via 41 includes multiple ground vias 41G and multiple power vias 41P, and the bonding portion 42 includes multiple ground bonding portions 42G and multiple power bonding portions 42P. The ground vias 41G are connected to the ground bonding portions 42G, and the power vias 41P are connected to the power bonding portions 42P.

[0054] The conductive vias 41 of each memory chip 1 can be spaced apart in the third direction Z, which is perpendicular to the upper surface of the logic chip 3. For example, ground vias 41G and power vias 41P are alternately arranged in the third direction Z to reduce electromagnetic interference between adjacent conductive vias 41.

[0055] Figure 6 This is a bottom view of a storage module 100. Figures 7-8 These are schematic diagrams of the active surfaces 13 of the two memory chips 1 of the chipset 10, and... Figures 6-8 Corresponding to the same semiconductor structure. (Reference) Figures 6-8 The chipset 10 includes a first memory chip 1a and a second memory chip 1b. Both memory chips 1a have a first power supply signal line group 121 and a second power supply signal line group 122; the power supply signal lines 12 of both the first and second power supply signal line groups 121 and 122 include a power signal line 12P and a ground signal line 12G. The first power supply signal line group 121 of the two memory chips 1a is led out through the power supply wiring layer 2 of the first memory chip 1a, and the second power supply signal line group 122 of the two memory chips 1a is led out through the power supply wiring layer 2 of the second memory chip 1b. That is, both power supply wiring layers 2 of the same chipset 10 are hybrid wiring layers 2PG.

[0056] Continue to refer to Figure 6Within the hybrid wiring layer 2PG, grounding wiring 20G and power wiring 20P are arranged alternately in the second direction Y, which helps to reduce electromagnetic interference between adjacent power wiring 20.

[0057] Figure 9 This is a bottom view of a storage module 100. Figures 10-11 These are schematic diagrams of the active surfaces 13 of the two memory chips 1 of the chipset 10, and... Figures 9-11 Corresponding to the same semiconductor structure. (Reference) Figures 9-11 In the first power supply signal line group 121, all power supply signal lines 12 are power signal lines 12P, and in the second power supply signal line group 122, all power supply signal lines 12 are ground signal lines 12G. The first power supply signal line group 121 of the two memory chips 1 is led out through the power supply wiring layer 2 of the first memory chip 1a, and the second power supply signal line group 122 of the two memory chips 1 is led out through the power supply wiring layer 2 of the second memory chip 1a. That is, the two power supply wiring layers 2 of the same chipset 10 are a power wiring layer 2P and a ground wiring layer 2G, respectively. The first power supply signal line group 121 is electrically connected to the power wiring layer 2P, and the second power supply signal line group 122 is electrically connected to the ground wiring layer 2G.

[0058] At this point, based on Figures 6-11 It is known that each memory chip 1 has a first power supply signal line group 121 and a second power supply signal line group 122; both the first power supply signal line group 121 and the second power supply signal line group 122 include multiple power supply signal lines 12; two first power supply signal line groups 121 within the same chipset 10 are electrically connected to one power supply wiring layer 2, and two second power supply signal line groups 122 within the same chipset 10 are electrically connected to another power supply wiring layer 2. That is, the power supply wiring layer 2 is shared by two power supply wiring layers 2 within the same chipset 10.

[0059] The advantages of this design are mainly as follows: First, the shared power supply wiring layer 2 is located between the two memory chips 1, which can shorten the distance between the power supply wiring layer 2 and the two memory chips 1, thereby helping to reduce the high power consumption caused by long distances; Second, only the dielectric layer 43 for insulation can be set between adjacent chipsets 10, thereby reducing the number of bonding parts 42 and simplifying the manufacturing process; Third, the power supply wiring layer 2 is shared by the two memory chips 1, and correspondingly, the number of power supply wiring 20 and the number of solder bumps 5 are reduced, which helps to provide more space for solder bumps 5 and avoid short circuits; Fourth, only two memory chips 1 in the chipset 10 share the power supply wiring layer 2, that is, the number of memory chips 1 in the chipset 10 is small, which helps to ensure the stability of power supply.

[0060] Continue to refer to Figure 6 and Figure 9The solder bumps 5 include multiple first solder bumps 51 and multiple second solder bumps 52. The first solder bumps 51 and the second solder bumps 52 are respectively connected to different power supply wiring layers 2 within the same chipset 10. The first solder bumps 51 and the second solder bumps 52 are staggered in the first direction X. Specifically, the first solder bumps 51 connected to the same power supply wiring layer 2 are spaced apart in the second direction Y, and the second solder bumps 52 connected to the same power supply wiring layer 2 are spaced apart in the second direction Y. In the first direction X, the gaps between the first solder bumps 51 and the two second solder bumps 52 are directly opposite each other, and the gaps between the second solder bumps 52 and the two first solder bumps 51 are directly opposite each other; that is, in the first direction X, the first solder bumps 51 and the second solder bumps 52 are not directly opposite each other. This helps to increase the distance between the first solder bumps 51 and the second solder bumps 52, thereby avoiding incorrect electrical connections between the first solder bumps 51 and the second solder bumps 52. It should be noted that multiple first welding bumps 51 connect to different power supply lines 20 within the power supply wiring layer 2, and multiple second welding bumps 52 connect to different power supply lines 20 within the power supply wiring layer 2. In other embodiments, the first welding bumps 51 may also be directly opposite the second welding bumps 52 in the first direction X.

[0061] Continue to refer to Figure 6 and Figure 9 In the first direction X, there is a first spacing d1 between two power supply wiring layers 2 within the same chipset 10; in the first direction X, there is a second spacing d2 between the first solder bump 51 and the second solder bump 52; the ratio of the first spacing d1 to the second spacing d2 is 1:1 to 1.2:1. It should be noted that if the second spacing d2 is too large, it may waste space between adjacent memory chips 1; if the second spacing d2 is too small, it may cause incorrect electrical connections between the first solder bump 51 and the second solder bump 52. Maintaining the first spacing d1 and the second spacing d2 within the above range helps to balance these two problems. For example, as... Figure 6 and Figure 9 As shown, the first spacing d1 can be the same as the second spacing d2, that is, the sidewalls opposite to the first welding bump 51 and the second welding bump 52 are flush with the sidewalls opposite to the two power supply wiring layers 2.

[0062] refer to Figures 12-13 , Figure 12 This is a partial cross-sectional view. Figure 13 for Figure 12The diagram shows a bottom view of the storage module 100. Power supply signal lines 12 within the same storage chip 1 are connected to the power supply wiring layer 2. The power supply wiring layers 2 of different storage chips 1 are independent of each other, and the power supply signal lines 12 of different storage chips 1 are also independent of each other. That is, the power supply signal lines 12 of multiple storage chips 1 do not need to be electrically connected together through conductive vias 41 and bonding portions 42. The power supply signal lines 12 within each storage chip 1 can be led out through the storage chip 1's own power supply wiring layer 2 without borrowing from the power supply wiring layers 2 of other storage chips 1. Since the power supply signal lines 12 of each storage chip 1 can be led out independently, it is beneficial to improve the stability of the power supply. Furthermore, the fabrication steps of the bonding portion 42 and conductive via 41 can be eliminated, thereby reducing production costs.

[0063] Continue to refer to Figure 13 For example, the power supply wiring layer 2 of each memory chip 1 can be a hybrid wiring layer 2PG, with power wiring 20P and ground wiring 20G alternately arranged in the second direction Y to reduce electromagnetic interference. Furthermore, multiple power supply wiring layers 2 can be formed on the same side of the memory chip 1, thereby unifying the manufacturing process of the power supply wiring layers 2.

[0064] Furthermore, the power supply wiring 20P of the multiple memory chips 1 can be arranged in a straight line in the first direction X, and the ground wiring 20G of the multiple memory chips 1 can also be arranged in a straight line in the first direction X. Alternatively, the power supply wiring 20P and the ground wiring 20G can be alternately arranged in a straight line in the first direction X. This helps to improve the uniformity of the semiconductor structure and simplifies the manufacturing process.

[0065] Example 2: The number of power supply wiring layers 2 can be greater than the number of memory chips 1. For example, refer to... Figures 14-15 , Figure 14 This is a partial cross-sectional view. Figure 15 for Figure 14 The diagram shows a bottom view of the storage module. A power supply wiring layer 2 is located between two adjacent storage chips 1, and this layer is electrically connected to the storage chips 1 on either side of it. The storage module 100 also has a power supply wiring layer 2 at both ends, which are electrically connected to the storage chips 1 at each end. In other words, except for the two power supply wiring layers 2 at the ends which are not shared by the storage chips 1, the remaining power supply wiring layers 2 in the middle are shared by the storage chips 1 on either side. The storage chips 1 at the beginning and end of the storage module 100 can also be understood as the outermost storage chips 1 of the storage module 100. The power supply wiring layer 2 located in the middle is connected to the power supply signal lines 12 of the two storage chips 1, which helps to reduce the number of solder bumps 5 and simplifies the manufacturing process. Furthermore, the power supply wiring layers 2 are distributed relatively uniformly within the storage module 100, which further simplifies the manufacturing process.

[0066] like Figure 15 As shown, the power supply wiring layer 2 includes a power supply wiring layer 2P and a ground wiring layer 2G. The power supply wiring layer 2P includes multiple power supply lines 20P, and the ground wiring layer 2G includes multiple ground lines 20G. The power supply wiring layer 2P and the ground wiring layer 2G are arranged alternately in the first direction X. In some other embodiments, all power supply wiring layers 2 may also be hybrid wiring layers 2PG, and the voltage signals of the power supply signal lines 12 led out from two adjacent hybrid wiring layers 2PG are different.

[0067] Continue to refer to Figures 14-15 The following example illustrates the sharing method of the power supply wiring layer 2. The power supply wiring layer 2P located on the front side of the storage module 10 can be directly connected to the power signal line 12P of the first storage chip 1a. Therefore, the first storage chip 1a may not have a power via 41P and a power bonding portion 42P. The first storage chip 1a and the second storage chip 1b share the ground wiring layer 2G, meaning their ground signal lines 12G are connected together through the ground via 41G and the ground bonding portion 42G, and are led out through the ground wiring layer 2G between them. The second storage chip 1b and the third storage chip 1c share the power supply wiring layer 2P, meaning their power signal lines 12P are connected together through the power via 41P and the power bonding portion 42P, and are led out through the power wiring layer 2P between them. Since the second storage chip 1b and the third storage chip 1c do not share the ground wiring layer 2G, their ground vias 41G and ground bonding portions 42G will not have an electrical connection.

[0068] In other words, if the power supply wiring layer 2 between two adjacent memory chips 1 is a power supply wiring layer 2P, then these two memory chips 1 are electrically connected through a power via 41P and a power bonding portion 42P. Similarly, if the power supply wiring layer 2 between two adjacent memory chips 1 is a ground wiring layer 2G, then these two memory chips 1 are electrically connected through a ground via 41G and a ground bonding portion 42G.

[0069] It is worth noting that since there is one more power supply wiring layer 2 than there are memory chips 1, one of the two power supply wiring layers 2 at the beginning and end does not need to extend along the active surface 13 of the memory chip 1, that is, it can be located on the back side of the memory chip 1. The remaining power supply wiring layers 2 are still located on the active surface 13 of the memory chip 1.

[0070] Example 3: The number of power supply wiring layers 2 can also be less than the number of memory chips 1. For example, refer to... Figures 16-17 , Figure 16 This is a partial cross-sectional view. Figure 17 for Figure 16 The storage module 100 shown is a bottom view; Figure 13The diagram illustrates a portion of the semiconductor structure. At least two adjacent memory chips 1 are bonded together to form a chipset 10; a power supply wiring layer 2 is provided between two adjacent chipsets 10, and the power supply wiring layer 2 is electrically connected to the memory chips 1 of the chipset 10 on both sides of it; the memory module 100 has a power supply wiring layer 2 at both ends, and is electrically connected to the chipset 10 at both ends respectively.

[0071] In other words, except for the two power supply wiring layers 2 at the beginning and end that are not shared by the chipset 10, all the power supply wiring layers 2 in the middle position are shared by the chipsets 10 on both sides. One power supply wiring layer 2 in the middle position is connected to the power supply signal lines 12 of the two chipsets 10. It is worth noting that the fewer the number of power supply wiring layers 2, the fewer the number of solder bumps 5. Therefore, it is beneficial to increase the distance between the solder bumps 5 and the coils in the first wireless communication unit 31 and the second wireless communication unit 11, thereby reducing electromagnetic interference generated by the solder bumps 5 and the coils and avoiding signal loss.

[0072] For example, each chipset 10 has two memory chips 1, and the power supply signal lines 12 with the same voltage signal in the two memory chips 1 are connected together through conductive vias 41 and bonding portions 42.

[0073] Continue to refer to Figures 16-17 The following example illustrates the sharing method of power supply wiring layer 2. The first chipset 101 and the second chipset 102 share the ground wiring layer 2G, meaning their ground signal lines 12G are connected together through ground vias 41G and ground bonding portions 42G, and are led out through the ground wiring layer 2G between them. The first chipset 101 and the second chipset 102 do not share the power wiring layer 2P, therefore their power vias 41P and power bonding portions 42P are not electrically connected. The second chipset 102 and the third chipset 103 share the power wiring layer 2P, meaning their power signal lines 12P are connected together through power vias 41P and power bonding portions 42P, and are led out through the power wiring layer 2P between them.

[0074] In some embodiments, reference Figures 2-4 , Figure 12 , Figure 14 , Figure 16 The storage module 100 also has an insulating film 71 on its surface facing the logic chip 3. The insulating film 71 can also be located between adjacent solder bumps 5, thereby isolating the solder bumps 5. Furthermore, the insulating film 71 can be made of a material with good adhesion to fix the solder bumps 5. For example, the insulating film 71 can be a polyimide film. Polyimide films have excellent high and low temperature resistance, electrical insulation, and adhesion.

[0075] In some embodiments, a filler adhesive layer 72 is further provided between the logic chip 3 and the memory chip 1, and the filler adhesive layer 72 covers the solder bumps 5. In addition, the filler adhesive layer 72 may also cover the insulating film 71 and the solder pads 32. The filler adhesive layer 72 can fix the solder bumps 5 and the solder pads 32, thereby ensuring the connection strength between the memory module 100 and the logic chip 3.

[0076] like Figures 18-19 as well as Figure 2 As shown, another embodiment of this disclosure provides a method for manufacturing a semiconductor structure, which can be used to manufacture the semiconductor structure provided in the foregoing embodiments. Detailed descriptions of the semiconductor structure can be found in the foregoing embodiments.

[0077] Specifically, refer to Figure 18 First, a power supply wiring layer 2 is fabricated on the active surface of the memory chip 1 to guide the power supply signal line 12 to the side edge of the memory chip 1. A dielectric layer 43 is formed covering the power supply wiring layer 2, and a bonding portion 42 is located within the dielectric layer 43.

[0078] After the bonding portion 42 is formed, multiple memory chips 1 are horizontally stacked and bonded using a hybrid bonding method to form a memory module 100. For example, each memory module 100 includes eight memory chips 1.

[0079] refer to Figure 19 Multiple storage modules 100 are bonded together using a first adhesive film 74, thereby increasing the capacity density and volume of the storage chip 1. The storage module 100 is rotated 90° to facilitate the subsequent fabrication of solder bumps 5 on the side of the storage module 100, and the solder bumps 5 are connected to the power supply wiring layer 2.

[0080] refer to Figure 2 A logic chip 3 is provided; a storage module 100 is soldered onto the logic chip 3 such that the first direction X is parallel to the upper surface of the logic chip 3, and the solder bump 5 is electrically connected to the power supply port 3a. For example, the solder bump 5 is soldered to the pad 32 of the logic chip 3 via a solder paste layer 73.

[0081] Thus, a semiconductor structure with multiple memory modules 100 can be formed. Although the horizontal cross-sectional area of ​​the memory modules 100 after rotation is small, the first adhesive film 74 can enhance the structural strength by bonding the multiple memory modules 100 together, and at the same time improve the problem of fewer stacked layers due to the bonding process.

[0082] like Figure 20 As shown, another embodiment of this disclosure also provides a semiconductor device, which may include the semiconductor structure provided in the foregoing embodiments. For a detailed description of the semiconductor structure, please refer to the foregoing embodiments.

[0083] The semiconductor device includes: a substrate 8; a logic chip 3 disposed on the substrate 8 and having a first wireless communication unit 31; a plurality of memory modules 100 stacked on the upper surface of the logic chip 3 along a first direction X, the first direction X being parallel to the upper surface of the logic chip 3; a first adhesive film 74 located between adjacent memory modules 100 and bonded to the memory modules 100; each memory module 100 includes a plurality of memory chips 1 stacked in the first direction X, each memory chip 1 having a second wireless communication unit 11, the second wireless communication unit 11 communicating wirelessly with the first wireless communication unit 31; at least one of the plurality of memory chips 1 has a power supply wiring layer 2, the power supply wiring layer 2 extending along the active surface 13 of the memory chip 1 toward the logic chip 3.

[0084] The substrate 8 provides electrical connection, protection, support, heat dissipation, and assembly for the logic chip 3 and the memory module 100. The logic chip 3 can be connected to the substrate 8 via solder balls 81. A power supply can be provided on the substrate 8, and the power supply port 3a of the logic chip 3 is connected to the power supply on the substrate 8 to supply power to the memory chip 1.

Claims

1. A semiconductor structure, characterized in that, include: A logic chip having a first wireless communication unit; Multiple storage modules are stacked on the upper surface of the logic chip along a first direction, which is parallel to the upper surface of the logic chip. The first adhesive film is located between adjacent storage modules and is bonded to the storage modules; The storage module includes a plurality of storage chips stacked in a first direction, each storage chip having a second wireless communication unit that communicates wirelessly with the first wireless communication unit. At least one of the plurality of memory chips has a power supply wiring layer that extends along the active surface of the memory chip to the logic chip; Each of the memory chips has a power supply signal line, and the power supply wiring layer is electrically connected to the power supply signal line; each of the memory chips has one power supply wiring layer; The end face of the power supply wiring layer facing the logic chip is exposed by the memory chip; The memory chip also has solder bumps that are connected to the end face. The logic chip has a power supply port, which is electrically connected to the solder bump. The memory chip has conductive vias; Two adjacent memory chips constitute a chipset; A bonding portion is provided between two chips in the same chipset, and the bonding portion is connected to the conductive via of the two memory chips to electrically connect the two memory chips; The two power supply wiring layers of the same chipset are located between the two memory chips; Each of the memory chips has a first power supply signal line group and a second power supply signal line group; both the first power supply signal line group and the second power supply signal line group include a plurality of power supply signal lines; Two first power supply signal line groups within the same chipset are electrically connected to one power supply wiring layer, and two second power supply signal line groups within the same chipset are electrically connected to another power supply wiring layer.

2. The semiconductor structure according to claim 1, characterized in that, In the first direction, the ratio of the thickness of the first adhesive film to the thickness of the storage module is 1:75 to 1:

95.

3. The semiconductor structure according to claim 2, characterized in that, The thickness of the first adhesive film in the first direction is 4μm~6μm.

4. The semiconductor structure according to claim 1, characterized in that, The first adhesive film covers the entire side of the adjacent storage module.

5. The semiconductor structure according to claim 1, characterized in that, The first adhesive film includes a plurality of spaced adhesive portions; The adhesive portion covers the opposite side of the adjacent storage module.

6. The semiconductor structure according to claim 5, characterized in that, The adhesive portion covers the side edge and the center of the side of the storage module.

7. The semiconductor structure according to claim 1, characterized in that, Also includes: The second adhesive film is located on the side of the storage module away from the logic chip or on the side close to the logic chip; and the second adhesive film spans multiple storage modules and is bonded to multiple storage modules.

8. The semiconductor structure according to claim 7, characterized in that, The second adhesive film is bonded to the first adhesive film.

9. The semiconductor structure according to claim 1, characterized in that, The memory chips located on opposite sides of the first adhesive film have the solder bumps.

10. The semiconductor structure according to claim 1, characterized in that, The two power supply wiring layers of the same chipset are a power wiring layer and a ground wiring layer, respectively; The power supply signal lines of the first power supply signal line group are power signal lines, and the first power supply signal line group is electrically connected to the power supply wiring layer; the power supply signal lines of the second power supply signal line group are ground signal lines, and the second power supply signal line group is electrically connected to the ground wiring layer.

11. The semiconductor structure according to claim 1, characterized in that, The plurality of solder bumps are connected to the same power supply wiring layer, and the plurality of solder bumps are spaced apart in a second direction; the second direction is parallel to the upper surface of the logic chip and perpendicular to the first direction; The solder bumps connected to the adjacent power supply wiring layer are staggered in the first direction.

12. A semiconductor device, characterized in that, include: substrate; A logic chip, disposed on the substrate, has a first wireless communication unit; Multiple storage modules are stacked on the upper surface of the logic chip along a first direction, which is parallel to the upper surface of the logic chip. The first adhesive film is located between adjacent storage modules and is bonded to the storage modules; The storage module includes a plurality of storage chips stacked in a first direction, each storage chip having a second wireless communication unit that communicates wirelessly with the first wireless communication unit. At least one of the plurality of memory chips has a power supply wiring layer that extends along the active surface of the memory chip to the logic chip; Each of the memory chips has a power supply signal line, and the power supply wiring layer is electrically connected to the power supply signal line; each of the memory chips has one power supply wiring layer; The end face of the power supply wiring layer facing the logic chip is exposed by the memory chip; The memory chip also has solder bumps that are connected to the end face. The logic chip has a power supply port, which is electrically connected to the solder bump. The memory chip has conductive vias; Two adjacent memory chips constitute a chipset; A bonding portion is provided between two chips in the same chipset, and the bonding portion is connected to the conductive via of the two memory chips to electrically connect the two memory chips; The two power supply wiring layers of the same chipset are located between the two memory chips; Each of the memory chips has a first power supply signal line group and a second power supply signal line group; both the first power supply signal line group and the second power supply signal line group include a plurality of power supply signal lines; Two first power supply signal line groups within the same chipset are electrically connected to one power supply wiring layer, and two second power supply signal line groups within the same chipset are electrically connected to another power supply wiring layer.

13. A semiconductor structure, characterized in that, include: A logic chip having a first wireless communication unit; Multiple storage modules are stacked on the upper surface of the logic chip along a first direction, which is parallel to the upper surface of the logic chip. The first adhesive film is located between adjacent storage modules and is bonded to the storage modules; The storage module includes a plurality of storage chips stacked in a first direction, each storage chip having a second wireless communication unit that communicates wirelessly with the first wireless communication unit. At least one of the plurality of memory chips has a power supply wiring layer that extends along the active surface of the memory chip to the logic chip; Each of the memory chips has a power supply signal line, and the power supply wiring layer is electrically connected to the power supply signal line; each of the memory chips has one power supply wiring layer; The end face of the power supply wiring layer facing the logic chip is exposed by the memory chip; The memory chip also has solder bumps that are connected to the end face. The logic chip has a power supply port, which is electrically connected to the solder bump. The plurality of solder bumps are connected to the same power supply wiring layer, and the plurality of solder bumps are spaced apart in a second direction; the second direction is parallel to the upper surface of the logic chip and perpendicular to the first direction; The solder bumps connected to the adjacent power supply wiring layer are staggered in the first direction.

14. The semiconductor structure according to claim 13, characterized in that, The first adhesive film covers the entire side of the adjacent storage module.

15. The semiconductor structure according to claim 13, characterized in that, The first adhesive film includes a plurality of spaced adhesive portions; The adhesive portion covers the opposite side of the adjacent storage module.

16. The semiconductor structure according to claim 15, characterized in that, The adhesive portion covers the side edge and the center of the side of the storage module.

17. The semiconductor structure according to claim 13, characterized in that, Also includes: The second adhesive film is located on the side of the storage module away from the logic chip or on the side close to the logic chip; and the second adhesive film spans multiple storage modules and is bonded to multiple storage modules.

18. The semiconductor structure according to claim 17, characterized in that, The second adhesive film is bonded to the first adhesive film.

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