Semiconductor structure and its fabrication method, memory

Abstract

This disclosure provides a semiconductor structure and its fabrication method, as well as a memory. The semiconductor structure fabrication method includes: a substrate; a magnetic tunnel junction stacked structure located on the substrate, comprising: a fixed layer, a bottom barrier layer located on the fixed layer, and a plurality of free layers and barrier layers alternately stacked on the bottom barrier layer; and a conductive layer covering a portion of the sidewalls of the magnetic tunnel junction stacked structure, wherein at least a portion of the free layers in the magnetic tunnel junction stacked structure are electrically connected through the conductive layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and includes, but is not limited to, a semiconductor structure and its fabrication method, and a memory. Background Technology

[0002] Magnetic Random Access Memory (MRAM) is a non-volatile magnetic random access memory that combines the high-speed read / write capabilities of Static Random Access Memory (SRAM) with the high integration density of Dynamic Random Access Memory (DRAM), and can be rewritten virtually an unlimited number of times. The architecture of MRAM primarily consists of a stacked structure of transistors (T) and magnetic tunnel junctions (MTJs). However, with the miniaturization of memory, the MTJ stacked structure still presents several challenges. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a semiconductor structure, a method for fabricating the same, and a memory.

[0004] One aspect of this disclosure provides a semiconductor structure, including:

[0005] Substrate;

[0006] A magnetic tunnel junction stacked structure, located on the substrate, includes: a fixed layer, a bottom barrier layer on the fixed layer, and a plurality of free layers and barrier layers alternately stacked on the bottom barrier layer; and

[0007] A conductive layer covers a portion of the sidewalls of the magnetic tunneling stack structure, through which at least a portion of the free layers in the magnetic tunneling stack structure are electrically connected.

[0008] In the above scheme, the sidewall of the conductive layer is flush with the sidewall of the fixed layer and the sidewall of the bottom barrier layer.

[0009] In the above scheme, the sidewall of the conductive layer is flush with the sidewall of the fixed layer, the sidewall of the bottom barrier layer, and the sidewall of the substrate.

[0010] In the above scheme, the conductive layer is located on the bottom barrier layer and covers all the free layers and the sidewalls of the barrier layer in the magnetic tunneling stack structure.

[0011] In the above scheme, the conductive layer is located on the bottommost free layer of the alternating stacked free layers and barrier layers and covers the sidewalls of the remaining free layers and barrier layers in the magnetic tunnel stacked structure.

[0012] In the above scheme, the semiconductor structure further includes: an insulating layer located between the conductive layer and the bottom barrier layer, wherein the top surface of the insulating layer is higher than the top surface of the bottommost free layer among the alternately stacked free layers and barrier layers.

[0013] In the above scheme, the top surface of the insulating layer is lower than the top surface of the bottommost barrier layer among the alternatingly stacked free layers and barrier layers.

[0014] In the above scheme, the sidewall of the insulating layer is flush with the sidewall of the conductive layer, and the insulating layer is in contact with a portion of the free layer. The dimension of the insulating layer along a preset direction is greater than or equal to the dimension of the conductive layer along the preset direction, and the preset direction is perpendicular to the direction in which the free layer and the barrier layer are stacked.

[0015] In the above scheme, the material of the conductive layer includes at least one of tantalum, tungsten, copper, or titanium nitride.

[0016] In the above scheme, the semiconductor structure further includes: a capping layer located on the magnetic tunnel junction stacked structure; the conductive layer covers the sidewall of the capping layer.

[0017] In the above scheme, the semiconductor structure further includes: bit lines, located on the capping layer and the conductive layer, and electrically connected to the conductive layer.

[0018] In the above scheme, the semiconductor structure further includes: a sidewall protective layer covering the conductive layer, the magnetic tunnel junction stacked structure, the capping layer, and the bit line.

[0019] In the above scheme, the semiconductor structure further includes a buffer layer located between the substrate and the fixing layer, wherein the sidewall of the buffer layer is flush with the sidewall of the substrate.

[0020] One aspect of this disclosure provides a memory, including one or more semiconductor structures as described in the above embodiments of this disclosure.

[0021] This disclosure provides, in one aspect, a method for fabricating a semiconductor structure, the method comprising:

[0022] Provide substrate;

[0023] A magnetic tunnel junction stack structure is formed on the substrate; forming the magnetic tunnel junction stack structure includes: forming a fixed layer, forming a bottom barrier layer on the fixed layer, and sequentially forming a plurality of alternating free layers and barrier layers on the bottom barrier layer;

[0024] A conductive layer is formed covering a portion of the sidewalls of the magnetic tunneling stack structure, and at least a portion of the free layers in the magnetic tunneling stack structure are electrically connected through the conductive layer.

[0025] In the above scheme, forming the magnetic tunneling stacked structure includes:

[0026] A fixed material layer, a bottom barrier material layer, and several alternating free material layers and barrier material layers are sequentially formed.

[0027] Remove some of the alternating free material layers and barrier material layers;

[0028] Further remove some of the remaining alternating free material layers and barrier material layers, except for the bottommost free material layer, to expose part of the top surface of the bottommost free layer, thus forming the barrier layer and the free layer.

[0029] After the conductive layer is formed, a portion of the fixing material layer and the bottom barrier material layer are removed to obtain the fixing layer and the bottom barrier layer, so that the sidewalls of the fixing layer and the bottom barrier layer are flush with the sidewalls of the conductive layer.

[0030] The formation of the conductive layer includes:

[0031] A conductive layer is formed on the exposed bottommost free layer, covering the remaining free layers and the barrier layer.

[0032] The method in the above scheme further includes:

[0033] A buffer layer is formed on the substrate before the magnetic tunnel junction stack structure is formed.

[0034] The magnetic tunnel junction stack structure is formed on the buffer layer;

[0035] Before forming the conductive layer, a capping layer is formed on the magnetic tunneling stack structure;

[0036] A conductive layer is formed that covers part of the sidewalls of the cap layer and the magnetic tunneling stack structure;

[0037] Bit lines are formed on the conductive layer and the magnetic tunnel junction stacked structure;

[0038] A protective layer is formed that covers the conductive layer, the magnetic tunneling stacked structure, the capping layer, and the sidewall of the bit line.

[0039] In various embodiments of this disclosure, a magnetic tunnel junction stack structure is formed on a substrate, wherein the magnetic tunnel junction stack structure includes a fixed layer, a bottom barrier layer located on the fixed layer, and a plurality of free layers and barrier layers alternately stacked on the bottom barrier layer; in addition, a conductive layer is provided on a portion of the sidewalls of the magnetic tunnel junction stack structure, the conductive layer electrically connecting at least a portion of the free layers in the magnetic tunnel junction stack structure. Thus, on the one hand, by forming several alternating free layers and barrier layers in the magnetic tunneling stack structure, the magnetic tunneling stack structure can have multiple free layer and barrier layer interfaces, thereby achieving high thermal stability. On the other hand, by electrically connecting some of the free layers in the magnetic tunneling stack structure through conductive layers, the resistance of the magnetic tunneling stack structure can be equivalent to the resistance in only a small number of barrier layers, or even only to the resistance in the bottom barrier layer, thereby reducing the resistance-area product (RA) of the magnetic tunneling stack structure and increasing the tunnel magnetoresistance ratio (TMR) of the magnetic tunneling stack structure. In other words, the semiconductor structure provided in this embodiment of the present disclosure has both high thermal stability and a high tunnel magnetoresistance ratio. Attached Figure Description

[0040] Figures 1a-1c This is a schematic diagram of the architecture of the three MRAM transistors provided in the embodiments of this disclosure;

[0041] Figure 2 This is a circuit connection diagram of an MRAM transistor provided in an embodiment of this disclosure;

[0042] Figures 3a-3c This is a schematic diagram of three magnetic tunnel junction stacked structures with different numbers of contact interfaces provided in the embodiments of this disclosure.

[0043] Figure 4 This is a schematic diagram showing the thermal stability variation trend of magnetic tunnel junction stacked structures with different numbers of contact interfaces provided in the embodiments of this disclosure.

[0044] Figure 5 This is a schematic diagram showing the variation trend of the magnetoresistance ratio of the magnetic tunnel junction stacked structure with different numbers of contact interfaces provided in the embodiments of this disclosure.

[0045] Figure 6 This is a semiconductor structure provided in this embodiment of the present disclosure, in which a conductive layer covers part of the sidewalls of the free layer and the barrier layer;

[0046] Figure 7a This is a semiconductor structure provided in this embodiment of the present disclosure, in which a conductive layer covers the sidewalls of all free layers and barrier layers;

[0047] Figure 7b This is another semiconductor structure provided in this disclosure where the conductive layer covers the sidewalls of all free layers and barrier layers;

[0048] Figure 8a This disclosure provides a semiconductor structure having an insulating layer and a conductive layer that is not flush with the sidewalls of the substrate.

[0049] Figure 8b This disclosure provides a semiconductor structure having an insulating layer and a conductive layer flush with the sidewalls of the substrate.

[0050] Figure 9a This is another semiconductor structure provided in the embodiments of the present disclosure, which has an insulating layer and a conductive layer that is not flush with the sidewall of the substrate;

[0051] Figure 9b This is another semiconductor structure provided in the embodiments of this disclosure, having an insulating layer and a conductive layer flush with the sidewall of the substrate;

[0052] Figure 10a This disclosure provides a semiconductor structure with bit lines and sidewall protection layers in an embodiment.

[0053] Figure 10b This is another semiconductor structure with bit lines and sidewall protection layers provided in the embodiments of this disclosure;

[0054] Figure 11 This is a schematic flowchart illustrating the fabrication process of a semiconductor structure provided in an embodiment of this disclosure;

[0055] Figures 12a-12d This is a cross-sectional schematic diagram illustrating the fabrication process of a semiconductor structure provided in an embodiment of this disclosure.

[0056] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The figures illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Implementation

[0057] To make the technical solutions and advantages of the embodiments of this disclosure clearer, the technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this disclosure are shown in the accompanying drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the implementation methods set forth herein. Rather, these implementation methods are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0058] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0059] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0060] Furthermore, for ease of description, spatial relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0061] In embodiments of this disclosure, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include various semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0062] In embodiments of this disclosure, the term "layer" refers to a portion of material including a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0063] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0064] The semiconductor structures disclosed herein are at least a portion of those to be used in subsequent processes to form the final device structure. Here, the final device may include a memory, including but not limited to magnetic random access memory (MRM). The following description uses MRM as an example only. However, it should be noted that the following description of MRM in the embodiments is for illustrative purposes only and is not intended to limit the scope of this disclosure.

[0065] Magnetic random access memory (MRM) offers promising performance in terms of speed, area, write cycles, and power consumption, making it a potential candidate for building next-generation non-volatile caches and main memory. With the development of MRAM technology, its array architecture has evolved from spin-transfer torque magnetic random access memory (STT-MRAM) to [reference missing]. Figure 1a To Voltage Controlled Magnetic Random Access Memory (VCMA-MRAM), see reference. Figure 1b Then, to the spin-orbit torque magnetic random access memory (SOT-MRAM), refer to Figure 1c However, regardless of whether it is STT-MRAM or SOT-MRAM, the memory is composed of multiple memory cell structures. Each memory cell structure mainly consists of a transistor T and a memory cell (magnetic tunnel junction stacked structure MTJ) controlled by the transistor. In other words, a magnetic random access memory includes at least one transistor T and one magnetic tunnel junction stacked structure MTJ.

[0066] The magnetic tunnel junction (MTJ) stacked structure mainly consists of three layers: a free layer, a fixed layer, and a barrier layer (also known as a tunneling oxide layer). Its primary operating principle utilizes the magnetic moments of the free and fixed layers to store information. When the magnetic moments of the free and fixed layers are parallel, the resistance is low, and a "1" is written. When the magnetic moments of the free and fixed layers are anti-parallel, the resistance is high, and a "0" is written. Furthermore, the memory read circuit determines the information in the memory by applying the same voltage and judging the magnitude of the output current, thereby completing the read operation.

[0067] Figure 2 This is a schematic diagram of the control circuit of a magnetic random access memory provided in an embodiment of this disclosure, such as... Figure 2As shown, the gate of transistor T is connected to the word line (WL); the source (drain) of transistor T is electrically connected to the fixed layer of the magnetic tunnel junction stacked structure (MTJ) through the source line (SL), while the free layer of the MTJ is connected to the bit line (BL). By applying different voltages between the bit line BL and the source line SL, a write current (Iwrite) is generated flowing through the MTJ. Iwrite can change the magnetization direction of the free layer of the MTJ, causing a change in the tunneling resistance, thus completing the storage of "0" and "1". The read mechanism of the magnetic random access memory circuit is that current flows in from the bit line BL and is output through the MTJ and transistor T. The magnitude of the voltage also depends on the resistance of the MTJ; different output voltages are generated under the same read current. Based on the output voltage, it can be determined whether the data stored in the memory cell is "0" or "1".

[0068] However, with the miniaturization of electronic products, it is difficult for magnetic tunnel junction stacked structures (MTJs) to simultaneously achieve both high thermal stability and a high tunnel magnetoresistance ratio.

[0069] Based on this, a semiconductor structure is proposed in the embodiments of this disclosure, with reference to... Figures 3a-3c The semiconductor structure includes:

[0070] Substrate 301;

[0071] A magnetic tunnel junction stacked structure 302, located on the substrate 301, includes: a fixed layer 3021, a bottom barrier layer 3022 located on the fixed layer 3021, and a plurality of free layers 3023 and barrier layers 3024 alternately stacked on the bottom barrier layer 3022; and

[0072] A conductive layer 303 covers a portion of the sidewalls of the magnetic tunneling stacked structure 302, and at least a portion of the free layers 3023 in the magnetic tunneling stacked structure 302 are electrically connected through the conductive layer 303.

[0073] refer to Figures 3a-3c The substrate 301 may be made of silicon (Si), germanium (Ge), silicon germanide (SiGe), etc.; in some specific embodiments, the substrate 301 may also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI).

[0074] Here, the magnetic tunneling stacked structure 302 may include multiple free layers 3023 and multiple barrier layers 3024. Figure 3aThe example only illustrates the case where the magnetic tunneling stacked structure 302 includes two free layers 3023 and two barrier layers 3024; Figure 3b The example only illustrates the case where the magnetic tunneling stacked structure 302 includes three free layers 3023 and three barrier layers 3024; Figure 3c The example only illustrates the case where the magnetic tunneling stacked structure 302 includes four free layers 3023 and four barrier layers 3024. It should be noted that the top layer of the magnetic tunneling stacked structure 302 is the barrier layer 3024.

[0075] The fixing layer 3021 is used to provide a fixed magnetic moment direction. The material of the fixing layer 3021 is a ferromagnetic material, and is therefore also called a ferromagnetic layer. The material of the fixing layer 3021 includes, but is not limited to, iron (Fe), cobalt (Co), cobalt-iron (CoFe) alloy, Heusler alloy, cobalt-iron-boron (CoFeB), etc.

[0076] The bottom barrier layer 3022 is an insulating layer used to act as an insulator between the two ferromagnetic layers; the material of the bottom barrier layer 3022 includes, but is not limited to, magnesium oxide (MgO).

[0077] The free layer 3023 is used to provide a changing magnetic moment direction, and it is also called a ferromagnetic layer; the material of the free layer 3023 includes, but is not limited to, iron (Fe), cobalt (Co), cobalt-iron (CoFe) alloy, Heusler alloy, cobalt-iron-boron (CoFeB), etc.

[0078] The barrier layer 3024 and the bottom barrier layer 3022 have the same function and material, as previously mentioned, and will not be repeated here.

[0079] Understandably, the magnetic tunnel junction stacked structure 302 can serve as the core storage cell of a memory. The magnetization direction of the ferromagnetic layer (bottom barrier layer 3022 or barrier layer 3024) in this core storage cell is typically in-plane. As recording density increases, in-plane magnetization in storage cells presents several problems. For example, if the magnetic tunnel junction stacked structure becomes too small, vortex effects will occur at the edges of the memory device, hindering information reading and writing. If the ferromagnetic layer in the magnetic tunnel junction stacked structure is a material with perpendicular magnetic anisotropy, this problem can be effectively resolved. Furthermore, since the magnetization state of the ferromagnetic layer (bottom barrier layer 3022 or barrier layer 3024) is not very sensitive to shape, smaller device sizes are actually more conducive to the stability of perpendicular magnetization. Additionally, in current-driven magnetization reversals based on spin torque effects, perpendicular materials possess lower critical reversal current densities and higher thermal stability. Therefore, in this embodiment of the present disclosure, the total number of contact interfaces between the ferromagnetic layer (bottom barrier layer 3022 or barrier layer 3024) and the free layer 3023 can be increased to further increase the perpendicular magnetic anisotropy (PMA) of the magnetic tunnel junction stacked structure.

[0080] For example, refer to Figure 3a The magnetic tunneling stacked structure 302 is a four-interface magnetic tunneling stacked structure; wherein, the magnetic tunneling stacked structure 302 includes a bottom barrier layer 3022, two barrier layers 3024, and two free layers 3023.

[0081] For example, refer to Figure 3b The magnetic tunneling stacked structure 302 is a six-interface magnetic tunneling stacked structure; wherein, the magnetic tunneling stacked structure 302 includes a bottom barrier layer 3022, three barrier layers 3024, and three free layers 3023.

[0082] For example, refer to Figure 3c The magnetic tunneling stacked structure 302 is an eight-interface magnetic tunneling stacked structure; wherein, the magnetic tunneling stacked structure 302 includes a bottom barrier layer 3022, four barrier layers 3024, and four free layers 3023.

[0083] Figure 4 This is a schematic diagram illustrating the changing trends of thermal stability in magnetic tunnel junction stacked structures with different numbers of contact interfaces; from Figure 4 As can be seen, the thermal stability coefficient (Δ) of the magnetic tunnel stacked structure gradually increases when the number of interfaces is four, six, and eight; that is, the thermal stability of the magnetic tunnel stacked structure improves as the number of contact interfaces between the free layer and the barrier layer increases.

[0084] Preferably, the magnetic tunneling stacked structure 302 in this embodiment is an eight-interface magnetic tunneling stacked structure.

[0085] However, as the number of stacked free layers and barrier layers increases, the resistance in the magnetic tunnel junction stack 302 increases, thereby reducing the resistance-area product (RA) in the magnetic tunnel junction stack 302, and simultaneously reducing the critical current and tunnel magnetoresistance ratio (TMR); for example, refer to Figure 5 As the contact surface between the barrier layer and the free layer changes from a four-interface to a six-interface, and then to an eight-interface, the tunneling magnetoresistance ratio (TMR) gradually decreases.

[0086] Based on this, in the embodiments of this disclosure, reference is made to Figures 3a to 3c A conductive layer 303 is disposed in the semiconductor structure; the conductive layer 303 is located on a portion of the sidewall of the magnetic tunnel junction stack structure 302, wherein the conductive layer 303 electrically connects at least a portion of the free layers 3023 in the magnetic tunnel junction stack structure 302; thus, the resistance in the magnetic tunnel junction stack structure 302 having interfaces of multiple barrier layers 3024 and free layers 3023 can be equivalent to the resistance in a few barrier layers, or even only equivalent to the resistance in the bottom barrier layer 3022, thereby reducing the RA (resistance-area product) of the magnetic tunnel junction stack structure 302, and thereby increasing the critical current and the tunnel magnetoresistance ratio (TMR) of the magnetic tunnel junction stack structure.

[0087] In other words, the semiconductor structure provided in this embodiment of the present disclosure has both high thermal stability and high tunnel magnetoresistance ratio by providing a conductive layer on a portion of the sidewall of the magnetic tunnel junction stacked structure 302.

[0088] In order to clearly describe the inventive intent of this disclosure, the magnetic tunneling stacked structure 302 with eight interfaces is used as an example for illustration. However, it should be noted that the description of the number of interfaces in the following embodiments is only for illustrative purposes and is not intended to limit the scope of this disclosure.

[0089] In some embodiments, reference Figure 3c The sidewalls of the conductive layer 303, the fixed layer 3021, and the bottom barrier layer 3022 are all flush.

[0090] It should be noted that the term "flush" as used here can be understood as roughly flush or basically flush. The gap (or difference) between the sidewalls of the conductive layer, the sidewalls of the fixing layer, and the sidewalls of the bottom barrier layer, which are within the allowable error range of the process, are all within the flush range described in the embodiments of this disclosure.

[0091] Here, the conductive layer 303 electrically connects multiple barrier layers 3024 and the bottom barrier layer 3022, so that the resistance of the semiconductor structure is only the resistance of the bottom barrier layer 3022; thereby increasing the tunnel magnetoresistance ratio (TMR) of the magnetic tunnel junction stacked structure.

[0092] In some embodiments, reference Figure 6 The sidewalls of the conductive layer 303, the fixed layer 3021, the bottom barrier layer 3022, and the substrate 301 are all flush.

[0093] The sidewall of the conductive layer 303 may be flush with or cover the sidewall of the bottommost free layer 3023 in the alternating stacked free layers and barrier layers. Figure 6 The conductive layer 303 is flush with the sidewall of the bottommost free layer 3023 in the alternating free layers and barrier layers. The sidewall of the conductive layer 303 may be flush with the sidewall of the substrate 301.

[0094] In some embodiments, reference Figure 7a and Figure 7b The conductive layer 303 is located on the bottom barrier layer 3022 and covers the sidewalls of all the free layers 3023 and barrier layers 3024 in the magnetic tunneling stacked structure 302.

[0095] At this time, the sidewall of the bottom barrier layer 3022 is flush with the sidewalls of all the free layers and barrier layers in the plurality of sequentially alternately stacked free layers 3023 and barrier layers 3024. It should be noted that, in this embodiment, the sidewall of the conductive layer 303 is flush with the sidewall of the fixed layer 3021 and the sidewall of the bottom barrier layer 3022; furthermore, the sidewall of the conductive layer 303 is not flush with the sidewall of the substrate 301, which can be referred to... Figure 7a The sidewalls of the conductive layer 303 can be flush with the sidewalls of the substrate 301, as can be seen from [reference needed]. Figure 7b .

[0096] In some embodiments, reference Figure 3c , Figure 6 The conductive layer 303 is located on the bottommost free layer 3023 of the alternating free layers 3023 and barrier layers 3024 and covers the sidewalls of the remaining free layers 3023 and barrier layers 3024 in the magnetic tunnel stacked structure 302.

[0097] Here, the conductive layer 303 electrically connects the multiple free layers 3023 to the bottom barrier layer 3022. The sidewalls of the conductive layer 303 are flush with the sidewalls of the fixed layer 3021 and the bottom barrier layer 3022; furthermore, the sidewalls of the conductive layer 303 may not be flush with the sidewalls of the substrate 301, as shown in the reference. Figure 3c The sidewalls of the conductive layer 303 can also be flush with the sidewalls of the substrate 301, see reference. Figure 6 .

[0098] In some embodiments, reference Figure 8a , Figure 8b , Figure 9a , Figure 9b The semiconductor structure further includes an insulating layer 306 located between the conductive layer 303 and the bottom barrier layer 3022, wherein the top surface of the insulating layer 306 is higher than the top surface of the bottommost free layer 3023 in the alternatingly stacked free layers and barrier layers.

[0099] Here, the insulating layer 306 is used to ensure that electrons tunnel into the bottommost free layer 3023 of the alternating free layers and barrier layers, rather than the outer conductive layer 303. To prevent electron tunneling, the top surface of the insulating layer 306 may be higher than the top surface of the bottommost barrier layer of the alternating free layers and barrier layers; here, whether the top surface of the insulating layer 306 is higher or lower than the top surface of the bottommost barrier layer of the alternating free layers and barrier layers, it does not affect the magnitude of the resistance in the semiconductor structure.

[0100] In some embodiments, reference Figure 8a , Figure 8b , Figure 9a , Figure 9b The top surface of the insulating layer is lower than the top surface of the bottommost barrier layer 3024 in the alternatingly stacked free layer 3023 and barrier layer 3024.

[0101] Here, the top surface of the insulating layer 306 is lower than the top surface of the bottommost barrier layer 3024 in the alternatingly stacked free layers 3023 and barrier layers 3024, which allows the conductive layer 303 to connect with more of the free layers in the alternatingly stacked free layers 3023 and barrier layers 3024.

[0102] In some embodiments, the sidewall of the insulating layer is flush with the sidewall of the conductive layer, the dimension of the insulating layer along a preset direction is greater than or equal to the dimension of the conductive layer along the preset direction, and the preset direction is perpendicular to the direction in which the free layer and the barrier layer are stacked.

[0103] Here, the direction in which the free layer and the barrier layer are stacked is perpendicular to the surface of the substrate 301; for example, the direction in which the free layer and the barrier layer are stacked is the Z-axis direction in the figure, and the preset direction can be the X-axis direction or the Y-axis direction (not shown in the figure) or other directions between the X-axis and the Y-axis.

[0104] It should be noted that the magnetic tunnel junction stacked structures shown in the embodiments of this disclosure are all cross-sectional views. In the corresponding cross-sectional views of the magnetic tunnel junction stacked structures, the shapes of the conductive layer, insulating layer, and multiple stacked layers are matched. Specifically, when the shape of the magnetic tunnel junction stacked structure is circular, the shape of the conductive layer is annular; when the shape of the magnetic tunnel junction stacked structure is cylindrical, the shape of the conductive layer is cylindrical; in addition, when the shape of the magnetic tunnel junction stacked structure is annular, the conductive layer may be only a part or several parts of the cylinder. Accordingly, the insulating layer is located between the conductive layer and the bottom barrier layer, and the projection of the insulating layer on the substrate surface at least covers the projection of the conductive layer on the substrate surface; in other words, the sidewall of the insulating layer is flush with the sidewall of the conductive layer, and the dimension of the insulating layer in the X-axis direction, Y-axis direction, or other directions between the X-axis and Y-axis is greater than or equal to the dimension of the conductive layer in the corresponding X-axis direction, Y-axis direction, or other directions between the X-axis and Y-axis.

[0105] For example, refer to Figure 8a , Figure 8b The sidewall of the insulating layer 306 is flush with the sidewall of the conductive layer 303, and the dimension of the insulating layer 306 in the X-axis direction is equal to the dimension of the conductive layer 303 in the X-axis direction; Reference Figure 9a , Figure 9b The sidewall of the insulating layer 306 is flush with the sidewall of the conductive layer 303. The sidewall of the insulating layer 306 is partially in contact with the conductive layer 303, and the dimension of the insulating layer 306 in the X-axis direction is larger than the dimension of the conductive layer 303 in the X-axis direction.

[0106] In some embodiments, the conductive layer 303 is made of at least one of tantalum, tungsten, copper, or titanium nitride. The insulating layer 306 is made of materials including, but not limited to, silicon oxide.

[0107] In some embodiments, reference Figures 3a to 3c , Figures 6 to 10b The semiconductor structure further includes: a capping layer 305 located on the magnetic tunnel junction stacked structure 302; and a conductive layer 303 covering the sidewalls of the capping layer 305.

[0108] The top surface of the conductive layer 303 is flush with the top surface of the capping layer 305. The capping layer 305 is used to protect the barrier layer 3024 from damage. The material of the capping layer 305 includes, but is not limited to, ruthenium (Ru).

[0109] In some embodiments, reference Figure 10a , Figure 10b The semiconductor structure further includes a bit line 307, located on the capping layer 305 and the conductive layer 303, and electrically connected to the conductive layer 303.

[0110] The bit line 307 is connected to multiple free layers 3023 via a conductive layer 303, and is used to transmit electrical signals during a read operation. The material of the bit line 307 includes, but is not limited to, tungsten (W).

[0111] In some embodiments, reference Figure 10a , Figure 10b The semiconductor structure further includes: a sidewall protective layer 308, which covers the conductive layer, the magnetic tunnel junction stacked structure, the capping layer, and the bit line.

[0112] The sidewall protective layer 308 can be used to protect the magnetic tunnel stacked structure 302 from damage by external factors; the material of the sidewall protective layer 308 is an insulating material, for example, the material of the sidewall protective layer 308 includes, but is not limited to, silicon oxide.

[0113] In some embodiments, reference Figures 3a to 3c , Figures 6 to 10b The semiconductor structure further includes a buffer layer 304 located between the substrate 301 and the fixing layer 3021, wherein the sidewall of the buffer layer 304 is flush with the sidewall of the substrate 301.

[0114] Here, the buffer layer 304 is located on the substrate 301, and the magnetic tunnel junction stack structure 302 is located on the buffer layer 304. The buffer layer 304 can be an antiferromagnetic thin film, which is used to ensure that the magnetic field direction of the fixed layer 3021 in the magnetic tunnel junction stack structure 302 remains unchanged when the semiconductor structure exchanges information with the external circuit, thereby improving the reliability of the semiconductor structure. The material of the buffer layer 304 includes, but is not limited to, cobalt-iron (CoFe) alloy, cobalt-iron-boron (CoFeB), etc.

[0115] Based on this, in various embodiments of this disclosure, a magnetic tunnel junction stack structure is formed on a substrate, wherein the magnetic tunnel junction stack structure includes a fixed layer, a bottom barrier layer located on the fixed layer, and a plurality of free layers and barrier layers arranged alternately in sequence on the bottom barrier layer; in addition, a conductive layer is provided on a portion of the sidewalls of the magnetic tunnel junction stack structure, and the conductive layer electrically connects at least a portion of the free layers in the magnetic tunnel junction stack structure. Thus, on the one hand, by forming several alternating free layers and barrier layers in the magnetic tunneling stack structure, the magnetic tunneling stack structure can have multiple free layer and barrier layer interfaces, thereby achieving high thermal stability. On the other hand, by electrically connecting some of the free layers in the magnetic tunneling stack structure through conductive layers, the resistance of the magnetic tunneling stack structure can be equivalent to the resistance in only a small number of barrier layers, or even only to the resistance in the bottom barrier layer, thereby reducing the resistance-area product (RA) of the magnetic tunneling stack structure and increasing the tunnel magnetoresistance ratio (TMR) of the magnetic tunneling stack structure. In other words, the semiconductor structure provided in this embodiment of the present disclosure has both high thermal stability and a high tunnel magnetoresistance ratio.

[0116] According to another aspect of this disclosure, a memory is provided, comprising: one or more semiconductor structures as described in any of the embodiments of this disclosure above.

[0117] In other embodiments, the semiconductor structure further includes peripheral circuitry for controlling the semiconductor structure.

[0118] According to another aspect of this disclosure, a method for fabricating a semiconductor structure is provided. Figure 11 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure; as shown below. Figure 11 As shown, the method for fabricating a semiconductor structure provided in this embodiment includes the following steps:

[0119] S1101: Provides a substrate;

[0120] S1102: A magnetic tunnel junction stacked structure is formed on the substrate; forming the magnetic tunnel junction stacked structure includes: forming a fixed layer, forming a bottom barrier layer on the fixed layer, and sequentially forming a plurality of alternating free layers and barrier layers on the bottom barrier layer.

[0121] S1103: Form a conductive layer covering a portion of the sidewalls of the magnetic tunneling stack structure, wherein at least a portion of the free layers in the magnetic tunneling stack structure are electrically connected through the conductive layer.

[0122] It should be understood that Figure 11The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 11 The steps shown can be rearranged in order according to actual needs. The following section combines... Figure 11 , Figure 12a , Figure 12b , Figure 12c , Figure 12d , Figure 3c , Figure 6 , Figure 10a , Figure 10b The method for fabricating the semiconductor structure provided in the embodiments of this disclosure will be described in detail.

[0123] It should be noted that the semiconductor structures described in the foregoing embodiments are of various types. Here and below, only one semiconductor structure from the foregoing embodiments will be described in detail. (Refer to...) Figure 10a , Figure 10b It should be understood that the methods for forming semiconductor structures described below are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0124] Execute step S1101, refer to Figure 12a Substrate 301 is provided.

[0125] Execute step S1102 to form a magnetic tunnel stacked structure.

[0126] It should be noted that a buffer layer can be formed on the substrate before forming the magnetic tunnel junction stacked structure. Specifically, a buffer layer is placed over the substrate, and the magnetic tunnel junction stacked structure is formed on the buffer layer 304. Methods for forming the buffer layer include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).

[0127] The magnetic tunneling stacked structure includes: a fixed layer, a bottom barrier layer located on the fixed layer, and several free layers and barrier layers arranged alternately on the bottom barrier layer.

[0128] In some embodiments, forming the magnetic tunneling stack structure includes:

[0129] A fixed material layer, a bottom barrier material layer, and several alternating free material layers and barrier material layers are sequentially formed.

[0130] Remove some of the alternating free material layers and barrier material layers;

[0131] Further remove some of the remaining alternating free material layers and barrier material layers, except for the bottommost free material layer, to expose part of the top surface of the bottommost free layer, thus forming the barrier layer and the free layer.

[0132] After the conductive layer is formed, a portion of the fixing material layer and the bottom barrier material layer are removed to obtain the fixing layer and the bottom barrier layer, so that the sidewalls of the fixing layer and the bottom barrier layer are flush with the sidewalls of the conductive layer.

[0133] The formation of the conductive layer includes:

[0134] A conductive layer is formed on the exposed bottommost free layer, covering the remaining free layers and the barrier layer.

[0135] refer to Figure 12a A fixed material layer 1201 is formed on the buffer layer 304, a bottom barrier material layer 1202 is formed on the fixed material layer 1201, and a plurality of alternating free material layers 1203 and barrier material layers 1204 are formed on the bottom barrier material layer 1202; and a cap material layer 1205 is formed on the barrier material layer 1204.

[0136] The methods for forming the fixed material layer 1201, the bottom barrier material layer 1202, the free material layer 1203, the barrier material layer 1204, and the capping material layer 1205 include, but are not limited to, PVD process, CVD process, ALD process, magnetron sputtering process, etc.

[0137] refer to Figure 12b Remove part of the free material layer 1203 and part of the barrier material layer 1204.

[0138] refer to Figure 12c Further, some of the remaining alternating free material layers 1203 and barrier material layers 1204, excluding the bottommost free material layer 1203, are removed to form free layer 3023 and barrier layer 3024.

[0139] In this process, part of the cap material layer 1205 is removed to form the cap layer 305.

[0140] The removal process includes, but is not limited to, dry etching; preferably, the removal process includes plasma dry etching.

[0141] Execute step S1103, refer to Figure 12d A conductive layer 303 is formed.

[0142] The conductive layer 303 covers a portion of the sidewall of the magnetic tunneling stack 302 and is used to electrically connect at least a portion of the free layers 3023 in the magnetic tunneling stack 302; thus, the resistance in the magnetic tunneling stack 302 can be reduced.

[0143] The methods for forming the conductive layer 303 include, but are not limited to, PVD, CVD, ALD and other processes.

[0144] It should be noted that the sidewall of the conductive layer 303 may be flush with only the sidewall of the bottommost free layer 3023 among the alternating free layers and barrier layers, as shown in the reference. Figure 12d Alternatively, the sides of the bottommost free layer 3023, fixed layer 3021, and bottom barrier layer 3022 in the aforementioned alternating free layers and barrier layers can all be flush with each other, as shown in the reference. Figure 3c It can also be flush with the sidewalls of the substrate 301, buffer layer 304, the bottommost free layer 3023, fixed layer 3021, and bottom barrier layer 3022 among the several alternating free layers and barrier layers, for reference. Figure 6 Its structure has been described previously and will not be repeated here.

[0145] In some embodiments, reference Figure 3c After the conductive layer 303 is formed, a portion of the fixing material layer 1201 is removed to form a fixing layer 3021; ​​and the bottom barrier material layer 1202 is removed to form a bottom barrier layer 3022.

[0146] Here, the sidewalls of the fixing layer 3021 and the bottom barrier layer 3022 are flush with the sidewalls of the conductive layer 303.

[0147] The removal process includes, but is not limited to, dry etching; preferably, the removal process includes plasma dry etching.

[0148] In some embodiments, reference Figure 10a The method further includes:

[0149] Bit lines 307 are formed on the conductive layer and the magnetic tunnel junction stacked structure;

[0150] A sidewall protective layer 308 is formed that covers the conductive layer 303, the magnetic tunneling stacked structure 302, the cap layer 305, and the bit line 307.

[0151] The methods for forming the bit line 307 and the sidewall protective layer 308 include, but are not limited to, processes such as PVD, CVD, and ALD.

[0152] In some embodiments, reference Figure 10b The method further includes:

[0153] An insulating layer 306 is formed between the conductive layer 303 and the bottom barrier layer 3022; the method for forming the insulating layer 306 includes, but is not limited to, PVD, CVD, ALD and other processes.

[0154] Here, for reference Figure 10b In some embodiments, the top surface of the insulating layer 306 may be higher than the top surface of the bottommost free layer 3023 among the alternatingly stacked free layers and barrier layers; in other embodiments, the top surface of the insulating layer 306 may be lower than the top surface of the bottommost barrier layer among the alternatingly stacked free layers and barrier layers. In still other embodiments, the sidewall of the insulating layer 306 is flush with the sidewall of the conductive layer 303, and the dimension of the insulating layer 306 along a predetermined direction is greater than or equal to the dimension of the conductive layer along the predetermined direction, the predetermined direction being perpendicular to the stacking direction of the free layers and barrier layers.

[0155] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. Furthermore, the various components shown or discussed may be coupled or directly coupled to each other.

[0156] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0157] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0158] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A magnetic tunnel junction stacked structure, located on the substrate, includes: a fixed layer, a bottom barrier layer on the fixed layer, and a plurality of free layers and barrier layers alternately stacked on the bottom barrier layer; and A conductive layer covers a portion of the sidewalls of the magnetic tunneling stack structure, through which at least a portion of the free layers in the magnetic tunneling stack structure are electrically connected; An insulating layer is located between the conductive layer and the bottom barrier layer, with the top surface of the insulating layer being higher than the top surface of the bottommost free layer among the alternatingly stacked free layers and barrier layers.

2. The semiconductor structure according to claim 1, characterized in that, The sidewalls of the conductive layer are flush with the sidewalls of the fixed layer and the bottom barrier layer.

3. The semiconductor structure according to claim 2, characterized in that, The sidewalls of the conductive layer are flush with the sidewalls of the fixed layer, the bottom barrier layer, and the substrate.

4. The semiconductor structure according to claim 2 or 3, characterized in that, The conductive layer is located on the bottom barrier layer and covers all the sidewalls of the free layers and barrier layers in the magnetic tunneling stack structure.

5. The semiconductor structure according to claim 2 or 3, characterized in that, The conductive layer is located on the bottommost free layer of the alternating stacked free layers and barrier layers and covers the sidewalls of the remaining free layers and barrier layers in the magnetic tunnel stacked structure.

6. The semiconductor structure according to claim 1, characterized in that, The top surface of the insulating layer is lower than the top surface of the bottommost barrier layer among the alternatingly stacked free layers and barrier layers.

7. The semiconductor structure according to claim 1, characterized in that, The sidewall of the insulating layer is flush with the sidewall of the conductive layer, and the insulating layer is in contact with a portion of the free layer. The dimension of the insulating layer along a predetermined direction is greater than or equal to the dimension of the conductive layer along the predetermined direction, and the predetermined direction is perpendicular to the direction in which the free layer and the barrier layer are stacked.

8. The semiconductor structure according to claim 1, characterized in that, The material of the conductive layer includes at least one of tantalum, tungsten, copper, or titanium nitride.

9. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes: a capping layer located on the magnetic tunnel junction stacked structure; and a conductive layer covering the sidewalls of the capping layer.

10. The semiconductor structure according to claim 9, characterized in that, The semiconductor structure further includes: bit lines located on the capping layer and the conductive layer, and electrically connected to the conductive layer.

11. The semiconductor structure according to claim 10, characterized in that, The semiconductor structure further includes: a sidewall protective layer covering the conductive layer, the magnetic tunnel junction stacked structure, the capping layer, and the bit line.

12. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a buffer layer located between the substrate and the fixing layer, wherein the sidewalls of the buffer layer are flush with the sidewalls of the substrate.

13. A memory, characterized in that, include: One or more semiconductor structures as described in any one of claims 1 to 12.

14. A method for fabricating a semiconductor structure, characterized in that, The method includes: Provide substrate; A magnetic tunnel junction stack structure is formed on the substrate; forming the magnetic tunnel junction stack structure includes: forming a fixed layer, forming a bottom barrier layer on the fixed layer, and sequentially forming a plurality of alternating free layers and barrier layers on the bottom barrier layer; A conductive layer is formed covering a portion of the sidewalls of the magnetic tunneling stack structure, and at least a portion of the free layers in the magnetic tunneling stack structure are electrically connected through the conductive layer; An insulating layer is formed between the conductive layer and the bottom barrier layer, with the top surface of the insulating layer being higher than the top surface of the bottommost free layer among the alternatingly stacked free layers and barrier layers.

15. The method for fabricating a semiconductor structure according to claim 14, characterized in that, The formation of the magnetic tunneling stacked structure includes: A fixed material layer, a bottom barrier material layer, and several alternating free material layers and barrier material layers are sequentially formed. Remove some of the alternating free material layers and barrier material layers; Further remove some of the remaining alternating free material layers and barrier material layers, except for the bottommost free material layer, to expose part of the top surface of the bottommost free layer, thus forming the barrier layer and the free layer. After the conductive layer is formed, a portion of the fixing material layer and the bottom barrier material layer are removed to obtain the fixing layer and the bottom barrier layer, so that the sidewalls of the fixing layer and the bottom barrier layer are flush with the sidewalls of the conductive layer. The formation of the conductive layer includes: A conductive layer is formed on the exposed bottommost free layer, covering the remaining free layers and the barrier layer.

16. The method for fabricating a semiconductor structure according to claim 14, characterized in that, The method further includes: A buffer layer is formed on the substrate before the magnetic tunnel junction stack structure is formed. The magnetic tunnel junction stack structure is formed on the buffer layer; Before forming the conductive layer, a capping layer is formed on the magnetic tunneling stack structure; A conductive layer is formed that covers part of the sidewalls of the cap layer and the magnetic tunneling stack structure; Bit lines are formed on the conductive layer and the magnetic tunnel junction stacked structure; A protective layer is formed that covers the conductive layer, the magnetic tunneling stacked structure, the capping layer, and the sidewall of the bit line.

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