Interactive display device and method for manufacturing such a device

Abstract

The present specification relates to a device comprising: - a transfer substrate (200) comprising electrical connection elements; and - a plurality of unit chips (153) attached and electrically connected to the transfer substrate (200), each unit chip (153) comprising at least one LED and an electronic circuit for controlling the at least one LED, the device further comprising, in association with at least one unit chip (153), a sensor or actuation element (211) external to the unit chip (153) attached and electrically connected to the transfer substrate (200), each unit chip (153) comprising an electronic circuit (READ) for reading or controlling the sensor or actuation element (211) associated with this chip.

Description

[0001] This application is based on and claims priority to French patent application FR2107693, filed on July 16, 2021, entitled “Interactive display device and method for manufacturing such device,” which is incorporated herein by reference in accordance with the law. Technical Field

[0002] This disclosure generally relates to the field of image display devices, and more specifically to an interactive image display device that combines light emission and optical capture functions, and a method of manufacturing such a device. More generally, this disclosure relates to an image display device that combines light emission and capture or actuation functions. Background Technology

[0003] For example, in the applicant's previously filed patent applications WO2017089676, EP3401958, and WO2018185433, an image display device comprising a plurality of basic monolithic electronic chips arranged in an array on a single transfer substrate has been provided. The basic chips are rigidly assembled onto the transfer substrate and connected to electrical connection elements of the transfer substrate for their control. Each chip includes one or more light-emitting diodes (LEDs) and circuitry for controlling the one or more LEDs, and each chip corresponds to a pixel of the device. The control circuitry includes a connection surface opposite the one or more LEDs, the connection surface including a plurality of electrical connection regions intended to connect to the transfer substrate for microchip control. The transfer substrate includes a connection surface that includes a plurality of electrical connection regions for each microchip, these electrical connection regions being intended to connect to the electrical connection regions of the microchip, respectively. The chips are transferred onto the transfer substrate, wherein their connection surfaces face the connection surfaces of the transfer substrate, and are secured to the transfer substrate to connect the electrical connection regions of each microchip to corresponding electrical connection regions of the transfer substrate.

[0004] This type of display device is particularly suitable for forming displays with large surface areas, such as displays for computers, televisions, tablets, etc.

[0005] More specifically, this consideration focuses on the formation of an interactive image display device that combines light emission and optical capture functions. More generally, this consideration focuses on the formation of an interactive image display device that combines light emission and capture or actuation functions. Summary of the Invention

[0006] One embodiment provides an apparatus comprising:

[0007] - A transfer substrate, comprising electrical connection elements; and

[0008] - Multiple basic chips, which are fixed and electrically connected to the transfer substrate, each basic chip including at least one LED and electronic circuitry for controlling the at least one LED.

[0009] The device also includes a capture or actuation element associated with at least one base chip, external to the base chip, the capture or actuation element being fixed and electrically connected to the transfer substrate, each base chip including electronic circuitry for reading from or controlling the capture or actuation element associated with that chip.

[0010] According to one embodiment, each capturing and actuating element is a photodetector.

[0011] According to one embodiment, each photodetector includes a photosensitive organic layer.

[0012] According to one embodiment, in each basic chip, the electronic circuitry for controlling the LED and the electronic circuitry for reading from or controlling the capturing or actuating element include MOS transistors formed inside and on top of a monocrystalline silicon layer.

[0013] According to one embodiment, in each basic chip, the LED is an inorganic LED.

[0014] According to one embodiment, in each basic chip, the LED is a gallium nitride LED.

[0015] According to one embodiment, each base chip includes a plurality of sub-pixels, each sub-pixel including an LED and circuitry for controlling the LED.

[0016] According to one embodiment, in each basic chip, circuitry for controlling the LEDs of different sub-pixels of the chip is connected to the same input terminal of the chip, the input terminal being connected to a corresponding connection area of ​​the transfer substrate, and is intended to sequentially receive emission setpoint signals of different sub-pixels of the chip.

[0017] According to one embodiment, in each basic chip, circuitry for controlling the LEDs of different sub-pixels of the chip is connected to different input terminals of the chip, which are respectively connected to different corresponding connection areas of the transfer substrate, for the purpose of receiving the emission setpoint signals of different sub-pixels of the chip in parallel.

[0018] According to one embodiment, in each basic chip, the circuitry for controlling the LED is configured to control the LED using a binary-coded digital setpoint signal.

[0019] According to one embodiment, in each basic chip, a photodetector readout circuit associated with the chip is connected to the chip's output terminal, which is connected to a corresponding connection area of ​​the transfer substrate, and is intended to deliver a signal representing the intensity of light received by the photodetector.

[0020] According to one embodiment, the capturing or actuating element is a piezoelectric transducer. Attached Figure Description

[0021] The above-described features and advantages, as well as other features and advantages, will be described in detail in the remainder of the disclosure of specific embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, wherein:

[0022] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F , Figure 1G , Figure 1H , Figure 1I and Figure 1J This is a cross-sectional view illustrating the sequential steps of an example method for manufacturing a basic pixel chip of an interactive display device according to one embodiment;

[0023] Figure 2 This is a top view schematically and partially illustrating an example of a transfer substrate of an interactive display device according to one embodiment;

[0024] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E This is a cross-sectional view illustrating successive steps in an example of a method for manufacturing an interactive display device according to one embodiment;

[0025] Figure 4 This is a circuit diagram of an example circuit of a basic pixel chip of an interactive display device according to one embodiment;

[0026] Figure 5 It is shown schematically. Figure 4 A diagram illustrating the operation of a basic pixel chip;

[0027] Figure 6 A circuit diagram of another example of a basic pixel chip in an interactive display device according to one embodiment; and

[0028] Figure 7 It is shown schematically. Figure 6 A diagram illustrating the operation of a basic pixel chip. Detailed Implementation

[0029] Similar features are indicated by similar reference numerals in the various figures. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0030] For clarity, only steps and elements useful for understanding the described embodiments are shown and described in detail. In particular, the various possible applications of the described interactive display device are not described in detail, and the described embodiments are compatible with all or most known applications of emitting display devices that integrate optical capture functions, and more generally emitting display devices that integrate capture or actuation functions, such as motion detection, facial recognition, identity authentication, etc.

[0031] Unless otherwise stated, when referring to two elements connected together, it means that there is no direct connection of any intermediate element other than a conductor, and when referring to two elements coupled together, it means that the two elements can be connected or they can be coupled via one or more other elements.

[0032] In the following description, when referring to terms such as “front,” “back,” “top,” “bottom,” “left,” “right,” which define absolute position, or terms such as “above,” “below,” “upper,” “lower,” or terms such as “horizontal,” “vertical,” which define direction, unless otherwise specified, they refer to the orientation of the accompanying drawings.

[0033] Unless otherwise stated, the expressions “about,” “roughly,” “basically,” and “approximately” indicate plus or minus 10%, preferably plus or minus 5%.

[0034] According to one aspect of the embodiments, an image display device is provided, comprising a plurality of basic monolithic electronic chips arranged in an array on the same transfer substrate. As described in the examples in the applicant's previously filed patent applications WO2017089676, EP3401958, and WO2018185433, the basic chips are rigidly assembled to the transfer substrate and connected to electrical connection elements of the transfer substrate. Each chip includes one or more LEDs and circuitry for controlling the one or more LEDs, and each chip corresponds to a pixel of the device. The control circuitry includes a connection surface opposite the one or more LEDs, the connection surface including a plurality of electrical connection regions (also referred to as terminals or pads) intended to connect to the transfer substrate for control of the microchips. The transfer substrate includes a connection surface that includes a plurality of electrical connection regions (also referred to as terminals or pads) for each microchip, these electrical connection regions being intended to connect to the electrical connection regions of the microchip, respectively. The chips are transferred onto the transfer substrate, wherein their connection surfaces face the connection surfaces of the transfer substrate, and are secured to the transfer substrate to connect the electrical connection regions of each microchip to corresponding electrical connection regions of the transfer substrate.

[0035] According to one aspect of the embodiment, the image display device further includes an optical capture function, such as an image capture function. For this purpose, the device includes a plurality of photodetectors, such as organic photodetectors, arranged in an array of rows and columns and defining an image sensor. The photodetectors are located outside the basic pixel chip of the display device and are disposed on a transfer substrate of the device, on the same side of the transfer substrate as the basic pixel chip. The photodetectors are connected to electrical connection terminals on the transfer substrate for reading out.

[0036] As an example, the device includes a photodetector arranged near each of the basic pixel chips. In other words, the array of basic pixel chips and the array of photodetectors in the display device are staggered arrays with the same size and spacing.

[0037] According to one aspect of the embodiment, each basic pixel chip of the display device integrates electronic circuitry for reading an electrical signal representing the light intensity received by a corresponding photodetector of the device (i.e., the light intensity at the same location in the pixel array). For this purpose, each basic pixel chip of the device includes a connection terminal that is individually connected to the electrode of the associated photodetector via conductive traces on a transfer substrate.

[0038] Examples of embodiments of such an interactive display device will now be described in further detail with reference to the accompanying drawings.

[0039] Figures 1A to 1J This is a cross-sectional view illustrating an example of a method for manufacturing the basic pixel chip of the device.

[0040] Figure 1A The view (a) schematically illustrates a control structure, which includes a first substrate 101 on which multiple basic integrated control circuits 103, for example identical or similar, corresponding to the integrated control circuits of each future basic pixel chip of the device, have been formed, inside and on top of the first substrate 101.

[0041] In the example shown, substrate 101 is an SOI (semiconductor-on-insulator) type substrate, including, for example, a semiconductor support substrate 101a made of silicon, an insulating layer 101b made of, for example, silicon oxide disposed on top of and in contact with the upper surface of the support substrate 101a, and an upper semiconductor layer 101c made of, for example, single crystal silicon disposed on top of and in contact with the upper surface of the insulating layer 101b.

[0042] In this example, basic control circuits 103 are formed inside and on top of the upper semiconductor layer 101c of substrate 101. Each basic control circuit 103 includes, for example, multiple transistors ( Figures 1A to 1I (Not shown in detail), such as MOS transistors, for example integrated inside and on top of a single-crystal silicon layer. The basic control circuit 103 is formed, for example, using CMOS (Complementary Metal-Oxide-Semiconductor) technology. Each basic control circuit 103 may include circuitry adapted to control the light emission of LED(s) of a future basic pixel chip of the device, and circuitry for reading from a photodetector associated with the future basic pixel chip of the device.

[0043] In this example, each basic control circuit 103 includes one or more metal connection pads 105a, 105b on its upper surface side. As an example, the pads 105a, 105b are flush with the upper surface of an upper insulating layer of an interconnect stack (not shown in detail in the figure), for example, made of silicon oxide, which coats the upper surface of the upper semiconductor layer 103c of the substrate 101. Therefore, in this example, the upper surface of the control structure in view (a) is a flat surface comprising alternating metal regions (pads 105a, 105b) and insulating regions.

[0044] As an example, each basic control circuit 103 includes a specific metal pad 105a for each LED of a future basic pixel chip of the device, designed to connect to the anode region of the LED and enable individual control of the light emission of the LED. Each basic control circuit 103 may also include a metal pad 105b designed to connect to the cathode region of each LED of a future basic pixel chip of the device. In cases where the basic chip comprises multiple LEDs, the cathode contact can be shared by all LEDs of the chip. Therefore, the basic control circuit 103 may include a single metal pad 105b.

[0045] As an example, each pixel element chip in the device includes three individually controllable LEDs adapted to emit blue, green, and red light, respectively. In this case, each basic control circuit 103 may include three separate metal pads 105a intended to be connected to the anode regions of the three LEDs, respectively, and a single metal pad 105b intended to be connected together to the cathode regions of the three LEDs. Figure 1A The diagram shows that each electronic circuit has only two metal pads 105a and one metal pad 105b.

[0046] Figure 1A A view (b) is also shown, schematically illustrating a structure including a second substrate 111 having an active LED stack 113 resting on its upper surface. The active LED stack 113 is, for example, an inorganic LED stack, such as based on one or more III-V type semiconductor materials, such as gallium nitride. The substrate 111 is made of, for example, sapphire or silicon.

[0047] The active LED stack 113 includes, for example, an N-type doped semiconductor layer forming a cathode layer, an active layer, and a P-type doped semiconductor layer (not described in detail in the figure) forming an anode layer, starting from the upper surface of the substrate 111. The active layer includes, for example, alternating layers of quantum wells made of a first semiconductor material and barrier layers made of a second semiconductor material defining a stack of multiple quantum wells.

[0048] The active stack 113 can be epitaxially formed on the upper surface of the substrate 111. As a variation, the active stack 113 is epitaxially formed on a growth substrate (not shown) and then transferred to the upper surface of the substrate 111.

[0049] At this stage, the stack 113 has not yet been configured into individual LEDs. In other words, each layer of the stack 113 extends continuously over the entire upper surface of the substrate 111 and has a substantially uniform thickness.

[0050] Figure 1B Includes view (a), which is shown in Figure 1A The step of depositing a metal layer 107 on top of and in contact with the upper surface of the control structure in view (a). In this example, layer 107 is... Figure 1A The interconnecting layers of the control structure in view (a) extend continuously with a substantially uniform thickness across the entire upper surface. Thus, layer 107 connects all the metal pads 105a, 105b of the control structure to each other.

[0051] Figure 1B It also includes view (b), which is shown in Figure 1AThe step shown in view (b) is to deposit a metal layer 115 on top of and in contact with the upper surface of the active LED stack 113. The metal layer 115 may be a single layer or a stack of multiple metal layers. Preferably, the metal layer 115 includes a layer made of the same material as layer 107 on its upper surface side.

[0052] Figure 1C This is shown as transferring and fixing the active LED stack 113 and the metal layer 115 to... Figure 1B The structure is obtained as a result of the steps on the structure of view (a).

[0053] exist Figure 1C middle, Figure 1B The orientation of the structure in view (a) remains unchanged. However, Figure 1B The structural elements of view (b) relative to Figure 1B The orientation was reversed.

[0054] During this step, substrate 111 is used as a handle to... Figure 1B The structure of view (b) is transferred Figure 1B The upper surface of the structure in view (a). The lower surface of metal layer 115 (on) Figure 1C In the orientation, corresponding to Figure 1B The upper surface of the orientation of the layer 115 is fixed to the upper surface of the metal layer 107. For example, this fixation is achieved by directly fixing the lower surface of the layer 115 or by molecularly fixing it to the upper surface of the layer 107, i.e., without any additional material between the two layers.

[0055] Then, substrate 111 is removed, for example by grinding and / or chemical etching, so that the upper surface of the active LED stack 113 (i.e., in this example, the upper surface of the cathode semiconductor layer of the active LED stack 113) can be accessed.

[0056] Figure 1D The steps for forming trench 121 are shown. Trench 121 extends vertically from the upper surface of an active LED stack and laterally defines a plurality of islands 123 corresponding to individual LEDs of the future base chip of the device within the stack 113. Trench 121 is formed, for example, by plasma etching. Figure 1D In the example shown, trench 121 terminates on the upper surface of metal layer 115. In a top view (not shown), trench 121 forms a grid that laterally separates the basic diodes 123 from each other.

[0057] Figure 1E A subsequent step is shown, for example, using the same etching mask (not shown) as in the previous step, to extend trench 121 vertically through metal layers 107 and 115. At the end of this step, trench 121 appears on the upper surface of the interconnect stack coated with the upper surface of substrate 101.

[0058] At the end of this step, a portion of the stack of layers 107 and 115 remaining beneath each LED 123 forms the anode of the LED. The anode contacts the upper surface of the metal connection pad 105a of the underlying basic control circuit 103 via its lower surface. Therefore, the anode of each LED is respectively connected to the metal connection pad 105a of the basic control circuit 103.

[0059] In this example, trench 121 is also formed in front of each metal connection pad 105b to allow access to the upper surface of the pad 105b.

[0060] Figure 1E The following steps for passivating the sides of LED 123 are also shown. To achieve this, a layer 125 made of an electrically insulating material (e.g., silicon oxide or silicon nitride) is deposited on the upper surface of the structure using a conformal deposition method. Layer 125 is then coated on the upper surface and sides of LED 123, as well as the sides of metal layers 107 and 115 located below LED 123, and at the bottom of trench 121, the upper surface of the interconnect stack of the coating substrate 101 is coated. A vertical anisotropic etching step is then performed to remove the horizontal portion of layer 125, retaining only the vertical portions of this layer that coat the sides of LED 123 and the sides of metal layers 107 and 115 located below LED 123.

[0061] Figure 1F The subsequent steps of filling trench 121 with metal 127 are illustrated. As an example, metal 127 is initially deposited on the entire upper surface of the structure with a thickness greater than the depth of trench 121 to completely fill trench 121. A planarization step is then performed, for example, by chemical mechanical polishing, to make the upper surface of LED 123 accessible. This results in a substantially flat upper surface with the semiconductor cathode region of LED 123, the vertical insulating region 125 of LED, and the metal region 127 filling trench 121 flush with it. In a top view (not shown), metal region 127 forms a conductive grid that laterally separates LEDs 123 from each other. Metal region 127 is electrically connected to metal pad 105b at the bottom of trench 121 and defines a common cathode contact metallization for all LEDs 123 in the structure.

[0062] Figure 1G The diagram illustrates a subsequent step of depositing a conductive layer 129 on the upper surface of this structure. The conductive layer 129 is transparent to the emission wavelength of the LEDs in the display device. Layer 129 is, for example, on... Figure 1FThe structure extends continuously with a substantially uniform thickness across its entire upper surface. Layer 129 is made of, for example, a transparent conductive oxide, such as indium tin oxide (ITO). As a variation, layer 129 can be a metal layer that is thin enough to be transparent, such as a silver layer thinner than 80 nm.

[0063] Layer 129 contacts the upper surface of the cathode semiconductor region of LED 123 via its lower surface and defines the common cathode of LED 123. Layer 129 also contacts the upper surface of metal region 127 via its lower surface. Thus, layer 129 electrically connects the cathode semiconductor region of each LED 123 to the common cathode contact metallization 127 of the structure.

[0064] Figure 1H Showing will Figure 1G The subsequent steps involve transferring the structure onto the temporary support substrate 140. Figure 1H In, the orientation of this structure is relative to Figure 1G The orientation is reversed. A temporary support substrate is fixed to the surface of the conductive layer 129 opposite to the substrate 101, i.e., it is in... Figure 1H The lower surface in the orientation (corresponding to its position) Figure 1G (The upper surface in the orientation). The temporary support substrate 140 is, for example, a silicon substrate. The temporary support substrate 140 can be fixed to the conductive layer 129 by means of an adhesive fixing layer or by direct fixing.

[0065] Figure 1H The following steps are also shown, for example, removing the support substrate 101a of the initial SOI structure by grinding and / or chemical etching to make the upper surface of the insulating layer 101b of the SOI structure accessible.

[0066] It should be noted that the described embodiments are not limited to the example described above where the substrate 101 is an SOI-type substrate. As a variation, the substrate 101 may be a solid semiconductor substrate, such as one made of silicon. In this case, in Figure 1A In the steps, for example by grinding, the substrate 101 can be removed from its back side (in Figure 1H The upper surface of the substrate is thinned. Then, an insulating passivation layer, for example made of silicon oxide, can be deposited on the thinned upper surface of the substrate in place of layer 101b of the SOI substrate. As a variation, layer 101b can be omitted.

[0067] Figure 1IThe diagram shows the structure obtained as a result of the steps of forming contact openings in layers 101b and 101c and forming contact metallization 131 inside and on top of said openings. Contact metallization 131 enables electrical contacts to be obtained on the metal layers (not shown in detail in the figures) of the interconnect stack disposed on the lower surface side of semiconductor layer 101c. Metallization 131 is, for example, electrically connected to transistors in a control circuit, which are themselves electrically connected to or coupled to connection metallizations 105a, 105b of the LED.

[0068] The metallization 131 forms the connection terminal of the future basic pixel chip of the apparatus, which is intended to be connected to the corresponding connection terminal of the transfer substrate of the apparatus.

[0069] Figure 1J The diagram shows the structure obtained as a result of the step of monolithizing the basic pixel chips of the device. For this purpose, trenches 151 extending vertically through layers 101b, 101c, 127, and 129 are formed from the upper surface of the structure along dicing lines. In this example, the trenches appear on the upper surface of a temporary support substrate 140. In a top view, the trenches 151 form a continuous grid that laterally defines, for example, a plurality of identical or similar basic pixel chips 153, each basic pixel chip 153 including basic control circuitry 103 and one or more LEDs 123. The trenches 151 are formed, for example, by plasma etching.

[0070] It should be noted that, in combination Figures 1A to 1J In the described example, the basic LED 123 is formed from the same LED active stack and all emits at the same wavelength. In cases where each of the basic chips 153 includes multiple LEDs 123, a step of forming differentiated light conversion elements on the different LEDs 123 of each chip can be provided, for example, after the deposition of the cathode conductive layer 129 and before the fixation of the temporary support substrate 140. For simplicity, the formation of the conversion elements is not shown in detail in the figures. The implementation of these elements is within the scope of the ability of those skilled in the art to read this disclosure. As a variation, each basic chip may include LEDs 123 with different properties adapted to emit in different wavelength ranges, in which case the conversion elements may be omitted.

[0071] The basic pixel chip 153 is intended to be transferred onto the transfer substrate 200 of the display device, as will be described below. Figures 3A to 3E A more detailed description.

[0072] Figure 2 This is a partial and simplified top view of an example embodiment of the transfer substrate 200 of the display device.

[0073] exist Figure 2In the image, only a portion of the transfer substrate corresponding to two adjacent pixels in the same row as the display device is shown.

[0074] The transfer substrate 200 includes, for example, a support plate or sheet 201 made of an insulating material (e.g., glass or plastic). As a variation, the support plate or sheet 201 includes conductive supports (e.g., metallic) covered with a layer of insulating material. The transfer substrate also includes electrical connection elements, particularly conductive traces and conductive regions, formed on the upper surface of the support plate 201. These electrical connection elements are formed, for example, by printing a series of conductive and insulating layers on the upper surface of the support plate 201. The electrical connection elements are formed, for example, by deposition or printing methods such as inkjet printing, screen printing, gravure printing, vacuum deposition, or any other suitable method.

[0075] In the example shown, the transfer substrate 201 includes two conductive metal layers M1 and M2 separated by an insulating layer (not shown), and a metal via V connecting the two metal layers through the insulating layer. In this example, the transfer substrate 201 also includes a metal connection region formed on the upper metal layer M2, which is intended to connect to a corresponding connection region 131 of the basic pixel chip 153 of the device.

[0076] Active circuitry for controlling the display device (which is adapted to power and control the basic chip of the device via electrical connection elements of the transfer substrate) is, for example, connected to electrical connection elements of the transfer substrate at the periphery of the transfer substrate 200.

[0077] In the example shown, the fabrication of the transfer substrate includes the following three consecutive deposition steps.

[0078] During the first deposition step, a direction substantially parallel to the column of the display device is formed on the upper surface of the support plate 210. Figure 2 Multiple conductive traces (in the vertical direction of the orientation) are formed. More specifically, in this example, during the first deposition step, for each column of the display device, three conductive traces C1, C2, and C3 are formed extending substantially the entire length of the column of the display device. Trace C1 is intended to distribute a high power supply potential VDD to the different basic pixel chips 153. Trace C2 is intended to transmit a signal DATA_D for adjusting the light intensity emitted by the LEDs 123 of the basic chips 153 in the column. Trace C3 is intended to transmit a signal DATA_S representing the light intensity received by the photodetectors of the pixels in the column.

[0079] The conductive elements formed during this first deposition step define the first conductive layer M1 of the transfer substrate.

[0080] During the second deposition step, the first conductor is covered with an insulating material (not shown in the figure) to allow the subsequent deposition of conductive traces extending over traces C1, C2 and C3 without creating short circuits with traces C1, C2 and C3.

[0081] During the third deposition step, a plurality of conductive traces are formed on the upper surface of the support plate 201, substantially parallel to the direction of the rows of the display device. More specifically, in this example, during the third deposition step, for each row of the display device, two conductive traces L1 and L2 extending substantially the entire length of the row of the display device are printed. Trace L1 is intended to transmit a signal SELECT that selects the corresponding pixel row. Trace L2 is intended to assign a low power supply potential VK (e.g., below potential VDD) to the basic pixel chip 153.

[0082] In this example, during the third deposition step, for each pixel of the display device, a metal region EL1 defining the lower electrode of the photodetector of the display device is further printed.

[0083] The conductive elements printed during this third deposition step define the second conductive layer M2 of the transfer substrate.

[0084] Following the third deposition step, for each pixel, six metal regions P1, P2, P3, P4, P5, and P6 are formed on the conductive region of the metal layer M2. These regions are designed to receive the six individual connection regions 131 of the basic pixel chip 153, respectively. Regions P1, P2, P3, P4, P5, and P6 are connected to the conductive traces C1, C2, C3, L1, L2, and the pixel electrode EL1, respectively, through conductive elements formed in the metal layer M2 and optionally through vias V (opening between the second and third deposition steps) and conductive elements formed in the metal layer M1.

[0085] Figures 3A to 3E This is a cross-sectional view illustrating the sequential steps of an example method for manufacturing an interactive display device according to one embodiment.

[0086] Figure 3A and 3B More specifically, the steps of transferring the basic pixel chip 153 together onto the transfer substrate 200 are shown.

[0087] The base chip 153 is initially fixed to the surface of the temporary support substrate 140. For example, by bonding... Figures 1A to 1J The described method forms a structure including a temporary support substrate 140 and a base chip 153. In the example shown, this structure is relative to... Figure 1J The orientation is reversed, that is, the basic chip 153 is arranged on the lower surface side of the temporary support substrate 140.

[0088] For the sake of simplicity, Figures 3A to 3E The diagram schematically shows the basic chip 153 and the transfer substrate 200, and is related to... Figure 1J and Figure 2 Compared to the previous representation, many components have been omitted.

[0089] Using a temporary support base plate 140 as a handle ( Figure 3A ), on the connection surface of the transfer substrate 200 (i.e., on Figure 3A and Figure 3B The basic chips 153 are transferred together on the front of the upper surface of the transfer substrate 200 in the orientation.

[0090] Then, the connection terminals 131 of the base chip 153 located on the lower surface side of the chip contact the corresponding connection areas P1, P2, P3, P4, P5, P6 of the transfer substrate 200 and are fixed to the connection pads P1, P2, P3, P4, P5, P6. The fixing of the connection terminals 131 of the base chip 153 to the connection areas of the transfer substrate is performed, for example, by direct fixing, by hot pressing, by soldering, by means of metal microstructures (e.g., micropillars) previously formed on the terminals 131, or by any other suitable fixing and connection method.

[0091] Once secured to the transfer substrate 200 via their connection terminals 131, the base chip 153 is separated from the temporary support substrate 140, and the temporary support substrate 140 is removed. Figure 3B This allows access to the emitting surface of LED 123 (not in...). Figures 3A to 3E (See details in the text).

[0092] The spacing between the basic chips 153 on the transfer substrate 200 can be greater than the spacing between the basic microchips 153 on the temporary support substrate 140. Preferably, the spacing between the basic chips 153 on the transfer substrate 200 is a multiple of the spacing between the basic microchips 153 on the temporary support substrate 140. In this case, as... Figure 3A and Figure 3B As shown, each transfer samples only a portion of the chip 153 from the support substrate 140. The other chips 153 remain attached to the temporary support substrate 140 and can be used to fill another portion of the transfer substrate 200 or another transfer substrate during another common transfer step.

[0093] Figure 3C The apparatus is shown after all the basic chips 153 have been fixed to the transfer substrate 200.

[0094] Figure 3DThe following steps are illustrated: depositing a portion of a photosensitive organic layer 203 (e.g., sensitive in the infrared or near-infrared range) on top of and in contact with the upper surface of the pixel electrode EL1 in each pixel. The portion of layer 203 is deposited, for example, by a partial printing method, such as screen printing or by a slot-die coating method. In each pixel, the organic layer portion 203 extends, for example, across the entire upper surface of the pixel electrode EL1.

[0095] Figure 3E The steps are illustrated in which a top electrode EL2 is deposited on top of and in contact with a portion of the photosensitive organic layer 203 of the pixel. Electrode EL2 extends, for example, over the entire upper surface of the portion of the photosensitive organic layer 203 of the pixel. Electrode EL2 is transparent to the wavelength sensitive to layer 203. As an example, electrode EL2 is made of a transparent conductive oxide such as ITO. In this example, in each pixel, the stack of layers EL1, 203, and EL2 forms a photodetector 211. Electrodes EL1 and EL2, for example, correspond to the cathode and anode of the device, respectively.

[0096] Electrode EL2 can be deposited locally using a template. As an example, the upper electrode EL2 is common to all pixels of the device. Electrode EL2, for example, forms a continuous grid covering the photosensitive layer portion 203 of all pixels of the device in a top view. The common electrode EL2 can then be connected to an application node of a fixed bias potential VA at the periphery of the pixel array.

[0097] After electrode EL2 is deposited, a protective transparent insulating layer (not shown) can optionally be deposited on the entire upper surface of the structure using a conformal deposition method, particularly the organic layer 203 of the base chip 153 for encapsulating the pixel and the LED. The protective layer is made of, for example, aluminum oxide (Al2O3) or silicon oxide.

[0098] Figure 4 This is a circuit diagram of an example of the basic pixel chip 153 of an interactive display device of the type described above.

[0099] In this example, chip 153 has respectively with Figure 2 The chip is connected to the six terminals or the bonding pads 131 of the six connection areas P1, P2, P3, P4, P5 and P6 of the support substrate 200.

[0100] Figure 4 The chip 153 includes three display sub-pixels, R, G, and B, which are adapted to emit light in three different wavelength ranges, such as red, green, and blue light, respectively. The chip 153 also includes a READ circuit for reading signals representing the light intensity received by the photodetector 211 of the pixel.

[0101] Each of the R, G, and B sub-pixels includes a MOS transistor SW having a first conductive node coupled (e.g., connected) to a terminal P1 to which a high power supply potential VDD is applied, and a second conductive node coupled (e.g., connected) to the anode of the LED 123 of that sub-pixel. In this example, the transistor SW is a P-channel MOS transistor, with the source of each transistor SW coupled (e.g., connected) to terminal P1 and its drain coupled (e.g., connected) to the anode of the LED 123 of that sub-pixel.

[0102] In each of the R, G, and B subpixels, the cathode of the subpixel's LED 123 is coupled (e.g., connected) to a terminal P5 to which a low power supply potential VK is applied.

[0103] In this example, LED 123 is controlled using a binary-encoded digital setpoint signal, such as a PWM (Pulse Width Modulation) control method, for example, the type described in the applicant's previously filed patent application EP3079142. Each of the R, G, and B sub-pixels includes a memory circuit 401 (MEM), such as SRAM (Static Random Access Memory) or a D-type flip-flop, adapted to store a sequence of binary values ​​(0 or 1) that respectively define the off or on state of transistor SW, thereby the off or on state of LED 123 of the sub-pixel. As a variation, memory circuit 401 may include simple switches and low-leakage capacitive elements. Each memory circuit includes an output node, for example, connected to the control node (gate) of transistor SW. In this example, each of the R, G, and B sub-pixels also includes a D flip-flop 403 having a data input node D, a data output node Q coupled (e.g., connected) to the input node of the sub-pixel's memory circuit 401, and a control node CK coupled (e.g., connected) to a terminal P4 to which a control signal SELECT is applied. In this example, the flip-flops 403 of the different sub-pixels of the chip are connected in series. More specifically, in the example shown, the data input node D of the trigger 403 of the R sub-pixel is coupled (e.g., connected) to the terminal P2 where the transmitted data signal DATA_D is applied, the data input node D of the trigger 403 of the G sub-pixel is coupled (e.g., connected) to the output node Q of the trigger 403 of the R sub-pixel, and the data input node D of the trigger 403 of the B sub-pixel is coupled (e.g., connected) to the output node Q of the trigger 403 of the G sub-pixel.

[0104] In this example, the circuit READ for reading from photodetector 211 includes three N-channel MOS transistors RST, SF, and RD. The drain of transistor RST is coupled (e.g., connected) to terminal P1 where a high supply potential VDD is applied, and its source is coupled (e.g., connected) to the cathode terminal P6 of photodetector 211. Figure 2 and Figures 3A to 3E In the example, electrode EL1 is used. In this example, the gate of transistor RST is connected to the drain of the same transistor. The drain of transistor SF is coupled (e.g., connected) to terminal P1, and its source is coupled (e.g., connected) to the drain of transistor RD. The gate of transistor SF is coupled (e.g., connected) to the source of transistor RST. The source of transistor RD is coupled (e.g., connected) to terminal P3 to provide the output signal DATA_S of the photodetector. The gate of transistor RD is coupled (e.g., connected) to terminal P4 where the control signal SELECT is applied.

[0105] Figure 5 It is shown schematically. Figure 4 A diagram illustrating the operation of the basic pixel chip 153. Specifically, Figure 5 The temporal variations of signals SELECT, DATA_S, DATA_D, MEM(R), MEM(G), and MEM(B) contained in the memory MEM of subpixels R, G, and B are shown.

[0106] In this example, the corresponding emission setpoint signals DATA R, DATA G, and DATA B of the LED 123 of the R, G, and B sub-pixels are time-division multiplexed digital signals (signal DATA_D) on terminal P2. At each rising edge of signal SELECT, the emission data bit of signal DATA_D is transmitted from terminal P2 to the memory 401 of the R sub-pixel, the preceding emission data bit is transmitted from the output terminal Q of the D flip-flop 403 of the R sub-pixel to the memory 401 of the G sub-pixel, and the previous emission data bit is transmitted from the output terminal Q of the D flip-flop 403 of the G sub-pixel to the memory 401 of the B sub-pixel. Therefore, three cycles of signal SELECT are required to transmit the three setpoint signals to the three R, G, and B sub-pixels of the display device, respectively.

[0107] The diode configuration of the transistor RST, operating in a weak inversion state, means that the voltage at its source responds logarithmically to the current flowing through its channel (in this case, the photocurrent generated by photodiode 211). Therefore, the readout circuit READ performs a logarithmic reading of the photocurrent generated by photodetector 211. During each activation cycle of the signal SELECT, the transistor RD of the readout circuit READ is turned on. The signal DATA_S delivered to the output terminal P3 is an analog voltage representing the instantaneous brightness received by the pixel photodetector 211. The signal DATA_S can be read and digitized at the bottom of the column. As an example, at each update of the emission setpoint signals of the R, G, and B sub-pixels of the chip, the pixel's signal DATA_S can be read three times consecutively, and the average of these three values ​​can be calculated to minimize readout noise.

[0108] Figure 6 This is a circuit diagram of another example of the circuit of the basic pixel chip 153 of the interactive display device of the above type.

[0109] In this example, the base chip 153 includes nine separate connection pads 131, which are designed to connect to nine separate metal connection areas P1, P2, P3, P4, P5, P6, P7, P8 and P9, respectively.

[0110] The interconnections of terminals P1, P2, P3, P4, and P5 of the individual pixels in the rows and columns are the same as or similar to those previously described. As in the previous example, terminal P6 is connected to the lower electrode (cathode) of the pixel photodetector 211. In this example, terminals P7 of pixels in the same column are interconnected via conductive traces in the same column (e.g., formed in layer M1 of the transfer substrate). Similarly, terminals P8 of pixels in the same column are interconnected via conductive traces in the same column (e.g., formed in layer M1 of the transfer substrate). Furthermore, in this example, terminals P9 of pixels in the same row are interconnected via conductive traces in the same row (e.g., formed in layer M2 of the transfer substrate). Those skilled in the art will be able to adjust the formation of the transfer substrate 200 of the device accordingly.

[0111] With Figure 4 The same as in the example, Figure 6 The chip 153 includes three display sub-pixels, R, G, and B, which are adapted to emit light in three different wavelength ranges, such as red, green, and blue light, respectively. The chip 153 also includes a READ circuit for reading signals representing the light intensity received by the photodetector 211 of the pixel.

[0112] Figure 6 Chip 153 and Figure 4 The difference between chip 153 and chip 153 is that... Figure 6 In the example, the emission setpoint signals DATA R, DATA G, and DATA B of different sub-pixels R, G, and B are not time-division multiplexed on a single data input terminal of the chip, but are applied in parallel to terminals P2, P7, and P8 respectively.

[0113] Therefore, in Figure 6 In the example, the following is omitted Figure 4 The chip 153 has a trigger 403 for the sub-pixel. In each of the R, G, and B sub-pixels, the memory circuit 401 has a data input node coupled (e.g., connected) to the corresponding data input terminals P2, P7, P8 of the sub-pixel, and a control node coupled (e.g., connected) to the terminal P4 to which the control signal SELECT is applied.

[0114] Figure 6 Chip 153 and Figure 4The difference between the chip 153 and the chip 153 is that, Figure 6 In the example, the gate of the reset transistor RST in the read circuit READ is not coupled to the drain of the transistor RST, but is connected to terminal P9, which has a reset control signal RESET applied to it.

[0115] Figure 7 It is shown schematically. Figure 6 A diagram illustrating the operation of the basic pixel chip 153. Figure 7 The time variations of signals RESET, SELECT, DATA_S, DATA R, DATA G, and DATA B are shown in more detail.

[0116] In this example, the RESET signal enables the reset transistor RST of the readout circuit READ of the photodetector 211. This allows a first value of the signal DATA_S to be sampled at the end of the integration cycle (during which the reset transistor RST remains off) and then immediately after the reset cycle of the photodetector 211 (during which the reset transistor RST remains on, and the end of the reset cycle marks the start of the second integration cycle) to be sampled. The difference between the two read values ​​defines the pixel's output value. Thus, double-sample readout is performed.

[0117] The described embodiments are not limited to the combination Figures 4 to 7 An example of a described electronic control circuit. As a variation, in... Figure 6 In the example, terminal P9 can be omitted, and the gate of the reset transistor RST is connected to the drain of the same transistor RST. This results in a chip with eight terminals, which, for its photodetector section, has... Figure 4 Similar to the operation of chips.

[0118] In another variation, Figure 4 In the example, the gate of the reset transistor RST may not be connected to the drain of the same transistor, but instead to an external terminal (not shown) intended to receive a reset control signal. This results in a chip with seven terminals, which, for its photodetector section, has... Figure 6 Similar to the operation of chips.

[0119] In another variation, Figure 4 In the example, an additional D flip-flop can be added to the readout circuit READ of the photodetector 211. This allows the reset transistor RST to be controlled according to the same offset principle as the LEDs 123 of the R, G, and B subpixels. A fourth control bit is then introduced into the signal DATA_D to drive the transistor RST. As an example, the transistor RST is controlled by the signal DATA_S ( Figure 5After three consecutive reads, it is controlled to be in the on state. In this case, the read circuit READ is preferably located on the right side of the circuit, that is, the additional trigger of the circuit READ has an input node connected to the output node Q of the trigger 403 of the B sub-pixel, an output node connected to the gate of the transistor RST, and a control node connected to the terminal P4 of the applied signal SELECT.

[0120] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to them. In particular, the described embodiments are not limited to combinations... Figures 1A to 1J , Figure 2 ,as well as Figures 3A to 3E Specific examples of embodiments of the described basic pixel chip and transfer substrate.

[0121] Furthermore, the described embodiments are not limited to the combination of Figures 4 to 7 Specific examples of embodiments of the described electronic circuitry for controlling a basic pixel chip.

[0122] Furthermore, the described embodiments are not limited to the specific case described above where the photodetector of the device is an organic photodiode. As a variation, the organic photodetector of the device can be replaced by an inorganic photodetector, such as an inorganic photodetector based on a III-V type semiconductor material, such as an indium gallium arsenide-based photodetector or an inorganic photodetector based on amorphous silicon. In another variation, the photodetector 211 can be formed from, for example, a matrix layer made of resin incorporating quantum dots.

[0123] More generally, any other capturing or actuating element can be used to completely or partially replace the photodetector. These capturing or actuating elements can be of any type. Non-limiting examples of such elements could be, for example, ultrasonic or acoustic transducers, such as piezoelectric transducers. This, for example, enables touch detection or proximity detection of objects (e.g., a user's hand) using direct piezoelectric effects, and / or tactile stimulation, and / or directional sound wave emission using, for example, indirect piezoelectric effects.

[0124] Therefore, actuation means, for example, the actuation of a piezoelectric actuator, in order to generate ultrasonic or vibrational patterns that can produce a tactile effect that is perceptible to the user.

[0125] As an example, piezoelectric actuators can be used to replace all or part of the photodetectors, each piezoelectric actuator comprising a stack of the following items:

[0126] - The lower electrode, for example, is metallic, made of silver, molybdenum, platinum, gold, or an alloy of one or more of these materials.

[0127] - A piezoelectric material layer, such as lead zirconium titanate (PZT), aluminum nitride (AlN), or any other piezoelectric material, and

[0128] - The upper electrode is, for example, metallic, made of silver, molybdenum, platinum, ruthenium, gold, or an alloy of one or more of these materials.

[0129] Applying an electric field between the upper and lower electrodes causes deformation of the piezoelectric material. Depending on the transmitted signal, such as a sinusoidal signal at a frequency defined as a specific operating frequency, the actuator generates ultrasonic waves or vibration patterns (e.g., bending mode type, or antisymmetric Lamb mode), capable of producing a tactile effect. This effect may be due to a change in the coefficient of friction, particularly when the generated vibration pattern is a Lamb mode.

[0130] The electronic circuitry used for reading from the base chip 153 is then replaced with electronic circuitry used for controlling the capture or actuation elements (e.g., circuitry for controlling the ultrasonic transducer during transmission and / or reception).

[0131] As an example, in Figure 6 In one embodiment, the RESET signal can be replaced by a control signal, such as a pulse or sine wave, which is used to actuate a capture or drive element (e.g., a piezoelectric element) instead of a photodiode when the SELECT signal is active.

[0132] As an example, the above is combined Figures 3A to 3E In the described method, the photosensitive organic layer 201 is replaced by a piezoelectric or ferroelectric layer, for example, made of aluminum nitride (AlN), lead zirconate titanate (PZT), or zinc oxide (ZnO). The stack comprising the lower electrode EL1, the piezoelectric layer, and the upper electrode EL2 can be directly deposited on the substrate 201, or fabricated separately and transferred onto the substrate 201. Each of electrodes EL1 and EL2 can be made of a metal or a transparent conductive oxide.

[0133] As a variation, the capture or actuation element can be arranged on the substrate 201 before the transfer step of the basic chip 153.

[0134] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art.

Claims

1. An apparatus comprising: - Transfer substrate (200), which includes electrical connection elements; as well as - Multiple discrete monolithic base chips (153) are fixedly and electrically connected to the transfer substrate (200). Each base chip (153) includes at least one LED (123) and electronic control circuitry, the electronic control circuitry including multiple transistors and circuitry for controlling the at least one LED (123). The device also includes a capture or actuation element associated with at least one base chip (153) external to the base chip (153), the capture or actuation element being fixed and electrically connected to the transfer substrate (200), wherein, in each base chip (153), the electronic control circuitry further includes electronic circuitry for reading from or controlling the capture or actuation element associated with the chip.

2. The apparatus of claim 1, wherein each capturing and actuating element is a photodetector.

3. The apparatus of claim 2, wherein each photodetector (211) comprises a photosensitive organic layer.

4. The apparatus according to any one of claims 1 to 3, wherein, In each basic chip (153), the at least one LED (123) is an inorganic LED.

5. The apparatus according to claim 4, wherein, In each basic chip (153), the at least one LED (123) is a gallium nitride LED.

6. The apparatus according to any one of claims 1 to 3, wherein, Each basic chip (153) includes multiple sub-pixels (R, G, B), and each sub-pixel includes an LED (123) and circuitry for controlling the LED (123).

7. The apparatus according to claim 6, wherein, In each basic chip (153), the circuit for controlling the LEDs (123) of different sub-pixels (R, G, B) of the chip is connected to the same input terminal of the chip, which is connected to a corresponding connection area of ​​the transfer substrate (200) to sequentially receive the emission setpoint signals (DATA R, DATA G, DATA B) of different sub-pixels (R, G, B) of the chip.

8. The apparatus according to claim 6, wherein, In each basic chip (153), the circuit for controlling the LEDs (123) of different sub-pixels (R, G, B) of the chip is connected to different input terminals of the chip, which are connected to different corresponding connection areas of the transfer substrate (200) to receive the emission setpoint signals (DATA R, DATA G, DATA B) of different sub-pixels (R, G, B) of the chip in parallel.

9. The apparatus according to any one of claims 1 to 3, wherein, In each basic chip (153), the circuitry for controlling the at least one LED (123) is configured to control the at least one LED by means of a binary-coded digital setpoint signal.

10. The apparatus according to claim 2, wherein, In each basic chip (153), the circuit (READ) for reading from the photodetector (211) associated with the chip is connected to the output terminal of the chip, which is connected to a corresponding connection area of ​​the transfer substrate (200) and is intended to deliver a signal (DATA_S) representing the light intensity received by the photodetector (211).

11. The apparatus according to claim 1, wherein, The capturing or actuating element is a piezoelectric transducer.

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