Imaging element and imaging device

Abstract

The photodiode (23), the first FD (21), the second FD (22), the TRG transistor (24), the amplification transistor (25), the DGC transistor (28) that switches the conversion gain when converting the charge into the pixel signal to the high gain or the low gain, the capacitor (29), the OFG transistor (30) that transfers the charge overflowing from the photodiode (23) to the second FD (22), the RST transistor (27), in the imaging operation in which the exposure time is long, after resetting in the state in which the conversion gain is switched to the high gain, the pixel signal is read as the high gain reset signal, thereafter, after the TRG transistor (24) is made to be on, the pixel signal is read as the high gain signal, and the first signal that is the difference between the high gain signal and the high gain reset signal is output.

Description

Technical Field

[0001] This invention relates to imaging elements and imaging devices. Background Technology

[0002] Previously, it was known that in camera devices with imaging elements, when capturing images of LED light sources, a phenomenon known as LED flicker would occur. LED flicker refers to the following phenomenon: the LED light source flickers at a certain frequency and at high speed, so depending on the timing of the flicker and the exposure time of the imaging element, the LED light source in the image may sometimes flicker or turn off.

[0003] Increasing the exposure time of the camera element reduces LED flicker, but generates a charge exceeding the capacity of the photodiode, causing it to saturate and fail to output a signal corresponding to brightness. To address this saturation, a technique has been proposed that combines images obtained through long exposures for low-light subjects and short exposures for high-light subjects. However, since LED light sources are high-light, short exposures are chosen, resulting in the LED flicker described above.

[0004] To solve the problems of LED flicker and photodiode saturation, the following device is known: adding a dual gain control transistor (hereinafter, DGC transistor) and a large-capacity capacitor capable of storing a large amount of charge generated due to long exposure to a general imaging element (for example, see Patent Document 1).

[0005] Here, use Figure 5 This simply explains the pixels of traditional camera elements. Figure 5 It is a circuit diagram of the pixels that were present in traditional camera elements.

[0006] Figure 5 The pixel 100 shown is constructed as follows: each pixel has 4 transistors, and a so-called 4Tr pixel is supplemented with a DGC transistor 28 and a large-capacity capacitor 29 capable of storing a large amount of charge generated due to long exposure.

[0007] The charge stored in the photodiode 23 is transferred to the first floating diffusion section (hereinafter, the first FD) 21 via the transfer transistor (hereinafter, the TRG transistor) 24. Even when the TRG transistor 24 is in a non-conducting state, the charge overflowing from the photodiode 23 is also transferred to the first FD 21.

[0008] Even when TRG transistor 24 is in a non-conducting state, the charge overflowing from photodiode 23 accumulates in the first FD 21. Therefore, the first FD 21 cannot be reset before the charge is read as a signal.

[0009] As a result, the reset level after a long exposure depends on the subject and the exposure time, making it difficult to converge the signal of pixel 100 within the range of the AD converter. In addition, although a reset is performed before the start of the long exposure, the time until the charge is read as a signal is longer, resulting in noise degradation in the signal obtained from pixel 100.

[0010] In addition, generally speaking, regarding the pixels of a camera element, there is a technique called pixel sharing, which involves sharing a portion of adjacent pixels, as reported in Patent Documents 2 and 3.

[0011] exist Figure 7 The document describes a pixel 101 that shares the floating diffuser portion of so-called 4Tr pixels. Without using pixel sharing, 4Tr × 4 pixels = 16Tr are needed, but in the pixel-shared pixel 101, 7Tr is also possible, so it is a necessary technique for miniaturization.

[0012] However, regarding Figure 5 As shown in the image, during the exposure time, the charge overflowing from the photodiode 23 of the pixel 100 flows into the common floating diffusion section 21. Therefore, when pixel sharing is performed, the charges of adjacent pixels 100 in the floating diffusion section 21 are mixed, so pixel sharing cannot be performed, and miniaturization is limited.

[0013] Existing technical documents

[0014] Patent documents

[0015] Patent Document 1: U.S. Publication No. 2017 / 0099423

[0016] Patent Document 2: Japanese Patent Application Publication No. 10-256521

[0017] Patent Document 3: Japanese Patent Application Publication No. 2006-54276 Summary of the Invention

[0018] The present invention was made in view of the following reasons, and its object is to provide an imaging element and imaging device that solves the problems of LED flicker and photodiode saturation, enables pixel sharing, easily converges the pixel signal to the range of the AD conversion device, and obtains a signal with reduced noise effects.

[0019] A first solution of the present invention to solve the above-mentioned problems is an imaging element, characterized by comprising: a photodiode that generates charge through photoelectric conversion; a first floating diffuser and a second floating diffuser that convert the charge into a potential corresponding to the amount of charge; a transfer transistor that transfers the charge of the photodiode to the first floating diffuser; an amplification transistor that generates a pixel signal corresponding to the potential converted by the first floating diffuser; a dual-gain control transistor disposed between the first floating diffuser and the second floating diffuser for switching the conversion gain when converting the charge into a pixel signal to high gain or low gain; a capacitor connected to the second floating diffuser; an overflow gate transistor disposed between the photodiode and the second floating diffuser; and a reset transistor that resets the first floating diffuser. The voltages of the diffusion section, the second floating diffusion section, the photodiode, and the capacitor are reset, and the imaging element can perform a series of imaging actions including shutter action, exposure, and pixel signal reading. The transmission transistor and the overflow gate transistor are set to be in a non-conducting state. During exposure, the charge overflowing from the photodiode flows into the second floating diffusion section and the capacitor. In the reading action of the imaging action, when the dual gain control transistor is switched to a high gain state, the pixel signal is read as a high gain reset signal after being reset by the reset transistor. Then, the pixel signal is read as a high gain signal after the transmission transistor is turned on, and a first signal is output as the difference between the high gain signal and the high gain reset signal.

[0020] The second aspect of the present invention, in the imaging element described in the first aspect, is characterized in that, during the reading operation of the imaging action, after reading the first signal, while the dual-gain control transistor is switched to a low gain state, the pixel signal is read as a low gain signal after the transmission transistor is turned on, and then, after resetting using the reset transistor, the pixel signal is read as a low gain reset signal, and a second signal is output as the difference between the low gain signal and the low gain reset signal.

[0021] The third aspect of the present invention, in the imaging element described in the first or second aspect, is characterized in that, during the readout operation of an imaging operation in which the exposure time is shorter than the imaging operation, in a state where the dual-gain control transistor is switched to high gain, after resetting using the reset transistor, the pixel signal is read as a short-time reset signal, and then, after the transmission transistor is turned on, the pixel signal is read as a short-time signal, and a third signal is output as the difference between the short-time signal and the short-time reset signal.

[0022] The fourth aspect of the present invention, in the imaging element described in any one of the first to third aspects, is characterized in that the capacitor is connected to a line selection signal, the line selection signal being capable of setting a first potential during exposure and a second potential during readout to be different.

[0023] The fifth aspect of the present invention, in the imaging element described in any one of the first to fourth aspects, is characterized in that the overflow gate transistor is turned on only during reset, or the imaging operation is always performed in a non-conducting state.

[0024] The sixth aspect of the present invention, in the imaging element described in any one of the first to fifth aspects, is characterized in that each pixel has the photodiode, the transmission transistor, the overflow gate transistor, the dual gain control transistor, and the second floating diffusion section, such that the first floating diffusion section, the reset transistor, the amplification transistor, and the row selection transistor for row selection are shared among multiple adjacent pixels.

[0025] The imaging device of the seventh aspect of the present invention is characterized by having an imaging element described in any one of the first to sixth aspects.

[0026] The present invention provides the following imaging element and imaging device: solving the problems of LED flicker and photodiode saturation, enabling pixel sharing, easily converging the pixel signal into the range of the AD conversion device, and obtaining a signal with reduced noise effects. Attached Figure Description

[0027] Figure 1 This is a block diagram showing the structure of the camera element according to Embodiment 1.

[0028] Figure 2 This is a circuit diagram showing the structure of the pixel in Embodiment 1.

[0029] Figure 3 This is a timing diagram of the camera element in Implementation Method 1.

[0030] Figure 4 This is a circuit diagram showing the structure of the pixel-shared pixels in Embodiment 1.

[0031] Figure 5 This is a circuit diagram illustrating the structure of a pixel in the prior art.

[0032] Figure 6 This is a timing diagram of existing camera elements.

[0033] Figure 7 This is a circuit diagram illustrating the structure of pixels sharing in the prior art.

[0034] (Symbol Explanation)

[0035] 10: Camera element; 20: Pixel; 21: First floating diffuser; 22: Second floating diffuser; 23: Photodiode; 24: TRG transistor; 25: Amplifying transistor; 26: SEL transistor; 27: RST transistor; 28: DGC transistor; 29: Capacitor; 30: OFG transistor. Detailed Implementation

[0036] <Implementation Method 1>

[0037] like Figure 1 As shown, the imaging element 10 in this embodiment is an XY address-based CMOS sensor capable of reading out pixel signals for each pixel 20. Specifically, the imaging element 10 includes a pixel array unit 11, a row scanning unit 12, a column processing unit 13, a column scanning unit 14, a timing control unit 15, row control lines 16, column signal lines 17, and a signal processing unit 18. In this embodiment, each part of the imaging element 10 can be mounted on the same substrate, and some parts, such as the signal processing unit 18, can be mounted on other substrates.

[0038] The pixel array section 11 is a structure in which many pixels 20 are arranged in a matrix-like two-dimensional configuration. The analog signals output from the pixels 20 are called pixel signals. The detailed structure of the pixels 20 will be described later.

[0039] The pixel array section 11 arranges row control lines 16 for each row and column signal lines 17 for each column of the matrix-configured pixels 20. The row control lines 16 transmit drive signals for driving the readout of pixel signals from the pixels 20.

[0040] The row scanning unit 12 includes a shift register, an address decoder, etc., and drives each pixel on a row-by-row basis. The pixel signal output from each pixel 20 of the row selected by the row scanning unit 12 is input to the column processing unit 13 via the column signal line 17 for each column.

[0041] The column processing unit 13 performs various processing operations on the pixel signals, such as Correlated Double Sampling (CDS) and Double Data Sampling (DDS). Furthermore, the column processing unit 13 has an analog-to-digital conversion function, converting analog pixel signals into digital pixel signals.

[0042] The column scanning unit 14 includes a shift register, an address decoder, etc., and sequentially selects the unit circuits corresponding to the columns of pixels 20 in the column processing unit 13. Through the selection scan performed by the column scanning unit 14, pixel signals that have undergone signal processing for each unit circuit in the column processing unit 13 are output sequentially.

[0043] The timing control unit 15 generates clock signals, control signals, etc., which serve as the reference for the operation of the row scanning unit 12, column processing unit 13, and column scanning unit 14, and applies clock signals, control signals, etc. to the row scanning unit 12, column processing unit 13, and column scanning unit 14 to perform control.

[0044] The signal processing unit 18 performs signal processing on the pixel signals output from the column processing unit 13. Examples of signal processing include various image processing techniques such as black level correction, buffering of digital pixel signals, deviation correction, and tone correction. Furthermore, the signal processing unit 18 can also convert N-bit parallel pixel signals into serial pixel signals and output them externally.

[0045] use Figure 2 Pixel 20 is described below. Pixel 20 includes a photodiode 23, a transmission transistor (hereinafter, TRG transistor) 24, a first floating diffuser 21 (hereinafter, 1FD21), a second floating diffuser 22 (hereinafter, 2FD22), an amplification transistor 25, a row selection transistor (hereinafter, SEL transistor) 26, a reset transistor (hereinafter, RST transistor) 27, a DGC transistor 28, a capacitor 29, and an overflow gate transistor (hereinafter, OFG transistor) 30.

[0046] Photodiode 23 is a device that stores electrons corresponding to the amount of light. The charge stored in photodiode 23 is transferred to the first FD 21 via TRG transistor 24. In addition, when the charge in photodiode 23 becomes saturated and overflows, the overflowing charge is transferred to the second FD 22 even if OFG transistor 30 is in a non-conducting state.

[0047] The first FD21 and the second FD22 convert the charge transferred from the photodiode 23 into a voltage signal and output it. The first FD21 is positioned between the TRG transistor 24 and the amplifying transistor 25. Additionally, the RST transistor 27 and the DGC transistor 28 are connected to the first FD21. The second FD22 is positioned between the DGC transistor 28 and the capacitor 29. Furthermore, the OFG transistor 30 is connected to the second FD22.

[0048] TRG transistor 24 is positioned between photodiode 23 and the first FD 21. When its gate is turned on, TRG transistor 24 transfers electrons from photodiode 23 to the first FD 21.

[0049] RST transistor 27 is positioned between the power supply voltage VDD and the first FD21. RST transistor 27 is turned on when the reset signal RST is applied, and the potential of the first FD21 is reset to the power supply voltage VDD.

[0050] The first FD21 is connected to the gate of the amplifying transistor 25, and the power supply voltage VDD and the SEL transistor 26 are connected to the drain and source. The amplifying transistor 25 outputs a pixel signal corresponding to the amount of charge transferred to the first FD21 to the SEL transistor 26.

[0051] SEL transistor 26 is a transistor used to select the row pixel 20. SEL transistor 26 is turned on (conducted) according to the row selection signal SEL input from the row scanning unit 12, and transmits the pixel signal output from the amplifying transistor 25 to the column signal line 17.

[0052] DGC transistor 28 is connected between 1FD21 and 2FD22. DGC transistor 28 switches the conversion gain of 1FD21 when converting charge into a voltage signal to either high or low gain. When DGC transistor 28 is turned on, 1FD21 and capacitor 29 are turned on, entering a state known as Low Conversion Gain (LCG). In the LCG state, charge is accumulated not only in 1FD21 but also in capacitor 29, allowing pixel 20 to handle a large amount of charge.

[0053] On the other hand, when the DGC transistor 28 is turned off, no charge is stored in the capacitor 29, so it cannot handle a larger charge than in the LCG state. However, it becomes a high-gain (HCG) state, which is known for its high efficiency in converting charge to potential. Generally speaking, HCG performs better for low-light subjects.

[0054] Capacitor 29 is connected to the second FD22 and the row selection signal SEL (in Figure 2 This is referred to as Floating Diffusion Control (FDC). The capacitance of capacitor 29 is set to a level capable of storing the large amount of charge generated in photodiode 23 due to prolonged exposure as described later. Furthermore, except during the readout of pixel signals as described later, the potential V2 of FDC is preferably set such that the potential difference between the second FD22 and ground (GND) is as small as possible. This potential difference can be set to be adjustable or fixed.

[0055] The OFG transistor 30 branches off from the photodiode 23 and the TRG transistor 24 and connects to the second FD 22. Even when both the OFG transistor 30 and the TRG transistor 24 are in a non-conducting state, the charge overflowing from the photodiode 23 will still flow into the second FD 22 through the OFG transistor 30. The non-conducting state of the OFG transistor 30 refers to a state where the potential V1 applied to the gate is set in such a way that the charge overflowing from the photodiode 23, as described above, can flow into the second FD 22 through the OFG transistor 30. The gate of the OFG transistor can also be fixed at potential V1.

[0056] use Figure 3 This describes the action of pixel 20. Figure 3 This is a timing diagram used to illustrate the operation of pixels. The LED timing at the top of the diagram represents the LED light source being turned on (lit up) in bright white, and the gray area represents the time it is turned off (extinguished). In this example, the LED light source is turned on for a certain period of time every 1 / 100th of a second, and then turned off.

[0057] Additionally, SEL is the row selection signal applied to SEL transistor 26. TRG is the signal applied to TRG transistor 24. DGC is the signal applied to DGC transistor 28. RST is the signal applied to RST transistor 27. OFG is the signal applied to OFG transistor 30. For any signal, ON indicates a conducting state, and OFF indicates a non-conducting state. These signals are input to each transistor by the timing control unit 15. Furthermore, FDC indicates its potential.

[0058] The imaging device in this embodiment refers to a series of actions, including shutter action, exposure, and pixel signal reading, as an imaging action. It can execute a first imaging action and a second imaging action based on the length of the exposure time. In the first imaging action, the exposure time is relatively long, and in the second imaging action, the exposure time is relatively short.

[0059] The first camera action is described below. First, the shutter action is performed (time T0). Specifically, during the shutter action, TRG transistor 24, DGC transistor 28, RST transistor 27, and OFG transistor 30 are all turned on. Through the shutter action, all the charges stored in photodiode 23, first FD 21, second FD 22, and capacitor 29 are reset.

[0060] After the shutter action ends, TRG transistor 24, DGC transistor 28, RST transistor 27, and OFG transistor 30 are all turned off, and exposure begins. This exposure occurs before TRG transistor 24 is turned on during the readout operation. During exposure, a charge corresponding to the amount of light remains in photodiode 23.

[0061] Furthermore, the FDC is turned off during the exposure process, specifically from the reset operation to the start of the readout operation. The potential V2 when the FDC is off is set to minimize the potential difference between the second FD22 and GND. At least, the potential V2 is lower than the potential when the row selection signal SEL is on. Thus, by decreasing the potential V2 of the FDC during exposure, the potential difference between the second FD22 and GND can be reduced. As a result, leakage current is reduced, and white spots in the pixel signal are suppressed.

[0062] Regarding exposure, to reduce the impact of LED flicker, a long exposure of 1 / 100s or more is set. When such a long exposure is used, the photodiode 23 is prone to saturation. As described above, it is designed so that even if the OFG transistor 30 is in a non-selected state, the charge overflowing from the photodiode 23 flows into the capacitor 29 via the second FD 22.

[0063] Next, the charge readout operation of photodiode 23 is performed (times T1-T5). Specifically, firstly, at time T1, SEL transistor 26 and RST transistor 27 are turned on. Additionally, FDC is turned on during the readout operation. By turning on RST transistor 27, the first FD21 is reset.

[0064] After the aforementioned reset, the pixel signal is read at time T2 after RST transistor 27 becomes off. This pixel signal is the reset signal of DGC transistor 28 in the off state, i.e., the HCG state, and will be referred to hereafter as HCG_rst (which is the high-gain reset signal described in the claims). HCG_rst is sent to column processing unit 13 via column signal line 17 and read by column processing unit 13. The reading of the pixel signal by column processing unit 13 is well known, so detailed description is omitted. HCG_signal, LCG_rst, LCG_signal, Short_signal, and Short_rst, which will be described later, are also read in the same way as HCG_rst.

[0065] Next, after time T2, TRG transistor 24 is turned on. As a result, the charge of photodiode 23 is transferred to the first FD 21. Then, at time T3, when TRG transistor 24 is turned off, the pixel signal is read. This pixel signal is also referred to as HCG_signal (the high-gain signal described in the claims).

[0066] From now on, HCG_signal-HCG_rst will be referred to as the first signal. The first signal represents the pixel signal after the charge at photodiode 23 changes under the HCG state at the time of readout (time T1). In addition, the processing of obtaining the first signal from HCG_signal and HCG_rst is performed by column processing unit 13, but since it is a known structure, detailed description is omitted.

[0067] Next, after reading the first signal, TRG transistor 24 and DGC transistor 28 are turned on. This turns on first FD 21, second FD 22, photodiode 23, and capacitor 29. All the charge accumulated in them is converted into a pixel signal. The pixel signal is read at time T4 after TRG transistor 24 is turned off. This pixel signal, converted from charge to signal in LCG state, is hereby referred to as LCG_signal (the low-gain signal described in the claims).

[0068] Next, after reading LCG_signal, RST transistor 27 is turned on, and then the pixel signal is read at time T5 after it is turned off. This pixel signal is the signal after being reset in the LCG state, and will be referred to as LCG_rst (which is the low-gain reset signal described in the claims).

[0069] From now on, LCG_signal-LCG_rst will be referred to as the second signal. The second signal represents the pixel signal after the charge at the first FD21, the second FD22, the photodiode 23, and the capacitor 29 has been transformed in the LCG state. Furthermore, the processing of obtaining the second signal from LCG_signal and LCG_rst is performed by the column processing unit 13, but since it is a known structure, detailed explanation is omitted.

[0070] Next, we will explain the second shooting action, which involves a short exposure. A short exposure is, for example, performed for a time shorter than 1 / 100th of a second.

[0071] Regarding DGC transistor 28, it becomes off after a long exposure. Additionally, during short exposures, FDC is maintained at potential V2. First, the shutter action is performed (time T6). Specifically, during the shutter action, TRG transistor 24, RST transistor 27, OFG transistor 30, and DGC transistor 28 are all turned on. Through the shutter action, all charges remaining in photodiode 23, first FD 21, second FD 22, and capacitor 29 are reset.

[0072] After the shutter action ends, TRG transistor 24, RST transistor 27, OFG transistor 30, and DGC transistor 28 are turned off, and exposure begins. This exposure occurs before TRG transistor 24 is turned on during the readout action. During exposure, a charge corresponding to the amount of light remains in photodiode 23.

[0073] Next, the charge readout operation of photodiode 23 is performed (times T7-T9). Specifically, at time T7, SEL transistor 26 and RST transistor 27 are turned on, and the first FD21 is reset by turning on RST transistor 27.

[0074] Next, a reset is performed, and the pixel signal is read at time T8 after RST transistor 27 becomes off. This pixel signal is the pixel signal of DGC transistor 28 in the off state, i.e., HCG state, and will be referred to hereafter as Short_rst (the short-time reset signal described in the claims).

[0075] Next, after reading Short_rst, TRG transistor 24 is turned on. As a result, charge is transferred from photodiode 23 to the first FD 21. At time T9, after TRG transistor 24 is turned off, a pixel signal is read. This pixel signal is the pixel signal in the HCG state, and will hereafter be referred to as Short_signal (the short-duration signal described in the claims).

[0076] Hereafter, Short_signal-Short_rst will be referred to as the third signal. This third signal represents the pixel signal after the charge amount at photodiode 23 changes under HCG state during a short exposure. Furthermore, the processing of obtaining the third signal from Short_signal and Short_rst is performed by column processing unit 13, but since this is a known structure, detailed explanation is omitted.

[0077] The imaging element 10 combines the first and second signals obtained as described above, thereby preventing saturation even during long exposures and enabling the output of a signal that suppresses LED flicker. Furthermore, by combining the first to third signals, LED flicker is suppressed, and a high dynamic range image can be formed. The combination of these first to third signals is performed by the signal processing unit 18, but since it can be performed using known methods, detailed descriptions are omitted.

[0078] exist Figure 4 In addition to the present invention, an example of pixel sharing in which floating diffusion portions of four adjacent pixels are shared is also described.

[0079] Pixel 20A is composed of photodiode 23, TRG transistor 24, DGC transistor 28, OFG transistor 30, second FD 22, and capacitor 29. In this example, four pixels 20A are formed. One of the first FD 21, RST transistor 27, amplification transistor 25, and SEL transistor 26 is shared among the four pixels 20A. In this structure, during exposure, the charge overflowing from each photodiode 23 flows into the second FD 22 and capacitor 29 of each pixel 20A, so no charge from each pixel 20A is mixed into the shared first FD 21.

[0080] Furthermore, regarding FDC, it's possible to use different signals for the four pixels at 20A, or to use a common signal for all four pixels to reduce wiring. Regarding OFG, it's also possible to use different signals for the four pixels at 20A, or to use a common signal for all four pixels to reduce wiring; a method where all four pixels are set to a fixed potential is also considered. Regarding the readout of shared pixels, it can be performed using known methods, so detailed explanations are omitted.

[0081] Here, use Figure 5 as well as Figure 6 For comparison with the imaging element 10 of this embodiment described above, a conventional pixel 100 will be described. Elements in pixel 100 that are the same as pixels 20 of the imaging element 10 will be given the same symbols, and repeated descriptions will be omitted.

[0082] like Figure 5 As shown, the conventional pixel 100 differs from the imaging element 10 of this embodiment in that it does not have an OFG transistor 30. Furthermore, as described in the prior art, even when the TRG transistor 24 is in a non-conducting state, the charge overflowing from the photodiode 23 is transferred to the first FD 21. Therefore, in the conventional pixel 100, the charge overflowing from the photodiode 23 flows into the first FD 21 via the TRG transistor 24, and then into the second FD 22 and capacitor 29 via the DGC transistor 28.

[0083] Figure 6 This is a timing diagram showing the operation of the conventional pixel 100. The shutter action at time T0 is the same as that of the imaging element 10 in this embodiment, so repeated descriptions are omitted.

[0084] Next, pixel signals are read throughout the entire time interval T1–T5. In this embodiment, the imaging element 10 turns on the RST transistor 27 during the period from time T1 to time T2 (see reference). Figure 3 Previously, pixel 100 could not turn on RST transistor 27 during the period from time T1 to time T2.

[0085] The reason why RST transistor 27 cannot be turned on is as follows. During long exposures to suppress LED flicker, photodiode 23 may saturate. To avoid this saturation, TRG transistor 24 is configured to transfer the charge overflowing from photodiode 23 to the first FD 21. As a result, from time T1 to time T2, the first FD 21 stores charge that must be converted into pixel signals, thus preventing reset.

[0086] Thus, in the previous pixel 100, regarding HCG_rst and HCG_signal, the first FD21 could not be reset before reading. Therefore, the reset level after a long exposure depends on the subject and the exposure time, making it difficult to converge the pixel signal of pixel 20 within the range of the AD conversion. In addition, the time from the reset of the first FD21 at time T0 to the time T3 when HCG_rst and HCG_signal are read is longer, so the noise of HCG_rst and HCG_signal deteriorates.

[0087] Regarding the conventional pixel 100, the operation after time T2 is the same as that of the imaging element 10 in this embodiment, so repeated descriptions are omitted.

[0088] Based on the differences from the conventional pixel 100 described above, the features of the imaging element 10 of this embodiment will be explained.

[0089] In the conventional pixel 100, as described above, when long exposures are performed to suppress LED flicker, it is impossible to reset the 1FD21 during pixel signal reading (see reference). Figure 6 (Time T1 to Time T2).

[0090] However, in this embodiment, the imaging element 10 uses the OFG transistor 30 to transfer the charge overflowing from the photodiode 23 to the second FD22 instead of the first FD21. In this way, the overflowing charge is stored in the second FD22 and the capacitor 29, so the first FD21 can be reset.

[0091] In this way, during the readout of the first signal, a reset can be performed just before HCG_rst and HCG_signal are read. Therefore, the reset level after a long exposure is independent of the subject and exposure time, making it easier to converge the pixel signal within the range of the AD conversion. Furthermore, compared to the conventional pixel 100, the time from the reset of the first FD21 at time T1 to the readout of HCG_rst and HCG_signal at time T3 is shorter, thus reducing the noise of the first signal (HCG_rst and HCG_signal).

[0092] Furthermore, according to the imaging element 10 of this embodiment, the first signal is converted from charge to pixel signal in HCG state during long exposure, so LED flicker is suppressed and low-light subjects are captured with higher quality.

[0093] In this embodiment, the imaging element 10 reads out a second signal after reading out the first signal. The second signal is obtained in the LCG state, that is, from all the charges of the photodiode 23, the first FD 21, the second FD 22, and the capacitor 29. With such an imaging element 10, the first signal and the second signal are combined, thereby suppressing LED flicker and enabling the acquisition of an unsaturated image even with long exposures.

[0094] In this embodiment, the imaging element 10 reads out a third signal obtained from a short exposure via a second imaging action. The third signal is obtained from a short exposure in HCG mode. Therefore, with such an imaging element 10, the first, second, and third signals are combined, thereby suppressing LED flicker, preventing saturation even with long exposures, and enabling the acquisition of images with high dynamic range.

[0095] In the imaging element 10 of this embodiment, capacitor 29 is connected to the line selection signal (FDC), which can select the first potential during the exposure process (FDC). Figure 3 V2 (off) and the second potential during readout ( Figure 3 The potential V2 is set to be lower than the potential at which the row selection signal is turned on during the exposure process. This reduces the potential difference between the second FD22 and GND during exposure, thereby reducing leakage current and suppressing white spots in the pixel signal.

[0096] In the imaging element 10 of this embodiment, the OFG transistor 30 can be either turned on during reset or always turned off. This reduces power consumption in the OFG transistor 30 or decreases the number of horizontal signal lines.

[0097] The imaging element 10 in this embodiment is as follows: Figure 4 As shown, pixel sharing can be achieved, which can reduce the number of components per pixel, thus solving the problems of LED flicker and photodiode 23 saturation, and achieving miniaturization.

[0098] The image sensor 10, as described above (not specifically illustrated), is mounted on a camera device. Examples of camera devices include camcorders that capture moving or still images, and smartphones with camera functionality. Such a camera device, in addition to the image sensor 10, also includes an optical system that directs light onto the image sensor 10, a memory that stores pixel signals, and... Figure 1 The signal processing unit 18, output unit, control unit, etc. are shown.

[0099] The optical system includes, for example, a zoom lens, a focusing lens, and an aperture, allowing light from the outside to enter the imaging element 10. A memory temporarily stores the pixel signals output by the imaging element 10. The signal processing unit 18 performs signal processing using the pixel signals stored in the memory, such as noise removal and white balance adjustment, to form image data. Additionally, the signal processing unit 18 performs pixel-by-pixel compositing processing to form image data. The output unit includes a display showing the image data processed by the signal processing unit 18, a communication unit for transmitting image data to a device that can communicate with a device different from the imaging device, and an interface for transmitting image data to recording media such as semiconductor memory and magnetic disks. The control unit controls the optical system, the imaging element, the signal processing unit 18, and the output to the output unit.

[0100] In this way, depending on the camera device, the pixel signal can be easily converged to the range of the AD conversion, and the noise of the first signal (HCG_rst and HCG_signal) can be reduced.

[0101] <Other Implementation Methods>

[0102] The above describes various embodiments of the present invention, but the basic structure of the present invention is not limited to the above structure.

[0103] For example, in the imaging element 10 of Embodiment 1, the OFG transistor 30 is turned on during shutter action and turned off otherwise. Thus, the voltage applied to the OFG transistor 30 can be variable, but is not limited to this, and can also be fixed at a potential V1.

[0104] In addition, in the imaging element 10 of Embodiment 1, capacitor 29 is connected to the line selection signal, but the structure is not limited to this. For example, capacitor 29 may also be connected to the power supply voltage VDD.

[0105] In the imaging element 10 of Embodiment 1, a first imaging action and a second imaging action are performed, but the situation is not limited to performing such actions. For example, the second imaging action with a short exposure may not be performed, and only the first imaging action with a long exposure may be performed.

Claims

1. A camera element, characterized in that, have: Photodiodes generate electrical charge through photoelectric conversion; The first floating diffusion section and the second floating diffusion section convert the charge into a potential corresponding to the amount of the charge; A transfer transistor transfers the charge of the photodiode to the first floating diffusion section; Amplifying transistors generate pixel signals corresponding to the potentials transformed by the first floating diffuser; A dual-gain control transistor is disposed between the first floating diffusion section and the second floating diffusion section, and is used to switch the conversion gain when converting charge into pixel signals to high gain or low gain; A capacitor is connected to the second floating diffuser. An overflow gate transistor is disposed between the photodiode and the second floating diffusion section; The reset transistor resets the voltages of the first floating diffusion section, the second floating diffusion section, the photodiode, and the capacitor. as well as The row selection transistor is turned on or off depending on the row selection signal. The capacitor is disposed between the second floating diffusion section and the floating diffusion section control signal line. The imaging element is capable of performing a series of first imaging actions, including shutter action, exposure, and pixel signal reading. The transmission transistor and the overflow gate transistor are configured such that, in the non-conducting state, the charge overflowing from the photodiode during exposure flows into the second floating diffuser and the capacitor. In the image capture operation, when the dual-gain control transistor is switched to a high-gain state, the pixel signal is read as a high-gain reset signal after being reset using the reset transistor. Then, the pixel signal is read as a high-gain signal after the transmission transistor is turned on, and a first signal is output as the difference between the high-gain signal and the high-gain reset signal. After reading the first signal, when the dual-gain control transistor is switched to a low-gain state, the pixel signal is read as a low-gain signal after the transmission transistor is turned on, and then, the pixel signal is read as a low-gain reset signal after being reset using the reset transistor. A second signal is output as the difference between the low-gain signal and the low-gain reset signal. When reading the second signal, the floating diffusion section control signal line is set to a high potential when the row selection signal is at a high potential.

2. The imaging element according to claim 1, characterized in that, In the reading action of the second imaging action, which includes shutter action, exposure, and pixel signal reading, when the dual-gain control transistor is switched to a high gain state, the pixel signal is read as a short-time reset signal after being reset by the reset transistor. Then, after the transmission transistor is turned on, the pixel signal is read as a short-time signal, and a third signal is output as the difference between the short-time signal and the short-time reset signal. The exposure time for the second camera action is shorter than that for the first camera action.

3. The imaging element according to claim 1, characterized in that, The potential of the floating diffusion section control signal line is set to a first potential during exposure and to a second potential different from the first potential during readout.

4. The imaging element according to claim 1, characterized in that, The overflow gate transistor is turned on only during reset, or the camera operation is always performed in a non-conducting state.

5. The imaging element according to claim 1, characterized in that, Each pixel comprises the photodiode, the transmission transistor, the overflow gate transistor, the dual-gain control transistor, and the second floating diffuser. The first floating diffuser, the reset transistor, the amplification transistor, and the row selection transistor for row selection are shared among multiple adjacent pixels.

6. A camera device, characterized in that, It has a camera element according to any one of claims 1 to 5.

Images