A Decomposition Method for Multi-Input Combinational Logic Gates

Abstract

This invention relates to a method for decomposing multi-input combinational logic gates. The method includes: obtaining the Boolean function and timing-critical inputs of the multi-input combinational logic gate; determining whether the multi-input combinational logic gate can be decomposed based on the Boolean function and timing-critical inputs; for decomposable multi-input combinational logic gates, performing a Shannon expansion on the Boolean function to obtain a first Boolean function; and replacing the multi-input combinational logic gate with a new combinational logic gate based on the first Boolean function to achieve the decomposition of the multi-input combinational logic gate, wherein the new combinational logic gate includes at least one two-input combinational logic gate. This invention decomposes multi-input combinational logic gates with large delays into two-input combinational logic gates with smaller delays and the remaining combinational logic gates based on Shannon expansion. This decomposition method can be combined with retiming optimization in logic synthesis to help retiming more effectively optimize the timing of the circuit.

Description

Technical Field

[0001] This invention belongs to the field of digital circuit technology, and specifically relates to a method for decomposing multi-input combinational logic gates. Background Technology

[0002] Logic synthesis is a crucial area in digital circuit design, involving the transformation of high-level logic descriptions into gate-level netlists. During the optimization phases related to logic synthesis, the circuit has already been mapped to a gate-level netlist. Retiming, as a key method for optimizing sequential logic, plays a vital role in this stage. The principle behind retiming's timing optimization lies in redistributing the combinational logic levels between registers by shifting registers, thereby balancing the combinational logic delays of each register-to-register path and increasing the circuit's maximum frequency. Since retiming only redistributes the combinational logic levels of each register-to-register path, it cannot reduce the overall combinational logic delay. Therefore, during retiming, combinational logic refactoring can be combined to reduce combinational logic delay and achieve better timing optimization results.

[0003] Existing methods often employ the concept of L-values ​​to combine retiming and combinational logic refactoring. This approach first divides the circuit into sub-circuits to be optimized, then moves the registers within these sub-circuits to their inputs. Next, the L-value corresponding to the sub-circuit's input is calculated, and the arrival time is replaced with this L-value. Afterward, combinational logic refactoring is performed on the sub-circuit. Finally, the registers are moved back to the sub-circuit based on the L-value. This method, combining L-values ​​with retiming and combinational logic refactoring, involves significant circuit modifications and is time-consuming. Furthermore, one of the fundamental ideas behind this method is to use L-values ​​to predict the final position of the registers after retiming; this prediction has considerable inaccuracy, thus often failing to achieve satisfactory timing optimization results in practical applications. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a method for decomposing multi-input combinational logic gates. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] This invention provides a method for decomposing multi-input combinational logic gates, comprising:

[0006] Step 1: Obtain the Boolean function and timing key input terminals of the multi-input combinational logic gate;

[0007] Step 2: Determine whether the multi-input combinational logic gate can be decomposed based on the Boolean function and the timing key input terminal;

[0008] Step 3: For decomposable multi-input combinational logic gates, perform Shannon expansion on the Boolean function to obtain the first Boolean function;

[0009] Step 4: Based on the first Boolean function, replace the multi-input combinational logic gate with a new combinational logic gate to decompose the multi-input combinational logic gate, wherein the new combinational logic gate includes at least one two-input combinational logic gate.

[0010] In one embodiment of the present invention, step 2 includes:

[0011] Step 2.1: Based on the Boolean function and the timing key input terminal, determine the truth table of the Boolean function when the input signal of the timing key input terminal is 0 and 1;

[0012] Step 2.2: Based on the truth table, determine whether the multi-input combinational logic gate belongs to the decomposable case.

[0013] In one embodiment of the present invention, the decomposability of the multi-input combinational logic gate includes:

[0014] Case 1: When the input of the timing key input terminal is 0, the value of the Boolean function is always equal to 1;

[0015] Case 2: When the input of the timing key input terminal is 1, the value of the Boolean function is always equal to 1;

[0016] Case 3: When the input of the timing key input terminal is 0, the value of the Boolean function is always equal to 0;

[0017] Case 4: When the input of the timing key input terminal is 1, the value of the Boolean function is always equal to 0;

[0018] Case 5: When the input of the timing key input terminal is 0, the value of the Boolean function is always equal to the value of the Boolean function when the input of the timing key input terminal is 1, after taking the negation of the value.

[0019] In one embodiment of the present invention, the expression of the first Boolean function is:

[0020] F1(a,F2(b,c,…));

[0021] Where F1(·) is the first Boolean function, a represents the timing critical input terminal of the multi-input combinational logic gate, and b, c, ... represent the remaining input terminals of the multi-input combinational logic gate excluding the timing critical input terminal; F2(·) is the second Boolean function, and the variables are composed of the remaining input terminals.

[0022] In one embodiment of the present invention, one of the input terminals of the two-input combinational logic gate is the timing critical input terminal.

[0023] In one embodiment of the present invention, when the multi-input combinational logic gate belongs to case 1, the first Boolean function is: ! (a·F2(b,c,…)), and the second Boolean function is: F(1,b,c,…);

[0024] When the multi-input combinational logic gate belongs to case 2, the first Boolean function is: a+F2(b,c,…), and the second Boolean function is: F(0,b,c,…).

[0025] When the multi-input combinational logic gate belongs to case 3, the first Boolean function is: a·F2(b,c,…), and the second Boolean function is: F(1,b,c,…);

[0026] When the multi-input combinational logic gate belongs to case 4, the first Boolean function is: ! (a+F2(b,c,…)), and the second Boolean function is: F(0,b,c,…);

[0027] When the multi-input combinational logic gate belongs to case 5, the first Boolean function is: The second Boolean function is: F(0,b,c,…);

[0028] Where · represents the logical AND operation, ! represents the logical NOT operation, and + represents the logical OR operation. F(·) represents the logical XOR operation, and F(·) represents the Boolean function of a multi-input combinational logic gate.

[0029] In one embodiment of the present invention, step 4 includes:

[0030] Step 4.1: Determine the two-input combinational logic gate based on the first Boolean function;

[0031] Step 4.2: Based on the second Boolean function, use a mapping tool to perform mapping to obtain the remaining combinational logic gates corresponding to the remaining input terminals;

[0032] Step 4.3: Replace the multi-input combinational logic gate with the two-input combinational logic gate and the remaining combinational logic gates as new combinational logic gates.

[0033] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0034] The decomposition method for multi-input combinational logic gates of this invention decomposes multi-input combinational logic gates with large delays into two-input combinational logic gates with smaller delays and the remaining combinational logic gates based on Shannon expansion. This method of reconstructing combinational logic based on Shannon expansion requires minimal changes to the circuit, decomposing only one multi-input combinational logic gate, and the computational cost of Shannon expansion is low. The method of this invention can be combined with retiming optimization in logic synthesis, enabling simpler and more efficient optimization of circuit timing. It also avoids the inaccuracies of using L-value prediction registers for final location, thus optimizing circuit timing more accurately.

[0035] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0036] Figure 1 This is a flowchart of a decomposition method for multi-input combinational logic gates provided in an embodiment of the present invention;

[0037] Figure 2 This is an example diagram illustrating the decomposition of multi-input combinational logic gates during a retiming process, provided by an embodiment of the present invention.

[0038] Figure 3 This is an example diagram provided by an embodiment of the present invention, which uses a two-input combinational logic gate and other combinational logic gates to replace a three-input logic gate;

[0039] Figure 4 This is a statistical graph showing the minimum feasible clock cycle improvement resulting from using the method of this invention to decompose combinational logic gates during the retiming process. Detailed Implementation

[0040] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following describes in detail a decomposition method for multi-input combinational logic gates proposed according to the present invention, in conjunction with the accompanying drawings and specific embodiments.

[0041] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0042] This invention provides a method for decomposing multi-input combinational logic gates. Please refer to [link to relevant documentation]. Figure 1, Figure 1 This is a flowchart of a decomposition method for multi-input combinational logic gates provided in an embodiment of the present invention, such as... Figure 1 As shown, the decomposition method for multi-input combinational logic gates in this embodiment includes:

[0043] Step 1: Obtain the Boolean function and timing key input terminals of the multi-input combinational logic gate;

[0044] Optionally, the key input terminals of multi-input combinational logic gates can be obtained using static timing analysis tools (programs, functions).

[0045] Step 2: Determine whether the multi-input combinational logic gate can be decomposed based on the Boolean function and the timing key input terminal;

[0046] In an optional embodiment, step 2 includes:

[0047] Step 2.1: Based on the Boolean function and the key timing input, determine the truth table corresponding to the Boolean function when the input signals of the key timing input are 0 and 1;

[0048] For example, taking a three-input AND gate as an example, its Boolean function is represented as F(a,b,c) = a·b·c, where · represents the logical AND operation. Its key timing input is a, and the other inputs are b and c. When the input signal of the key timing input a is 0 and 1, the truth table of the Boolean function is shown in Table 1. That is, to calculate the truth table of F(0,b,c) and F(1,b,c), the method is to replace 'a' in F(a,b,c) with 0 and 1 respectively, and then calculate the corresponding truth table.

[0049] Table 1. Truth tables for F(0,b,c) and F(1,b,c)

[0050] 00 0 0 01 0 0 10 0 0 11 0 1

[0051] Step 2.2: Based on the truth table, determine whether the multi-input combinational logic gate belongs to the decomposable case.

[0052] Optionally, the cases in which multi-input combinational logic gates can be decomposed include:

[0053] Case 1: When the input to the timing critical input is 0, the value of the Boolean function is always equal to 1;

[0054] Case 2: When the input at the timing critical input is 1, the value of the Boolean function is always equal to 1;

[0055] Case 3: When the input to the timing critical input is 0, the value of the Boolean function is always equal to 0;

[0056] Case 4: When the input at the timing critical input is 1, the value of the Boolean function is always equal to 0;

[0057] Case 5: The value of the Boolean function when the input to the timing key input is 0 is always equal to the inverse of the value of the Boolean function when the input to the timing key input is 1.

[0058] In this embodiment, if the multi-input combinational logic gate is determined to fall under one of the above 5 situations according to the truth table, the multi-input combinational logic gate can be decomposed using the decomposition method of this embodiment of the invention; otherwise, the multi-input combinational logic gate cannot be decomposed.

[0059] Step 3: For multi-input combinational logic gates that can be decomposed, perform Shannon expansion on the Boolean function to obtain the first Boolean function;

[0060] Shannon expansion is a transformation method for Boolean functions. It can expand the original Boolean function F(a,b,c...) into the form a·F(1,b,c...)+! a·F(0,b,c...), where ! represents the logical NOT operation.

[0061] Alternatively, the first Boolean function obtained by performing a Shannon expansion on the Boolean function can be expressed as:

[0062] F1(a,F2(b,c,…));

[0063] Where F1(·) represents the first Boolean function, a represents the timing critical input terminal of the multi-input combinational logic gate, and b, c, ... represent the remaining input terminals of the multi-input combinational logic gate excluding the timing critical input terminal; F2(·) represents the second Boolean function, and the variables are composed of the remaining input terminals.

[0064] Optionally, when the multi-input combinational logic gate belongs to case 1, the first Boolean function is: ! (a·F2(b,c,…)), and the second Boolean function is: F(1,b,c,…);

[0065] When the multi-input combinational logic gate belongs to case 2, the first Boolean function is: a+F2(b,c,…), and the second Boolean function is: F(0,b,c,…).

[0066] When the multi-input combinational logic gate belongs to case 3, the first Boolean function is: a·F2(b,c,…), and the second Boolean function is: F(1,b,c,…).

[0067] When the multi-input combinational logic gate belongs to case 4, the first Boolean function is: ! (a+F2(b,c,…)), and the second Boolean function is: F(0,b,c,…);

[0068] When the multi-input combinational logic gate belongs to case 5, the first Boolean function is: The second Boolean function is: F(0,b,c,…);

[0069] Where · represents the logical AND operation, ! represents the logical NOT operation, and + represents the logical OR operation. F(·) represents the logical XOR operation, and F(·) represents the Boolean function of a multi-input combinational logic gate.

[0070] Step 4: Based on the first Boolean function, replace the multi-input combinational logic gate with a new combinational logic gate to achieve the decomposition of the multi-input combinational logic gate;

[0071] In this embodiment, the new combinational logic gate includes at least one two-input combinational logic gate, one of the input terminals of which is a timing-critical input terminal.

[0072] In an optional embodiment, step 4 includes:

[0073] Step 4.1: Determine the two-input combinational logic gate based on the first Boolean function;

[0074] Step 4.2: Based on the second Boolean function, use the mapping tool to perform mapping to obtain the remaining combinational logic gates corresponding to the remaining input terminals;

[0075] Optionally, the expression of the second Boolean function and the arrival times of the remaining input terminals b, c, ... of the original multi-input combinational logic gate can be passed to a mapping tool (program, function) for mapping, thereby obtaining the remaining combinational logic gates corresponding to the remaining input terminals.

[0076] Step 4.3: Replace the multi-input combinational logic gate with the two-input combinational logic gate and the remaining combinational logic gates as new combinational logic gates.

[0077] In this embodiment, the connection between the multi-input combinational logic gate and other logic gates can be disconnected first, and then a new combinational logic gate can be used to replace the original multi-input combinational logic gate and connect it with other logic gates.

[0078] The decomposition method for multi-input combinational logic gates in this invention, based on Shannon expansion, decomposes multi-input combinational logic gates with large delays into two-input combinational logic gates with smaller delays and the remaining combinational logic gates. This method of reconstructing combinational logic based on Shannon expansion requires minimal circuit modification, decomposing only one multi-input combinational logic gate, and the computational cost of Shannon expansion is low. This method can be combined with retiming optimization in logic synthesis, enabling simpler and more efficient optimization of circuit timing. It also avoids the inaccuracies of using L-value prediction registers for final location, thus optimizing circuit timing more accurately.

[0079] Furthermore, please refer to [see also] Figure 3The decomposition method of multi-input combinational logic gates in this embodiment will be illustrated by taking a three-input AND gate as an example.

[0080] The Boolean function representation of the three-input AND gate F is F(a,b,c)=a·b·c, with a as the key timing input and b and c as the other inputs. The truth table corresponding to the calculated key timing input is shown in Table 1.

[0081] After calculating the truth tables of F(0,b,c) and F(1,b,c), we can determine whether the three-input AND gate F can be decomposed into two-input combinational logic gates and other logic gates based on their truth tables. Assume there are five types of two-input logic gates in the technology library: AND gate, NAND gate, OR gate, NOR gate, and XOR gate. Then the Boolean function F(a,b,c) has five decomposition cases, as shown in Table 2, where + represents the logical OR operation. This represents the logical XOR operation.

[0082] Table 2. Decomposition of F(a,b,c)

[0083]

[0084] Taking the truth table in Table 1 as an example, when the input of the timing key input terminal of the three-input AND gate F is 0, the value of its Boolean function is always equal to 0. Therefore, the Boolean function of the three-input AND gate F can be decomposed as: F1(a,F2(b,c))=a·F2(b,c), F2(b,c)=F(1,b,c)=b·c.

[0085] Therefore, according to the first Boolean function F1(·), a two-input combinational logic gate should be selected as a two-input AND gate F1. The expression of the second Boolean function F2(·) and the arrival times of the input terminals b and c of the original three-input combinational logic gate are passed to the mapping tool (program, function) for mapping, so that the remaining combinational logic gates corresponding to the remaining input terminals can be obtained, that is, mapped into a two-input AND gate F2.

[0086] To replace the original three-input AND gate F with two two-input AND gates F1 and F2, firstly, disconnect the three-input AND gate F from other logic gates. Then, connect the output of the two-input AND gate F1, mapped by the first Boolean function F1(·), to the logic gate driven by the three-input AND gate F. Connect the two inputs of the two-input AND gate F1 to the logic gate that originally drove the three-input AND gate F via input port a, and to the output of the two-input AND gate F2, respectively. Connect the two inputs of the two-input AND gate F2 to the logic gate that originally drove the three-input AND gate F via input ports b and c, respectively.

[0087] The decomposition method of multi-input combinational logic gates in this embodiment of the invention can be combined with the retiming method to optimize the timing logic of the circuit. Before using the retiming method to optimize the timing logic of the circuit, the decomposition method of multi-input combinational logic gates in this embodiment of the invention can be used to decompose the multi-input combinational logic gates.

[0088] Please refer to the above. Figure 2 The effect of combining the decomposition method and retiming method of the multi-input combinational logic gates of the present invention for timing logic optimization in this embodiment is explained. Figure 2 This is an example diagram illustrating the decomposition of multi-input combinational logic gates during a retiming process, provided by an embodiment of the present invention. Figure 2 The first image at the top center is a schematic diagram of the circuit structure before timing optimization. Figure 2 The second image in the middle is a schematic diagram of the timing-optimized circuit structure using only the retiming method; Figure 3 The third figure in the lower middle section is a schematic diagram of the timing-optimized circuit structure after combining the present invention with the retiming method.

[0089] Resetting involves reallocating combinational logic in register-to-register paths via move registers. When the number of combinational logic levels in one register-to-register path decreases, the number of combinational logic levels in another register-to-register path increases. Therefore, the following situations often occur: Figure 2 As shown, the critical path from reg1 to reg2 terminates at a multi-input combinational logic gate. After retiming the shift register reg2, this multi-input combinational logic gate is assigned to the path from reg2 to reg3. Because the multi-input combinational logic gate has a large delay, the path from reg2 to reg3 becomes a new critical path, degrading timing. In this situation, the multi-input combinational logic gate decomposition method of this invention can be used. First, this multi-input combinational logic gate is decomposed into a two-input logic gate with a smaller delay and the remaining combinational logic gates. Then, retiming is performed. After the multi-input combinational logic gate is decomposed, the path from reg2 to reg3 only adds a two-input combinational logic gate with a smaller delay, avoiding becoming a new critical path, thereby achieving the goal of optimizing circuit timing.

[0090] Please refer to the above. Figure 4 , Figure 4 This is a statistical graph showing the improvement in minimum feasible clock cycle resulting from the use of the method proposed in this invention for decomposition of combinational logic gates during retiming. The horizontal axis represents different test circuits and the average improvement value. The graph shows that the decomposition method for multi-input combinational logic gates proposed in this invention effectively reduces the minimum feasible clock cycle of the circuit during retiming, with an average reduction of 37 ns across ten test circuits.

[0091] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element. Terms such as "connected" or "linked" are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0092] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for decomposing multi-input combinational logic gates, characterized in that, include: Step 1: Obtain the Boolean function and timing key input terminals of the multi-input combinational logic gate; Step 2: Determine whether the multi-input combinational logic gate can be decomposed based on the Boolean function and the timing key input terminal; Step 3: For decomposable multi-input combinational logic gates, perform Shannon expansion on the Boolean function to obtain the first Boolean function; Step 4: Based on the first Boolean function, replace the multi-input combinational logic gate with a new combinational logic gate to decompose the multi-input combinational logic gate, wherein the new combinational logic gate includes at least one two-input combinational logic gate; Step 2 includes: Step 2.1: Based on the Boolean function and the timing key input terminal, determine the truth table of the Boolean function when the input signal of the timing key input terminal is 0 and 1; Step 2.2: Based on the truth table, determine whether the multi-input combinational logic gate belongs to the decomposable case; The multi-input combinational logic gate can be decomposed in the following ways: Case 1: When the input of the timing key input terminal is 0, the value of the Boolean function is always equal to 1; Case 2: When the input of the timing key input terminal is 1, the value of the Boolean function is always equal to 1; Case 3: When the input of the timing key input terminal is 0, the value of the Boolean function is always equal to 0; Case 4: When the input of the timing key input terminal is 1, the value of the Boolean function is always equal to 0; Case 5: The value of the Boolean function when the input of the timing key input terminal is 0 is always equal to the value of the Boolean function when the input of the timing key input terminal is 1, after taking the negation of the value. The expression for the first Boolean function is: ； in, This is the first Boolean function. This represents the key timing input of a multi-input combinational logic gate. This refers to the remaining inputs of a multi-input combinational logic gate, excluding the timing-critical inputs. This is the second Boolean function, and its variables are composed of the remaining input terminals.

2. The decomposition method for multi-input combinational logic gates according to claim 1, characterized in that, One of the input terminals of the two-input combinational logic gate is the timing critical input terminal.

3. The decomposition method for multi-input combinational logic gates according to claim 1, characterized in that, When the multi-input combinational logic gate belongs to case 1, the first Boolean function is: The second Boolean function is: ; When the multi-input combinational logic gate belongs to case 2, the first Boolean function is: The second Boolean function is: ; When the multi-input combinational logic gate belongs to case 3, the first Boolean function is: The second Boolean function is: ; When the multi-input combinational logic gate belongs to case 4, the first Boolean function is: The second Boolean function is: ; When the multi-input combinational logic gate belongs to case 5, the first Boolean function is: The second Boolean function is: ; in, This represents the logical AND operation. Represents the logical NOT operation. Represents a logical OR operation. This represents the logical XOR operation. Boolean functions representing multi-input combinational logic gates.

4. The decomposition method for multi-input combinational logic gates according to claim 2, characterized in that, Step 4 includes: Step 4.1: Determine the two-input combinational logic gate based on the first Boolean function; Step 4.2: Based on the second Boolean function, use a mapping tool to perform mapping to obtain the remaining combinational logic gates corresponding to the remaining input terminals; Step 4.3: Replace the multi-input combinational logic gate with the two-input combinational logic gate and the remaining combinational logic gates as new combinational logic gates.

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