Chip hybrid simulation method based on general verification methodology and image processing algorithm

Abstract

The application discloses a chip hybrid simulation method based on a general verification methodology and an image processing algorithm. The method comprises the following steps: after receiving a chip simulation task, starting a verification platform; inputting excitation data into a design module to be tested to simulate and process a target chip, and obtaining simulation output data; sending the simulation output data and the excitation data to an image processing model for processing; performing format conversion to obtain simulation data code streams and excitation data code streams; processing the excitation data code streams to obtain image algorithm output data code streams; comparing the simulation data code streams and the image algorithm output data code streams to obtain a verification result. The application solves the technical problem that in the related art, the interconnection and connectivity of an image algorithm model and a UVM simulation verification platform are isolated in the mode for simulating and verifying a chip, errors in data and algorithm processing flow errors are easily caused, and the simulation efficiency and accuracy of the UVM platform are reduced.

Description

Technical Field

[0001] This invention relates to the field of chip simulation and control technology, and more specifically, to a hybrid chip simulation method based on a general verification methodology and an image processing algorithm. Background Technology

[0002] For consumer electronics products in the chip industry (such as computers, laptops, tablets, monitors, and televisions), more and more products need to use image processing and optimization to achieve more perfect display effects, reduced power consumption, and increased refresh rates.

[0003] To ensure the timely market launch of electronic products, the high quality, stability, and efficiency of chips have become the competitive advantages of various electronic products. As display screens achieve increasingly larger image resolutions and faster speeds, and image processing algorithms become more complex, unprecedented efficiency and accuracy challenges arise for the front-end simulation and verification of chips.

[0004] Currently, the simulation verification of image processing chips generally employs the following method: Algorithm engineers develop specific image processing algorithms, then write algorithm models using programming languages ​​(such as C, Python, MATLAB, etc.) for algorithm verification and output algorithm data. Chip verification engineers build a UVM simulation verification platform to simulate the device under test (DUT) and output simulation data; finally, the two sets of data are compared one-to-one to obtain the overall design comparison results. This chip verification method isolates the interconnectivity and connectivity between the algorithm model and the UVM simulation verification platform, causing errors in data and algorithm processing flow, reducing the simulation efficiency and accuracy of the UVM platform, and hindering the reuse and acceleration of subsequent test cases.

[0005] The aforementioned technologies for simulating and verifying chips isolate the interconnectivity and connectivity between the image algorithm model and the UVM simulation verification platform, which can easily lead to data errors and algorithm processing errors, thereby reducing the simulation efficiency and accuracy of the UVM platform. Currently, no effective solution has been proposed. Summary of the Invention

[0006] This invention provides a chip hybrid simulation method based on a general verification methodology and an image processing algorithm. This method addresses the technical problem in related technologies where chip simulation verification methods isolate the interconnectivity and connectivity between the image algorithm model and the UVM simulation verification platform, which can easily lead to data errors and algorithm processing flow errors, thereby reducing the simulation efficiency and accuracy of the UVM platform.

[0007] According to one aspect of the present invention, a hybrid chip simulation method based on a general verification methodology and an image processing algorithm is provided, comprising: upon receiving a chip simulation task, generating a startup instruction based on the chip simulation task to trigger the startup of a general verification methodology verification platform, wherein the verification platform integrates an image processing model; after the simulation environment of the verification platform is running, inputting stimulus data to a design-under-test (DUT) module to perform simulation processing on the target chip corresponding to the chip simulation task in the DUT module using the stimulus data, thereby obtaining simulation output data; acquiring the stimulus data and the simulation output data, and sending the stimulus data and the simulation output data to the image processing model. The method involves: analyzing and processing the output data using the image processing model to obtain simulation results for the target chip; converting the format of the simulation output data and the stimulus data in the image processing model to obtain simulation data streams and stimulus data streams recognizable by the image processing algorithm in the image processing model; processing the stimulus data streams using the image processing algorithm to obtain image algorithm output data streams; comparing the simulation data streams and the image algorithm output data streams in the image processing model to obtain verification results for the target chip based on the comparison results, wherein the verification results are used to indicate whether the actual function of the target chip is consistent with the functional description information.

[0008] Optionally, before generating a startup instruction based on the chip simulation task to trigger the startup of the general verification methodology verification platform, the chip hybrid simulation method based on the general verification methodology and image processing algorithm further includes: calling the logic code of the design under test module to design the design under test module, wherein the logic code is code pre-written according to the chip simulation requirements; determining multiple components required to generate the verification platform based on the functional description information of the target chip, wherein the multiple components are components required for simulating the target chip; encapsulating the multiple components using the methodology architecture corresponding to the verification platform, and connecting the encapsulated multiple components to obtain the verification platform including the design under test module and the encapsulated and connected multiple components.

[0009] Optionally, after the simulation environment of the verification platform is running, stimulus data is input to the design-under-test (DUT) module to perform simulation processing on the target chip corresponding to the chip simulation task in the DUT module using the stimulus data, thereby obtaining simulation output data. This includes: triggering the startup of the top-level configuration module in the verification platform to configure the registers of the DUT module according to the functional description information of the target chip, and setting the simulation environment of the verification platform using the top-level configuration module; triggering the startup of the scene exciter in the verification platform to generate the stimulus data, and inputting the stimulus data to the DUT module to drive the DUT module to perform simulation processing on the target chip, thereby obtaining the simulation output data.

[0010] Optionally, the simulation output data and the stimulus data in the image processing model are format-converted to obtain a simulation data bitstream recognizable by the image processing algorithm in the image processing model. This includes: during the process of inputting stimulus data into the design-under-test module to simulate the target chip in the design-under-test module using the stimulus data, triggering the logic monitor of the verification platform to start, acquiring the stimulus data and the simulation output data, and inputting the stimulus data and the simulation output data into the image processing model; after determining that the image processing model has received the simulation output data, using the data processing module in the image processing model to perform format conversion on the simulation output data to obtain the simulation data bitstream.

[0011] Optionally, before processing the excitation data stream using the image processing algorithm to obtain the image algorithm output data stream, the chip hybrid simulation method based on general verification methodology and image processing algorithm further includes: obtaining the configuration information of the register model in the verification platform and the setting information of the simulation environment in the verification platform; sending the configuration information and the setting information to the configuration module of the image processing model, so as to use the configuration module to preprocess the configuration information and the setting information, so that the configuration module is paired and integrated with the top-level configuration module of the verification platform.

[0012] Optionally, the image processing algorithm is used to process the excitation data stream to obtain the image algorithm output data stream, including: using the image processing algorithm and the configuration information of the register model in the verification platform to perform analysis and processing of the excitation data stream in a predetermined dimension to obtain the image algorithm output data stream, wherein the predetermined dimension includes at least one of the following: pixel depth, color temperature, contrast, color vividness, and transition smoothness.

[0013] Optionally, comparing the simulated data stream and the image algorithm output data stream in the image processing model to obtain the verification result of the target chip based on the comparison result includes: comparing the simulated data stream and the image algorithm output data stream in the image processing model to obtain a comparison result; when the comparison result indicates that the simulated data stream and the image algorithm output data are both consistent or the number of inconsistencies between the simulated data stream and the image algorithm output data is less than a predetermined threshold, determining that the actual function of the target chip is consistent with the function description information; when the comparison result indicates that the number of inconsistencies between the simulated data stream and the image algorithm output data is not less than a predetermined threshold, determining that the actual function of the target chip is inconsistent with the function description information.

[0014] Optionally, after comparing the simulation data stream and the image algorithm output data stream in the image processing model to obtain the verification result of the target chip based on the comparison result, the chip hybrid simulation method based on general verification methodology and image processing algorithm further includes: storing the verification result in a log.

[0015] According to another aspect of the present invention, a chip hybrid simulation apparatus based on a general verification methodology and an image processing algorithm is also provided, comprising: a triggering unit, configured to generate a start command based on the chip simulation task after receiving a chip simulation task, thereby triggering the start of a general verification methodology verification platform, wherein the verification platform integrates an image processing model; a first acquisition unit, configured to input stimulus data to a design-under-test (DUT) module after the simulation environment of the verification platform is running, so as to use the stimulus data to perform simulation processing on the target chip corresponding to the chip simulation task in the DUT module, thereby obtaining simulation output data; and a second acquisition unit, configured to acquire the stimulus data and the simulation output data, and send the stimulus data and the simulation output data to the image processing model. The system comprises five parts: a first part, a second part, and a third part, a fourth part, and a fifth part, and a sixth part, each part, which are used to: 1) analyze and process the output data using the image processing model to obtain simulation results for the target chip; 2) perform format conversion on the simulation output data and the stimulus data in the image processing model to obtain simulation data streams and stimulus data streams recognizable by the image processing algorithm in the image processing model; 3) process the stimulus data stream using the image processing algorithm to obtain image algorithm output data streams; and 4) compare the simulation data streams and the image algorithm output data streams in the image processing model to obtain verification results for the target chip based on the comparison results, wherein the verification results indicate whether the actual function of the target chip is consistent with the functional description information.

[0016] Optionally, the chip hybrid simulation device based on a general verification methodology and an image processing algorithm further includes: a sixth acquisition unit, configured to, before generating a startup instruction based on the chip simulation task to trigger the startup of the general verification methodology verification platform, call the logic code of the design under test module to design the design under test module, wherein the logic code is code pre-written according to the chip simulation requirements; a determination unit, configured to, based on the functional description information of the target chip, determine multiple components required to generate the verification platform, wherein the multiple components are components required for simulating the target chip; and a seventh acquisition unit, configured to, using the methodology architecture corresponding to the verification platform, encapsulate the multiple components and connect the encapsulated multiple components to obtain the verification platform including the design under test module and the encapsulated and connected multiple components.

[0017] Optionally, the first acquisition unit includes: a first trigger module, configured to trigger the startup of the top-level configuration module in the verification platform, so as to configure the registers of the design under test module according to the functional description information of the target chip, and to set the simulation environment of the verification platform using the top-level configuration module; and a second trigger module, configured to trigger the startup of the scene exciter in the verification platform, so as to generate the excitation data, and input the excitation data to the design under test module, so as to drive the design under test module to perform simulation processing on the target chip using the excitation data, and obtain the simulation output data.

[0018] Optionally, the third acquisition unit includes: a third trigger module, configured to trigger the startup of the logic monitor of the verification platform during the process of inputting stimulus data to the design under test module to perform simulation processing on the target chip in the design under test module using the stimulus data, so as to collect the stimulus data and the simulation output data, and input the stimulus data and the simulation output data into the image processing model; and a first acquisition module, configured to, after determining that the image processing model has received the simulation output data, use the data processing module in the image processing model to perform format conversion on the simulation output data to obtain the simulation data bitstream.

[0019] Optionally, the chip hybrid simulation device based on a general verification methodology and an image processing algorithm further includes: an eighth acquisition unit, used to acquire configuration information of the register model in the verification platform and setting information of the simulation environment in the verification platform before processing the excitation data stream using the image processing algorithm to obtain the image algorithm output data stream; and a processing unit, used to send the configuration information and the setting information to the configuration module of the image processing model, so as to preprocess the configuration information and the setting information using the configuration module, so as to pair and integrate the configuration module with the top-level configuration module of the verification platform.

[0020] Optionally, the fourth acquisition unit includes: a second acquisition module, used to perform analysis and processing of the excitation data bitstream in a predetermined dimension using the image processing algorithm and the configuration information of the register model in the verification platform to obtain the image algorithm output data bitstream, wherein the predetermined dimension includes at least one of the following: pixel depth, color temperature, contrast, color vividness, and transition smoothness.

[0021] Optionally, the fifth acquisition unit includes: a third acquisition module, configured to compare the simulated data bitstream and the image algorithm output data bitstream in the image processing model to obtain a comparison result; a first determination module, configured to determine that the actual function of the target chip is consistent with the function description information when the comparison result indicates that the simulated data bitstream and the image algorithm output data are both consistent or the number of inconsistencies between the simulated data bitstream and the image algorithm output data is less than a predetermined threshold; and a second determination module, configured to determine that the actual function of the target chip is inconsistent with the function description information when the comparison result indicates that the number of inconsistencies between the simulated data bitstream and the image algorithm output data is not less than a predetermined threshold.

[0022] Optionally, the chip hybrid simulation device based on general verification methodology and image processing algorithm further includes: a storage unit comparing the simulation data bitstream in the image processing model and the output data bitstream of the image algorithm to obtain the verification result of the target chip based on the comparison result, wherein the verification result is used to indicate whether the actual function of the target chip is consistent with the function description information, and then storing the verification result in a log.

[0023] According to another aspect of the present invention, a chip hybrid simulation system based on a general verification methodology and an image processing algorithm is also provided, wherein the chip hybrid simulation system based on a general verification methodology and an image processing algorithm uses any of the above-described chip hybrid simulation methods based on a general verification methodology and an image processing algorithm.

[0024] According to another aspect of the present invention, a computer-readable storage medium is also provided, the computer-readable storage medium including a stored program, wherein the program executes any of the above-described chip hybrid simulation methods based on general verification methodology and image processing algorithms.

[0025] According to another aspect of the present invention, a processor is also provided, the processor being used to run a program, wherein the program, when running, executes any of the above-described chip hybrid simulation methods based on general verification methodology and image processing algorithms.

[0026] In this embodiment of the invention, upon receiving a chip simulation task, a startup command is generated based on the chip simulation task to trigger the startup of a general verification methodology verification platform. This verification platform integrates an image processing model. After the simulation environment of the verification platform is running, stimulus data is input to the design-under-test (DUT) module. The DUT module then uses the stimulus data to perform simulation processing on the target chip corresponding to the chip simulation task, obtaining simulation output data. The stimulus data and simulation output data are acquired and sent to the image processing model. The image processing model analyzes and processes the output data to obtain the simulation results for the target chip. The simulation output data and stimulus data in the image processing model are then processed. The format is converted to obtain the simulation data bitstream and excitation data bitstream that the image processing algorithm in the image processing model can recognize. The excitation data bitstream is processed using the image processing algorithm to obtain the output data bitstream of the image algorithm. The simulation data bitstream and the output data bitstream of the image processing model are compared to obtain the verification result of the target chip based on the comparison result. The verification result is used to indicate whether the actual function of the target chip is consistent with the functional description information. The above technical solution achieves the goal of integrating the image algorithm model with the UVM simulation verification platform. While simulating the target chip using the chip simulation verification platform, the input and output data used in the simulation can be input to the image processing model for algorithm-level processing. This allows for comprehensive verification of whether the actual function of the target chip matches its functional description based on the simulation output and the image algorithm model's processing results. This interconnects the image algorithm model and the UVM simulation verification platform, avoiding data errors and algorithm processing flow errors, thus improving the simulation efficiency and accuracy of the UVM platform. Furthermore, it solves the problem in related technologies where chip simulation verification methods isolate the interconnectivity and connectivity between the image algorithm model and the UVM simulation verification platform, easily leading to data errors and algorithm processing flow errors, thereby reducing the simulation efficiency and accuracy of the UVM platform. Attached Figure Description

[0027] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0028] Figure 1This is a hardware structure block diagram of a mobile terminal based on a chip hybrid simulation method using a general verification methodology and image processing algorithm, according to an embodiment of the present invention.

[0029] Figure 2 This is a flowchart of a chip hybrid simulation method based on a general verification methodology and an image processing algorithm according to an embodiment of the present invention;

[0030] Figure 3 This is a schematic diagram of a chip simulation and verification platform according to an embodiment of the present invention;

[0031] Figure 4 This is a flowchart of an optional chip hybrid simulation method based on a general verification methodology and an image processing algorithm according to an embodiment of the present invention;

[0032] Figure 5 This is a schematic diagram of the chip simulation and verification process according to an embodiment of the present invention;

[0033] Figure 6 This is a schematic diagram of a chip hybrid simulation device based on a general verification methodology and image processing algorithm according to an embodiment of the present invention. Detailed Implementation

[0034] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0035] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0036] As described in the background section, the methods used in related technologies for chip simulation verification isolate the interconnectivity and connectivity between the image algorithm model and the UVM simulation verification platform, which can easily lead to data errors and algorithm processing flow errors, thereby reducing the simulation efficiency and accuracy of the UVM platform. To address these shortcomings, this invention provides a chip hybrid simulation method based on a general verification methodology and image processing algorithms.

[0037] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0038] The methods and embodiments provided in this invention can be executed on a mobile terminal, a computer terminal, or a similar computing device. Taking running on a mobile terminal as an example, Figure 1 This is a hardware structure block diagram of a mobile terminal based on a chip hybrid simulation method using a general verification methodology and image processing algorithms, according to an embodiment of the present invention. Figure 1 As shown, a mobile terminal may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. The mobile terminal may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the mobile terminal described above. For example, the mobile terminal may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0039] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the chip hybrid simulation method based on general verification methodology and image processing algorithms in this embodiment of the invention. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thereby implementing the above-described method. The memory 104 may include high-speed random access memory and non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to the mobile terminal via a network. Examples of the aforementioned networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof. The transmission device 106 is used to receive or send data via a network. Specific examples of the aforementioned networks may include wireless networks provided by the mobile terminal's communication provider. In one example, the transmission device 106 includes a network interface controller (NIC), which can be connected to other network devices via a base station to communicate with the Internet. In one example, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0040] According to an embodiment of the present invention, a method embodiment of a chip hybrid simulation method based on a general verification methodology and an image processing algorithm is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0041] Figure 2 This is a flowchart of a chip hybrid simulation method based on a general verification methodology and image processing algorithm according to an embodiment of the present invention, such as... Figure 2 As shown, the method includes the following steps:

[0042] Step S202: After receiving the chip simulation task, a start command is generated based on the chip simulation task to trigger the start of the general verification methodology verification platform, wherein the verification platform integrates an image processing model.

[0043] Optionally, the aforementioned Universal Verification Methodology (UVM) is a standard verification methodology for integrated circuit design, derived from open verification methodologies, and offers a greater degree of automation.

[0044] According to the above embodiments of the present invention, before step S202, that is, before generating a startup instruction based on the chip simulation task to trigger the startup of the general verification methodology verification platform, the chip hybrid simulation method based on the general verification methodology and image processing algorithm further includes: calling the logic code of the design under test module to design and obtain the design under test module, wherein the logic code is code pre-written according to the chip simulation requirements; determining multiple components required to generate the verification platform according to the functional description information of the target chip, wherein the multiple components are components required for simulating the target chip; encapsulating the multiple components using the methodology architecture corresponding to the verification platform, and connecting the encapsulated multiple components to obtain a verification platform including the design under test module and the encapsulated and connected multiple components.

[0045] The following is combined with Figure 3 The embodiments of the present invention will be described in detail below. Figure 3 This is a schematic diagram of a chip simulation and verification platform according to an embodiment of the present invention. Figure 3 As shown, before chip simulation begins, a UVM-based chip simulation and verification platform will be established. This platform mainly includes a top-level module (test_top) and a module under test. The top-level environment of this top-level module includes top-level configuration (top_cfg), image processing model (alg_model), register model (reg_model), algorithm agent (alg_agent), logic monitor (dut_monitor), scene exciter (video_seq), etc. Secondly, the simulation software, scripts, and file paths must be set up.

[0046] The functions of each module in the chip simulation and verification platform are explained below:

[0047] 1) Top-level module (test_top): Responsible for establishing the entire simulation environment. It calls the logic code of the design under test (DUT) module and encapsulates components such as the top-level environment (top_env), top-level configuration (top_cfg), register model (reg_model), and registers (i.e., registers in the DUT module) based on the UVM methodology architecture, and connects the various modules to make it a whole simulation environment.

[0048] 2) Top-level environment (top_env): Responsible for calling the top-level module (test_top), register model (reg_model), image processing model (alg_model), algorithm agent (alg_agent), etc., and providing configuration information (including video image color depth, length, number of frames, number of pixels, register configuration bus type, speed and number of lanes, etc.), module enable, module connection, data transfer and other information to various modules, and incorporating them into the top_env module. During the simulation, it will automatically call the function methods in the module to realize the module function.

[0049] 3) Top-level configuration (top_cfg): Responsible for providing various configurations for the entire algorithm's functional modules, mainly including: environment configuration, process configuration, data flow configuration, register function configuration, comparison mechanism configuration, etc.

[0050] 4) Register Model (reg_model): This model provides the register model for the entire simulation environment, enabling read, write, reset, dynamic configuration, and static configuration of registers. Here, the register model is the UVM simulation verification platform.

[0051] 5) Image processing model (alg_model): Responsible for calling the algorithm program model written in Python, and analyzing and comparing the algorithm processing data and DUT output data according to the register configuration information;

[0052] 6) Algorithm Agent (alg_agent): Responsible for instantiating the logic monitor (dut_monitor) and scene exciter (video_seq), as well as inter-module connections, etc. Instantiated modules are embedded into the algorithm agent by directly calling the module name and try out the function methods inside the instantiated module;

[0053] 7) Logic Monitor (dut_monitor): Responsible for monitoring the input and output data of the logic code and transmitting it to the image processing model;

[0054] 8) Scene exciter (video_seq): Responsible for generating input excitation data for the algorithm model and DUT. By importing the video image color depth, length, frame rate, and number of pixels from reg_model and top_cfg, it generates bit data streams, DE, vsync, hsync and other input signals, and connects them to the DUT module interface.

[0055] Step S204: After the simulation environment of the verification platform is running, the stimulus data is input to the design under test module so as to use the stimulus data to perform simulation processing on the target chip corresponding to the chip simulation task in the design under test module and obtain simulation output data.

[0056] Optionally, the simulation output data mentioned above can be used as a reference to verify whether the actual function of the target chip is consistent with the functional description information.

[0057] In this embodiment, after the simulation environment of the verification platform is running, the scene exciter in the verification platform can be triggered to generate excitation data. This excitation data is then used as the driver for the design-under-test module to perform simulation processing on the target chip.

[0058] Figure 4 This is a flowchart of an optional chip hybrid simulation method based on a general verification methodology and image processing algorithm according to an embodiment of the present invention, such as... Figure 4 As shown, when chip simulation begins, the simulation software version, file path, environment variables, etc., are configured first. Then, the simulation script is run in the system terminal. At this point, a simulation verification platform based on the UVM methodology will be established. The simulation platform consists of two parts: the logic code DUT and the environment integration components. These components mainly include the top-level module (test_top), the top-level environment (top_env), the top-level configuration (top_cfg), the register model (reg_model), the image processing model (alg_model), and the algorithm agent (alg_agent), etc.

[0059] Next, after the entire simulation environment is established, the simulation platform will automatically start the simulation process, performing real-time image algorithm model processing, DUT synchronous simulation, and data interaction. Finally, the simulation platform will automatically process the data, analyze and compare all data information, register configuration information, etc., analyze the simulation results and data content, and finally confirm the correct judgment result of the design simulation. Then, the entire simulation process will end, and the simulation data log records, simulation files, and waveforms will be saved.

[0060] According to the above embodiments of the present invention, in step S204, after the simulation environment of the verification platform is running, stimulus data is input to the design under test (DUT) module so that the target chip corresponding to the chip simulation task can be simulated in the DUT module using the stimulus data to obtain simulation output data. This includes: triggering the top-level configuration module in the verification platform to start, so that the top-level configuration module can configure the registers of the DUT module according to the functional description information of the target chip, and setting the simulation environment of the verification platform using the top-level configuration module; triggering the scene exciter in the verification platform to start, so as to generate stimulus data, and inputting the stimulus data to the DUT module so that the DUT module can be driven by the stimulus data to perform simulation processing on the target chip to obtain simulation output data.

[0061] As above Figure 3As shown, after the simulation environment of the verification platform is running, the top-level configuration (top_cfg) module is started, and all registers and environment settings are configured (the configuration includes: environment configuration, process configuration, data flow configuration, register function configuration, comparison mechanism configuration). The corresponding configuration parameters are sent to the image processing model (alg_model), algorithm agent (alg_agent), and register model (reg_model). After the algorithm agent (alg_agent) receives the configuration data, it starts the logic monitor (dut_monitor) and scene exciter (video_seq), and drives the generated video_data (excitation data) to the design under test (DUT).

[0062] It should be noted that the registers here refer to the registers inside the chip and are unrelated to UVM. Although the registers here and the register models in UVM use the same configuration, they process their respective data. The reason for using both the chip's registers and the UVM's register model to process data is to avoid the situation where the simulation processing and image processing algorithms use the same configuration data. This is because if there are problems with the configuration data, both the simulation processing and image processing algorithms will use incorrect data, resulting in invalid verification results for the target chip.

[0063] Step S206: Acquire stimulus data and simulation output data, and send the stimulus data and simulation output data to the image processing model so that the image processing model can be used to analyze and process the output data to obtain the simulation results of the target chip.

[0064] As above Figure 3 As shown, while the Design Under Test (DUT) continuously receives video_data (excitation data), the logic monitor (dut_monitor) runs continuously, constantly sampling the DUT's input and output data, and transmitting the data to the image processing model (alg_model). In the image processing model (alg_model), the data and input information are processed and the comparison results are output.

[0065] Step S208: Convert the format of the simulation output data and excitation data in the image processing model to obtain the simulation data bitstream and excitation data bitstream that can be recognized by the image processing algorithm in the image processing model.

[0066] When processing the data, compatibility issues need to be considered. To ensure that subsequent steps can proceed smoothly, the obtained simulation output data and stimulus data need to be converted into a simulation data stream and stimulus data stream that can be recognized by the image processing algorithm in the image processing model (alg_model).

[0067] According to the above embodiments of the present invention, in step S208, the simulation output data and stimulus data in the image processing model are format converted to obtain a simulation data bitstream that can be recognized by the image processing algorithm in the image processing model. This includes: during the process of inputting stimulus data into the design under test module to perform simulation processing on the target chip in the design under test module using the stimulus data, triggering the logic monitor of the verification platform to start, so as to collect stimulus data and simulation output data, and inputting the stimulus data and simulation output data into the image processing model; after determining that the image processing model has received the simulation output data, the data processing module in the image processing model is used to convert the simulation output data to obtain a simulation data bitstream.

[0068] The following is combined with Figure 5 The embodiments of the present invention will be described in detail below. Figure 5 This is a schematic diagram of the chip simulation and verification process according to an embodiment of the present invention. Figure 5 As shown, after receiving the stimulus data and simulation output data, the image processing model (alg_model) will send them to the data_pro module for integration and analysis (format conversion), and then send them to the Comparator module to obtain the simulation data bitstream and stimulus data bitstream.

[0069] The data_pro module here is mainly responsible for extracting pixels from the excitation data and simulation output data of the DUT, packaging them, and saving them into a queue in byte order. This allows the image processing model to compare the two data after processing the input data to verify whether the target chip is qualified.

[0070] Step S210: The excitation data bitstream is processed using an image processing algorithm to obtain the image algorithm output data bitstream.

[0071] Optionally, the image algorithm outputs a data stream in a specific format required for subsequent verification of the target chip.

[0072] After obtaining the data stream in a specific format (simulation data stream and image algorithm output data stream, i.e., data_in), it is transmitted to the PYTHON algorithm model. The PYTHON algorithm model does not consume simulation time during operation and can output the ideal data after image analysis and processing in real time. The data is then output to the comparison module of the image processing algorithm model in a specific format.

[0073] It should be noted that, in the embodiments of the present invention, the image processing algorithm includes, but is not limited to, the PYTHON algorithm, and may also be other types of algorithms.

[0074] According to the above embodiments of the present invention, before step S210, that is, before processing the excitation data stream using the image processing algorithm to obtain the output data stream of the image algorithm, the chip hybrid simulation method based on the general verification methodology and the image processing algorithm further includes: obtaining the configuration information of the register model in the verification platform and the setting information of the simulation environment in the verification platform; sending the configuration information and setting information to the configuration module of the image processing model, so as to use the configuration module to preprocess the configuration information and setting information, so as to pair and integrate the configuration module with the top-level configuration module of the verification platform.

[0075] As above Figure 5 As shown, when the data_pro module performs format conversion on the stimulus data and simulation output data (data_out), the image processing model (alg_model) also passes the configuration information of the top-level configuration (top_cfg) and register model (reg_model) to the cfg module for preprocessing. The cfg module mainly includes: register name, register field value, register address, register configuration bus type, speed, and number of lanes, etc. By pairing and integrating these basic information with the top-level configuration (top_cfg) module, the required processing status configuration data can be obtained.

[0076] According to the above embodiments of the present invention, in step S210, the excitation data bitstream is processed by an image processing algorithm to obtain an image algorithm output data bitstream, including: using the image processing algorithm and the configuration information of the register model in the verification platform to perform analysis and processing of the excitation data bitstream in a predetermined dimension to obtain the image algorithm output data bitstream, wherein the predetermined dimension includes at least one of the following: pixel depth, color temperature, contrast, color vividness, and transition smoothness.

[0077] As above Figure 5 As shown, the image processing algorithm model (alg_model) can directly call programs written in the PYTHON programming language to perform data processing and analysis on input images of a specific format. This processing and analysis mainly targets the pixel depth, color temperature, contrast, color vibrancy, and transition smoothness of video images to ensure that the video data meets the chip requirements.

[0078] In addition, during the simulation, the image processing algorithm model (alg_model) will synchronously collect the input and output data (i.e., stimulus data and simulation output data) of the DUT, and synchronously introduce the input data (stimulation data) and register configuration data (register name, register field value, register address, register configuration bus type, speed and number of lanes, etc.) into the PYTHON algorithm model.

[0079] Step S212: Compare the simulated data stream in the image processing model with the output data stream of the image algorithm to obtain the verification result of the target chip based on the comparison result. The verification result is used to indicate whether the actual function of the target chip is consistent with the functional description information.

[0080] After the PYTHON algorithm model outputs data in a specific format to the comparison module of the image processing algorithm model, the simulation data stream and the image algorithm output data stream are compared in the comparison module. Then, the verification result of the target chip is obtained based on the comparison result to verify whether the actual function of the target chip is consistent with its functional description information.

[0081] According to the above embodiments of the present invention, in step S212, comparing the simulated data stream and the image algorithm output data stream in the image processing model to obtain the verification result of the target chip based on the comparison result includes: comparing the simulated data stream and the image algorithm output data stream in the image processing model to obtain a comparison result; when the comparison result indicates that the simulated data stream and the image algorithm output data are consistent or the number of inconsistencies between the simulated data stream and the image algorithm output data is less than a predetermined threshold, determining that the actual function of the target chip is consistent with the function description information; when the comparison result indicates that the number of inconsistencies between the simulated data stream and the image algorithm output data is not less than a predetermined threshold, determining that the actual function of the target chip is inconsistent with the function description information.

[0082] Optionally, the aforementioned predetermined threshold is used to determine whether the actual function of the target chip is consistent with the function description information. Its specific value can be obtained from a large number of experiments, and no specific requirements are made for its value here.

[0083] As above Figure 5 As shown, after the PYTHON algorithm model processes and analyzes the excitation data stream and simulation data stream, it transmits the analysis results to the Comparator module. The Comparator module analyzes and compares the final data to obtain the simulation verification results of the entire image processing chip.

[0084] For example, if the number of inconsistencies between the simulated data stream and the image algorithm output data stream exceeds 5 (taking 5 as an example of a predetermined threshold), the actual function of the target chip is considered inconsistent with its functional description information, that is, the chip is a defective chip; if the number of inconsistencies between the simulated data stream and the image algorithm output data stream is less than 5 (taking 5 as an example of a predetermined threshold), the actual function of the target chip is considered consistent with its functional description information, that is, the chip is a qualified chip.

[0085] According to the above embodiments of the present invention, after step S212, that is, after comparing the simulation data bitstream in the image processing model and the image algorithm output data bitstream to obtain the verification result of the target chip based on the comparison result, the chip hybrid simulation method based on the general verification methodology and the image processing algorithm further includes: storing the verification result in a log.

[0086] The comparison module of the image processing algorithm model here compares the data after receiving the data output by the DUT and PYTHON algorithm models respectively, and prints and records the comparison results in the log directory. The data output by each model adopts a unified data byte packing format, which mainly includes video format data type, data depth, and pixel byte data.

[0087] As shown above, through the above steps, after receiving the chip simulation task, a start command can be generated based on the chip simulation task to trigger the start of the general verification methodology verification platform. This verification platform integrates an image processing model. After the simulation environment of the verification platform is running, stimulus data is input to the design-under-test (DUT) module. The DUT module then uses the stimulus data to perform simulation processing on the target chip corresponding to the chip simulation task, obtaining simulation output data. The stimulus data and simulation output data are acquired and sent to the image processing model. The image processing model analyzes and processes the output data to obtain the simulation results for the target chip. The simulation output data and stimulus data in the image processing model are format-converted to obtain a simulation data stream and stimulus data stream recognizable by the image processing algorithm in the image processing model. The image processing algorithm processes the stimulus data stream to obtain the image algorithm... The system outputs a data stream; it compares the simulation data stream in the image processing model with the output data stream of the image algorithm to obtain the verification result of the target chip based on the comparison result. The verification result is used to indicate whether the actual function of the target chip is consistent with the functional description information. By integrating the image algorithm model with the UVM simulation verification platform, the system can simulate the target chip using the chip simulation verification platform while simultaneously inputting the simulation input data and simulation output data into the image processing model for algorithm-level processing. This allows for comprehensive verification of whether the actual function of the target chip is consistent with its functional description information based on the simulation output result and the image algorithm model processing result. This achieves the technical effect of interconnecting the image algorithm model and the UVM simulation verification platform to avoid data errors and algorithm processing flow errors, thereby improving the simulation efficiency and accuracy of the UVM platform.

[0088] Therefore, the technical solution provided by the above embodiments of the present invention solves the technical problem that the method of simulating and verifying chips in the related art isolates the interconnection and connectivity between the image algorithm model and the UVM simulation and verification platform, which easily causes data errors and algorithm processing flow errors, thereby reducing the simulation efficiency and accuracy of the UVM platform.

[0089] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0090] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0091] According to embodiments of the present invention, a chip hybrid simulation apparatus based on a general verification methodology and an image processing algorithm is also provided for implementing the above-described chip hybrid simulation method based on a general verification methodology and an image processing algorithm. Figure 6 This is a schematic diagram of a chip hybrid simulation device based on a general verification methodology and image processing algorithm according to an embodiment of the present invention, such as... Figure 6 As shown, the device includes: a trigger unit 601, a first acquisition unit 603, a second acquisition unit 606, a third acquisition unit 607, a fourth acquisition unit 609, and a fifth acquisition unit 611. The following is a detailed description of this chip hybrid simulation device based on a general verification methodology and image processing algorithms.

[0092] The triggering unit 601 is used to generate a start command based on the chip simulation task after receiving the chip simulation task, so as to trigger the start of the general verification methodology verification platform, wherein the verification platform integrates an image processing model.

[0093] The first acquisition unit 603 is used to input stimulus data into the design under test module after the simulation environment of the verification platform is running, so as to use the stimulus data to perform simulation processing on the target chip corresponding to the chip simulation task in the design under test module and obtain simulation output data.

[0094] The second acquisition unit 605 is used to acquire stimulus data and simulation output data, and send the stimulus data and simulation output data to the image processing model so that the image processing model can analyze and process the output data to obtain the simulation results of the target chip.

[0095] The third acquisition unit 607 is used to convert the format of the simulation output data and excitation data in the image processing model to obtain the simulation data bitstream and excitation data bitstream that can be recognized by the image processing algorithm in the image processing model.

[0096] The fourth acquisition unit 609 is used to process the excitation data bitstream using an image processing algorithm to obtain the image algorithm output data bitstream.

[0097] The fifth acquisition unit 611 is used to compare the simulation data bitstream in the image processing model with the image algorithm output data bitstream, so as to obtain the verification result of the target chip based on the comparison result. The verification result is used to indicate whether the actual function of the target chip is consistent with the function description information.

[0098] It should be noted that the triggering unit 601, the first acquisition unit 603, the second acquisition unit 606, the third acquisition unit 607, the fourth acquisition unit 609, and the fifth acquisition unit 611 mentioned above correspond to steps S202 to S212 in the above embodiments. The six units and the corresponding steps implement the same instances and application scenarios, but are not limited to the content disclosed in the above embodiments.

[0099] As can be seen from the above, in the scheme described in the above embodiments of the present invention, after receiving the chip simulation task, the triggering unit can generate a start command based on the chip simulation task to trigger the start of the general verification methodology verification platform, wherein the verification platform integrates an image processing model; then, after the first acquisition unit runs in the simulation environment of the verification platform, it inputs the stimulus data to the design under test module, so as to use the stimulus data to perform simulation processing on the target chip corresponding to the chip simulation task in the design under test module, and obtain simulation output data; then, the second acquisition unit acquires the stimulus data and simulation output data, and sends the stimulus data and simulation output data to the image processing model, so as to use the image processing model to analyze and process the output data to obtain the simulation result of the target chip; then, the third acquisition unit performs format conversion on the simulation output data and stimulus data in the image processing model to obtain the simulation data bitstream and stimulus data bitstream that the image processing algorithm in the image processing model can recognize; then, the fourth acquisition unit uses the image processing... The algorithm processes the stimulus data stream to obtain the image algorithm output data stream. Finally, the fifth acquisition unit compares the simulation data stream in the image processing model with the image algorithm output data stream to obtain the verification result of the target chip based on the comparison result. The verification result is used to indicate whether the actual function of the target chip is consistent with the functional description information. This achieves the goal of verifying whether the actual function of the target chip is consistent with its functional description information by integrating the image algorithm model with the UVM simulation verification platform. While using the chip simulation verification platform to simulate the target chip, the input data and simulation output data used in the simulation can be input to the image processing model for algorithm-level processing. Thus, the simulation output result and the image algorithm model processing result can be used to comprehensively verify whether the actual function of the target chip is consistent with its functional description information. This achieves the technical effect of interconnecting the image algorithm model and the UVM simulation verification platform to avoid data errors and algorithm processing flow errors, and improves the simulation efficiency and accuracy of the UVM platform.

[0100] Therefore, the technical solution provided by the above embodiments of the present invention solves the technical problem that the method of simulating and verifying chips in the related art isolates the interconnection and connectivity between the image algorithm model and the UVM simulation and verification platform, which easily causes data errors and algorithm processing flow errors, thereby reducing the simulation efficiency and accuracy of the UVM platform.

[0101] Optionally, the chip hybrid simulation device based on a general verification methodology and image processing algorithm further includes: a sixth acquisition unit, used to design the design-under-test module by calling the logic code of the design-under-test module before generating a start command based on the chip simulation task to trigger the start of the general verification methodology verification platform, wherein the logic code is code pre-written according to the chip simulation requirements; a determination unit, used to determine multiple components required to generate the verification platform based on the functional description information of the target chip, wherein the multiple components are components required for simulating the target chip; and a seventh acquisition unit, used to encapsulate the multiple components using the methodology architecture corresponding to the verification platform, and connect the encapsulated multiple components to obtain a verification platform including the design-under-test module and the encapsulated and connected multiple components.

[0102] Optionally, the first acquisition unit includes: a first trigger module, used to trigger the startup of the top-level configuration module in the verification platform, so as to configure the registers of the design under test module according to the functional description information of the target chip, and to set the simulation environment of the verification platform using the top-level configuration module; and a second trigger module, used to trigger the startup of the scene exciter in the verification platform, so as to generate excitation data, and input the excitation data to the design under test module, so as to drive the design under test module to perform simulation processing on the target chip and obtain simulation output data.

[0103] Optionally, the third acquisition unit includes: a third triggering module, used to trigger the start of the logic monitor of the verification platform during the process of inputting stimulus data into the design under test module to simulate the target chip in the design under test module using the stimulus data, so as to collect stimulus data and simulation output data, and input the stimulus data and simulation output data into the image processing model; and a first acquisition module, used to convert the format of the simulation output data using the data processing module in the image processing model after determining that the image processing model has received the simulation output data, so as to obtain the simulation data bitstream.

[0104] Optionally, the chip hybrid simulation device based on a general verification methodology and an image processing algorithm further includes: an eighth acquisition unit, used to acquire the configuration information of the register model in the verification platform and the setting information of the simulation environment in the verification platform before processing the excitation data stream using the image processing algorithm to obtain the output data stream of the image algorithm; and a processing unit, used to send the configuration information and setting information to the configuration module of the image processing model so that the configuration module can preprocess the configuration information and setting information to pair and integrate with the top-level configuration module of the verification platform.

[0105] Optionally, the fourth acquisition unit includes: a second acquisition module, used to perform analysis and processing of the excitation data bitstream in a predetermined dimension using the image processing algorithm and the configuration information of the register model in the verification platform to obtain the image algorithm output data bitstream, wherein the predetermined dimension includes at least one of the following: pixel depth, color temperature, contrast, color vividness, and transition smoothness.

[0106] Optionally, the fifth acquisition unit includes: a third acquisition module, used to compare the simulated data bitstream and the image algorithm output data bitstream in the image processing model to obtain a comparison result; a first determination module, used to determine that the actual function of the target chip is consistent with the function description information when the comparison result indicates that the simulated data bitstream and the image algorithm output data are both consistent or the number of inconsistencies between the simulated data bitstream and the image algorithm output data is less than a predetermined threshold; and a second determination module, used to determine that the actual function of the target chip is inconsistent with the function description information when the comparison result indicates that the number of inconsistencies between the simulated data bitstream and the image algorithm output data is not less than a predetermined threshold.

[0107] Optionally, the chip hybrid simulation device based on general verification methodology and image processing algorithm further includes: after the storage unit compares the simulation data bitstream in the image processing model with the output data bitstream of the image algorithm to obtain the verification result of the target chip based on the comparison result, it stores the verification result in the log.

[0108] According to another aspect of the present invention, a chip hybrid simulation system based on a general verification methodology and an image processing algorithm is also provided. The chip hybrid simulation system based on a general verification methodology and an image processing algorithm uses any of the above-described chip hybrid simulation methods based on a general verification methodology and an image processing algorithm.

[0109] According to another aspect of the present invention, a computer-readable storage medium is also provided, the computer-readable storage medium including a stored program, wherein the program executes any of the above-described chip hybrid simulation methods based on general verification methodology and image processing algorithms.

[0110] Optionally, in this embodiment, the computer-readable storage medium may be located in any computer terminal in a group of computer terminals in a computer network, or in any communication device in a group of communication devices.

[0111] Optionally, in this embodiment, the computer-readable storage medium is configured to store program code for performing the following steps: upon receiving a chip simulation task, generating a startup instruction based on the chip simulation task to trigger the startup of a general verification methodology verification platform, wherein the verification platform integrates an image processing model; after the simulation environment of the verification platform is running, inputting stimulus data to the design-under-test (DUT) module to perform simulation processing on the target chip corresponding to the chip simulation task in the DUT module using the stimulus data, and obtaining simulation output data; acquiring the stimulus data and simulation output data, and sending the stimulus data and simulation output data to the image processing model. The method involves using an image processing model to analyze and process the output data to obtain simulation results for the target chip; converting the format of the simulation output data and stimulus data in the image processing model to obtain simulation data bitstream and stimulus data bitstream that the image processing algorithm in the image processing model can recognize; processing the stimulus data bitstream using the image processing algorithm to obtain the image algorithm output data bitstream; and comparing the simulation data bitstream in the image processing model and the image algorithm output data bitstream to obtain the verification result of the target chip based on the comparison result. The verification result is used to indicate whether the actual function of the target chip is consistent with the functional description information.

[0112] Optionally, in this embodiment, the computer-readable storage medium is configured to store program code for performing the following steps: calling the logic code of the design under test (DUT) module to design and obtain the DUT module, wherein the logic code is code pre-written according to chip simulation requirements; determining multiple components required to generate a verification platform based on the functional description information of the target chip, wherein the multiple components are components required for simulating the target chip; encapsulating the multiple components using the methodology architecture corresponding to the verification platform, and connecting the encapsulated multiple components to obtain a verification platform including the DUT module and the encapsulated and connected multiple components.

[0113] Optionally, in this embodiment, the computer-readable storage medium is configured to store program code for performing the following steps: triggering the startup of the top-level configuration module in the verification platform to configure the registers of the design under test module according to the functional description information of the target chip, and setting the simulation environment of the verification platform using the top-level configuration module; triggering the startup of the scene exciter in the verification platform to generate excitation data, and inputting the excitation data to the design under test module to drive the design under test module to perform simulation processing on the target chip and obtain simulation output data.

[0114] Optionally, in this embodiment, the computer-readable storage medium is configured to store program code for performing the following steps: during the process of inputting stimulus data into the design under test module to simulate the target chip in the design under test module using the stimulus data, the logic monitor of the verification platform is triggered to start, so as to collect stimulus data and simulation output data, and input the stimulus data and simulation output data into the image processing model; after determining that the image processing model has received the simulation output data, the data processing module in the image processing model is used to perform format conversion on the simulation output data to obtain the simulation data bitstream.

[0115] Optionally, in this embodiment, the computer-readable storage medium is configured to store program code for performing the following steps: obtaining configuration information of the register model in the verification platform and setting information of the simulation environment in the verification platform; sending the configuration information and setting information to the configuration module of the image processing model, so as to use the configuration module to preprocess the configuration information and setting information, so as to pair and integrate the configuration module with the top-level configuration module of the verification platform.

[0116] Optionally, in this embodiment, the computer-readable storage medium is configured to store program code for performing the following steps: analyzing and processing the excitation data bitstream in a predetermined dimension using an image processing algorithm and configuration information of the register model in the verification platform to obtain the image algorithm output data bitstream, wherein the predetermined dimension includes at least one of the following: pixel depth, color temperature, contrast, color vividness, and transition smoothness.

[0117] Optionally, in this embodiment, the computer-readable storage medium is configured to store program code for performing the following steps: comparing the simulated data stream and the image algorithm output data stream in the image processing model to obtain a comparison result; when the comparison result indicates that the simulated data stream and the image algorithm output data are consistent or the number of inconsistencies between the simulated data stream and the image algorithm output data is less than a predetermined threshold, determining that the actual function of the target chip is consistent with the function description information; when the comparison result indicates that the number of inconsistencies between the simulated data stream and the image algorithm output data is not less than a predetermined threshold, determining that the actual function of the target chip is inconsistent with the function description information.

[0118] Optionally, in this embodiment, the computer-readable storage medium is configured to store program code for performing the following steps: storing the verification results in a log.

[0119] According to another aspect of the present invention, a processor is also provided, which is used to run a program, wherein the program executes any of the above-described chip hybrid simulation methods based on general verification methodology and image processing algorithms.

[0120] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0121] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0122] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For instance, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces; the indirect coupling or communication connection between units or modules may be electrical or other forms.

[0123] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0124] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0125] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0126] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A chip hybrid simulation method based on a general verification methodology and image processing algorithms, characterized in that, include: Upon receiving a chip simulation task, a startup command is generated based on the chip simulation task to trigger the startup of the general verification methodology verification platform, wherein the verification platform integrates an image processing model. After the simulation environment of the verification platform is running, the stimulus data is input to the design under test module so that the target chip corresponding to the chip simulation task can be simulated in the design under test module using the stimulus data to obtain simulation output data. The stimulus data and the simulation output data are acquired, and the stimulus data and the simulation output data are sent to the image processing model so that the output data can be analyzed and processed by the image processing model to obtain the simulation results of the target chip. The simulation output data and the excitation data in the image processing model are converted into formats to obtain a simulation data bitstream and an excitation data bitstream that can be recognized by the image processing algorithm in the image processing model. The image processing algorithm is used to process the excitation data bitstream to obtain the image algorithm output data bitstream; The simulated data stream and the output data stream of the image algorithm in the image processing model are compared to obtain the verification result of the target chip based on the comparison result. The verification result is used to indicate whether the actual function of the target chip is consistent with the function description information.

2. The chip hybrid simulation method based on general verification methodology and image processing algorithm according to claim 1, characterized in that, Before generating a startup instruction based on the chip simulation task to trigger the startup of the general verification methodology verification platform, the process also includes: The design module under test is obtained by calling the logic code of the design module under test, wherein the logic code is pre-written according to the chip simulation requirements; Based on the functional description information of the target chip, a plurality of components required to generate the verification platform are determined, wherein the plurality of components are components required for simulating the target chip; The multiple components are encapsulated using the methodology architecture corresponding to the verification platform, and the encapsulated multiple components are connected to obtain the verification platform including the design under test module and the encapsulated and connected multiple components.

3. The chip hybrid simulation method based on general verification methodology and image processing algorithm according to claim 1, characterized in that, After the simulation environment of the verification platform is running, the stimulus data is input to the design-under-test (DUT) module. The DUT module then uses this stimulus data to perform simulation processing on the target chip corresponding to the chip simulation task, obtaining simulation output data, including: The top-level configuration module in the verification platform is triggered to start, so that the top-level configuration module can configure the registers of the design under test module according to the functional description information of the target chip, and set the simulation environment of the verification platform. The scene exciter in the verification platform is triggered to generate the excitation data, and the excitation data is input to the design under test module to drive the design under test module to perform simulation processing on the target chip and obtain the simulation output data.

4. The chip hybrid simulation method based on general verification methodology and image processing algorithm according to claim 1, characterized in that, The simulation output data and the excitation data in the image processing model are format-converted to obtain a simulation data bitstream that can be recognized by the image processing algorithm in the image processing model, including: During the process of inputting stimulus data into the design under test module to simulate the target chip in the design under test module, the logic monitor of the verification platform is triggered to start, so as to collect the stimulus data and the simulation output data, and input the stimulus data and the simulation output data into the image processing model; After determining that the image processing model has received the simulation output data, the data processing module in the image processing model is used to convert the format of the simulation output data to obtain the simulation data bitstream.

5. The chip hybrid simulation method based on general verification methodology and image processing algorithm according to claim 1, characterized in that, Before processing the excitation data bitstream using the image processing algorithm to obtain the image algorithm output data bitstream, the method further includes: Obtain the configuration information of the register model in the verification platform and the setting information of the simulation environment in the verification platform; The configuration information and the setting information are sent to the configuration module of the image processing model so that the configuration module can preprocess the configuration information and the setting information, thereby enabling the configuration module to be paired and integrated with the top-level configuration module of the verification platform.

6. The chip hybrid simulation method based on general verification methodology and image processing algorithm according to claim 1, characterized in that, The image processing algorithm is used to process the excitation data bitstream to obtain the image algorithm output data bitstream, including: The image processing algorithm and the configuration information of the register model in the verification platform are used to analyze and process the excitation data bitstream in a predetermined dimension to obtain the output data bitstream of the image algorithm. The predetermined dimension includes at least one of the following: pixel depth, color temperature, contrast, color vividness, and transition smoothness.

7. The chip hybrid simulation method based on a general verification methodology and image processing algorithm according to any one of claims 1 to 6, characterized in that, The simulation data stream and the output data stream of the image algorithm in the image processing model are compared to obtain the verification result of the target chip based on the comparison result, including: The simulated data stream and the image algorithm output data stream are compared in the image processing model to obtain a comparison result; When the comparison result indicates that the simulated data stream and the image algorithm output data are consistent, or the number of inconsistencies between the simulated data stream and the image algorithm output data is less than a predetermined threshold, it is determined that the actual function of the target chip is consistent with the function description information. When the comparison result indicates that the number of inconsistencies between the simulated data bitstream and the image algorithm output data is not less than a predetermined threshold, it is determined that the actual function of the target chip is inconsistent with the function description information.

8. The chip hybrid simulation method based on general verification methodology and image processing algorithm according to claim 7, characterized in that, After comparing the simulated data bitstream and the image algorithm output data bitstream in the image processing model to obtain the verification result of the target chip based on the comparison result, the method further includes: The verification results are stored in the log.

9. A chip hybrid simulation device based on a general verification methodology and image processing algorithms, characterized in that, include: A triggering unit is used to generate a start command based on the chip simulation task after receiving the chip simulation task, so as to trigger the start of the general verification methodology verification platform, wherein the verification platform integrates an image processing model; The first acquisition unit is used to input stimulus data to the design under test module after the simulation environment of the verification platform is running, so as to use the stimulus data to perform simulation processing on the target chip corresponding to the chip simulation task in the design under test module to obtain simulation output data. The second acquisition unit is used to acquire the stimulus data and the simulation output data, and send the stimulus data and the simulation output data to the image processing model, so as to use the image processing model to analyze and process the output data to obtain the simulation results of the target chip; The third acquisition unit is used to perform format conversion on the simulation output data and the excitation data in the image processing model to obtain a simulation data bitstream and an excitation data bitstream that can be recognized by the image processing algorithm in the image processing model. The fourth acquisition unit is used to process the excitation data bitstream using the image processing algorithm to obtain the image algorithm output data bitstream; The fifth acquisition unit is used to compare the simulation data bitstream and the image algorithm output data bitstream in the image processing model to obtain the verification result of the target chip based on the comparison result, wherein the verification result is used to indicate whether the actual function of the target chip is consistent with the function description information.

10. A processor, characterized in that, The processor is used to run a program, wherein the program executes the chip hybrid simulation method based on a general verification methodology and an image processing algorithm as described in any one of claims 1 to 8.

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