A control circuit and a semiconductor memory

Abstract

The embodiment of the present disclosure provides a control circuit and a semiconductor memory, the control circuit is connected with a sensitive amplifier circuit, and the control circuit comprises a pre-charge control module and a power supply control module, wherein: the pre-charge control module comprises a pre-charge driving module and a pre-charge module, and the pre-charge driving module is connected with a first power supply, and is used for providing a pre-charge driving signal for the pre-charge module through the pre-charge driving module, and the pre-charge driving signal is used for controlling the pre-charge module to perform pre-charge processing on the sensitive amplifier circuit; the power supply control module comprises a power supply driving module and a reference power supply module, and the power supply driving module is connected with a second power supply, and is used for providing a power supply driving signal for the reference power supply module through the power supply driving module, and the reference power supply module is controlled to provide a reference voltage for the sensitive amplifier circuit according to the power supply driving signal. In this way, the first power supply is different from the second power supply, the power supply noise in different stages can be effectively suppressed, the read-write speed is improved, and then the performance of the sensitive amplifier is improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a control circuit and a semiconductor memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers, consisting of many repeating memory cells. During data reading, the read data signal for each memory cell is read sequentially via the local data line, global data line, and data bus; conversely, during data writing, the write data signal is written to the memory cell sequentially via the data bus, global data line, and local data line.

[0003] Currently, a sense amplifier (SA) is placed between the storage unit and the local data line. To improve the signal quality of the storage unit's contents, the stored data needs to be amplified by this sense amplifier before being read or written. However, noise can be easily introduced at different operating stages of this sense amplifier, making the data signal amplification process in related technologies insufficient, thus requiring further improvement in the performance of the sense amplifier. Summary of the Invention

[0004] This disclosure provides a control circuit and a semiconductor memory that can effectively suppress power supply noise at different stages, improve read and write speed, and thus improve the performance of the sensitive amplifier.

[0005] In a first aspect, embodiments of this disclosure provide a control circuit connected to a sensitive amplification circuit, and the control circuit includes a pre-charge control module and a power control module, wherein:

[0006] The precharge control module includes a precharge drive module and a precharge module. The precharge drive module is connected to the first power supply and is used to provide a precharge drive signal to the precharge module. The precharge drive signal is used to control the precharge module to perform precharge processing for the sensitive amplifier circuit.

[0007] The power control module includes a power drive module and a reference power supply module. The power drive module is connected to the second power supply and is used to provide a power drive signal to the reference power supply module through the power drive module. Based on the power drive signal, the reference power supply module is controlled to provide a reference voltage to the sensitive amplifier circuit. The first power supply and the second power supply are different.

[0008] In some embodiments, the control circuit further includes a power switch module, and the power switch module is connected to a third power source, wherein: the power switch module is used to receive a power enable signal and control the state of the switching transistor inside the power switch module according to the power enable signal, so as to provide a second power source to the power drive module through the third power source, and the first power source is different from the third power source.

[0009] In some embodiments, the third power supply includes a first operating power supply and a second operating power supply, the first operating power supply and the second operating power supply being in different voltage domains and / or having different temperature characteristics, and the power enable signal including a first power enable sub-signal and a second power enable sub-signal; the power switch module includes a first switch transistor and a second switch transistor, wherein: the first end of the first switch transistor is connected to the first operating power supply, the control end of the first switch transistor is connected to the first power enable sub-signal, the first end of the second switch transistor is connected to the second operating power supply, the control end of the second switch transistor is connected to the second power enable sub-signal, the second end of the first switch transistor is connected to the second end of the second switch transistor, and one of the first switch transistor and the second switch transistor is selectively turned on to provide a second power supply to the power drive module.

[0010] In some embodiments, when the sensitive amplifier circuit is operating in the bias elimination phase, the first switch is turned on to provide a second power supply to the power drive module through the first operating power supply; and when the sensitive amplifier circuit is operating in the signal amplification phase, the second switch is turned on to provide a second power supply to the power drive module through the second operating power supply.

[0011] In some embodiments, the power switch module includes at least one of the following: a pull-up power switch module and a pull-down power switch module; wherein the first and second switching transistors of the pull-up power switch module are PMOS transistors, the first and second switching transistors of the pull-down power switch module are NMOS transistors, and the first operating power supply connected to the pull-up power switch module is different from the first operating power supply connected to the pull-down power switch module, and the second operating power supply connected to the pull-up power switch module is different from the second operating power supply connected to the pull-down power switch module.

[0012] In some embodiments, when the number of power switch modules is at least one, the control circuit further includes a power switch control module, wherein: the power switch control module is configured to receive a bias cancellation enable signal and a target power enable signal, and generate at least one set of power enable signals based on the bias cancellation enable signal and the target power enable signal; wherein each set of power enable signals includes a first power enable sub-signal and a second power enable sub-signal, and at least one set of power enable signals corresponds to at least one power switch module.

[0013] In some embodiments, the target power enable signal includes a first target power enable signal and a second target power enable signal, and the power switch control module includes a first logic control module and a second logic control module, wherein: the first logic control module is used to receive the bias cancellation enable signal and the second target power enable signal, and output at least one first power enable sub-signal; the second logic control module is used to receive the bias cancellation enable signal and the first target power enable signal, and output at least one second power enable sub-signal; wherein the first target power enable signal and the first power enable sub-signal have the same valid state, and the second target power enable signal and the second power enable sub-signal have the same valid state.

[0014] In some embodiments, the first logic control module includes a first NOT gate, a first NAND gate, a first level conversion module, and a second NOT gate, wherein: the input of the first NOT gate is used to receive a second target power enable signal; the output of the first NOT gate is connected to the first input of the first NAND gate; the second input of the first NAND gate is used to receive a bias cancellation enable signal; the output of the first NAND gate is connected to the input of the first level conversion module; the output of the first level conversion module is connected to the input of the second NOT gate; and the output of the second NOT gate is used to output at least one first power enable sub-signal. The second logic control module includes a first NOR gate, a third NOT gate, a second level switching module, and a fourth NOT gate, wherein: the first input of the first NOR gate is used to receive a bias cancellation enable signal; the second input of the first NOR gate is used to receive a first target power enable signal; the output of the first NOR gate is connected to the input of the third NOT gate; the output of the third NOT gate is connected to the input of the second level conversion module; the output of the second level conversion module is connected to the input of the fourth NOT gate; and the output of the fourth NOT gate is used to output at least one second power enable sub-signal.

[0015] In some embodiments, the power switch control module further includes a fifth NOT gate, wherein: the input of the fifth NOT gate is used to receive a bias cancellation inverted signal, and the output of the fifth NOT gate is used to output a bias cancellation enable signal.

[0016] In some embodiments, the precharge module includes a precharge switch transistor, wherein: a first end of the precharge switch transistor is connected to a precharge power supply, a control end of the precharge switch transistor is used to receive a precharge drive signal, and a second end of the precharge switch transistor is connected to a readout bit line.

[0017] In some embodiments, the precharge module includes a precharge switch, wherein: a first end of the precharge switch is connected to a readout bit line, a control end of the precharge switch is used to receive a precharge drive signal, and a second end of the precharge switch is connected to a complementary readout bit line.

[0018] In some embodiments, the precharge drive module includes a precharge inverter, wherein: the input terminal of the precharge inverter is used to receive a precharge enable signal, the control terminal of the precharge inverter is connected to a first power supply, and the output terminal of the precharge inverter is used to output a precharge drive signal.

[0019] In a second aspect, embodiments of this disclosure provide a semiconductor memory, which includes a control circuit, a plurality of memory blocks, and a sensitive amplification module disposed between two adjacent memory blocks. A switching module is disposed between two adjacent sensitive amplification modules. The control circuit includes a pre-charge control module and a power control module. The sensitive amplification module includes a sensitive amplification circuit and a pre-charge control module. The switching module includes a power control module, wherein:

[0020] The precharge control module includes a precharge drive module and a precharge module. The precharge drive module is connected to the first power supply and is used to provide a precharge drive signal to the precharge module through the precharge drive module. Based on the precharge drive signal, the precharge module controls the precharge module to perform precharge processing for the sensitive amplifier circuit.

[0021] The power control module includes a power drive module and a reference power supply module. The power drive module is connected to the second power supply and is used to provide a power drive signal to the reference power supply module through the power drive module. Based on the power drive signal, the reference power supply module is controlled to provide a reference voltage to the sensitive amplifier circuit. The first power supply and the second power supply are different.

[0022] In some embodiments, the semiconductor memory further includes a power switch module as described in the first aspect and a power switch control module as described in the first aspect, wherein: the power switch module and the power switch control module are both located in the switch module; or, the power switch module is located in the switch module and the power switch control module is located in the peripheral area of ​​the semiconductor memory; or, the power switch module and the power switch control module are both located in the peripheral area of ​​the semiconductor memory.

[0023] This disclosure provides a control circuit and a semiconductor memory. The control circuit is connected to a sensitive amplifier circuit and includes a pre-charge control module and a power control module. The pre-charge control module includes a pre-charge drive module and a pre-charge module, with the pre-charge drive module connected to a first power supply. The pre-charge drive module provides a pre-charge drive signal to the pre-charge module, which controls the pre-charge module to perform pre-charge processing on the sensitive amplifier circuit. The power control module includes a power drive module and a reference power supply module, with the power drive module connected to a second power supply. The power drive module provides a power drive signal to the reference power supply module, which then controls the reference power supply module to provide a reference voltage to the sensitive amplifier circuit based on the power drive signal. The first power supply and the second power supply are different. Because the pre-charge drive module and the power drive module use different power supplies, power supply noise at different stages can be isolated, effectively improving SA noise suppression and read / write speed. This optimizes the signal amplification process of the sensitive amplifier circuit, thereby improving the performance of the sensitive amplifier. Attached Figure Description

[0024] Figure 1 A schematic diagram illustrating an application scenario for a sensitive amplifier;

[0025] Figure 2 A schematic diagram of the composition structure of a control circuit provided in an embodiment of this disclosure. Figure 1 ;

[0026] Figure 3 A schematic diagram of the composition structure of a control circuit provided in an embodiment of this disclosure. Figure 2 ;

[0027] Figure 4 A schematic diagram of the composition structure of a control circuit provided in an embodiment of this disclosure. Figure 3 ;

[0028] Figure 5 A schematic diagram of the composition structure of a control circuit provided in an embodiment of this disclosure. Figure 4 ;

[0029] Figure 6 A schematic diagram of the composition structure of a control circuit provided in an embodiment of this disclosure. Figure 5 ;

[0030] Figure 7 A schematic diagram of the composition structure of a power switch control module provided in this embodiment of the present disclosure. Figure 1 ;

[0031] Figure 8 A schematic diagram of the composition structure of a power switch control module provided in this embodiment of the present disclosure. Figure 2 ;

[0032] Figure 9 A schematic diagram of the composition structure of a pull-up power supply control module provided in an embodiment of this disclosure;

[0033] Figure 10 A schematic diagram illustrating the composition of a pull-down power supply control module provided in an embodiment of this disclosure;

[0034] Figure 11 A schematic diagram of the composition structure of a sensitive amplifier circuit provided in this embodiment of the present disclosure. Figure 1 ;

[0035] Figure 12 A schematic diagram of the composition structure of a sensitive amplifier circuit provided in this embodiment of the present disclosure. Figure 2 ;

[0036] Figure 13 A schematic diagram of the composition structure of a sensitive amplifier circuit provided in this embodiment of the present disclosure. Figure 3 ;

[0037] Figure 14 This is a schematic diagram illustrating an application scenario of a sensitive amplifier provided in an embodiment of this disclosure;

[0038] Figure 15 A signal timing diagram of a sensitive amplifier provided in an embodiment of this disclosure;

[0039] Figure 16 This is a schematic diagram of the composition structure of a semiconductor memory provided in an embodiment of this disclosure. Detailed Implementation

[0040] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely for explaining the relevant applications and are not intended to limit the applications. Furthermore, it should be noted that, for ease of description, only the parts relevant to the relevant applications are shown in the accompanying drawings.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0042] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0043] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific order of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0044] It should also be noted that the high and low levels used for signals in the embodiments of this disclosure refer to the logic levels of the signals. A signal having a high level is different from having a low level. For example, a high level may correspond to a signal having a first voltage, while a low level may correspond to a signal having a second voltage. In some embodiments, the first voltage is greater than the second voltage. Furthermore, the logic level of a signal may be different from or opposite to the described logic level. For example, a signal described as having a logic "high" level may alternatively have a logic "low" level, and a signal described as having a logic "low" level may alternatively have a logic "high" level.

[0045] Understandably, during DRAM operation, sensitive amplifiers are needed to amplify signals in various operational processes. See also Figure 1 This illustrates a schematic diagram of an application scenario for a sensitive amplifier. For example... Figure 1 As shown, this application scenario may include a first signal line 11, a second signal line 12, and a sensitive amplifier 13. Among them,

[0046] The first signal line 11 has a first switch Sx and a first capacitor C1 for receiving the signal to be processed, Vin+; the second signal line 12 has a second switch Sy and a second capacitor C2 for receiving a reference signal to be processed, Vin-; the sensitive amplifier 13 amplifies both the signal to be processed, Vin+, and the reference signal to be processed, Vin-, with a voltage difference ΔVin between them. The first switch Sx and the second switch Sy control the connection between the first signal line 11, the second signal line 12, and the sensitive amplifier 13; the first capacitor C1 and the second capacitor C2 filter the signal to be processed, Vin+, and the reference signal to be processed, Vin-, reducing their high-frequency characteristics.

[0047] Specifically, the sensitive amplifier 13 may include a first switch M1, a second switch M2, a third switch M3, and a fourth switch M4. The control terminal of the first switch M1, the control terminal of the second switch M2, the first terminal of the third switch M3, and the first terminal of the fourth switch M4 are all connected to the reference signal to be processed Vin-, and the first terminal of the first switch M1, the first terminal of the second switch M2, the control terminal of the third switch M3, and the control terminal of the fourth switch M4 are all connected to the signal to be processed Vin+. In this application scenario, there are also a fifth switch M5 and a sixth switch M6. The control terminal of the fifth switch M5 is connected to the first control signal SAP. The first terminal of the fifth switch M5 is connected to the power signal VBLH. The second terminal of the fifth switch M5 is connected to the second terminals of the first switch M1 and the third switch M3 to form a first reference signal terminal, denoted by PCS. The control terminal of the sixth switch M6 is connected to the second control signal SAN. The first terminal of the sixth switch M6 is connected to the ground signal GND. The second terminal of the sixth switch M6 is connected to the second terminals of the second switch M2 and the fourth switch M4 to form a second reference signal terminal, denoted by NCS.

[0048] In addition, a pre-charging circuit may exist between the first signal line 11 and the second signal line 12, and a pre-charging circuit may also exist between the second terminal of the third switch M3 and the second terminal of the fourth switch M4, for pre-charging the first reference signal terminal and the second reference signal terminal.

[0049] It should be noted that, in Figure 1 In this circuit, the first switch M1, the third switch M2, and the fifth switch M5 are P-type field-effect transistors (PMOSFETs, or PMOS transistors for short); the second switch M2, the fourth switch M4, and the sixth switch M6 are N-type field-effect transistors (NMOSFETs, or NMOS transistors for short).

[0050] It should also be noted that, in Figure 1 In this circuit, the first switch M1 and the second switch M2 form an inverter INV1, and the third switch M3 and the fourth switch M4 form another inverter INV2. Their inputs and outputs are connected respectively, thus forming a latch. The power supply signal VBLH provides power to the sensitive amplifier 13 and is connected to the sensitive amplifier 13 by the fifth switch M5; the ground signal GND is the ground line of the sensitive amplifier and is connected to the sensitive amplifier 13 by the sixth switch M6.

[0051] In this embodiment, the working process can be divided into three stages: a precharge (EQ) stage, a small signal input stage, and a signal amplification stage. Specifically, in the EQ stage, the precharge circuit precharges the sensitive amplifier 13; in the small signal input stage, the small signal can be drawn from... Figure 1 The input is either Sx or Sy; during the signal amplification stage, the signal can be amplified by the sensitive amplifier 13.

[0052] In related technologies, stored data needs to be amplified by a sensitive amplifier before being read or written to improve the signal quality of the stored cell content. However, in traditional sensitive amplifiers, the pre-charge circuit and the pull-down reference circuit share a single power supply, which can easily introduce noise at different operating stages of the sensitive amplifier (SA), negatively impacting the sensitivity margin and thus affecting the amplification process of the data signal, resulting in a need to improve the performance of the sensitive amplifier. Based on this, embodiments of this disclosure provide a control circuit connected to a sensitive amplifier circuit. This control circuit includes a pre-charge control module and a power control module. The pre-charge control module includes a pre-charge drive module and a pre-charge module, and the pre-charge drive module is connected to a first power supply. It provides a pre-charge drive signal to the pre-charge module, which controls the pre-charge module to perform pre-charge processing on the sensitive amplifier circuit. The power control module includes a power drive module and a reference power supply module, and the power drive module is connected to a second power supply. It provides a power drive signal to the reference power supply module, and controls the reference power supply module to provide a reference voltage to the sensitive amplifier circuit based on the power drive signal. The first power supply and the second power supply are different. In this way, since the precharge drive module and the power drive module use different power supplies, power supply noise at different stages can be isolated, which effectively improves SA noise suppression and read / write speed, and optimizes the signal amplification process of the sensitive amplifier circuit. At the same time, based on the difference between the first power supply and the second power supply, the sense margin can also be optimized, thereby improving the performance of the sensitive amplifier.

[0053] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0054] In one embodiment of this disclosure, see Figure 2 This illustration shows a schematic diagram of the composition structure of a control circuit provided in an embodiment of the present disclosure. Figure 2 As shown, the control circuit 20 may include a precharge control module 21 and a power control module 22, wherein:

[0055] The precharge control module 21 includes a precharge drive module 211 and a precharge module 212. The precharge drive module 211 is connected to the first power supply and is used to provide a precharge drive signal to the precharge module 212. The precharge drive signal is used to control the precharge module 212 to perform precharge processing for the sensitive amplifier circuit.

[0056] The power control module 22 includes a power drive module 221 and a reference power module 222. The power drive module 221 is connected to the second power supply and is used to provide a power drive signal to the reference power module 222 through the power drive module 221, and control the reference power module 222 to provide a reference voltage to the sensitive amplifier circuit according to the power drive signal; wherein, the first power supply and the second power supply are different.

[0057] It should be noted that, in the embodiments of this disclosure, the control circuit 20 can be applied in various signal amplification scenarios, such as the sensitive amplifier in DRAM.

[0058] It should also be noted that, in Figure 2 In this circuit, the first power supply can be represented by VDD1, and the second power supply can be represented by VDD2. Additionally, the control circuit 20 can be connected to the sensitive amplifier circuit 30. Specifically, during the pre-charge phase, the pre-charge drive module 211 provides a pre-charge drive signal to the pre-charge module 212, enabling the pre-charge module 212 to perform pre-charge processing on the sensitive amplifier circuit 30. During the signal amplification phase, the power drive module 221 provides a power drive signal to the reference power supply module 222, enabling the reference power supply module 222 to provide a reference voltage to the sensitive amplifier circuit, thereby enabling signal amplification processing.

[0059] Understandably, the second power source can be a directly supplied external power source, or it can be obtained from an external power source after relevant processing. In some embodiments, in Figure 2 Based on the control circuit 20 shown, see Figure 3 The control circuit 20 may further include a power switch module 23, and the power switch module 23 is connected to a third power source, wherein:

[0060] The power switch module 23 is used to receive the power enable signal and control the state of the switching transistor inside the power switch module according to the power enable signal, so as to provide a second power supply to the power drive module 221 through the third power supply. The first power supply is different from the third power supply.

[0061] It should be noted that in this embodiment, the third power supply can be represented by VDD3. The second power supply can be obtained from the third power supply through processing by the power switch module 23, thereby enabling the power drive module 221 to provide different second power supplies at different stages, achieving the purpose of reducing power supply noise. In other words, the power switch module 23 has a voltage regulation function, and can output different second power supplies while keeping the third power supply VDD3 constant.

[0062] In parallel, to better enable the power switch module 23 to output different second power supplies at different stages, in some embodiments, the third power supply may include a first operating power supply and a second operating power supply, and the first operating power supply and the second operating power supply are in different voltage domains and / or have different temperature characteristics. Specifically, the first operating power supply is different from the second operating power supply; the first operating power supply provides the operating power required for the first stage of the power drive module 221, and the second operating power supply provides the operating power required for the second stage of the power drive module 221.

[0063] It should also be noted that when the third power supply includes both the first and second operating power supplies, the power enable signal may include both the first and second power enable sub-signals. Accordingly, in some embodiments, in... Figure 3 Based on the control circuit 20 shown, see Figure 4 The power switch module 23 may include a first switch transistor Q1 and a second switch transistor Q2; wherein, the first end of the first switch transistor Q1 is connected to the first working power supply, the control end of the first switch transistor Q1 is connected to the first power enable sub-signal, the first end of the second switch transistor Q2 is connected to the second working power supply, the control end of the second switch transistor Q2 is connected to the second power enable sub-signal, the second end of the first switch transistor Q1 is connected to the second end of the second switch transistor Q2, and one of the first switch transistor Q1 and the second switch transistor Q2 is selectively turned on to provide a second power supply to the power drive module 221.

[0064] It should be noted that in this embodiment, the first switch Q1 and the second switch Q2 will not be turned on simultaneously. Instead, at different stages, only one of the first switch Q1 and the second switch Q2 is turned on, thereby providing different second power supplies to the power drive module 221. In some embodiments, the first power enable sub-signal is also used to control the conduction level of the first switch Q1, and the second power enable sub-signal is also used to control the conduction level of the second switch Q2, thereby adjusting the magnitude of the second power supply VDD2.

[0065] Specifically, in this embodiment, if the sensitive amplifier circuit 30 operates in the first stage, then for the power switch module 23, the first switch Q1 is controlled to be in the on state according to the first power enable sub-signal, and the second switch Q2 is controlled to be in the off state according to the second power enable sub-signal, so as to provide the second power to the power drive module 221 through the first working power supply; if the sensitive amplifier circuit 30 operates in the second stage, then for the power switch module 23, the first switch Q1 is controlled to be in the off state according to the first power enable sub-signal, and the second switch Q2 is controlled to be in the on state according to the second power enable sub-signal, so as to provide the second power to the power drive module 221 through the second working power supply.

[0066] It should also be noted that, in the embodiments disclosed herein, the first stage can be an offset cancellation (OC or NC) stage, and the second stage can be a signal amplification (Develop) stage. Therefore, in some embodiments, when the sensitive amplifier circuit 30 operates in the offset cancellation stage, the first switch Q1 is turned on to provide a second power supply to the power drive module 221 through the first operating power supply; when the sensitive amplifier circuit 30 operates in the signal amplification stage, the second switch Q2 is turned on to provide a second power supply to the power drive module 221 through the second operating power supply.

[0067] In this embodiment, the second power supply is adjusted according to the OC and Develop phases, which can improve SA noise suppression, read / write speed control, and sense margin optimization. Furthermore, during the adjustment process, the first operating power supply in the OC phase and the second operating power supply in the Develop phase are in different voltage domains and / or have different temperature characteristics; that is, the second power supply required by the power drive module 221 can be separated according to the OC and Develop phases, and the operating power supplies in the OC and Develop phases can have their corresponding voltage trim ranges and temperature characteristics adjusted separately, which is more beneficial for the sense margin optimization of the sensitive amplifier circuit 30.

[0068] It is also understood that, in the embodiments of this disclosure, the power control module 22 can be a pull-up power control module or a pull-down power control module. In some embodiments, for the power control module 22, in Figure 2 Based on the control circuit 20 shown, see Figure 5 The control circuit 20 may further include a pull-up power supply control module 24 and a pull-down power supply control module 25, wherein:

[0069] The pull-up power control module 24 includes a pull-up power drive module 241 and a pull-up reference power module 242. The pull-up power drive module 241 is connected to the fourth power supply and is used to provide a pull-up power drive signal to the pull-up reference power module 242 through the pull-up power drive module 241, and control the pull-up reference power module 242 to provide a first reference voltage to the sensitive amplifier circuit 30 according to the pull-up power drive signal.

[0070] The pull-down power supply control module 25 includes a pull-down power supply driver module 251 and a pull-down reference power supply module 252. The pull-down power supply driver module 251 is connected to the fifth power supply and is used to provide a pull-down power supply drive signal to the pull-down reference power supply module 252 through the pull-down power supply driver module 251, and control the pull-down reference power supply module 252 to provide a second reference voltage to the sensitive amplifier circuit 30 according to the pull-down power supply drive signal.

[0071] In this embodiment, the first power supply is different from the fourth power supply, and also different from the fifth power supply. The fourth power supply can be represented by VDD4, and the fifth power supply can be represented by VDD5. Furthermore, the pull-up power supply control module 24 can be... Figure 2 The power control module 22 or the pull-down power control module 25 can be... Figure 2 The internal structure of the power control module 22, namely the pull-up power control module 24 and the pull-down power control module 25, is the same as that of the power control module 22.

[0072] In other words, when the control circuit 20 includes two power control modules 22, these two power control modules can be referred to as pull-up power control module 24 and pull-down power control module 25. Since the second power supply can be generated by the power switch module and its connected first and second working power supplies, correspondingly, for the pull-up power control module 24, the fourth power supply can also be generated by the power switch module and its connected first and second working power supplies; similarly, for the pull-down power control module 25, the fifth power supply can also be generated by the power switch module and its connected first and second working power supplies.

[0073] Thus, in cases where the power control module 22 can be a pull-up power control module and / or a pull-down power control module, in some embodiments, the power switch module 23 includes at least one of the following: a pull-up power switch module and a pull-down power switch module;

[0074] The pull-up power switch module includes a first switch transistor and a second switch transistor, which can be PMOS transistors. The pull-down power switch module includes a first switch transistor and a second switch transistor, which can be NMOS transistors. Moreover, the first working power supply connected to the pull-up power switch module is different from the first working power supply connected to the pull-down power switch module, and the second working power supply connected to the pull-up power switch module is different from the second working power supply connected to the pull-down power switch module.

[0075] In the embodiments disclosed herein, see details. Figure 5The control circuit 20 may further include a pull-up power switch module 26 and a pull-down power switch module 27. The pull-up power switch module 26 is connected to the pull-up power drive module 241 and provides a fourth power supply VDD4 to the pull-up power drive module 241, enabling the pull-up power drive module 241 to drive the pull-up reference power supply module 242, thereby providing a first reference voltage to the sensitive amplifier circuit 30. The pull-down power switch module 27 is connected to the pull-down power drive module 251 and provides a fifth power supply VDD5 to the pull-down power drive module 251, enabling the pull-down power drive module 251 to drive the pull-down reference power supply module 252, thereby providing a second reference voltage to the sensitive amplifier circuit 30.

[0076] It should also be noted that, in Figure 5 In the above, the pull-up power switch module 26 may include a first switch P1 and a second switch P2. The first end of the first switch P1 is connected to the third working power supply VNOCP, and the control end of the first switch P1 is connected to the first power enable sub-signal. The first end of the second switch P2 is connected to the fourth working power supply VPCSG, and the control end of the second switch P2 is connected to the second power enable sub-signal. The second end of the first switch P1 is connected to the second end of the second switch P2, and one of the first switch P1 and the second switch P2 is selectively turned on to provide the fourth power supply VDD4 to the pull-up power drive module 241.

[0077] The pull-down power switch module 27 may include a first switch transistor N1 and a second switch transistor N2. The first end of the first switch transistor N1 is connected to the fifth working power supply VNOC, and the control end of the first switch transistor N1 is connected to the first power enable sub-signal. The first end of the second switch transistor N2 is connected to the sixth working power supply VNCSGH, and the control end of the second switch transistor N2 is connected to the second power enable sub-signal. The second end of the first switch transistor N1 is connected to the second end of the second switch transistor N2, and one of the first switch transistor N1 and the second switch transistor N2 is selectively turned on to provide the fifth power supply VDD5 to the pull-down power drive module 251.

[0078] It should be noted that, in this embodiment, for the pull-up power switch module 26, during the OC phase, the first switch P1 is turned on to provide a second power supply to the pull-up power drive module 241 through the third operating power supply vnocp; during the signal amplification phase, the second switch P2 is turned on to provide a second power supply to the pull-up power drive module 241 through the fourth operating power supply vpcsg (specifically, the fourth power supply). Since the third operating power supply vnocp and the fourth operating power supply vpcsg are in different voltage domains and / or have different temperature characteristics, they can provide different second power supplies to the pull-up power drive module 241 at different stages. For the pull-down power switch module 27, during the OC phase, the first switch N1 is turned on to provide a second power supply to the pull-down power drive module 251 through the fifth operating power supply vnoc; during the signal amplification phase, the second switch N2 is turned on to provide a second power supply to the pull-down power drive module 251 through the sixth operating power supply vncsgh (specifically, the fifth power supply). Since the fifth operating power supply vnoc and the sixth operating power supply vncsgh are in different voltage domains and / or have different temperature characteristics, they can provide different second power supplies to the pull-down power supply driver module 251 at different stages.

[0079] In this way, the second power supply required by both the pull-up power supply driver module 241 and the pull-down power supply driver module 251 can be separated according to the OC stage and the Develop stage. Moreover, the operating power supply of the OC stage and the Develop stage can be adjusted according to the corresponding voltage trim range and temperature characteristics, thereby improving SA noise suppression, read / write speed control and sense margin optimization, and ultimately improving the performance of the sensitive amplifier.

[0080] It is also understandable that when the number of power switch modules 23 is at least one, the required power enable signal corresponds to at least one set. Therefore, in Figure 5 Based on the control circuit 20 shown, in some embodiments, see [reference needed]. Figure 6 The control circuit 20 may further include a power switch control module 28, wherein:

[0081] The power switch control module 28 is used to receive the bias cancellation enable signal and the target power enable signal, and generate at least one set of power enable signals based on the bias cancellation enable signal and the target power enable signal; wherein each set of power enable signals includes a first power enable sub-signal and a second power enable sub-signal, and at least one set of power enable signals has a corresponding relationship with at least one power switch module.

[0082] It should be noted that, in Figure 6Taking the pull-up power switch module 26 and the pull-down power switch module 27 as an example, after receiving the bias cancellation enable signal and the target power enable signal, the power switch control module 28 can output two sets of power enable signals. One set of power enable signals is sent to the pull-up power switch module 26, and the other set of power enable signals is sent to the pull-down power switch module 27.

[0083] It should also be noted that, in the embodiments of this disclosure, the target power enable signal may include a first target power enable signal and a second target power enable signal. Accordingly, in some embodiments, see [link to relevant documentation]. Figure 7 The power switch control module 28 may include a first logic control module 281 and a second logic control module 282, wherein:

[0084] The first logic control module 281 is used to receive the bias cancellation enable signal and the second target power enable signal, and output at least one first power enable sub-signal.

[0085] The second logic control module 282 is used to receive the bias cancellation enable signal and the first target power enable signal, and output at least one second power enable sub-signal.

[0086] Here, the first target power enable signal and the first power enable sub-signal have the same valid state, and the second target power enable signal and the second power enable sub-signal have the same valid state. In other words, the valid levels of the first target power enable signal and the first power enable sub-signal correspond to the same operating state, and the valid levels of the second target power enable signal and the second power enable sub-signal correspond to the same operating state.

[0087] It should also be noted that the power switch control module 28 can output at least one set of power enable signals, and the number of power enable signals is related to the number of power switch modules 23. Specifically, if the control circuit 20 includes two power switch modules, such as a pull-up power switch module and a pull-down power switch module, then the power switch control module 28 needs to output two sets of power enable signals, with each set of power enable signals corresponding to one power switch module, such as... Figure 6 The pull-up power switch module 26 is connected to one set of power enable signals, and the pull-down power switch module 27 is connected to another set of power enable signals.

[0088] In some embodiments, such as Figure 7 As shown, the first logic control module 281 may include a first NOT gate U1, a first NAND gate U2, a first level conversion module U3, and a second NOT gate U4, wherein:

[0089] The input terminal of the first NOT gate U1 is used to receive the second target power enable signal. The output terminal of the first NOT gate U1 is connected to the first input terminal of the first NAND gate U2. The second input terminal of the first NAND gate U2 is used to receive the bias cancellation enable signal. The output terminal of the first NAND gate U2 is connected to the input terminal of the first level conversion module U3. The output terminal of the first level conversion module U3 is connected to the input terminal of the second NOT gate U4. The output terminal of the second NOT gate U4 is used to output at least one first power enable sub-signal.

[0090] The second logic control module 282 may include a first NOR gate U5, a third NOT gate U6, a second level switching module U7, and a fourth NOT gate U8, wherein:

[0091] The first input of the first NOR gate U5 is used to receive the bias cancellation enable signal, the second input of the first NOR gate U5 is used to receive the first target power enable signal, the output of the first NOR gate U5 is connected to the input of the third NOT gate U6, the output of the third NOT gate U6 is connected to the input of the second level conversion module U7, the output of the second level conversion module U7 is connected to the input of the fourth NOT gate U8, and the output of the fourth NOT gate U8 is used to output at least one second power enable sub-signal.

[0092] It should be noted that, in the embodiments of this disclosure, the first level switching module U3 or the second level switching module U7 can realize voltage domain switching, and different voltage domains can correspond to different sets of power enable signals; after the power switch control module 28 outputs at least one set of power enable signals, these power enable signals can be sent to different power switch modules.

[0093] It should also be noted that, for the power switch control module 28, in Figure 7 Based on the power switch control module 28 shown, in some embodiments, see [reference needed]. Figure 8 The power switch control module 28 may also include a fifth NOT gate U9, wherein:

[0094] The input terminal of the fifth NOT gate U9 is used to receive the bias cancellation inverted signal. The output terminal of the fifth NOT gate U9 is connected to the second input terminal of the first NAND gate U2 and the first input terminal of the first NOR gate U5, respectively, to provide the bias cancellation enable signal to the second input terminal of the first NAND gate U2 and the first input terminal of the first NOR gate U5.

[0095] It should be noted that, in this embodiment of the disclosure, the bias cancellation inverted signal and the bias cancellation enable signal are a pair of inverted signals. The bias cancellation enable signal can be represented by NcEn, and the bias cancellation inverted signal can be represented by NcEnN.

[0096] It should also be noted that, in this embodiment of the present disclosure, the power switch control module 28, as a master control circuit, can provide a set of power enable signals (including a first power enable sub-signal and a second power enable sub-signal) for different power switch modules. Furthermore, the first power enable sub-signal and the second power enable sub-signal in each set are generated based on a bias cancellation inverted signal, and the first power enable sub-signal and the second power enable sub-signal will not be simultaneously in an active level state; that is, there is a timing relationship between the bias cancellation inverted signal and the first power enable sub-signal and the second power enable sub-signal.

[0097] It is also understandable that in the pull-up power supply control module 24, for the pull-up reference power supply module 242, the pull-up reference power supply module 242 may include multiple pull-up switching transistors, wherein:

[0098] The control terminal (gate) of the pull-up switch is used to receive the pull-up power supply drive signal. The first terminal of the pull-up switch is connected to the pull-up reference power supply, and the second terminal of the pull-up switch is used to output the first reference voltage PCS.

[0099] Accordingly, for the pull-up power supply driver module 241, the pull-up power supply driver module 241 may include multiple pull-up inverters, wherein:

[0100] The control terminal of the pull-up inverter is connected to the pull-up drive power supply. The input terminal of the pull-up inverter is used to receive the pull-up control input signal, and the output terminal of the pull-up inverter is used to output the pull-up power drive signal.

[0101] It should be noted that, in this embodiment, the number of pull-up switches is the same as the number of pull-up inverters. The output terminal of each pull-up inverter is connected to the control terminal of the corresponding pull-up switch, providing a pull-up power drive signal to the pull-up switch.

[0102] For example, the pull-up power supply driver module 241 includes three pull-up inverters, and the pull-up reference power supply module 242 includes three pull-up switching transistors. See details below. Figure 9 In the pull-up power supply control module 24, the pull-up power supply drive module 241 may include a first pull-up inverter I1, a second pull-up inverter I2, and a third pull-up inverter I3, and the pull-up reference power supply module 242 may include a first pull-up switch M1, a second pull-up switch M2, and a third pull-up switch M3, wherein:

[0103] In the pull-up power supply driver module 241, the input terminal of the first pull-up inverter I1 is used to receive the first control input signal Vpu1, and the output terminal of the first pull-up inverter I1 is used to output the first pull-up power supply driver signal Pup1; the input terminal of the second pull-up inverter I2 is used to receive the second control input signal Vpu2, and the output terminal of the second pull-up inverter I2 is used to output the second pull-up power supply driver signal Pup2; the input terminal of the third pull-up inverter I3 is used to receive the third control input signal Vpu3, and the output terminal of the third pull-up inverter I3 is used to output the third pull-up power supply driver signal Pup3; the control terminals of the first pull-up inverter I1, the second pull-up inverter I2, and the third pull-up inverter I3 are all connected to the pull-up drive power supply vpcsgloc. In the pull-up reference power supply module 242, the first terminal of the first pull-up switch M1 is connected to the first pull-up reference power supply vblh1, the first terminal of the second pull-up switch M2 is connected to the second pull-up reference power supply vblh2, and the first terminal of the third pull-up switch M3 is connected to the third pull-up reference power supply vblh3. The control terminal of the first pull-up switch M1 is used to receive the first pull-up power supply drive signal Pup1, the control terminal of the second pull-up switch M2 is used to receive the second pull-up power supply drive signal Pup2, and the control terminal of the third pull-up switch M3 is used to receive the third pull-up power supply drive signal Pup3. The second terminals of the first pull-up switch M1, the second pull-up switch M2, and the third pull-up switch M3 are connected to output the first reference voltage PCS. Here, the first pull-up reference power supply vblh1, the second pull-up reference power supply vblh2, and the third pull-up reference power supply vblh3 can be the same or different; no limitation is made here.

[0104] It is important to note that, in Figure 9 In this context, the pull-up drive power supply vpcsgloc (i.e., the fourth power supply described in the aforementioned embodiment) is provided by the pull-up power switch module 26. For example... Figure 9 As shown, in the pull-up power switch module 26, the first terminal of the first switch P1 is connected to the third working power supply vnocp, the control terminal of the first switch P1 is connected to the first power enable sub-signal SCmosOcEn, the first terminal of the second switch P2 is connected to the fourth working power supply vpcsg, the control terminal of the second switch P2 is connected to the second power enable sub-signal SCmosSDTEn, the second terminal of the first switch P1 is connected to the second terminal of the second switch P2, and one of the first switch P1 and the second switch P2 is selectively turned on to provide the pull-up drive power supply vpcsgloc for the pull-up power drive module 241.

[0105] It is also understandable that in the pull-down power control module 25, for the pull-down reference power module 252, the pull-down reference power module 252 may include multiple pull-down switching transistors, wherein:

[0106] The control terminal of the pull-down switch is used to receive the pull-down power supply drive signal. The first terminal of the pull-down switch is connected to the pull-down reference power supply, and the second terminal of the pull-down switch is used to output the second reference voltage NCS.

[0107] Accordingly, for the pull-down power supply driver module 251, the pull-down power supply driver module 251 may include multiple pull-down inverters, wherein:

[0108] The control terminal of the pull-down inverter is connected to the pull-down drive power supply. The input terminal of the pull-down inverter is used to receive the pull-down control input signal, and the output terminal of the pull-down inverter is used to output the pull-down power supply drive signal.

[0109] It should be noted that, in this embodiment, the number of pull-down switches is the same as the number of pull-down inverters. The output of each pull-down inverter is connected to the control terminal of the corresponding pull-down switch, providing a pull-down power drive signal to the pull-down switch.

[0110] For example, consider a pull-down power supply driver module 251 that includes three pull-down inverters and a pull-down reference power supply module 252 that includes three pull-down switching transistors. See also... Figure 10 In the pull-down power control module 25, the pull-down power drive module 251 may include a first pull-down inverter I4, a second pull-down inverter I5, and a third pull-down inverter I6, and the pull-down reference power module 252 may include a first pull-down switch M4, a second pull-down switch M5, and a third pull-down switch M6, wherein:

[0111] In the pull-down power supply driver module 251, the input terminal of the first pull-down inverter I4 is used to receive the fourth control input signal Vpd1, and the output terminal of the first pull-down inverter I4 is used to output the first pull-down power supply driver signal Pdn1; the input terminal of the second pull-down inverter I5 is used to receive the fifth control input signal Vpd2, and the output terminal of the second pull-down inverter I5 is used to output the second pull-down power supply driver signal Pdn2; the input terminal of the third pull-down inverter I6 is used to receive the sixth control input signal Vpd3, and the output terminal of the third pull-down inverter I6 is used to output the third pull-down power supply driver signal Pdn3; the control terminals of the first pull-down inverter I4, the second pull-down inverter I5, and the third pull-down inverter I6 are all connected to the pull-down driver power supply vncsgloc. In the pull-down reference power supply module 252, the control terminal of the first pull-down switch M4 is used to receive the first pull-down power supply drive signal Pdn1, the control terminal of the second pull-down switch M5 is used to receive the second pull-down power supply drive signal Pdn2, and the control terminal of the third pull-down switch M6 is used to receive the third pull-down power supply drive signal Pdn3; the first terminals of the first pull-down switch M4, the second pull-down switch M5, and the third pull-down switch M6 are connected to output the second reference voltage NCS; the second terminals of the first pull-down switch M4, the second pull-down switch M5, and the third pull-down switch M6 are all connected to the pull-down reference power supply VSS.

[0112] It is important to note that, in Figure 10 In this context, the pull-down drive power supply vncsgloc (i.e., the fifth power supply described in the aforementioned embodiment) is provided by the pull-down power switch module 27. For example... Figure 10 As shown, in the pull-down power switch module 27, the first terminal of the first switch N1 is connected to the fifth working power supply vnoc, the control terminal of the first switch N1 is connected to the first power enable sub-signal SCmosOcEn, the first terminal of the second switch N2 is connected to the sixth working power supply vncsgh, the control terminal of the second switch N2 is connected to the second power enable sub-signal SCmosSDTEn, the second terminal of the first switch N1 is connected to the second terminal of the second switch N2, and one of the first switch N1 and the second switch N2 is selectively turned on to provide the pull-down drive power supply vncsgloc for the pull-down power drive module 251.

[0113] Furthermore, in this embodiment, the third operating power supply vnocp and the fourth operating power supply vpcsg are in different voltage ranges and / or have different temperature characteristics, thereby providing different pull-up drive power supplies vpcsgloc to the pull-up power drive module 241 at different stages; the fifth operating power supply vnoc and the sixth operating power supply vncsgh are in different voltage domains and / or have different temperature characteristics, thereby providing different pull-down drive power supplies vncsgloc to the pull-down power drive module 251 at different stages; thus, the pull-up / pull-down drive power supplies can be adjusted according to the OC stage and the Develop stage, which can isolate the power supply noise in the OC stage and the Develop stage, thereby effectively improving SA noise suppression and read / write speed, and is also more beneficial for sense margin optimization.

[0114] It is also understood that, in some embodiments of this disclosure, for the sensitive amplifier circuit 30, see [reference needed]. Figure 11 The sensitive amplifier circuit 30 may include a seventh switch M7, an eighth switch M8, a ninth switch M9, a tenth switch M10, an eleventh switch M11, a twelfth switch M12, a thirteenth switch M13, and a fourteenth switch M14. Specifically, the seventh switch M7, the eighth switch M8, the ninth switch M9, and the tenth switch M10 form an amplification module; the eleventh switch M11 and the twelfth switch M12 form an isolation control module; and the thirteenth switch M13 and the fourteenth switch M14 form a bias cancellation module.

[0115] Here, the first terminal of the seventh switch M7 is connected to the first terminal of the eighth switch M8, and both are used to receive the first reference voltage PCS; the second terminal of the ninth switch M9 is connected to the second terminal of the tenth switch M10, and both are used to receive the second reference voltage NCS; the second terminal of the seventh switch M7, the control terminal of the eighth switch M8, the first terminal of the ninth switch M9, the second terminal of the twelfth switch M12, and the first terminal of the thirteenth switch M13 are all connected to the complementary readout bit line saBlb; the second terminal of the eighth switch M8, the control terminal of the seventh switch M7, the first terminal of the tenth switch M10, and the first terminal of the eleventh switch M11 are all connected to the complementary readout bit line saBlb. The second terminal of the fourteenth switch M14 is connected to the readout bit line saBla; the second terminal of the eleventh switch M11, the second terminal of the thirteenth switch M13, and the control terminal of the ninth switch M9 are all connected to the bit line Bla; the first terminal of the twelfth switch M12, the first terminal of the fourteenth switch M14, and the control terminal of the tenth switch M10 are all connected to the complementary bit line Blb; the control terminals of the eleventh switch M11 and the twelfth switch M12 are used to receive the isolation control signal Iso; the control terminals of the thirteenth switch M13 and the fourteenth switch M14 are used to receive the bias cancellation enable signal NcEn. Additionally, in Figure 11 In this circuit, the ninth switch M9, the tenth switch M10, the eleventh switch M11, the twelfth switch M12, the thirteenth switch M13, and the fourteenth switch M14 can be NMOS transistors, while the seventh switch M7 and the eighth switch M8 can be PMOS transistors.

[0116] Taking DRAM as an example, the sensitive amplifier circuit 30 is connected to the target memory cell via a bit line and to the complementary memory cell via a complementary bit line. Initially, the potentials on the bit line and the complementary bit line are the same. After the target memory cell on the bit line is turned on, it shares charge with the bit line, causing the potential on the bit line to rise or fall; the complementary memory cell on the complementary bit line is always off, so the potential on the complementary bit line remains unchanged. Due to the rise and fall of the potential on the bit line, the voltage difference between the bit line and the complementary bit line changes, causing some devices in the sensitive amplifier circuit 30 to conduct and perform signal amplification. At this time, the signal received by the sensitive amplifier circuit 30 from the bit line can be considered as the signal to be processed, and the signal received by the sensitive amplifier circuit 30 from the complementary bit line can be considered as the reference signal to be processed. Thus, during the signal amplification stage, when the eleventh switch M11 and the twelfth switch M12 are turned on according to the isolation control signal Iso, the transmission speed of the signal to be processed between the target memory cell and the amplification module can be accelerated, thereby quickly raising or lowering the potential of the bit line or the complementary bit line, improving the signal amplification speed.

[0117] In some embodiments, for the precharge module 212, in Figure 11 Based on the sensitive amplifier circuit 30 shown, referring to 12, the precharge module 212 may include a precharge switch transistor M15, wherein:

[0118] The first terminal of the precharge switch M15 is connected to the precharge power supply VAD2. The control terminal of the precharge switch M15 is used to receive the precharge drive signal PreEQ. The second terminal of the precharge switch M15 is connected to the readout bit line saBla.

[0119] Furthermore, such as Figure 12 As shown, the precharge drive module 211 may include a precharge inverter I7, wherein:

[0120] The input terminal of the precharge inverter I7 is used to receive the precharge enable signal eqN, the control terminal of the precharge inverter I7 is connected to the first power supply Vdleq, and the output terminal of the precharge inverter I7 is used to output the precharge drive signal PreEQ.

[0121] It should be noted that, in this embodiment of the disclosure, the precharge drive signal PreEQ output by the precharge drive module 211 can control the precharge module 212 to perform precharge processing on the sensitive amplifier circuit 30, thereby enabling the voltage on the read bit line saBla to be precharged to a preset value.

[0122] In other embodiments, for the precharge module 212, in Figure 11 Based on the sensitive amplifier circuit 30 shown, and referring to 13, the precharge module 212 may include a precharge switch transistor M16, wherein:

[0123] The first terminal of the precharge switch M16 is connected to the read bit line saBla. The control terminal of the precharge switch M16 is used to receive the precharge drive signal EQ. The second terminal of the precharge switch M16 is connected to the complementary read bit line saBlb.

[0124] Furthermore, such as Figure 13 As shown, the precharge drive module 211 may include a precharge inverter I8, wherein:

[0125] The input terminal of the precharge inverter I8 is used to receive the precharge enable signal eqN, the control terminal of the precharge inverter I8 is connected to the first power supply Vdleq, and the output terminal of the precharge inverter I8 is used to output the precharge drive signal EQ.

[0126] It should be noted that, in this embodiment of the present disclosure, the precharge drive signal EQ output by the precharge drive module 211 can control the precharge module 212 to perform precharge processing on the sensitive amplifier circuit 30, thereby enabling voltage balancing between the readout bit line saBla and the complementary readout bit line saBlb.

[0127] In addition, whether Figure 12The precharge driver module 211 and precharge module 212 in the middle are still Figure 13 The pre-charge drive module 211 and pre-charge module 212 in the system have different power supplies, namely the first power supply Vdleq and the third, fourth, fifth, and sixth operating power supplies Vnocp, Vpcsg, Vnoc, and Vncsgh. This allows them to isolate power supply noise at different stages and suppress power supply noise. It should be noted that different power supplies refer to different external sources for the power supply signals, not necessarily different voltage values.

[0128] In some other implementations, for the sensitive amplifier circuit 30, Figure 12 The precharge drive module 211 and precharge module 212 in the middle and Figure 13 The precharge drive module 211 and the precharge module 212 can coexist. Figure 12 The precharge drive module 211 and precharge module 212 are used to precharge the voltage on the read bit line saBla to a preset value, while Figure 13 The precharge drive module 211 and precharge module 212 are used to achieve voltage balancing between the read bit line saBla and the complementary read bit line saBlb.

[0129] In summary, this disclosure provides a control circuit 20 connected to a sensitive amplifier circuit, comprising a pre-charge control module and a power control module. The pre-charge control module includes a pre-charge drive module and a pre-charge module, with the pre-charge drive module connected to a first power supply. The power control module includes a power drive module and a reference power supply module, with the power drive module connected to a second power supply, and the first and second power supplies are different. Because the pre-charge drive module and the power drive module use different power supplies, power supply noise at different stages can be isolated, effectively improving SA noise suppression and read / write speed. This optimizes the signal amplification process of the sensitive amplifier circuit, thereby improving the performance of the sensitive amplifier.

[0130] In another embodiment of this disclosure, the control circuit 20 described in the foregoing embodiments is applied to a sensitive amplifier. See also Figure 14 This illustration shows a schematic diagram of an application scenario for a sensitive amplifier provided in an embodiment of this disclosure. For example... Figure 14 As shown, in this application scenario, there are bit line Bla, complementary bit line Blb, readout bit line saBla, complementary readout bit line saBlb, and a sensitive amplifier 51. A first storage cell 52 is provided on bit line Bla, and a second storage cell 53 is provided on complementary bit line Blb. Here, both the first storage cell 52 and the second storage cell 53 can each serve as the object of a preset instruction.

[0131] In addition, the sensitive amplifier 51 may include a pull-up power supply control circuit 511, a pull-down power supply control circuit 512, a sensitive amplifier circuit 513, and a precharge control circuit 514. The pull-up power supply control circuit 511 includes a first pull-up inverter I1, a second pull-up inverter I2, a third pull-up inverter I3, a first pull-up switch M1, a second pull-up switch M2, and a third pull-up switch M3; the pull-down power supply control circuit 512 includes a first pull-down inverter I4, a second pull-down inverter I5, a third pull-down inverter I6, a first pull-down switch M4, a second pull-down switch M5, and a third pull-down switch M6; the sensitive amplifier circuit 513 includes a seventh switch M7, an eighth switch M8, a ninth switch M9, a tenth switch M10, an eleventh switch M11, a twelfth switch M12, a thirteenth switch M13, and a fourteenth switch M14; and the precharge control circuit 514 includes a precharge switch M15 and a precharge inverter I7. Here, regarding... Figure 14 For details on the circuit's working principle, please refer to the aforementioned content, which will not be repeated here.

[0132] exist Figure 14 In this circuit, the control terminals of the first pull-up inverter I1, the second pull-up inverter I2, and the third pull-up inverter I3 are all connected to the pull-up drive power supply Vpcsg; the control terminals of the first pull-down inverter I4, the second pull-down inverter I5, and the third pull-down inverter I6 are all connected to the pull-down drive power supply Vncsgh; and the control terminal of the precharge inverter I7 is connected to the precharge drive power supply Vdleq.

[0133] It should be noted that in related technologies, the pre-charge drive power supply Vdleq and the pull-down drive power supply Vncsgh share the same power supply. The SA operates at different stages, resulting in noise, which is detrimental to the sense margin. Furthermore, because the temperature characteristics of the power supply are identical at different stages, the sensitive amplifier lacks flexibility. However, in the embodiments of this disclosure, for Figure 14 For the sensitive amplifier shown, the precharge drive power supply Vdleq and the pull-down drive power supply Vncsgh use different power supplies, and the precharge drive power supply Vdleq and the pull-up drive power supply Vpcsg also use different power supplies, thereby isolating power bus noise at different stages (such as the OC stage and the Develop stage).

[0134] exist Figure 14 Based on this, see Figure 15 This illustrates a signal timing diagram of a sensitive amplifier provided in an embodiment of the present disclosure. Figure 15As shown, Iso refers to the aforementioned isolation control signal, which can be a first voltage value and a second voltage value; PreEQ refers to the aforementioned precharge drive signal; NcEn refers to the aforementioned bias cancellation enable signal (also represented by Nc, or called noise cancellation signal); SanEn refers to the aforementioned pull-down power supply drive signals (Pdn1, Pdn2, Pdn3, etc.); SapEn refers to the aforementioned pull-up power supply drive signals (Pup1, Pup2, Pup3, etc.); WL refers to the word line enable signal. When WL is in the second level state, the word line where the target memory cell is located is enabled. When WL is in the first level state, the word line containing the target memory cell is closed, thus the target memory cell and the bit line are not connected. PCS / NCS refers to the first reference voltage signal / second reference voltage signal. The first reference voltage signal has a fourth voltage value and a fifth voltage value, and the second reference voltage signal has a fourth voltage value and a sixth voltage value, with the fourth voltage value being between the fifth and sixth voltage values. Bla refers to the bit line, Blb refers to the complementary bit line, saBla refers to the read bit line, and saBlb refers to the complementary read bit line. The first level state represents a low level state, and the second level state represents a high level state.

[0135] like Figure 15 As shown, when the amplifier circuit is in the idle phase, the isolation control signal Iso maintains the second voltage value, the precharge drive signal PreEQ and the bias cancellation enable signal NcEn are in the second level state, the pull-down power supply drive signal SanEn and the pull-up power supply drive signal SapEn are both in the first level state, the word line enable signal WL is in the first level state, the first reference voltage signal PCS and the second reference voltage signal NCS maintain the fourth voltage value, and the bit line Bla and the complementary bit line Blb are both in the fourth voltage value; at this time, preparations are made for executing the user's operation instructions. It should be noted that due to process deviations and other reasons, the performance of the ninth switch M9 and the tenth switch M10 is different, resulting in a voltage difference dVt between the read bit line saBla and the complementary read bit line saBlb. In order to balance the voltage on both sides, after the precharge phase, the bias cancellation phase needs to be entered. Ideally, dVt should approach zero as much as possible.

[0136] Specifically, assuming the target memory cell is the first memory cell 52, after the user sends a read command for the target memory cell, the sensitive amplifier circuit 513 enters the bias elimination stage from the standby stage. At this time, the isolation control signal Iso is adjusted from the second voltage value to the first voltage value, the precharge drive signal PreEQ is adjusted from the second level state to the first level state, and the pull-down power drive signal SanEn / pull-up power drive signal SapEn are both adjusted from the first level state to the second level state. Therefore, the first reference voltage signal PCS changes from the fourth voltage value to the fifth voltage value, and the second reference voltage signal NCS changes from the fourth voltage value to the sixth voltage value, while the bias elimination enable signal NcEn remains at the second level state, thereby performing bias elimination processing on the sensitive amplifier circuit 513. Afterwards, the pull-down power drive signal SanEn / pull-up power drive signal SapEn switches to the first level state, and the first reference voltage signal PCS and the second reference voltage signal NCS continue to be powered by the precharge control circuit 514 to recover to the fourth voltage value.

[0137] After the bias cancellation phase ends, when the word line enable signal WL changes to the second level, the word line containing the target memory cell is turned on, thus the sensitive amplifier circuit 513 enters the word line enable phase, specifically the first charge sharing (CS) phase, at which time the target memory cell (e.g., the first memory cell 52) is read. Figure 15 As shown, taking the data stored in the first storage cell 52 as "0" as an example, after the first charge sharing phase ends, the voltage of bit line Bla decreases, thus generating the signal to be processed, while the complementary bit line Blb forms the reference signal to be processed. Furthermore, during the first charge sharing phase, the isolation control signal Iso maintains the first voltage value, preventing bit line Bla from connecting with the read bit line saBla, and preventing the complementary bit line Blb from connecting with the complementary read bit line saBlb. The precharge drive signal PreEQ, the bias cancellation enable signal NcEn, and the pull-down power drive signal SanEn / pull-up power drive signal SapEn are all in the first level state.

[0138] After the first charge sharing phase ends, the sensitive amplifier circuit 513 enters the second charge sharing phase. In the second charge sharing phase, the isolation control signal Iso maintains the second voltage value, connecting bit line Bla to the read bit line saBla, and bit line Blb to saBlb. This allows the sensitive amplifier circuit 513 to receive the signal to be processed and the reference signal to be processed into its internal node, reducing the voltage of the read bit line saBla. This can be considered as charge sharing between bit line Bla / complementary bit line Blb and read bit line saBla / complementary read bit line saBlb. Furthermore, all signals except the isolation control signal Iso maintain the voltage values ​​from the previous phase.

[0139] After the second charge sharing phase ends, the sensitive amplifier circuit 513 enters the amplification phase. The pull-down power supply drive signal SanEn and the pull-up power supply drive signal SapEn are adjusted from the first level state to the second level state, thereby changing the first reference voltage signal PCS from the fourth voltage value to the fifth voltage value and the second reference voltage signal NCS from the fourth voltage value to the sixth voltage value. The voltage of the readout bit line saBla decreases, causing the seventh switch M7 to turn on. The first reference voltage signal PCS pulls up the voltage of the complementary readout bit line saBlb, causing the tenth switch M10 to turn on. The second reference voltage signal NCS pulls down the voltage of the readout bit line saBla. Thus, the sensitive amplifier circuit 513 can amplify the signal to be processed (the signal of bit line Bla) and the reference signal to be processed (the signal of complementary bit line Bla) according to the first reference voltage signal PCS and the second reference voltage signal NCS. The isolation control signal Iso still maintains the second voltage value to complete the signal amplification on the signal to be processed (the signal of bit line Bla) and the reference signal to be processed (the signal of complementary bit line Bla).

[0140] Additionally, if the data stored in the first storage cell 52 is "1", the voltage of the bit line Bla in the first amplification stage will be pulled up. Since the isolation control signal Iso is at the second voltage value, it can suppress the rise rate on the bit line Bla / complementary bit line Blb and reduce the noise on the bit line Bla / complementary bit line Blb. However, the signal on the readout bit line saBla / complementary readout bit line saBlb inside the sensitive amplification circuit 513 can quickly reach the high reference potential / low reference potential.

[0141] After the amplification phase ends, when the word line enable signal WL changes to the first level, the word line where the target memory cell is located is adjusted to the off state. At this time, the sensitive amplifier circuit 513 enters the word line off phase. Meanwhile, the isolation control signal Iso maintains the second voltage value, and the precharge drive signal PreEQ and the bias cancellation enable signal NcEn maintain the first level. In addition, during this phase, the pull-down power drive signal SanEn and the pull-up power drive signal SapEn will be adjusted from the second level to the first level.

[0142] Furthermore, the sensitive amplifier circuit 513 enters the pre-charge stage, and the pre-charge drive signal PreEQ and the bias cancellation enable signal NcEn are adjusted to the second level state. At this time, the first reference voltage signal PCS / second reference voltage signal NCS will be restored to the fourth voltage value, and the bit line Bla / complementary bit line Blab and the readout bit line saBla / complementary readout bit line saBlb will be restored to the same voltage value.

[0143] After the pre-charge phase ends, the sensitive amplifier circuit 513 enters the idle phase again to prepare for the next operation.

[0144] In this embodiment of the disclosure, for the precharge drive signal PreEQ and the bias cancellation enable signal NcEn, when they are in the second level state, their corresponding voltage values ​​can be provided by the precharge drive power supply Vdleq; for the pull-up power drive signal SapEn, when it is in the second level state, its corresponding voltage value can be provided by the pull-up drive power supply Vpcsg (specifically the third working power supply vnocp and the fourth working power supply vpcsg); for the pull-down power drive signal SanEn, when it is in the second level state, its corresponding voltage value can be provided by the pull-down drive power supply Vncsgh (specifically the fifth working power supply vnoc and the sixth working power supply vncsgh); for the first reference voltage signal PCS / second reference voltage signal NCS, bit line Bla / complementary bit line Blab, their lowest value is the ground signal, which can be provided by the pull-down reference power supply VSS.

[0145] In summary, the specific implementation of the aforementioned embodiments has been described in detail based on the above embodiments. It can be seen that, according to the technical solution of the aforementioned embodiments, since the precharge control circuit 514 and the pull-up power control circuit 511 / pull-down power control circuit 512 use different power supplies, power supply noise at different stages can be isolated, thereby effectively improving SA noise suppression and read / write speed. This can optimize the signal amplification process of the sensitive amplifier circuit and thus improve the performance of the sensitive amplifier.

[0146] In some embodiments, see Figure 16 This illustration shows a schematic diagram of the structural composition of a semiconductor memory provided in an embodiment of this disclosure. Figure 16 As shown, the semiconductor memory includes a control circuit, multiple memory blocks, and a sensitive amplification circuit module disposed between two adjacent memory blocks. A switching module is disposed between two adjacent sensitive amplification modules. The control circuit includes a pre-charge control module and a power control module. The sensitive amplification module memory block includes a sensitive amplification circuit and a pre-charge control module. The switching module includes a power control module.

[0147] The precharge control module may include a precharge drive module and a precharge module, and the precharge drive module is connected to the first power supply. It is used to provide a precharge drive signal to the precharge module through the precharge drive module, and control the precharge module to perform precharge processing for the sensitive amplifier circuit according to the precharge drive signal.

[0148] The power control module may include a power drive module and a reference power supply module, and the power drive module is connected to the second power supply. It is used to provide a power drive signal to the reference power supply module through the power drive module, and control the reference power supply module to provide a reference voltage to the sensitive amplifier circuit according to the power drive signal; wherein, the first power supply and the second power supply are different.

[0149] Taking four storage blocks as an example, according to Figure 16 As can be seen, in the first direction, a sensitive amplification module, including a sensitive amplification circuit, a pre-charge module, and a pre-charge drive module, is arranged between adjacent memory blocks; in the second direction, a line decoder is arranged between adjacent memory blocks, and a switching module is also arranged between adjacent sensitive amplification modules, with the switching module located between adjacent line decoders. Here, a memory block can be multiple memory sections divided in the first direction of a memory bank, i.e., each memory block is a memory section.

[0150] In some embodiments, the semiconductor memory may further include the power switch module and the power switch control module described in the foregoing embodiments, wherein: the power switch module and the power switch control module are both located in the switch module; or, the power switch module is located in the switch module, and the power switch control module is located in the peripheral area of ​​the semiconductor memory; or, both the power switch module and the power switch control module are located in the peripheral area of ​​the semiconductor memory. By placing the power switch module and the power switch control module in the peripheral area, it is possible to merge the power switch modules and power switch control modules corresponding to multiple memory blocks in the same memory bank, or even multiple memory banks in the same memory bank, to perform overall control, thereby saving chip area and increasing the number of chips per wafer (Die Per Wafer, DPW).

[0151] It is understood that the aforementioned overall control refers to the use of a single power switch control module to control power switch modules corresponding to multiple memory blocks or multiple memory cells, thereby reducing the number of power switch control modules, and the use of a single power switch module to control the power conduction of multiple memory blocks or multiple memory cells. Furthermore, when the power switch module is located in the peripheral area, the corresponding power supply is generated in the peripheral area.

[0152] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure.

[0153] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0154] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0155] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0156] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0157] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0158] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A control circuit, characterized in that, The control circuit is connected to the sensitive amplification circuit, and the control circuit includes a pre-charge control module and a power control module, wherein: The precharge control module includes a precharge drive module and a precharge module, and the precharge drive module is connected to the first power supply. It is used to provide a precharge drive signal to the precharge module through the precharge drive module. The precharge drive signal is used to control the precharge module to perform precharge processing on the sensitive amplifier circuit. The power control module includes a power drive module and a reference power module, and the power drive module is connected to a second power source. It is used to provide a power drive signal to the reference power module through the power drive module, and control the reference power module to provide a reference voltage to the sensitive amplifier circuit according to the power drive signal; wherein, the first power source and the second power source are different.

2. The control circuit according to claim 1, characterized in that, The control circuit further includes a power switch module, and the power switch module is connected to a third power source, wherein: The power switch module is used to receive a power enable signal and control the state of the switch tube inside the power switch module according to the power enable signal, so as to provide the second power to the power drive module through the third power supply, wherein the first power supply is different from the third power supply.

3. The control circuit according to claim 2, characterized in that, The third power supply includes a first working power supply and a second working power supply. The first working power supply and the second working power supply are in different voltage domains and / or have different temperature characteristics. The power enable signal includes a first power enable sub-signal and a second power enable sub-signal. The power switch module includes a first switch transistor and a second switch transistor; wherein, a first end of the first switch transistor is connected to the first operating power supply, and a control end of the first switch transistor is connected to the first power enable sub-signal; a first end of the second switch transistor is connected to the second operating power supply, and a control end of the second switch transistor is connected to the second power enable sub-signal; a second end of the first switch transistor is connected to a second end of the second switch transistor; and one of the first switch transistor and the second switch transistor is selectively turned on to provide the second power supply to the power drive module.

4. The control circuit according to claim 3, characterized in that, When the sensitive amplifier circuit is operating in the bias elimination stage, the first switch is turned on to provide the second power supply to the power drive module through the first operating power supply; When the sensitive amplifier circuit is operating in the signal amplification stage, the second switch is turned on to provide the second power supply to the power drive module through the second operating power supply.

5. The control circuit according to claim 3, characterized in that, The power switch module includes at least one of the following: a pull-up power switch module and a pull-down power switch module; The pull-up power switch module includes a first switch transistor and a second switch transistor that are PMOS transistors, and the pull-down power switch module includes a first switch transistor and a second switch transistor that are NMOS transistors. The first working power supply connected to the pull-up power switch module is different from the first working power supply connected to the pull-down power switch module, and the second working power supply connected to the pull-up power switch module is different from the second working power supply connected to the pull-down power switch module.

6. The control circuit according to claim 5, characterized in that, When the number of power switch modules is at least one, the control circuit further includes a power switch control module, wherein: The power switch control module is used to receive a bias cancellation enable signal and a target power enable signal, and generate at least one set of power enable signals based on the bias cancellation enable signal and the target power enable signal; wherein each set of power enable signals includes a first power enable sub-signal and a second power enable sub-signal, and at least one set of power enable signals corresponds to at least one power switch module.

7. The control circuit according to claim 6, characterized in that, The target power enable signal includes a first target power enable signal and a second target power enable signal, and the power switch control module includes a first logic control module and a second logic control module, wherein: The first logic control module is used to receive the bias cancellation enable signal and the second target power enable signal, and output at least one first power enable sub-signal; The second logic control module is used to receive the bias cancellation enable signal and the first target power enable signal, and output at least one second power enable sub-signal; Wherein, the first target power enable signal and the first power enable sub-signal have the same valid state, and the second target power enable signal and the second power enable sub-signal have the same valid state.

8. The control circuit according to claim 7, characterized in that, The first logic control module includes a first NOT gate, a first NAND gate, a first level conversion module, and a second NOT gate, wherein: The input terminal of the first NOT gate is used to receive the second target power enable signal. The output terminal of the first NOT gate is connected to the first input terminal of the first NAND gate. The second input terminal of the first NAND gate is used to receive the bias cancellation enable signal. The output terminal of the first NAND gate is connected to the input terminal of the first level conversion module. The output terminal of the first level conversion module is connected to the input terminal of the second NOT gate. The output terminal of the second NOT gate is used to output at least one of the first power enable sub-signals. The second logic control module includes a first NOR gate, a third NOT gate, a second level conversion module, and a fourth NOT gate, wherein: The first input terminal of the first NOR gate is used to receive the bias cancellation enable signal, the second input terminal of the first NOR gate is used to receive the first target power enable signal, the output terminal of the first NOR gate is connected to the input terminal of the third NOT gate, the output terminal of the third NOT gate is connected to the input terminal of the second level conversion module, the output terminal of the second level conversion module is connected to the input terminal of the fourth NOT gate, and the output terminal of the fourth NOT gate is used to output at least one second power enable sub-signal.

9. The control circuit according to claim 7, characterized in that, The power switch control module further includes a fifth NOT gate, wherein: The input terminal of the fifth NOT gate is used to receive the bias cancellation inverted signal, and the output terminal of the fifth NOT gate is used to output the bias cancellation enable signal.

10. The control circuit according to claim 1, characterized in that, The precharge module includes a precharge switch transistor, wherein: The first end of the precharge switch is connected to the precharge power supply, the control end of the precharge switch is used to receive the precharge drive signal, and the second end of the precharge switch is connected to the readout bit line.

11. The control circuit according to claim 1, characterized in that, The precharge module includes a precharge switch transistor, wherein: The first end of the precharge switch is connected to the readout bit line, the control end of the precharge switch is used to receive the precharge drive signal, and the second end of the precharge switch is connected to the complementary readout bit line.

12. The control circuit according to claim 10 or 11, characterized in that, The precharge drive module includes a precharge inverter, wherein: The input terminal of the precharge inverter is used to receive the precharge enable signal, the control terminal of the precharge inverter is connected to the first power supply, and the output terminal of the precharge inverter is used to output the precharge drive signal.

13. A semiconductor memory, characterized in that, The semiconductor memory includes a control circuit, multiple memory blocks, and a sensitive amplification module disposed between two adjacent memory blocks. A switching module is disposed between two adjacent sensitive amplification modules. The control circuit includes a pre-charge control module and a power control module. The sensitive amplification module includes a sensitive amplification circuit and the pre-charge control module. The switching module includes the power control module, wherein: The precharge control module includes a precharge drive module and a precharge module, and the precharge drive module is connected to the first power supply. It is used to provide a precharge drive signal to the precharge module through the precharge drive module, and control the precharge module to perform precharge processing on the sensitive amplifier circuit according to the precharge drive signal. The power control module includes a power drive module and a reference power module, and the power drive module is connected to a second power source. It is used to provide a power drive signal to the reference power module through the power drive module, and control the reference power module to provide a reference voltage to the sensitive amplifier circuit according to the power drive signal; wherein, the first power source and the second power source are different.

14. The semiconductor memory according to claim 13, characterized in that, The semiconductor memory further includes the power switch module as described in claim 2 and the power switch control module as described in claim 6, wherein: Both the power switch module and the power switch control module are located within the switch module; or... The power switch module is located within the switch module, and the power switch control module is located in the peripheral area of ​​the semiconductor memory; or, Both the power switch module and the power switch control module are located in the peripheral area of ​​the semiconductor memory.

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