A method for manufacturing a 2.5D packaging structure

Abstract

The application provides a preparation method of a 2.5D packaging structure. After the preparation of the pads on the first surface of the semiconductor substrate is completed, the flip chip is directly flipped on the pads, and the plastic encapsulating material layer is formed. The supporting substrate is provided and bonded to the plastic encapsulating material layer. The semiconductor substrate is turned over and thinned. After the metal bump array is prepared on the first surface of the semiconductor substrate, the supporting substrate is removed. The preparation of the whole 2.5D packaging structure only needs one supporting substrate, and the bonding and removal of the supporting substrate are only performed once. Thus, the use of one supporting substrate is reduced, the production cost is saved, the bonding and removal process of the supporting substrate is reduced once, the production time and production materials are saved, the production cost is reduced, and the production efficiency is improved. In addition, the distance between the top end of the plastic encapsulating material layer and the top end of the chip is greater than 100 μm, the chip is completely covered, the chip is protected from adverse effects, and the reliability and yield of the packaging structure are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor fabrication, and in particular to a method for fabricating a 2.5D packaging structure. Background Technology

[0002] With the ever-increasing performance requirements of high-performance computing (HPC) chips such as CPUs, GPUs, and FPGAs, traditional packaging technologies such as flip-chip (FC) and point-of-purchase (POP) packaging can no longer meet the demands, leading to a growing need for 2.5D / 3D packaging technologies. Currently, TSMC's CoWoS is a well-known 2.5D packaging technology that can package multiple chips together, achieving small package size, low power consumption, and fewer pins.

[0003] Currently, the fabrication of 2.5D packaging structures typically involves first preparing the front-side pads of the substrate, then bonding the pads to a first supporting substrate, and finally preparing a metal bump array on the back side of the substrate. The prepared metal bump array is then bonded to a second supporting substrate. The first supporting substrate is removed, and the chip is flip-chip bonded and molded. Finally, the second supporting substrate is removed to complete the 2.5D packaging structure. A single 2.5D packaging structure requires two supporting substrates and undergoes two bonding and removal processes, resulting in high production costs and wasted processing time and materials due to the bonding and removal of the supporting substrates. This invention aims to optimize the process flow, reducing the use of one supporting substrate and saving the bonding and removal time of one supporting substrate, thereby lowering production costs and improving production efficiency. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for preparing a 2.5D packaging structure to solve the problem of resource waste faced by the prior art in 2.5D packaging.

[0005] To achieve the above and other related objectives, the present invention provides a method for fabricating a 2.5D packaging structure, the method comprising the following steps:

[0006] S1. A semiconductor substrate is provided, the semiconductor substrate including a first surface and a second surface disposed opposite to each other, and a TSV conductive pillar is formed in the semiconductor substrate, the TSV conductive pillar including a first end of the TSV conductive pillar exposed on the first surface and a second end of the TSV conductive pillar located in the semiconductor substrate.

[0007] S2. A first dielectric layer is formed on the first surface, the first dielectric layer is etched to expose the first end of the TSV conductive pillar, and a pad electrically connected to the first end of the TSV conductive pillar is formed on the first dielectric layer.

[0008] S3. Provide a chip, flip-chip onto the pad, and electrically connect the chip to the pad;

[0009] S4. A molding compound layer is formed on the first dielectric layer, the molding compound layer covering the chip and the first dielectric layer;

[0010] S5. Provide a support substrate and bond the support substrate to the molding compound layer;

[0011] S6. Thin the semiconductor substrate to expose the second end of the TSV conductive pillar;

[0012] S7. A second dielectric layer is formed on the second surface of the semiconductor substrate, the second dielectric layer is etched to expose the second end of the TSV conductive pillar, and a metal bump array is formed on the second dielectric layer, wherein the metal bump array is electrically connected to the second end of the TSV conductive pillar.

[0013] S8. Remove the supporting substrate;

[0014] Preferably, before forming a molding compound layer on the first dielectric layer, the method further includes the step of filling the gap between the chip and the first dielectric layer with an underfill adhesive.

[0015] Preferably, after forming the molding compound layer, the process further includes a planarization process for the molding compound layer.

[0016] Preferably, the distance D between the top of the molding compound layer and the top of the chip is greater than 100 μm.

[0017] Preferably, the formed TSV conductive pillar, the pad, and the metal bump are located on the same vertical line.

[0018] Preferably, the method for forming the TSV conductive pillar includes one or a combination of laser drilling, mechanical drilling, deep reactive ion etching, and photo-assisted electrochemical etching.

[0019] Preferably, the active surface of the chip is provided with metal microbumps, which make electrical contact with the pads.

[0020] Preferably, the chip is one or a combination of a bare chip or a packaged chip, and the number of the chips is N, where N≥2.

[0021] Preferably, after removing the support substrate, the process further includes the steps of applying a film and wafer dicing.

[0022] Preferably, the film used in the film application step includes any one of blue film, UV film, and DFA film.

[0023] As described above, the method for fabricating a 2.5D packaging structure according to the present invention has the following beneficial effects: After completing the preparation of the pads on the first surface of the semiconductor substrate, the chip is flip-chip bonded and a molding compound layer is formed directly on the pads. A support substrate is provided and bonded to the molding compound layer. The semiconductor substrate is flipped and thinned. After a metal bump array is prepared on the first surface of the semiconductor substrate, the support substrate is removed. The entire fabrication of the 2.5D packaging structure requires only one support substrate and only one bonding and removal process. This reduces the use of one support substrate, thereby saving production costs. It also reduces the bonding and removal process of the support substrate, saving production time and materials, reducing production costs, and improving production efficiency.

[0024] In addition, the distance between the top of the molding compound layer and the top of the chip is greater than 100μm, completely covering the chip, protecting the chip from adverse effects, and improving the reliability of the packaging structure and the yield. Attached Figure Description

[0025] Figure 1 The diagram shown is a flowchart of a method for fabricating a 2.5D packaging structure according to an embodiment of the present invention.

[0026] Figure 2 Displayed as Figure 1 A schematic diagram of the structure presented in step S1.

[0027] Figure 3 Displayed as Figure 1 A schematic diagram of the structure presented in step S2.

[0028] Figure 4 Displayed as Figure 1 A schematic diagram of the structure presented in step S3.

[0029] Figure 5 Displayed as Figure 1 A schematic diagram of the structure presented in step S4.

[0030] Figure 6 Displayed as Figure 1 The structural diagrams presented in steps S5 and S6.

[0031] Figure 7 Displayed as Figure 1 A schematic diagram of the structure presented in step S7.

[0032] Figure 8 The diagram shown is a schematic diagram of a film-coated structure for a 2.5D packaging structure according to an embodiment of the present invention.

[0033] Label Explanation

[0034] 100: Semiconductor substrate, 110: TSV conductive pillar, 120: First dielectric layer, 130: Pad, 140: Second dielectric layer, 200: Chip, 210: Metal microbump, 220: Underfill adhesive, 230: Molding material layer, 300: Support substrate, 400: Metal bump array, 500: Blue film, S1~S8: Steps. Detailed Implementation

[0035] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0036] like Figures 1-8 In detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure will be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0037] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0038] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0039] like Figure 1 As shown, the present invention provides a method for fabricating a 2.5D packaging structure, which includes the following steps:

[0040] S1. A semiconductor substrate 100 is provided, the semiconductor substrate 100 includes a first surface and a second surface disposed opposite to each other, and a TSV conductive pillar 110 is formed in the semiconductor substrate 100, the TSV conductive pillar 110 includes a first end of the TSV conductive pillar 110 exposed on the first surface and a second end of the TSV conductive pillar 110 located in the semiconductor substrate 100.

[0041] S2. A first dielectric layer 120 is formed on the first surface, the first dielectric layer 120 is etched to expose the first end of the TSV conductive pillar 110, and a pad 130 electrically connected to the first end of the TSV conductive pillar 110 is formed on the first dielectric layer 120.

[0042] S3. Provide chip 200, flip-chip 200 onto pad 130, and electrically connect chip 200 to pad 130;

[0043] S4. A molding compound layer 230 is formed on the first dielectric layer 120, the molding compound layer 230 covering the chip 200 and the first dielectric layer 120;

[0044] S5. Provide a support substrate 300 and bond the support substrate 300 to the molding compound layer 230;

[0045] S6. Thin the semiconductor substrate 100 to expose the second end of the TSV conductive pillar 110;

[0046] S7. A second dielectric layer 140 is formed on the second surface of the semiconductor substrate 100, the second dielectric layer 140 is etched to expose the second end of the TSV conductive pillar 110, and a metal bump array 400 is formed on the second dielectric layer 140, wherein the metal bump array 400 is electrically connected to the second end of the TSV conductive pillar 110.

[0047] S8. Remove the support substrate 300;

[0048] like Figure 1 Step S1 in the middle and Figure 2 As shown, a semiconductor substrate 100 is provided. The semiconductor substrate 100 includes a first surface and a second surface disposed opposite to each other. A TSV hole is formed from the first surface of the semiconductor substrate 100 into the semiconductor substrate 100. A conductive material is filled into the TSV hole to form a TSV conductive pillar 110. The TSV conductive pillar 110 includes a first end and a second end. The first end of the TSV conductive pillar 110 is exposed on the first surface of the semiconductor substrate 100, and the second end of the TSV conductive pillar 110 is located in the semiconductor substrate 100.

[0049] Specifically, the semiconductor substrate 100 includes, but is not limited to, semiconductor substrates such as silicon substrates, silicon-germanium substrates, or gallium nitride substrates. No particular limitation is made here, and the substrate may be selected as needed. TSV holes are formed on the first surface of the semiconductor substrate 100. The method for forming the TSV holes includes one or a combination of laser drilling, mechanical drilling, deep reactive ion etching, and photo-assisted electrochemical etching. The TSV holes are filled with conductive material to form TSV conductive pillars 110. The conductive material is one or a combination of copper, aluminum, gold, silver, nickel, titanium, tantalum, etc., and the filling method is any one or a combination of electroplating, electroless plating, screen printing, and wire bonding. At the same time, in order to prevent the conductive material from diffusing into the semiconductor substrate, a layer of one or a combination of Ta, TaN, Ti, and TiN may be deposited first as a diffusion barrier layer or adhesion layer.

[0050] like Figure 1 S2 step and Figure 3 As shown, a first dielectric layer 120 is formed on the first surface, the first dielectric layer 120 is etched to expose the first end of the TSV conductive pillar 110, and a pad 130 electrically connected to the first end of the TSV conductive pillar 110 is formed on the first dielectric layer 120.

[0051] Specifically, the first dielectric layer 120 includes epoxy resin, silicone, PI, silicon oxide, etc. In this embodiment, the first dielectric layer 120 is made of PI. The first dielectric layer 120 is etched to expose the first end of the TSV conductive pillar 110 at the opening of the first dielectric layer 120.

[0052] A metal layer is deposited on the first dielectric layer 120 by methods such as electroplating, physical vapor deposition, or chemical vapor deposition. The metal layer can be one or a combination of copper, aluminum, gold, silver, nickel, titanium, tantalum, etc. The metal layer is etched to form a pad 130. The pad 130 is vertically located above the first end of the TSV conductive post 110 and electrically connected to the first end of the TSV conductive post 110. In this embodiment, the pad is manufactured by a copper-nickel-gold electroplating process.

[0053] like Figure 1 S3 step and Figure 4 As shown, a chip 200 is provided, which is flip-chip mounted onto the pad 130 and electrically connected to the pad 130.

[0054] Specifically, the chip 200 includes one or a combination of bare chips and packaged chips, which is set according to actual needs and is not particularly limited here. In this embodiment, the number of chips 200 is shown as 3, but the number of chips 200 is not limited to this. Depending on the requirements, the number of chips 200 can be greater than or equal to 2, such as 2, 4, 5, or more.

[0055] As an example, the active surface of the chip 200 is provided with metal microbumps 210, which are electrically in contact with the pads 130.

[0056] Specifically, a metal microbump 210 is provided on the active surface of the chip 200. The metal microbump 210 is electrically connected to the internal circuit of the chip 200 and makes electrical contact with the pad 130 through the metal microbump 210. The chip 200 is flip-chip mounted on the first surface of the semiconductor substrate 100. The chips 200 can be arranged side by side or staggered on the first surface, depending on the specific needs.

[0057] like Figure 1 S4 step and Figure 5 As shown, a molding compound layer 230 is formed on the first dielectric layer 120, and the molding compound layer 230 covers the chip 200 and the first dielectric layer 120.

[0058] Specifically, the molding compound layer 230 includes, but is not limited to, a polyimide layer, a silicone layer, and an epoxy resin layer. The method for forming the molding compound layer 230 includes one of compression molding, transfer molding, liquid sealing molding, molding underfill, capillary underfill, vacuum lamination, and spin coating. The molding compound layer 230 covers the chip 200 and the first dielectric layer 120.

[0059] As an example, after forming the molding compound layer 230, a planarization process is also included for the molding compound layer 230. In order to improve the flatness of the surface of the molding compound layer 230 and facilitate bonding to the support substrate, the molding compound layer 230 is planarized. The planarization process includes mechanical polishing, chemical mechanical polishing, etc.

[0060] As an example, the distance D between the top of the molding compound layer 230 and the top of the chip 200 is greater than 100 μm. After polishing, the molding compound layer 230 covers the chip 200, and the top of the molding compound layer 230 is at least 100 μm away from the top of the chip 200. This isolates the chip 200 from the outside environment, preventing impurities in the air from corroding the chip circuitry and causing a decline in electrical performance. At the same time, it also protects and fixes the chip 200 from the influence of subsequent process operations such as polishing to thin the semiconductor substrate 100, thereby improving the reliability of the packaging structure and the yield.

[0061] As an example, before forming the molding compound layer 230 on the first dielectric layer 120, the step of filling the gap between the chip 200 and the first dielectric layer 120 with underfill adhesive 220 is included.

[0062] Specifically, to further strengthen the connection between the chip 200 and the semiconductor substrate 100 and enhance the drop resistance of the package structure, before forming the molding compound layer 230, an underfill adhesive 220 with smaller particle size than the molding compound is used to fill the gap between the chip 200 and the first dielectric layer 120 to form an underfill layer. This underfill layer provides better bonding strength and effectively protects the chip 200 from external forces, improving package quality.

[0063] The underfill adhesive 220 includes epoxy resin, but may also be other filler materials with smaller particles. The underfill adhesive 220 is filled by one or more of the following methods: capillary filling, molding filling, dispensing and spin coating.

[0064] like Figure 1 S5 steps and Figure 6 As shown, a support substrate 300 is provided, and the support substrate 300 is bonded to the molding compound layer 230.

[0065] Specifically, the support substrate 300 can be one of a glass substrate, a ceramic substrate, a polymer substrate, and a metal substrate. The support substrate 300 provides a supporting plane for the subsequent packaging structure to prevent problems such as cracking, breakage, and warping of the semiconductor chip during subsequent fabrication. It needs to be removed later. Therefore, in this embodiment, a relatively low-cost glass substrate is used. The glass substrate is bonded to the molding compound layer 230 through an adhesive layer. The adhesive layer includes, but is not limited to, UV adhesive, and is selected according to actual needs. The adhesion strength of the UV adhesive tape will decrease under light of a specific wavelength, making the glass substrate easier to peel off.

[0066] like Figure 1 S6 step and Figure 6 As shown, the semiconductor substrate 100 is thinned to expose the second end of the TSV conductive pillar 110.

[0067] Specifically, the semiconductor substrate 100 is flipped so that the second surface of the semiconductor substrate 100 faces upward, and then the semiconductor substrate 100 is thinned by methods such as chemical mechanical polishing to expose the second end of the TSV conductive pillar 110. The second surface treated by chemical mechanical polishing and other methods has a good flatness, which can improve the bonding strength between interfaces in subsequent packaging, prevent delamination, cracking and other problems in the process, and also reduce the contact resistance between the subsequent metal bump array 400 and the TSV conductive pillar 110.

[0068] like Figure 1 Step S7 in the middle and Figure 7As shown, a second dielectric layer 140 is formed on the second surface of the semiconductor substrate 100, the second dielectric layer 140 is etched to expose the second end of the TSV conductive pillar 110, and a metal bump array 400 is formed on the second dielectric layer 140, the metal bump array 400 being electrically connected to the second end of the TSV conductive pillar 110.

[0069] Specifically, the second dielectric layer 140 includes, but is not limited to, epoxy resin, silicone, PI, and silicon oxide. In this embodiment, the second dielectric layer 140 is made of PI. The second dielectric layer 140 is etched to expose the second end of the TSV conductive post 110 at the opening of the second dielectric layer 140.

[0070] A bottom metal layer is formed on the second dielectric layer 140, completely covering the second dielectric layer 140 and making electrical contact with the second end of the TSV conductive pillar 110 at the opening of the second dielectric layer 140. The bottom metal layer is formed by physical vapor deposition or sputtering. The bottom metal layer includes a diffusion barrier layer and / or a seed layer. The diffusion barrier layer, also called an adhesive layer, includes one or a combination of Ti, TiN, Ta, and TaN. It not only prevents the seed layer from diffusing into the second dielectric layer 140 but also increases the adhesion between them. The seed layer is formed on the diffusion barrier layer and is generally a Cu seed layer, but can also be formed from a Cu alloy.

[0071] A patterned mask layer is formed on the bottom metal layer, with an opening corresponding to the second end of the TSV conductive pillar 110 perpendicularly above it. A metallization layer and a solder layer are deposited in the opening of the mask layer using methods such as electroplating or electroless plating. The metallization layer and the solder layer are in perpendicular electrical contact with the bottom metal layer. Then, the mask layer and the uncovered bottom metal layer are removed by etching methods such as wet etching or dry etching. A bump array is formed on the solder layer using C4 soldering. The metallization layer, the solder layer, and the bump array together constitute a metal bump array 400, which is perpendicularly electrically connected to the second end of the TSV conductive pillar 110 through the bottom metal layer.

[0072] As an example, the formed TSV conductive pillar 110, the pad 130, and the metal bump are located on the same vertical line.

[0073] Specifically, the pad 130 is vertically located above and electrically connected to the first end of the TSV conductive post 110. The metal bump array 400 is vertically electrically connected to the second end of the TSV conductive post 110 through the bottom metal layer. Therefore, the TSV conductive post 110, the pad 130, and the metal bumps are located on the same vertical line, which reduces the resistance between the TSV conductive post 110, the pad 130, and the metal bumps, and also reduces the signal delay between the TSV conductive post 110, the pad 130, and the metal bumps.

[0074] like Figure 1 S8 steps and Figure 8 As shown, the support substrate 300 is removed. In this embodiment, the adhesive layer between the support substrate 300 and the molding material layer 230 is a UV adhesive. The adhesive layer is irradiated with UV light to reduce its stickiness, making it easy to separate the support substrate 300 from the molding material layer 230.

[0075] As an example, after removing the support substrate 300, the process also includes the steps of applying a film and cutting the wafer.

[0076] Specifically, the aforementioned 2.5D packaging structure can be a wafer-level packaging structure to improve production capacity. The diagram can be understood as a chip unit in a wafer-level 2.5D packaging structure. After the above packaging and removal of the support substrate 300, a film is attached to the metal bump array 400 surface in the 2.5D packaging structure, and then it is positioned in a laser cutting device for slicing. The small chips formed after slicing will not scatter, making them easy to handle and store.

[0077] As an example, the film used in the film application step includes any one of Blue Film 500, UV film, and DFA film. UV film is commonly used for LED chips, DFA film is commonly used for ultra-small, ultra-thin chips, and 3D stacked small form factor high-integration packaged chips, while Blue Film 500 is widely used due to its mature and stable product, high cost performance, and large shipment volume. The specific film used depends on actual needs.

[0078] In summary, the fabrication method of the 2.5D packaging structure of the present invention has the following beneficial effects: after completing the preparation of the pads on the first surface of the semiconductor substrate, the chip is flipped and a molding compound layer is formed directly on the pads; a support substrate is provided and bonded to the molding compound layer; the semiconductor substrate is flipped and thinned; a metal bump array is prepared on the first surface of the semiconductor substrate, and then the support substrate is removed. The entire fabrication of the 2.5D packaging structure requires only one support substrate and only one bonding and removal process, thus reducing the use of one support substrate, thereby saving production costs. It also reduces the bonding and removal process of the support substrate, saving production time and materials, lowering production costs, and improving production efficiency.

[0079] In addition, the distance between the top of the molding compound layer and the top of the chip is greater than 100μm, completely covering the chip, protecting the chip from adverse effects, and improving the reliability of the packaging structure and the yield.

[0080] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a 2.5D package structure, characterized in that, The method for fabricating the 2.5D packaging structure includes the following steps: S1. A semiconductor substrate is provided, the semiconductor substrate including a first surface and a second surface disposed opposite to each other, and a TSV conductive pillar is formed in the semiconductor substrate, the TSV conductive pillar including a first end of the TSV conductive pillar exposed on the first surface and a second end of the TSV conductive pillar located in the semiconductor substrate. S2. A first dielectric layer is formed on the first surface, the first dielectric layer is etched to expose the first end of the TSV conductive pillar, and a pad electrically connected to the first end of the TSV conductive pillar is formed on the first dielectric layer. S3. Provide a chip, flip-chip onto the pad, and electrically connect the chip to the pad; S4. A molding compound layer is formed on the first dielectric layer, the molding compound layer covering the chip and the first dielectric layer; S5. Provide a support substrate and bond the support substrate to the molding compound layer; S6. Thin the semiconductor substrate to expose the second end of the TSV conductive pillar; S7. A second dielectric layer is formed on the second surface of the semiconductor substrate, the second dielectric layer is etched to expose the second end of the TSV conductive pillar, and a metal bump array is formed on the second dielectric layer, wherein the metal bump array is electrically connected to the second end of the TSV conductive pillar. S8. Remove the supporting substrate.

2. The method of claim 1, wherein: Before forming a molding compound layer on the first dielectric layer, the method further includes the step of filling the gap between the chip and the first dielectric layer with an underfill adhesive.

3. The method for fabricating the 2.5D packaging structure according to claim 1, characterized in that: After forming the molding compound layer, the process further includes a planarization process for the molding compound layer.

4. The method for fabricating the 2.5D packaging structure according to claim 3, characterized in that: The distance D between the top of the molding compound layer and the top of the chip is greater than 100 μm.

5. The method for fabricating the 2.5D packaging structure according to claim 1, characterized in that: The formed TSV conductive pillars, pads, and metal bumps are located on the same vertical line.

6. The method for fabricating the 2.5D packaging structure according to claim 1, characterized in that: The method for forming the TSV conductive pillar includes one or a combination of laser drilling, mechanical drilling, deep reactive ion etching, and photo-assisted electrochemical etching.

7. The method for fabricating the 2.5D packaging structure according to claim 1, characterized in that: The active surface of the chip has metal microbumps, which make electrical contact with the pads.

8. The method for fabricating the 2.5D packaging structure according to claim 1, characterized in that: The chip is one or a combination of a bare chip or a packaged chip, and the number of the chips is N, where N≥2.

9. The method for fabricating the 2.5D packaging structure according to claim 1, characterized in that: After removing the supporting substrate, the process also includes film application and wafer dicing.

10. The method for fabricating the 2.5D packaging structure according to claim 9, characterized in that: The film used in the film application step includes any one of blue film, UV film, and DFA film.

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