Semiconductor structure and method of manufacturing a semiconductor structure

Abstract

The embodiment of the present disclosure relates to the semiconductor field, and provides a semiconductor structure and a manufacturing method of the semiconductor structure, the semiconductor structure comprising: a bearing structure; a plurality of layers of chip modules stacked alternately on the bearing structure; the chip module comprising a facing area and a non-facing area; the facing areas of all the chip modules are arranged oppositely, and the non-facing areas of two adjacent layers of chip modules are arranged staggeredly; the facing area has a first interface and a second interface; the facing area has two opposite sides, the first interface is located at one of the two opposite sides, and the second interface is located between the two opposite sides; the surface of the facing area has a wiring layer, the wiring layer is electrically connected with the second interface and extends to the other of the two opposite sides; the first interface of the chip module is electrically connected with the wiring layer of the adjacent chip module; and the first interface and the second interface of the bottom chip module are electrically connected with the bearing structure. The embodiment of the present disclosure can at least improve the heat dissipation degree of the semiconductor structure, and further improve the performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure pertains to the field of semiconductors, and specifically relates to a semiconductor structure and a method for manufacturing the semiconductor structure. Background Technology

[0002] Chip stacking technologies, such as High Bandwidth Memory (HBM) and Low Power Double Data Rate (LPDDR), extend the original one-dimensional memory layout to three dimensions. This involves stacking many chips together and packaging them, thereby significantly increasing chip density and achieving large capacity and high bandwidth.

[0003] However, as the number of stacked layers increases, the heat generated by the chip during operation can accumulate, adversely affecting product performance. For example, increased temperature can affect the volume of the semiconductor structure, leading to mechanical cracks in the material; increased temperature can also affect the electrical performance of the chip, making it difficult to achieve the expected function. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and a method for manufacturing the semiconductor structure, which at least helps to improve the heat dissipation of the semiconductor structure, thereby improving the performance of the semiconductor structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, wherein the semiconductor structure includes: a carrier structure; multiple layers of chip modules stacked alternately on the carrier structure, each chip module including at least one chip; each chip module including a front-facing region and a non-front-facing region; the front-facing regions of all the chip modules are arranged facing each other, and the non-front-facing regions of adjacent layers of chip modules are staggered; each front-facing region has a first interface and a second interface; each front-facing region has opposite sides, the first interface being located on one of the opposite sides, and the second interface being located between the opposite sides; the surface of the front-facing region has a wiring layer, the wiring layer being electrically connected to the second interface and extending to the other side of the opposite sides; the first interface of each chip module is electrically connected to the wiring layer of an adjacent chip module; the first interface and the second interface of the bottom layer of chip modules are electrically connected to the carrier structure.

[0006] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for manufacturing a semiconductor structure. The method includes: providing a plurality of chip modules, each chip module including at least one chip; each chip module including a front-facing region and a non-front-facing region; the front-facing region having a first interface and a second interface; the front-facing region having opposite sides, the first interface being located on one of the opposite sides, and the second interface being located between the opposite sides; forming a wiring layer on the surface of the front-facing region, the wiring layer being electrically connected to the second interface and extending to the other of the opposite sides; providing a carrier structure on which the plurality of chip modules are staggered and stacked on the carrier structure, with the front-facing regions of all chip modules facing each other; the non-front-facing regions of adjacent layers of chip modules being staggered; and electrically connecting the first interface of each chip module to the wiring layer of the adjacent chip module; and electrically connecting the first interface and the second interface of the bottom layer of chip modules to the carrier structure.

[0007] The technical solution provided in this disclosure has at least the following advantages: multiple chip modules are stacked in an alternating manner, thereby increasing the distance between non-facing areas, i.e., increasing the heat dissipation space; the facing area of ​​the chip module has a wiring layer, which can improve the heat dissipation speed of the facing area; in addition, the wiring layer can change the layout of the second interface to facilitate signal connection between chips. Attached Figure Description

[0008] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0009] Figure 1 A schematic diagram of an LPDDR product is shown;

[0010] Figure 2 A schematic diagram of an HBM product is shown;

[0011] Figures 3-5 Schematic diagrams of different semiconductor structures provided in one embodiment of this disclosure are shown respectively;

[0012] Figures 6-7 A top view of a different semiconductor structure provided in one embodiment of this disclosure is shown;

[0013] Figures 8-9 A schematic diagram of two chip modules provided in another embodiment of this disclosure is shown. Detailed Implementation

[0014] As is known from the background technology, as the number of stacked layers increases, the heat generated by the chip during operation will accumulate, thus adversely affecting product performance. This will be explained in detail below.

[0015] Figure 1 An LPDDR product is provided. (Reference) Figure 1 Chips 100 are bonded to each other using die-attach film (DAF) or film on wire (FOW). Figure 2 An HBM product is provided, for reference. Figure 2 In HBM, chip 100 is bonded using a non-conductive film (NCF), or molded underfill is applied between chips 100. However, these adhesives and bonding layers have relatively weak heat dissipation capabilities. Furthermore, as the number of stacked layers increases and chips 100 become thinner, the space between chips 100 becomes smaller; this reduced heat dissipation space leads to heat accumulation, which in turn affects the performance of the semiconductor structure.

[0016] This disclosure provides a semiconductor structure in which chip modules are stacked in an interleaved manner to increase the heat dissipation space; the front area of ​​the chip modules has a wiring layer, which can better conduct heat from the chip surface; in addition, the wiring layer can change the layout of the second interface, thereby facilitating the electrical connection between the second interface and the first interface of the adjacent chip to realize signal connection between the chips.

[0017] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0018] like Figures 3-7As shown, one embodiment of this disclosure provides a semiconductor structure, which includes: a carrier structure 4; multilayer chip modules 10 stacked alternately on the carrier structure 4, each chip module 10 including at least one chip 1; each chip module 10 includes a front-facing area A and a non-front-facing area B; the front-facing areas A of all chip modules 10 are arranged facing each other, and the non-front-facing areas B of adjacent chip modules 10 are staggered; the front-facing area A has a first interface 21 and a second interface 22; the front-facing area A has two opposite sides, the first interface 21 is located on one of the opposite sides, and the second interface 22 is located between the opposite sides; the surface of the front-facing area A has a wiring layer 3, which is electrically connected to the second interface 22 and extends to the other of the opposite sides; the first interface 21 of the chip module 10 is electrically connected to the wiring layer 3 of the adjacent chip module 10; the first interface 21 and the second interface 22 of the bottom chip module 10 are electrically connected to the carrier structure 4.

[0019] This design has at least the following advantages:

[0020] First, the orthographic projections of adjacent chip modules 10 on the support structure 4 do not completely overlap; among them, the distance between adjacent non-opposite areas B is larger, thus the heat dissipation space is larger; the distance between adjacent opposite areas A is small, thus a wiring layer 3 is set on the surface of opposite area A, so that the heat on the surface of opposite area A can be better conducted.

[0021] Second, the wiring layer 3 is electrically connected to the second interface 22 and extends to the side facing the area A, so that the wiring layer 3 can be opposite to the first interface 21 of the adjacent chip 1. This facilitates the signal connection between the chips 1, and thus enables the signal connection between multiple chips 1 and the carrier structure 4.

[0022] Third, the first interface 21 is located at the edge of the area directly opposite A; the wiring layer 3 changes the layout of the second interface 22, leading it out to the edge of the area directly opposite A. That is, the connection points of the two chips 1 are both located at the edge of the area directly opposite A. Compared to the middle area of ​​the area directly opposite A, the connection points being located at the edge can improve the stability of the chip 1 stack and prevent the chip 1 from tipping over or collapsing.

[0023] The semiconductor structure will be described in detail below with reference to the accompanying drawings.

[0024] refer to Figures 3-5The support structure 41 and the chip module 10 can be fixed together by the soldering part 5, and signal connection can be achieved. In some embodiments, the support structure 41 can be a substrate. The substrate mainly serves to protect the chip 1 and electrically connect the chip 1 to the peripheral circuit board. The substrate is made of a material with good heat dissipation performance, such as an organic substrate or a ceramic substrate. In other embodiments, the chip 1 can be a memory chip, such as a dynamic random access memory (DRAM), and the chip 21 can also be a logic chip, with the memory chip and the logic chip communicating with each other.

[0025] In some embodiments, the chip 21 closer to the support structure 1 can be a logic chip, and the chip 21 farther from the support structure 1 can be a memory chip.

[0026] In other embodiments, the carrier structure 41 may be a logic chip.

[0027] refer to Figures 3-5 The semiconductor structure also includes a filler layer 7, which covers the chip module 10 and the carrier structure 4. The filler layer 7 protects the chip module 10 from external environmental influences, such as resisting external moisture and solvents, and also resisting thermal shock and mechanical vibration during semiconductor structure assembly. In some embodiments, the filler layer 7 can be made of epoxy resin, i.e., EMC (Epoxy Molding Compound).

[0028] Alternating arrangement of chip modules 10 increases the filling space of the filling layer 7, thereby reducing the difficulty of filling, improving the filling effect, and ensuring a good seal. Furthermore, larger particles of filling material can be used to improve heat dissipation.

[0029] The first interface 21 and the second interface 22 will be described in detail below.

[0030] refer to Figures 3-5 For ease of understanding, the two opposite sides of the facing area A are defined as the first side L and the second side R. The first side L of the facing area A of all chip modules 10 are arranged in the same direction, and the second side R of the facing area A of all chip modules 10 are arranged in the same direction.

[0031] Since the chip modules 10 are stacked alternately, for two adjacent chip modules 10, the first interface 21 of one chip module 10 is located on the first side L, and the wiring layer 3 of the chip module 10 extends from the first side L and the second side R to the second side R; the first interface 21 of the other chip module 10 is located on the second side R, and the wiring layer 3 of the chip module 10 extends from the first side L and the second side R to the first side L.

[0032] It should be noted that the first interface 21 is located at the edge of the directly opposite area A, but since the directly opposite area A is also connected to the non-directly opposite area B, the first interface 21 is located in the middle area of ​​the entire chip module 10. Furthermore, the second interface 22 is also located in the middle area of ​​the entire chip module 10, rather than at the edge. The middle area here can be understood as the middle position of the top or bottom surface of the chip module 10.

[0033] The reason why the first interface 21 and the second interface 22 are located in the middle area of ​​the chip module 10 is that the chip 1 typically includes an array area and a peripheral area; the peripheral area contains control circuitry, and the array area contains storage units. The circuitry in the peripheral area controls the read and write processes of the storage units. The peripheral area is located in the middle area of ​​the chip 1, and the array area is located at the edge of the chip 1. The first interface 21 and the second interface 22 are electrically connected to the circuitry in the peripheral area; therefore, the first interface 21 and the second interface 22 are typically located in the middle area of ​​the chip 1.

[0034] In some embodiments, the first interface 21 and the second interface 22 may be solder pads 51 formed on the surface of the chip 1 to bring out different signals within the chip 1. After the circuitry within the chip 1 is manufactured, the first interface 21 and the second interface 22, which are connected to the circuitry, can be directly formed on the front side of the chip 1 to simplify the manufacturing process. In other embodiments, the first interface 21 and the second interface 22 may also be located on the back side of the chip 1.

[0035] Each chip 1 can have multiple first interfaces 21 and multiple second interfaces 22, thereby providing the chip 1 with a variety of different electrical signals. In some embodiments, multiple first interfaces 21 of the same chip 1 can be arranged in a straight line, and multiple second interfaces 22 of the same chip 1 can be arranged in a straight line, thus simplifying the structure. In other embodiments, adjacent first interfaces 21 and adjacent second interfaces 22 of the same chip 1 can also be slightly offset. This allows for full utilization of the space on the surface of the chip 1, facilitating an increase in the number of first interfaces 21 and second interfaces 22, and increasing the spacing between adjacent first interfaces 21 and adjacent second interfaces 22, thereby reducing signal interference.

[0036] refer to Figure 3 and Figure 4 In some embodiments, the first interface 21 and the second interface 22 of the top-layer chip module 10 are located on the bottom surface of the chip module 10. Therefore, it is unnecessary to form a through-hole 610 and a through-hole 620 in the top-layer chip module 10 to bring the first interface 21 and the second interface 22 to the bottom surface of the chip module 10. That is, manufacturing steps can be reduced, and manufacturing costs can be lowered. In other embodiments, the top-layer chip module 10 may also have a first conductive via 610 and a second conductive via 620, which will be described in detail later.

[0037] The first interface 21 and the second interface 22 of the non-top-level chip module 10 are located on the bottom or top surface of the chip module 10. The non-top-level chip module 10 has a through-hole 610 and a through-hole 620. The first through-hole 610 is electrically connected to the first interface 21, and the second through-hole 620 is electrically connected to the second interface 22. That is, the first through-hole 610 and the second through-hole 620 serve as signal transmission paths in the vertical direction. Therefore, it is not necessary to electrically connect each chip module 10 to the carrier structure 4 through conductive structures such as leads or lead frames, which helps to reduce the size of the semiconductor structure and improve the integration of the semiconductor structure.

[0038] Specifically, in the direction perpendicular to the upper surface of the bearing structure 4, the first conductive through hole 610 can be directly opposite to and connected to the first interface 21, and the second conductive through hole 620 can be directly opposite to and connected to the second interface 22, thereby increasing the contact area between the first conductive through hole 610 and the first interface 21 and the contact area between the second conductive through hole 620 and the second interface 22.

[0039] Since the first conductive via 610 and the second conductive via 620 penetrate the chip module 10 in a direction perpendicular to the upper surface of the supporting structure 4, and the electrical signal of the first conductive via 610 is the same as the electrical signal of the first interface 21, and the electrical signal of the second conductive via 620 is the same as the electrical signal of the second interface 22, it can be understood that the top and bottom surfaces of the non-top layer chip module 10 both have the first interface 21 and the second interface 22.

[0040] The following will provide a detailed description of wiring layer 3.

[0041] In some embodiments, reference Figure 3 and Figure 5 The non-top-level chip module 10 has wiring layers 3 on both its top and bottom surfaces. Specifically, refer to... Figure 3 One wiring layer 3 is connected to the second interface 22, and the other wiring layer 3 is connected to the end of the second conductive via 620 furthest from the second interface 22. (Reference) Figure 5 The wiring layers 3 on both the top and bottom surfaces of the chip module 10 are connected to the second interface 22. As mentioned above, under the electrical connection of the second conductive via 620, both the top and bottom surfaces of the chip module 10 have the second interface 22. Therefore, by providing wiring layers 3 on both the top and bottom surfaces of the chip module 10, the layout of the second interface 22 on the top and bottom surfaces of the chip module 10 can be changed, thus facilitating signal connection between multiple chip modules 10.

[0042] In other embodiments, reference is made to Figure 4If there are two chip modules 10, i.e., the non-top-level chip module 10 is the bottom-level chip module 10, then the bottom surface of this chip module 10 does not need to have a wiring layer 3 to change the layout of the second interface 22; instead, the bottom of the second conductive via 620 is directly soldered to the supporting structure 4. Since this soldering position is located in the central area of ​​the chip module 10, in order to ensure the stability of the structure, a soldering part 5 can also be added at the edge of the chip module 10. The added soldering part 5 also helps to guide heat transfer.

[0043] refer to Figures 3-5 Each adjacent chip module 10 also has multiple solder joints 5, located on opposite sides of the facing area A, with some solder joints 5 located on the first side L and some on the second side R. The solder joints 5 are connected to the wiring layer 3 of one chip module 10 and to the first interface 21 or the first conductive via 610 of the other chip module 10. In other words, the solder joints 5 not only fix the two chip modules 10 together but also enable electrical connection between them.

[0044] In other words, since the first interface 21 is located at the edge of the opposing region A, and the second interface 22 is extended to the other edge of the opposing region A by changing the layout of the wiring layer 3, the soldering part 5 can also be located at the edge of the opposing region A. Compared to being located at the center of the opposing region A, the soldering part 5 being located at the edge of the opposing region A helps to enhance the connection strength of adjacent chip modules 10, thereby improving the structural robustness.

[0045] For example, the welding part 5 may include two solder pads 51 and a welding bump 52 located between the two solder pads 51, wherein the solder pads 51 may be made of copper and the welding bump 52 may be made of tin-silver alloy.

[0046] In some embodiments, the welded portions 5 are symmetrically distributed with respect to the center of the opposing region A. That is, improving the uniformity of the distribution of the welded portions 5 balances the connection forces of adjacent chip modules 10, thereby improving the structural robustness.

[0047] It should be noted that the soldering part 5 protrudes from the surface of the chip module 10, so adjacent chip modules 10 can be spaced apart, thereby forming a heat dissipation space between adjacent chip modules 10. In addition, the soldering part 5 has excellent heat dissipation capacity, so some of the heat generated by the chip 1 can be transferred to the soldering part 5, and then conducted outward from the soldering part 5, thereby improving the heat dissipation effect.

[0048] The following will provide examples of chip modules 10 with different numbers of chips 1.

[0049] In some embodiments, reference Figures 3-4Chip module 10 includes a chip 1, meaning that adjacent chips 1 can be stacked alternately. Chip 1 has a through-hole 61 and a through-hole 62, where the first through-hole 61 serves as a first conductive via 610 and the second through-hole 62 serves as a second conductive via 620. For example, the first through-hole 61 and the second through-hole 62 can be through-silicon vias (TSVs). Each non-top layer chip 1 can have wiring layers 3 on its top and bottom surfaces, thereby enhancing heat dissipation.

[0050] Furthermore, the chips 1 can be stacked face-to-face or back-to-back. The front side generates more heat than the back side; therefore, the front side can also be considered the heat-generating surface. In other embodiments, the chips 1 can also be stacked face-to-back, thus there is only one front side in the area between adjacent chips 1. This results in a more uniform distribution of the heat-generating surfaces, which helps avoid heat accumulation.

[0051] In other embodiments, reference is made to Figure 5 The chip module 10 includes multiple chips 1, and the orthographic projections of the multiple chips 1 within the chip module 10 on the support structure 4 coincide. The first through-holes 61 of the multiple chips 1 are facing each other and electrically connected, forming a first conductive through-hole 610; the second through-holes 62 of the multiple chips 1 are facing each other and electrically connected, forming a second conductive through-hole 620. It is worth noting that the multiple first through-holes 61 within the chip module 10 are electrically connected together through a bonding portion 23; the multiple second through-holes 62 within the chip module 10 are also electrically connected together through a bonding portion 23.

[0052] If the top-level chip module 10 has multiple chips 1, then the top-level chip module 10 also needs to form a first conductive via 610 and a second conductive via 620 to realize the signal connection of multiple chips 1. If the top-level chip module 10 has only one chip 1, the first conductive via 610 and the second conductive via 620 do not need to be formed.

[0053] Continue to refer to Figure 5 In the non-top-level chip module 10, the top surface of the topmost chip 1 can have a wiring layer 3, the bottom surface of the bottommost chip 1 can have a wiring layer 3, and the surfaces of two opposing chips 1 can be without a wiring layer 3. This simplifies the manufacturing process.

[0054] It is worth noting that when there are more than two chips 1 within the chip module 10, the surface of the chip module 10 located in the middle position may not have a wiring layer 3. The main reason is that interfaces with the same electrical signals can be aligned within the chip module 10; therefore, there is no need to use a wiring layer 3 to change the position of the interfaces. This reduces the number of wiring layers 3, thereby simplifying the manufacturing process.

[0055] Multiple chips 1 within the chip module 10 can be connected using a hybrid bonding method. Specifically, the surface of each chip 1 has a bonding portion 23 and a dielectric layer (not shown in the figure). The upper surface of the bonding portion 23 can be flush with the upper surface of the dielectric layer, or the upper surface of the bonding portion 23 can have a slight indentation relative to the upper surface of the dielectric layer. Under heating conditions, the bonding portions 23 of two adjacent chips 1 will slightly expand and bond together, thereby forming an electrical connection; the dielectric layers of two adjacent chips 1 can be connected together by intermolecular forces. This hybrid bonding method improves the reliability of the chip module 10. In other embodiments, bump bonding technology can also be used to pre-bond multiple chips 1 to form the chip module 10.

[0056] Furthermore, when the chip module 10 includes multiple stacked chips 1, the front surface of the uppermost chip 1 in the chip module 10 can face outwards, and the front surface of the lowermost chip 1 in the chip module 10 can also face outwards. That is, the heat-generating surfaces of the outermost two chips 1 are both facing outwards, thereby enabling timely heat dissipation and reducing heat accumulation.

[0057] For example, the chip module 10 includes two chips 1, and the front A of both chips 1 faces outward. That is, the two chips 1 are bonded back to back, thereby ensuring that the heat of each chip 1 in the chip module 10 can be dissipated in a timely manner.

[0058] In some embodiments, the number of chips 1 in the chip module 10 is less than three. It should be noted that if the number of chips 1 in the chip module 10 is too large, the heat from the chip 1 located in the middle of the chip module 10 may not dissipate in time. Therefore, controlling the number of chips 1 in the chip module 10 to three or less is beneficial to improving the overall heat dissipation effect of the chip module 10.

[0059] In some embodiments, the number of chips 1 in the multiple chip modules 10 is the same. This simplifies the manufacturing process and improves the stability of the stack. In other embodiments, the number of chips 1 in the multiple chip modules 10 may also be different. For example, the chip modules 10 located at the top and bottom layers may have more chips 1, while the chip modules 10 located in the middle may have fewer chips 1, thereby reducing the heat accumulation in the chip modules 10 located in the middle.

[0060] refer to Figures 3-5 Both the first through-hole 61 and the second through-hole 62 are located in the middle region of chip 1. As mentioned above, the first interface 21 and the second interface 22 are usually located in the middle region of chip 1. Since the first through-hole 61 is electrically connected to the first interface 21 and the second through-hole 62 is electrically connected to the second interface 22, the first through-hole 61 and the second through-hole 62 can also be located in the middle region of chip 1.

[0061] Because the first via 61 and the second via 62 have good thermal conductivity, the heat dissipation rate of the central region of chip 1 is faster than that of the edge region. One edge region of chip 1 is located in the non-facing region B and is exposed in the fill layer 7, which increases the heat dissipation space of this edge region; the other edge region of chip 1 is located in the facing region A, and this edge region is provided with a wiring layer 3, which is also connected to the soldering part 5. That is, this edge region can dissipate heat through the heat dissipation channel formed by the soldering part 5, the first via 61 of the adjacent chip 1, and its own wiring layer 3. It can be seen that the staggered stacking method, in conjunction with the wiring layer 3, can balance the heat dissipation of the central region and the edge region, thereby improving the overall heat dissipation effect of the semiconductor structure.

[0062] refer to Figures 6-7 The following will explain in detail the positional relationship between the directly opposite area A and the non-directly opposite area B. Figures 6-7 Top views of different semiconductor structures are shown for a more intuitive understanding. Figures 6-7 Only chip module 10 in the semiconductor structure is shown.

[0063] refer to Figure 6 In some embodiments, the facing area A and the non-facing area B of the same chip module 10 are arranged in a first direction X, which is parallel to the upper surface of the support structure 4. That is, the facing area A and the non-facing area B are arranged side by side. For example, the orthographic projections of the facing area A and the non-facing area B onto the support structure 4 are both rectangular, and one side of the facing area A and the non-facing area B coincides. In other words, for two adjacent chip modules 10, they are misaligned in the first direction X and aligned in the second direction Y. The second direction Y is parallel to the upper surface of the support structure 4 and perpendicular to the first direction X. This misalignment method is relatively simple and helps to ensure the stability of the structure.

[0064] In other embodiments, the non-opposite area B of the same chip module 10 partially surrounds the opposite area A. For example, the orthographic projections of both the opposite area A and the non-opposite area B onto the support structure 4 are rectangular, and the two sides of both areas coincide. That is, for two adjacent chip modules 10, they are misaligned in both the first direction X and the second direction Y. This increases the heat dissipation space in both the first direction X and the second direction Y simultaneously, thereby improving heat dissipation.

[0065] In some embodiments, reference Figure 3 and Figure 5 The areas of the orthographic projections of multiple opposing regions A onto the support structure 4 are the same; the areas of the orthographic projections of multiple non-opposing regions B onto the support structure 4 are also the same. This helps to balance the heat dissipation of the multiple chip modules 10.

[0066] In some embodiments, reference Figure 3 and Figure 5 In the odd-numbered layers, the non-aligned areas B of the chip modules 10 coincide on the orthographic projection of the carrier structure 4; similarly, the non-aligned areas B of the even-numbered layers also coincide on the carrier structure 4. This allows the center of gravity of the semiconductor structure to move closer to the center, thereby improving structural stability. Furthermore, the shape of the semiconductor structure is more regular, which simplifies the packaging process. Additionally, it facilitates unifying the positions of the first interface 21 and the second interface 22 of the chip modules 10, thus making it easier to solder adjacent chip modules 10.

[0067] In some embodiments, the ratio of the area of ​​the orthographic projection of the facing region A onto the supporting structure 4 to the area of ​​the orthographic projection of the non-facing region B onto the supporting structure 4 is 3:1 to 1:1. It is understood that if the area of ​​the orthographic projection of the facing region A is too small, the chip module 10 may collapse or tip over, and the space utilization will be low; if the area of ​​the orthographic projection of the non-facing region B is too small, the heat dissipation space of the chip module 10 will be small. When the areas of the orthographic projections of the facing region A and the non-facing region B are within the above range, it is beneficial to improve the stability of the chip module 10, improve space utilization, and effectively reduce the degree of heat accumulation.

[0068] In summary, in this embodiment, the chip module 10 is stacked in an interleaved manner using wiring layer 3 and soldering portion 5, allowing for vertical signal connection between the first conductive via 610 and the second conductive via 620. Wiring layer 3, soldering portion 5, and the first conductive via 610 and second conductive via 620 improve heat conduction in the directly opposite area A; the non-directly opposite area B has a larger heat dissipation space, thus increasing heat dissipation speed. Therefore, heat dissipation in both the directly opposite area A and the non-directly opposite area B can be enhanced simultaneously. Furthermore, using the first conductive via 610 and the second conductive via 620 reduces line resistance, thereby reducing heat generation.

[0069] like Figures 8-9 as well as Figure 3 As shown, another embodiment of this disclosure provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure provided by an embodiment of this application will be described in detail below with reference to the accompanying drawings.

[0070] refer to Figures 8-9 The system provides multiple chip modules 10, each including a front-facing area A and a non-front-facing area B. The front-facing area A has a first interface 21 and a second interface 22. The front-facing area A has two opposite sides, with the first interface 21 located on one of the opposite sides and the second interface 22 located between the opposite sides. A wiring layer 3 is formed on the surface of the front-facing area A, and the wiring layer 3 is electrically connected to the second interface 22 and extends to the other of the opposite sides.

[0071] Specifically, refer to Figure 8A chip 1 is provided as the top-layer chip module 10. A pad is formed at the bottom of the chip 1 to serve as a first interface 21 and a second interface 22; the pad material can be a metal such as aluminum or copper. A solder pad 51 and a solder bump 52 are formed directly below the first interface 21. A wiring layer 3 is formed to connect to the second interface 22, and the solder pad 51 and solder bump 52 are formed on the side of the wiring layer 3 away from the second interface 22. This chip 1 does not require the formation of a through-hole 61 and a through-hole 62, simplifying the manufacturing process.

[0072] refer to Figure 9 Multiple chips 1 are provided as a non-top-layer chip module 10. A pad is formed on the top surface of the chip 1 to serve as a first interface 21 and a second interface 22. A solder pad 51 is formed directly above the first interface 21 to form a wiring layer 3 connected to the second interface 22, and a solder pad 51 is formed on the side of the wiring layer 3 away from the second interface 22. Furthermore, a first through-hole 61 and a second through-hole 62 are formed through the chip 1, with the upper end of the first through-hole 61 connected to the first interface 21 and the upper end of the second through-hole 62 connected to the second interface 22. A wiring layer 3 is formed on the bottom surface of the chip 1, and the wiring layer 3 is connected to the lower end of the second through-hole 62. A solder pad 51 is formed on the side of the wiring layer 3 away from the second through-hole 62 and at the lower end of the first through-hole 61.

[0073] In other embodiments, the chip module 10 may include a plurality of chips 1, wherein the first through holes 61 in the plurality of chips 1 are electrically connected to form a first conductive through hole 610, and the second through holes 62 in the plurality of chips 1 are electrically connected to form a second conductive through hole 620.

[0074] based on Figures 8-9 As can be seen from the steps, a first conductive via 610 and a second conductive via 620 are formed through the non-top-layer chip module 10. The first conductive via 610 is electrically connected to the first interface 21, and the second conductive via 620 is electrically connected to the second interface 22. The first conductive via 610 and the second conductive via 620 enable faster heat dissipation in the middle area of ​​the chip module 10.

[0075] refer to Figure 3 A carrier structure 4 is provided, on which multiple chip modules 10 are stacked alternately, with the facing areas A of all chip modules 10 facing each other; the non-facing areas B of two adjacent layers of chip modules 10 are staggered; the first interface 21 of the chip module 10 is electrically connected to the wiring layer 3 of the adjacent chip module 10; and the first interface 21 and the second interface 22 of the bottom layer chip module 10 are electrically connected to the carrier structure 4.

[0076] A molding bottom filling process is used to form a filling layer 7 that covers the chip module 10 and the supporting structure 4. The staggered arrangement of the chip modules 10 can increase the filling space, so large-particle filling material can be selected to improve heat dissipation.

[0077] In summary, in this embodiment, solder pads 51 and solder bumps 52 are formed on the lower surface of the first interface 21 of the top-layer chip module 10, and a wiring layer 3 is formed on the lower surface of the second interface 22, thereby extending the signal of the second interface 22 to the edge of the chip 1. Subsequently, solder pads 51 and solder bumps 52 are formed on the lower surface of the wiring layer 3. The non-top-layer chip module 10 uses the wiring layer 3 to extend the signal of the second interface 22 to the edge of the chip 1. Additionally, a first conductive via 610 and a second conductive via 620 are formed in the chip module 10. Subsequently, the chip module 10 is staggered and filled using a molding underfill process. This improves the heat dissipation of the semiconductor structure, thereby improving its performance.

[0078] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0079] Although embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure. Therefore, any changes or modifications made in accordance with the claims and description of the present disclosure should fall within the scope of the patent coverage of the present disclosure.

Claims

1. A semiconductor structure, characterized in that, include: Load-bearing structure; The multi-layered chip modules are stacked alternately on the support structure, each chip module including at least one chip; each chip module includes a facing area and a non-facing area; the facing areas of all the chip modules are arranged facing each other, and the non-facing areas of adjacent layers of chip modules are staggered. The facing area has a first interface and a second interface; the facing area has opposite sides, the first interface is located on one of the opposite sides, and the second interface is located between the opposite sides; the surface of the facing area has a wiring layer, the wiring layer is electrically connected to the second interface, and extends to the other side of the opposite sides; The first interface of the chip module is electrically connected to the wiring layer of the adjacent chip module; The first and second interfaces of the underlying chip module are electrically connected to the carrier structure.

2. The semiconductor structure according to claim 1, characterized in that, The first interface and the second interface of the top-level chip module are located on the bottom surface of the chip module; The first interface and the second interface of the non-top-level chip module are located on the bottom or top surface of the chip module; the non-top-level chip module has a through first conductive via and a through second conductive via, the first conductive via being electrically connected to the first interface, and the second conductive via being electrically connected to the second interface.

3. The semiconductor structure according to claim 2, characterized in that, The top and bottom surfaces of the non-top layer chip module both have the wiring layer, and one wiring layer is connected to the second interface, while the other wiring layer is connected to the end of the second conductive via away from the second interface.

4. The semiconductor structure according to claim 2, characterized in that, There are multiple solder joints between adjacent chip modules, and the solder joints are located on opposite sides of the facing area; the solder joints are connected to the wiring layer of one chip module and to the first interface or the first conductive via of another chip module.

5. The semiconductor structure according to claim 2, characterized in that, The chip has a first through hole and a second through hole. The chip module includes a chip, wherein the first through hole serves as the first conductive through hole, and the second through hole serves as the second conductive through hole; Alternatively, the chip module may include multiple chips, with the first vias of the multiple chips facing each other and electrically connected, forming the first conductive via; and the second vias of the multiple chips facing each other and electrically connected, forming the second conductive via.

6. The semiconductor structure according to claim 5, characterized in that, Both the first via and the second via are located in the middle region of the chip.

7. The semiconductor structure according to claim 1, characterized in that, The opposing area and the non-opposite area of ​​the same chip module are arranged in a first direction, which is parallel to the upper surface of the support structure.

8. The semiconductor structure according to claim 1, characterized in that, The non-opposite area of ​​the same chip module partially surrounds the opposite area.

9. The semiconductor structure according to claim 1, characterized in that, The areas of the orthographic projections of the multiple opposing regions onto the supporting structure are the same; The areas of the orthographic projections of the multiple non-aligned regions onto the load-bearing structure are the same.

10. The semiconductor structure according to claim 9, characterized in that, The non-opposite regions of the chip modules in the odd-numbered layers have their orthogonal projections onto the support structure. The non-opposite regions of the chip modules in the even-numbered layers have their orthogonal projections onto the support structure.

11. The semiconductor structure according to claim 1, characterized in that, The ratio of the area of ​​the orthogonal projection of the opposite region onto the load-bearing structure to the area of ​​the orthogonal projection of the non-opposite region onto the load-bearing structure is 3:1 to 1:

1.

12. The semiconductor structure according to claim 1, characterized in that, Also includes: A filler layer that covers the chip module and the carrier structure.

13. A method for manufacturing a semiconductor structure, characterized in that, A plurality of chip modules are provided, each chip module including at least one chip; each chip module includes a front-facing area and a non-front-facing area; the front-facing area has a first interface and a second interface; the front-facing area has opposite sides, the first interface is located on one of the opposite sides, and the second interface is located between the opposite sides. A wiring layer is formed on the surface of the opposite area, the wiring layer being electrically connected to the second interface and extending to the other side of the opposite sides; A carrier structure is provided on which multiple chip modules are stacked alternately, with the facing areas of all chip modules facing each other; the non-facing areas of two adjacent layers of chip modules are staggered; the first interface of each chip module is electrically connected to the wiring layer of the adjacent chip module; and the first and second interfaces of the bottom layer chip modules are electrically connected to the carrier structure.

14. The method for manufacturing a semiconductor structure according to claim 13, characterized in that, Also includes: A first conductive via and a second conductive via are formed within the non-top-level chip module. The first conductive via is electrically connected to the first interface, and the second conductive via is electrically connected to the second interface.

15. The method for manufacturing a semiconductor structure according to claim 13, characterized in that, Also includes: A molding bottom filling process is used to form a filling layer covering the chip module and the carrier structure.

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