Semiconductor structure and method of forming the same

Abstract

The present disclosure relates to the technical field of semiconductor technology, and discloses a semiconductor structure and a forming method thereof. The forming method comprises the following steps: providing a substrate; forming a lower electrode layer on one side of the substrate; forming a dielectric layer on a surface of the lower electrode layer; forming an upper electrode layer on a surface of the dielectric layer; and forming a semiconductor layer on a surface of the upper electrode layer, wherein the semiconductor layer comprises a host material and a guest material doped in the host material, and the doping proportion of the guest material decreases from the side far away from the upper electrode layer to the side close to the upper electrode layer. The forming method can reduce the risk of leakage of the dielectric layer and improve the yield of products.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a method for forming the same. Background Technology

[0002] Due to their advantages such as small size, high integration, and high transfer speed, memory is widely used in mobile devices such as mobile phones and tablets. Capacitors, as the core component of dynamic random access memory (DRAM), are primarily used to store electrical charge.

[0003] A capacitor mainly consists of a lower electrode layer, a dielectric layer, an upper electrode layer, and a semiconductor layer formed on the surface of the upper electrode layer. During the manufacturing process of a capacitor, modified ions are usually added during the molding of the semiconductor layer. However, the modified ions are prone to diffuse into the dielectric layer, causing leakage current in the dielectric layer, which in turn reduces the signal resolution of the memory and results in low product reliability.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] In view of this, the present disclosure provides a semiconductor structure and a method for forming the same, which can reduce the risk of leakage current in the dielectric layer and improve product yield.

[0006] According to one aspect of this disclosure, a method for forming a semiconductor structure is provided, comprising:

[0007] Provide substrate;

[0008] A lower electrode layer is formed on one side of the substrate;

[0009] A dielectric layer is formed on the surface of the lower electrode layer;

[0010] An upper electrode layer is formed on the surface of the dielectric layer;

[0011] A semiconductor layer is formed on the surface of the upper electrode layer. The semiconductor layer includes a host material and a guest material doped in the host material. The doping ratio of the guest material decreases sequentially from the side away from the upper electrode layer to the side closer to the upper electrode layer.

[0012] In one exemplary embodiment of this disclosure, the doping ratio of the guest material to the host material of the semiconductor layer ranges from 0 to 4%.

[0013] In an exemplary embodiment of this disclosure, the semiconductor layer includes a plurality of sub-film layers that are sequentially stacked on the surface of the upper electrode layer, and in two adjacent sub-film layers, the doping ratio of the guest material in the sub-film layer closer to the substrate is less than the doping ratio of the guest material in the sub-film layer farther from the substrate.

[0014] In one exemplary embodiment of this disclosure, a semiconductor layer is formed on the surface of the upper electrode layer, including:

[0015] A first sub-film layer, a second sub-film layer, a third sub-film layer, and a fourth sub-film layer are sequentially stacked on the surface of the upper electrode layer. The doping ratio of the guest material to the host material in the first sub-film layer ranges from 0.5% to 1.5%.

[0016] In one exemplary embodiment of this disclosure, the doping ratio of the guest material to the host material in the second sub-film layer ranges from 1.5% to 2.5%.

[0017] In one exemplary embodiment of this disclosure, the doping ratio of the guest material to the host material in the third sub-film layer ranges from 2.5% to 3.5%.

[0018] In one exemplary embodiment of this disclosure, the doping ratio of the guest material to the host material in the fourth sub-film layer ranges from 3.5% to 4%.

[0019] In one exemplary embodiment of this disclosure, the host material is germanium-silicon, and the guest material includes boron ions.

[0020] In one exemplary embodiment of this disclosure, a semiconductor layer is formed on the surface of the upper electrode layer, including:

[0021] Boron-containing gas is introduced at a first preset flow rate during a first preset time period; at a second preset flow rate during a second preset time period; at a third preset flow rate during a third preset time period; and at a fourth preset flow rate during a fourth preset time period.

[0022] In one exemplary embodiment of this disclosure, the first preset time period, the second preset time period, the third preset time period, and the fourth preset time period are sequentially consecutive, the first preset flow rate is less than the second preset flow rate, the second preset flow rate is less than the third preset flow rate, and the third preset flow rate is less than the fourth preset flow rate.

[0023] In one exemplary embodiment of this disclosure, the boron-containing gas includes at least one of borane or boron chloride.

[0024] In one exemplary embodiment of this disclosure, a lower electrode layer is formed on one side of the substrate, comprising:

[0025] A stacked film layer is formed on the surface of the substrate;

[0026] Multiple capacitor contact holes are formed in an array within the stacked film layer;

[0027] A lower electrode layer is formed that conformally adheres to the sidewalls and bottom of the capacitor contact hole;

[0028] The dielectric layer is conformally attached to the surface of the lower electrode layer;

[0029] The upper electrode layer is conformally attached to the surface of the dielectric layer;

[0030] The semiconductor layer covers the surface of the upper electrode layer and fills each of the capacitor contact holes.

[0031] According to one aspect of this disclosure, a semiconductor structure is provided, comprising:

[0032] Substrate;

[0033] The lower electrode layer is located on one side of the substrate;

[0034] A dielectric layer is located on the surface of the lower electrode layer;

[0035] The upper electrode layer is located on the surface of the dielectric layer;

[0036] A semiconductor layer is located on the surface of the upper electrode layer. The semiconductor layer includes a host material and a guest material doped in the host material. The doping ratio of the guest material decreases sequentially from the side away from the upper electrode layer to the side closer to the upper electrode layer.

[0037] In one exemplary embodiment of this disclosure, the doping ratio of the guest material to the host material of the semiconductor layer ranges from 0 to 4%.

[0038] In an exemplary embodiment of this disclosure, the semiconductor layer includes a plurality of sub-film layers that are sequentially stacked on the surface of the upper electrode layer, and in two adjacent sub-film layers, the doping ratio of the guest material in the sub-film layer closer to the substrate is less than the doping ratio of the guest material in the sub-film layer farther from the substrate.

[0039] In an exemplary embodiment of this disclosure, the semiconductor layer includes a first sub-film layer, a second sub-film layer, a third sub-film layer, and a fourth sub-film layer that are sequentially stacked and distributed on the surface of the upper electrode layer, wherein the doping ratio of the guest material to the host material in the first sub-film layer ranges from 0.5% to 1.5%.

[0040] In one exemplary embodiment of this disclosure, the doping ratio of the guest material to the host material in the second sub-film layer ranges from 1.5% to 2.5%.

[0041] In one exemplary embodiment of this disclosure, the doping ratio of the guest material to the host material in the third sub-film layer ranges from 2.5% to 3.5%.

[0042] In one exemplary embodiment of this disclosure, the doping ratio of the guest material to the host material in the fourth sub-film layer ranges from 3.5% to 4%.

[0043] In one exemplary embodiment of this disclosure, the host material is germanium-silicon, and the guest material includes boron ions.

[0044] The semiconductor structure and its formation method disclosed herein have several advantages. Firstly, the lower electrode layer, dielectric layer, and upper electrode layer can constitute a capacitor structure for storing charge. The semiconductor layer, located on the surface of the upper electrode layer, facilitates sufficient contact between the charge and the upper electrode layer, thereby improving capacitor charging efficiency. Secondly, during the formation of the semiconductor layer, a guest material can be added to the host material to form a solid solution between the host and guest materials. This lowers the melting point of the material used to form the semiconductor layer, improves material flowability, and prevents voids in the semiconductor layer, thus improving product yield. Simultaneously, lowering the melting point of the material allows for a suitable reduction in reaction temperature, thereby simplifying the process. Thirdly, the lower concentration of the guest material near the upper electrode layer reduces the amount of guest material at the interface between the semiconductor layer and the upper electrode layer. This reduces the ion concentration of the guest material between the interface and the dielectric layer, decreasing the amount of ions diffusing from the guest material into the dielectric layer, thereby reducing leakage current in the dielectric layer, improving signal resolution, and enhancing product reliability.

[0045] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0046] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0047] Figure 1 This is a schematic diagram of a semiconductor structure in related technologies;

[0048] Figure 2 This is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0049] Figure 3 This is a schematic diagram of the semiconductor structure in the embodiments of this disclosure;

[0050] Figure 4 In order to implement this public method Figure 3 A magnified view of a portion of region A in the middle;

[0051] Figure 5 In another implementation method of this disclosure Figure 3 A magnified view of a portion of region A in the middle.

[0052] Explanation of reference numerals in the attached figures:

[0053] 100. Capacitor structure; 101. Lower electrode layer; 102. Dielectric layer; 103. Upper electrode layer; 200. Semiconductor layer; 201. Void; 1. Substrate; 2. Capacitor structure; 21. Lower electrode layer; 22. Dielectric layer; 23. Upper electrode layer; 3. Semiconductor layer; 31. First sub-film layer; 32. Second sub-film layer; 33. Third sub-film layer; 34. Fourth sub-film layer. Detailed Implementation

[0054] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0055] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0056] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion meaning and that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” “third,” and “fourth,” etc., are used only as markers and are not a limitation on the number of objects.

[0057] Capacitors are the core components of memory devices, primarily used to store electrical charge, such as... Figure 1 As shown, the capacitor mainly comprises multiple capacitor structures 100 arranged in an array (including a lower electrode layer 101, a dielectric layer 102, and an upper electrode layer 103) and a semiconductor layer 200 covering the surface of each capacitor structure 100. To increase storage capacity, the aspect ratio of the capacitor structures 100 is often high, and the semiconductor layer 200 needs to fill the gaps between the capacitor structures 100. During this process, due to the high aspect ratio of the capacitor structures 100, voids 201 are prone to appear inside the semiconductor layer 200 during its formation. Therefore, modified ions 202 need to be added to the semiconductor layer 201 to improve the material flowability during the semiconductor layer 200 deposition process, thereby avoiding voids 201. However, because the modified ions 202 have a small atomic radius, during thin film deposition or after heat treatment, the modified ions 202 easily diffuse through the upper electrode layer 103 into the dielectric layer 102, causing leakage in the dielectric layer 102, thus reducing the signal resolution of the memory and resulting in lower product reliability.

[0058] This disclosure provides a method for forming a semiconductor structure, which may be a capacitor. Figure 2 A schematic diagram of the method for forming the semiconductor structure of this disclosure is shown. See also... Figure 2 As shown, the forming method may include steps S110-S150, wherein:

[0059] Step S110: Provide a substrate;

[0060] Step S120: A lower electrode layer is formed on one side of the substrate;

[0061] Step S130: A dielectric layer is formed on the surface of the lower electrode layer;

[0062] Step S140: An upper electrode layer is formed on the surface of the dielectric layer;

[0063] Step S150: A semiconductor layer is formed on the surface of the upper electrode layer. The semiconductor layer includes a host material and a guest material doped in the host material. The doping ratio of the guest material decreases sequentially from the side away from the upper electrode layer to the side closer to the upper electrode layer.

[0064] The method for forming a semiconductor structure disclosed herein, on the one hand, allows the lower electrode layer, dielectric layer, and upper electrode layer to constitute a capacitor structure for storing charge; the semiconductor layer, located on the surface of the upper electrode layer, facilitates sufficient contact between the charge and the upper electrode layer, thereby improving capacitor charging efficiency. On the other hand, during the formation of the semiconductor layer, a guest material can be added to the host material to form a solid solution between the host and guest materials, thereby lowering the melting point of the material used to form the semiconductor layer, improving material flowability, preventing voids in the semiconductor layer, and improving product yield; simultaneously, lowering the melting point of the material used to form the semiconductor layer allows for a suitable reduction in reaction temperature, thus reducing process complexity. Furthermore, the lower concentration of the guest material near the upper electrode layer reduces the content of the guest material at the interface of the semiconductor layer near the upper electrode layer, thereby reducing the ion concentration of the guest material between the interface of the semiconductor layer near the upper electrode layer and the dielectric layer, reducing the amount of ions from the guest material diffusing into the dielectric layer, thus reducing leakage current in the dielectric layer and further improving product yield.

[0065] The steps of the method for forming a semiconductor structure according to the embodiments of this disclosure will be described in detail below:

[0066] like Figure 2 As shown, in step S110, a substrate is provided.

[0067] like Figure 3 As shown, the substrate 1 can be a flat plate structure, which can be rectangular, circular, elliptical, polygonal or irregular shape, and its material can be a semiconductor material, for example, silicon, but not limited to silicon or other semiconductor materials. No special limitation is made on the shape and material of the substrate 1 here.

[0068] In some embodiments of this disclosure, the substrate 1 may include an array region and a peripheral region, which may be distributed adjacent to each other, with the peripheral region surrounding the outer perimeter of the array region. For example, the array region may be a circular region, a rectangular region, or an irregularly shaped region; of course, it may also be a region of other shapes, without particular limitation. The peripheral region may be an annular region surrounding the outer perimeter of the array region; it may be a circular annular region, a rectangular annular region, or an annular region of other shapes, which will not be listed here.

[0069] The array area can be used to form capacitor arrays, transistor arrays, word line structures, and bit line structures connecting transistors and capacitors. The peripheral area can be used to form word line contact plugs. The word line contact plugs can connect word line drivers, sense amplifiers, row decoders, column decoders, and special function control circuits located in the peripheral area. The control circuits can realize the storage and retrieval functions of transistors and capacitors by controlling the word lines and bit lines.

[0070] In some embodiments of this disclosure, the substrate 1 may include a plurality of storage node contact plugs arranged in an array, each storage node contact plug being located within the array region; each storage node contact plug being a conductive structure, and adjacent storage node contact plugs being insulated from each other.

[0071] like Figure 2 As shown, in step S120, a lower electrode layer is formed on one side of the substrate.

[0072] Multiple capacitor structures 2 can be formed on one side of the substrate 1. The orthographic projection of each capacitor structure 2 on the substrate 1 can be located within the array area, and each capacitor structure 2 can be connected to the contact plug of each memory node in a one-to-one correspondence.

[0073] In some embodiments of this disclosure, the capacitor structure 2 may include a lower electrode layer 21, a dielectric layer 22, and an upper electrode layer 23. During the formation of the capacitor structure 2, the lower electrode layer 21 of the capacitor structure 2 may be formed first on one side of the substrate 1. The lower electrode layer 21 may be columnar, with one end of it being in contact with the storage node contact plug in the substrate 1, and the other end extending away from the substrate 1.

[0074] In one exemplary embodiment of this disclosure, forming a lower electrode layer 21 on one side of the substrate 1 (i.e., step S120) may include steps S210-S230, wherein:

[0075] Step S210: A stacked film layer is formed on the surface of the substrate 1.

[0076] The stacked film layers may include multiple support layers and multiple sacrificial layers, which may be alternately distributed on the substrate 1. In the stacked film layers, the film layer closest to the substrate 1 may be a support layer, and the film layer farthest from the substrate 1 may also be a support layer. Both the support layers and the sacrificial layers may be made of insulating materials, and the materials of the support layers and the sacrificial layers may be different. For example, the material of the support layer may be silicon nitride, and the material of the sacrificial layer may be silicon oxide.

[0077] Stacked films can be formed on the surface of substrate 1 through processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, magnetron sputtering or thermal evaporation. Of course, stacked films can also be formed by other means. No special limitation is made on the formation method of stacked films here.

[0078] Step S220: A plurality of capacitor contact holes are formed in an array within the stacked film layer.

[0079] Multiple capacitor contact holes arranged in an array can be formed in the stacked film layers using an etching process. Each capacitor contact hole can be exposed one-to-one with the storage node contact plug in the substrate 1. The capacitor contact holes can be circular, elliptical, rectangular, polygonal, or irregularly shaped hole structures. No special limitation is made on the shape of the capacitor contact holes here.

[0080] Step S230: A lower electrode layer 21 is formed that conformally attaches to the sidewall and bottom of the capacitor contact hole.

[0081] A lower electrode layer 21 can be formed within the capacitor contact hole, conforming to the inner wall of the capacitor contact hole. The lower electrode layer 21 can be connected to the storage node contact plug through the capacitor contact hole, allowing the stored charge in the lower electrode layer 21 to be input to the storage dielectric contact plug, thus facilitating capacitor storage. For example, the lower electrode layer 21 can be formed within the capacitor contact hole using methods such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, vacuum evaporation, magnetron sputtering, or thermal evaporation. Of course, other processes can also be used to form the lower electrode layer 21; no specific limitations are placed on the formation method of the lower electrode layer 21 here. The material of the lower electrode layer 21 can be titanium or tantalum, and its thickness can be 2nm to 8nm. For example, it can be 2nm, 4nm, 6nm, or 8nm. Of course, the lower electrode layer 21 can also be made of other materials or have other thicknesses, which will not be listed here.

[0082] like Figure 2 As shown, in step S130, a dielectric layer is formed on the surface of the lower electrode layer.

[0083] After the lower electrode layer 21 is formed, the sacrificial layer can be removed, leaving only the support layers. The dielectric layer 22 can be a thin film formed on the surface of the lower electrode layer 21, which can be conformally attached to the surface of the lower electrode layer 21. The dielectric layer 22 can be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition, etc. Of course, other methods can also be used to form the dielectric layer 22, which will not be listed here. The dielectric layer 22 can be a single-layer film structure made of the same material, or a mixed film structure made of film layers of different materials. For example, it can include materials with high dielectric constants, such as alumina, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide, or mixtures thereof. Of course, other materials can also be used, which will not be listed here.

[0084] like Figure 2 As shown, in step S140, an upper electrode layer is formed on the surface of the dielectric layer.

[0085] The upper electrode layer 23 can be conformally attached to the surface of the dielectric layer 22. It can be formed on the surface of the dielectric layer 22 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, other methods can also be used to form the upper electrode layer 23; no specific limitation is made here. The material of the upper electrode layer 23 can be titanium nitride, and its thickness can be 4nm to 8nm. For example, it can be 4nm, 4.5nm, 5nm, 5.5nm, 6nm, 6.5nm, 7nm, 7.5nm, or 8nm. Of course, the upper electrode layer 23 can also be made of other materials or have other thicknesses, which will not be listed here. In this embodiment, the lower electrode layer 21, the dielectric layer 22, and the upper electrode layer 23 can constitute a capacitor structure 2, which can be used to store charge.

[0086] like Figure 2 As shown, in step S150, a semiconductor layer is formed on the surface of the upper electrode layer. The semiconductor layer includes a host material and a guest material doped in the host material. The doping ratio of the guest material decreases sequentially from the side away from the upper electrode layer to the side closer to the upper electrode layer.

[0087] In some embodiments of this disclosure, the semiconductor layer 3 may cover the surface of the upper electrode layer 23 and fill the capacitor contact holes. The provision of the semiconductor layer 3 facilitates sufficient contact between the charge and the upper electrode layer 23, thereby improving the capacitor charging efficiency. The semiconductor layer 3 can be formed on the surface of the upper electrode layer 23 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, other methods can also be used to form the semiconductor layer 3, and no particular limitation is made here on the formation method of the semiconductor layer 3.

[0088] In one exemplary embodiment of this disclosure, the thickness of the semiconductor layer 3 can be 200nm to 300nm. For example, its thickness can be 200nm, 250nm or 300nm. Of course, the semiconductor layer 3 can also be of other thicknesses, which will not be listed here.

[0089] During the formation of semiconductor layer 3, due to the typically large aspect ratio of capacitor contact holes, voids 201 are easily formed during the filling of semiconductor material, leading to a decrease in product yield. Therefore, in some embodiments of this disclosure, during the deposition of semiconductor layer 3, the material used to form semiconductor layer 3 is doped to improve material flowability, thereby avoiding the formation of voids 201 and improving product yield.

[0090] For example, the semiconductor layer 3 may include a host material and a guest material doped in the host material. During the formation of the semiconductor layer 3, a solid solution may be formed between the host material and the guest material, thereby lowering the melting point of the material used to form the semiconductor layer 3, improving the material flowability, avoiding the formation of voids 201 in the semiconductor layer 3, and improving product yield. At the same time, since the melting point of the material used to form the semiconductor layer 3 is lowered, the reaction temperature can be appropriately reduced, thereby reducing the difficulty of the process.

[0091] In one exemplary embodiment of this disclosure, such as Figure 4 As shown, the doping ratio of the guest material decreases sequentially from the side furthest from the upper electrode layer 23 to the side closest to the upper electrode layer 23. Because the concentration of the guest material is lower on the side closest to the upper electrode layer 23, the content of the guest material at the interface of the semiconductor layer 3 near the upper electrode layer 23 is reduced. This, in turn, reduces the ion concentration of the guest material between the interface of the semiconductor layer 3 near the upper electrode layer 23 and the dielectric layer 22. This reduces the amount of ions in the guest material diffusing into the dielectric layer 22, thereby reducing the leakage current of the dielectric layer 22 and improving product yield.

[0092] In one exemplary embodiment of this disclosure, the host material may be germanium-silicon, and the guest material may include boron ions. The doping concentration of boron ions in the semiconductor layer 3 decreases sequentially from the side furthest from the upper electrode layer 23 to the side closest to the upper electrode layer 23. This reduces the boron ion concentration at the boundary between the upper electrode layer 23 and the semiconductor layer 3, thereby reducing the amount of boron ions diffusing into the dielectric layer 22, thus reducing the leakage current of the dielectric layer 22 and improving product yield.

[0093] In some exemplary embodiments of this disclosure, the doping ratio of the guest material to the host material in the semiconductor layer 3 can be gradually varied. For example, the doping ratio of the guest material in the semiconductor layer 3 can gradually increase from the side closer to the upper electrode layer 23 to the side farther from the upper electrode layer 23; that is, the doping ratio of the guest material in the semiconductor layer 3 can gradually decrease from the side farther from the upper electrode layer 23 to the side closer to the upper electrode layer 23. For example, the doping ratio of the guest material at the boundary of the semiconductor layer 3 near the upper electrode layer 23 can be 0, and the doping ratio of the guest material at the boundary of the semiconductor layer 3 away from the upper electrode layer 23 can be the maximum value of a preset doping ratio. The doping ratio between the boundary of the semiconductor layer 3 near the upper electrode layer 23 and the boundary of the semiconductor layer 3 away from the upper electrode layer 23 can gradually increase from 0 to the maximum value of the preset doping ratio.

[0094] In some exemplary embodiments of this disclosure, the maximum value of the preset doping ratio can be 3%, 4%, 5%, 6%, 7%, or 8%, etc. Of course, the maximum value of the preset doping ratio can also be other values, which will not be listed here. For example, the range of the doping ratio of the guest material to the host material of the semiconductor layer 3 can include 0-3%, 0-4%, 0-5%, 0-6%, 0-7%, or 0-8%, etc. Of course, the range of the doping ratio of the guest material to the host material of the semiconductor layer 3 can also include other ranges, which will not be listed here.

[0095] Taking a preset maximum doping ratio of 4% as an example, the doping ratio between the boundary of the semiconductor layer 3 near the upper electrode layer 23 and the boundary away from the upper electrode layer 23 can be gradually increased from 0 to 4%; or, the doping ratio between the boundary of the semiconductor layer 3 near the upper electrode layer 23 and the boundary away from the upper electrode layer 23 can be gradually increased from 0.5% to 4%; or, the doping ratio between the boundary of the semiconductor layer 3 near the upper electrode layer 23 and the boundary away from the upper electrode layer 23 can be gradually increased from 1% to 4%.

[0096] In some other embodiments of this disclosure, the semiconductor layer 3 may include a plurality of sub-film layers having a certain guest material doping concentration gradient. Each sub-film layer may be stacked sequentially on the surface of the upper electrode layer 23. In adjacent sub-film layers, the doping ratio (or doping concentration) of the guest material in the sub-film layer closer to the substrate 1 is less than the doping ratio (or doping concentration) of the guest material in the sub-film layer farther from the substrate 1.

[0097] In one exemplary embodiment of this disclosure, the semiconductor layer 3 may include 2, 3, 4, 5, 6, 7, or 8 sub-film layers. Of course, it may also include other numbers of sub-film layers, which will not be listed here. The thickness of each sub-film layer may be the same or different, and no special limitation is made here.

[0098] For example, when semiconductor layer 3 includes two sub-film layers, the doping ratio of the guest material in the sub-film layer closest to substrate 1 can be 1%, and the doping ratio of the guest material in the sub-film layer farther from substrate 1 can be 4%. When semiconductor layer 3 includes three sub-film layers, the doping ratio of the guest material in the sub-film layer closest to substrate 1 can be 1%, the doping ratio of the guest material in the sub-film layer farthest from substrate 1 can be 3%, and the doping ratio of the guest material in the middle sub-film layer can be 2%. When semiconductor layer 3 includes other numbers of sub-film layers, the doping ratio of the guest material in each sub-film layer can gradually increase from the side closest to substrate 1 to the side farther from substrate 1. For example... In the case of semiconductor layer 3 comprising 8 sub-film layers (for ease of distinction, each sub-film layer can be sequentially defined as the first sub-film layer, the second sub-film layer, the third sub-film layer, ... the eighth sub-film layer along the side closest to substrate 1 to the side furthest from substrate 1), the doping ratio of the guest material in the first sub-film layer is less than the doping ratio of the guest material in the second sub-film layer, the doping ratio of the guest material in the second sub-film layer is less than the doping ratio of the guest material in the third sub-film layer, the doping ratio of the guest material in the third sub-film layer is less than the doping ratio of the guest material in the fourth sub-film layer, ... the doping ratio of the guest material in the seventh sub-film layer is less than the doping ratio of the guest material in the eighth sub-film layer. For example, the doping ratio of the guest material in the first sub-film layer can be 0%, the doping ratio of the guest material in the second sub-film layer can be 0.5%, the doping ratio of the guest material in the third sub-film layer can be 1.5%, the doping ratio of the guest material in the fourth sub-film layer can be 2.5%, the doping ratio of the guest material in the fifth sub-film layer can be 3.5%, the doping ratio of the guest material in the sixth sub-film layer can be 4.5%, the doping ratio of the guest material in the seventh sub-film layer can be 5.5%, and the doping ratio of the guest material in the eighth sub-film layer can be 6.5%. Of course, the semiconductor layer 3 may also include other numbers of sub-film layers, and the doping ratio of the guest material in each sub-film layer may also be other values, which will not be listed here.

[0099] The following section provides a detailed explanation of the specific layout of semiconductor layer 3, which includes four sub-film layers:

[0100] like Figure 5As shown, for ease of distinction, each sub-film layer can be defined as the first sub-film layer 31, the second sub-film layer 32, the third sub-film layer 33, and the fourth sub-film layer 34, respectively. That is, the semiconductor layer 3 may include the first sub-film layer 31, the second sub-film layer 32, the third sub-film layer 33, and the fourth sub-film layer 34, which are sequentially stacked and distributed on the surface of the upper electrode layer 23. The first sub-film layer 31 may be located on the surface of the upper electrode layer 23. The doping ratio of the guest material in the second sub-film layer 32 may be greater than the doping ratio of the guest material in the first sub-film layer 31. The doping ratio of the guest material in the third sub-film layer 33 may be greater than the doping ratio of the guest material in the second sub-film layer 32. The doping ratio of the guest material in the fourth sub-film layer 34 may be greater than the doping ratio of the guest material in the third sub-film layer 33.

[0101] In one exemplary embodiment of this disclosure, the thicknesses of the first sub-film layer 31, the second sub-film layer 32, the third sub-film layer 33, and the fourth sub-film layer 34 can be the same. For example, the thicknesses of the first sub-film layer 31, the second sub-film layer 32, the third sub-film layer 33, and the fourth sub-film layer 34 can all be 50 nm; or, the thicknesses of the first sub-film layer 31, the second sub-film layer 32, the third sub-film layer 33, and the fourth sub-film layer 34 can all be 60 nm; or, the thicknesses of the first sub-film layer 31, the second sub-film layer 32, the third sub-film layer 33, and the fourth sub-film layer 34 can all be 75 nm. Of course, the thicknesses of the first sub-film layer 31, the second sub-film layer 32, the third sub-film layer 33, and the fourth sub-film layer 34 can also be other thicknesses, which will not be listed here.

[0102] In another exemplary embodiment of this disclosure, at least two of the first sub-film layer 31, the second sub-film layer 32, the third sub-film layer 33, and the fourth sub-film layer 34 have different thicknesses. For example, the second sub-film layer 32, the third sub-film layer 33, and the fourth sub-film layer 34 have the same thickness, while the first sub-film layer 31 has a different thickness from the other sub-film layers; for example, the second sub-film layer 32, the third sub-film layer 33, and the fourth sub-film layer 34 all have a thickness of 60 nm; the first sub-film layer 31 has a thickness of 70 nm. Alternatively, the thicknesses of the first sub-film layer 31, the second sub-film layer 32, the third sub-film layer 33, and the fourth sub-film layer 34 are all different; for example, the first sub-film layer 31 has a thickness of 50 nm, the second sub-film layer 32 has a thickness of 60 nm, the third sub-film layer 33 has a thickness of 65 nm, and the fourth sub-film layer 34 has a thickness of 75 nm.

[0103] In some embodiments of this disclosure, the doping ratio of the guest material to the host material in the first sub-film layer 31 may range from 0.5% to 1.5%. For example, the doping ratio of the guest material to the host material in the first sub-film layer 31 may be 0.5%, 0.7%, 0.9%, 1.1%, 1.3%, or 1.5%. Of course, the doping ratio of the guest material to the host material in the first sub-film layer 31 may also be other ratios, which will not be listed here.

[0104] The doping ratio of the guest material to the host material in the second sub-film layer 32 can range from 1.5% to 2.5%. For example, the doping ratio of the guest material to the host material in the second sub-film layer 32 can be 1.5%, 1.7%, 1.9%, 2.1%, 2.3%, or 2.5%. Of course, the doping ratio of the guest material to the host material in the second sub-film layer 32 can also be other ratios, which will not be listed here.

[0105] The doping ratio of the guest material to the host material in the third sublayer 33 can range from 2.5% to 3.5%. For example, the doping ratio of the guest material to the host material in the third sublayer 33 can be 2.5%, 2.7%, 2.9%, 3.1%, 3.3%, or 3.5%. Of course, the doping ratio of the guest material to the host material in the third sublayer 33 can also be other ratios, which will not be listed here.

[0106] The doping ratio of the guest material to the host material in the fourth sub-film layer 34 can range from 3.5% to 4%. For example, the doping ratio of the guest material to the host material in the fourth sub-film layer 34 can be 3.5%, 3.6%, 3.7%, 3.8%, 3.9%, or 4%. Of course, the doping ratio of the guest material to the host material in the fourth sub-film layer 34 can also be other ratios, which will not be listed here.

[0107] Preferably, the doping ratio of the guest material to the host material in the first sub-film layer 31 is 1%, the doping ratio of the guest material to the host material in the second sub-film layer 32 is 2%, the doping ratio of the guest material to the host material in the third sub-film layer 33 is 3%, and the doping ratio of the guest material to the host material in the fourth sub-film layer 34 is 4%.

[0108] The following section details the specific process of forming the semiconductor layer 3, taking the formation of the semiconductor layer 3 on the surface of the upper electrode layer 23 by atomic layer deposition as an example:

[0109] The structure consisting of substrate 1, upper electrode layer 23, dielectric layer 22, and lower electrode layer 21 can be placed in the reaction chamber, where a semiconductor layer 3 can be formed. The formation of the semiconductor layer 3 can be divided into multiple time periods; for example, the reaction process can be divided into a first preset time period, a second preset time period, a third preset time period, and a fourth preset time period. The doping ratio of the guest material in the semiconductor layer 3 can be controlled by introducing boron-containing gas at different flow rates during different time periods.

[0110] For example, during the deposition of semiconductor layer 3, a first fixed flow rate of silicon-containing gas and a second fixed flow rate of germanium-containing gas can be continuously introduced into the reaction chamber. At the same time, a first preset flow rate of boron-containing gas can be introduced during a first preset time period; a second preset flow rate of boron-containing gas can be introduced during a second preset time period; a third preset flow rate of boron-containing gas can be introduced during a third preset time period; and a fourth preset flow rate of boron-containing gas can be introduced during a fourth preset time period.

[0111] In some embodiments of this disclosure, the silicon-containing gas may be silane, the germanium-containing gas may be germanane, and the boron-containing gas may be at least one of borane or boron chloride. Of course, the silicon-containing gas may also be other gases that can provide silicon, the germanium-containing gas may also be other gases that can provide germanium, and the boron-containing gas may also be other gases that can provide boron. No specific limitations are made here on the specific types of silicon-containing gas, germanium-containing gas, and boron-containing gas.

[0112] In some embodiments of this disclosure, the first fixed flow rate can be 300 sccm to 400 sccm, for example, the first fixed flow rate can be 300 sccm, 350 sccm or 400 sccm; the second fixed flow rate can be 550 sccm to 650 sccm, for example, the second fixed flow rate can be 550 sccm, 600 sccm or 650 sccm; the first preset flow rate can be 1 to 5 sccm, for example, the first preset flow rate can be 1 sccm, 2 sccm, 3 sccm, 4 sccm or 5 sccm; the second preset flow rate can be 5 to 15 sccm, for example, the second preset flow rate can be 5 sccm, 10 sccm or 15 sccm; the third preset flow rate can be 15 to 25 sccm, for example, the third preset flow rate can be 15 sccm, 20 sccm or 25 sccm; the fourth preset flow rate can be 35 to 40 sccm, for example, the fourth preset flow rate can be 35 sccm, 36 sccm, 37 sccm, 38 sccm, 39 sccm or 40 sccm.

[0113] In some embodiments of this disclosure, when the semiconductor layer 3 includes a first sub-film layer 31, a second sub-film layer 32, a third sub-film layer 33, and a fourth sub-film layer 34, the first sub-film layer 31 can be formed within a first preset time period, the second sub-film layer 32 can be formed within a second preset time period, the third sub-film layer 33 can be formed within a third preset time period, and the fourth sub-film layer 34 can be formed within a fourth preset time period.

[0114] For example, the durations of the first, second, third, and fourth preset time periods can be the same or different, without any special limitation. For instance, when the thicknesses of the first sub-film layer 31, the second sub-film layer 32, the third sub-film layer 33, and the fourth sub-film layer 34 are all equal, the durations of the first, second, third, and fourth preset time periods can all be equal. For example, the durations of the first, second, third, and fourth preset time periods can all be 80 seconds, 81 seconds, 82 seconds, 83 seconds, 84 seconds, or 85 seconds.

[0115] In some embodiments of this disclosure, the first preset flow rate may be less than the second preset flow rate, the second preset flow rate may be less than the third preset flow rate, and the third preset flow rate may be less than the fourth preset flow rate. This results in the doping ratio (or doping concentration) of boron ions in the first sub-film layer 31 formed within the first preset time period being less than the doping ratio (or doping concentration) of boron ions in the second sub-film layer 32 formed within the second preset time period, the doping ratio (or doping concentration) of boron ions in the second sub-film layer 32 formed within the second preset time period being less than the doping ratio (or doping concentration) of boron ions in the third sub-film layer 33 formed within the third preset time period being less than the doping ratio (or doping concentration) of boron ions in the fourth sub-film layer 34 formed within the fourth preset time period.

[0116] In one exemplary embodiment of this disclosure, the semiconductor layer 3 can be formed by chemical vapor deposition under the conditions of a temperature of 445°C, a pressure of 8 torr in the reaction chamber, and the silicon-containing gas being silane, the germanium-containing gas being germanane, and the boron-containing gas being borane. It should be noted that during the chemical vapor deposition process, the flow rate ratio of the silicon-containing gas to the germanium-containing gas can be 40:60, and at the same time, the flow rate of the boron-containing gas increases sequentially with the increase of deposition time.

[0117] It should be noted that although the steps of the semiconductor structure formation method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0118] This disclosure also provides a semiconductor structure, which can be formed by the semiconductor structure formation method in any of the above embodiments. Figure 3 A schematic diagram of the semiconductor structure of this disclosure is shown, such as... Figure 3As shown, the semiconductor structure disclosed herein may include a substrate 1, a lower electrode layer 21, a dielectric layer 22, an upper electrode layer 23, and a semiconductor layer 3, wherein:

[0119] The lower electrode layer 21 may be located on one side of the substrate 1;

[0120] The dielectric layer 22 may be located on the surface of the lower electrode layer 21;

[0121] The upper electrode layer 23 may be located on the surface of the dielectric layer 22;

[0122] Semiconductor layer 3 may be located on the surface of upper electrode layer 23. Semiconductor layer 3 includes a host material and a guest material doped in the host material. The doping ratio of the guest material decreases sequentially from the side away from upper electrode layer 23 to the side closer to upper electrode layer 23.

[0123] The semiconductor structure disclosed herein, on the one hand, comprises a lower electrode layer 21, a dielectric layer 22, and an upper electrode layer 23, which can form a capacitor structure 2 for storing charge; the semiconductor layer 3 is located on the surface of the upper electrode layer 23, facilitating sufficient contact between the charge and the upper electrode layer 23, thereby improving the capacitor charging efficiency. On the other hand, since the concentration of the guest material near the upper electrode layer 23 is lower, the content of the guest material at the interface of the semiconductor layer 3 near the upper electrode layer 23 is reduced, thereby reducing the ion concentration of the guest material between the interface of the semiconductor layer 3 near the upper electrode layer 23 and the dielectric layer 22. This reduces the amount of ions in the guest material diffusing into the dielectric layer 22, thereby reducing the leakage current of the dielectric layer 22 and further improving the product yield.

[0124] The specific details and beneficial effects of the semiconductor structure disclosed herein have been described in detail in the corresponding semiconductor structure formation method. The structural details can be found in the embodiments of the semiconductor structure formation method, and will not be repeated here.

[0125] For example, the semiconductor structure can be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. Of course, it can also be other semiconductor structures, which will not be listed here.

[0126] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A lower electrode layer is formed on one side of the substrate; A dielectric layer is formed on the surface of the lower electrode layer; An upper electrode layer is formed on the surface of the dielectric layer; A semiconductor layer is formed on the surface of the upper electrode layer. The semiconductor layer includes a host material and a guest material doped in the host material. The doping ratio of the guest material decreases sequentially from the side away from the upper electrode layer to the side closer to the upper electrode layer. The doping ratio of the guest material to the host material in the semiconductor layer ranges from 0 to 4%.

2. The forming method according to claim 1, characterized in that, The semiconductor layer includes a plurality of sub-film layers stacked sequentially on the surface of the upper electrode layer, and in two adjacent sub-film layers, the doping ratio of the guest material in the sub-film layer closer to the substrate is less than the doping ratio of the guest material in the sub-film layer farther from the substrate.

3. The forming method according to claim 1, characterized in that, A semiconductor layer is formed on the surface of the upper electrode layer, including: A first sub-film layer, a second sub-film layer, a third sub-film layer, and a fourth sub-film layer are sequentially stacked on the surface of the upper electrode layer. The doping ratio of the guest material to the host material in the first sub-film layer ranges from 0.5% to 1.5%.

4. The forming method according to claim 3, characterized in that, The doping ratio of the guest material to the host material in the second sub-film layer ranges from 1.5% to 2.5%.

5. The forming method according to claim 3, characterized in that, The doping ratio of the guest material to the host material in the third sub-film layer ranges from 2.5% to 3.5%.

6. The forming method according to claim 3, characterized in that, The doping ratio of the guest material to the host material in the fourth sub-film layer ranges from 3.5% to 4%.

7. The forming method according to any one of claims 1-6, characterized in that, The host material is germanium-silicon, and the guest material includes boron ions.

8. The forming method according to claim 7, characterized in that, A semiconductor layer is formed on the surface of the upper electrode layer, including: Boron-containing gas is introduced at a first preset flow rate during a first preset time period; at a second preset flow rate during a second preset time period; at a third preset flow rate during a third preset time period; and at a fourth preset flow rate during a fourth preset time period.

9. The forming method according to claim 8, characterized in that, The first preset time period, the second preset time period, the third preset time period, and the fourth preset time period are sequentially consecutive, and the first preset flow rate is less than the second preset flow rate, the second preset flow rate is less than the third preset flow rate, and the third preset flow rate is less than the fourth preset flow rate.

10. The forming method according to claim 8, characterized in that, The boron-containing gas includes at least one of borane or boron chloride.

11. The forming method according to claim 7, characterized in that, A lower electrode layer is formed on one side of the substrate, comprising: A stacked film layer is formed on the surface of the substrate; Multiple capacitor contact holes are formed in an array within the stacked film layer; A lower electrode layer is formed that conformally adheres to the sidewalls and bottom of the capacitor contact hole; The dielectric layer is conformally attached to the surface of the lower electrode layer; The upper electrode layer is conformally attached to the surface of the dielectric layer; The semiconductor layer covers the surface of the upper electrode layer and fills each of the capacitor contact holes.

12. A semiconductor structure, characterized in that, include: Substrate; The lower electrode layer is located on one side of the substrate; A dielectric layer is located on the surface of the lower electrode layer; The upper electrode layer is located on the surface of the dielectric layer; A semiconductor layer is located on the surface of the upper electrode layer. The semiconductor layer includes a host material and a guest material doped in the host material. The doping ratio of the guest material decreases sequentially from the side away from the upper electrode layer to the side closer to the upper electrode layer. The doping ratio of the guest material to the host material in the semiconductor layer ranges from 0 to 4%.

13. The semiconductor structure according to claim 12, characterized in that, The semiconductor layer includes a plurality of sub-film layers stacked sequentially on the surface of the upper electrode layer, and in two adjacent sub-film layers, the doping ratio of the guest material in the sub-film layer closer to the substrate is less than the doping ratio of the guest material in the sub-film layer farther from the substrate.

14. The semiconductor structure according to claim 12, characterized in that, The semiconductor layer includes a first sub-film layer, a second sub-film layer, a third sub-film layer and a fourth sub-film layer stacked sequentially on the surface of the upper electrode layer, wherein the doping ratio of the guest material to the host material in the first sub-film layer ranges from 0.5% to 1.5%.

15. The semiconductor structure according to claim 14, characterized in that, The doping ratio of the guest material to the host material in the second sub-film layer ranges from 1.5% to 2.5%.

16. The semiconductor structure according to claim 14, characterized in that, The doping ratio of the guest material to the host material in the third sub-film layer ranges from 2.5% to 3.5%.

17. The semiconductor structure according to claim 14, characterized in that, The doping ratio of the guest material to the host material in the fourth sub-film layer ranges from 3.5% to 4%.

18. The semiconductor structure according to any one of claims 12-17, characterized in that, The host material is germanium-silicon, and the guest material includes boron ions.

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