Depletion mode anode shorted lateral insulated gate bipolar transistor and method of manufacturing the same

Abstract

The present application relates to a kind of depletion mode anode short-circuit lateral insulated gate bipolar transistor and its manufacturing method, the transistor includes: drift region, with first conductivity type;Collection area, in the drift region, with second conductivity type, the first conductivity type and second conductivity type are opposite conductivity type;Anode region, with first conductivity type;Second conductivity type doped region, with the anode region directly, and at least a part between the anode region and the drift region;The doping concentration of the second conductivity type doped region is less than the doping concentration of the collection area;First conductivity type buried region, below the anode region, and with the second conductivity type doped region directly;The majority carrier concentration of the first conductivity type buried region is greater than the majority carrier concentration of the second conductivity type doped region.The present application can improve the phenomenon of voltage foldback of device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a depletion-type anode short-circuit lateral insulated gate bipolar transistor, and also to a method for manufacturing a depletion-type anode short-circuit lateral insulated gate bipolar transistor. Background Technology

[0002] An insulated-gate bipolar transistor (IGBT) is a composite power semiconductor device composed of a metal-oxide-semiconductor field-effect transistor (MOSFET) and a bipolar junction transistor (BJT). Lateral IGBTs (LIGBTs) are easily integrated into silicon-based, especially SOI (silicon-on-insulator) based power integrated circuits. LIGBTs not only possess the advantages of strong gate control and high input impedance of MOSFET devices, but also offer advantages such as high current handling capability and low on-state voltage drop due to their conductivity modulation effect. However, the conductivity modulation effect is a double-edged sword; a large number of non-equilibrium carriers stored in the drift region during conduction form a tail current during turn-off. Anode short-circuit (SA) technology is crucial for addressing the tail current formed during turn-off. By introducing an N-type anode region at the anode terminal, a large number of electrons stored in the drift region can be rapidly extracted through this N-type anode region, reducing the current tail time and accelerating the turn-off speed, thereby reducing turn-off losses and achieving a good trade-off between on-state voltage drop and turn-off losses.

[0003] However, the introduction of a short-circuit anode structure can cause voltage snapback in the device. SA-LIGBTs operate with low current and high voltage in unipolar mode, and high voltage and low current in bipolar mode. When transitioning from unipolar to bipolar mode, there is a period of increased current and decreased voltage, resulting in a negative resistance region, known as the snapback phenomenon. The snapback phenomenon increases the forward voltage drop of the device, especially at low temperatures, causing some cells to fail to turn on, resulting in uneven current distribution, which is not conducive to parallel operation of the device. Summary of the Invention

[0004] Therefore, it is necessary to provide a depletion-type anode short-circuit lateral insulated gate bipolar transistor that can suppress voltage foldback.

[0005] A depletion-type anode-short-circuit lateral insulated-gate bipolar transistor includes: a drift region having a first conductivity type; a collector region disposed in the drift region having a second conductivity type, wherein the first conductivity type and the second conductivity type are opposite conductivity types; an anode region having the first conductivity type; a second conductivity type doped region directly contacting the anode region, and at least a portion of which is located between the anode region and the drift region; wherein the doping concentration of the second conductivity type doped region is less than the doping concentration of the collector region; and a first conductivity type buried region located below the anode region and directly contacting the second conductivity type doped region; wherein the majority carrier concentration of the first conductivity type buried region is greater than the majority carrier concentration of the second conductivity type doped region.

[0006] The aforementioned depletion-type anode short-circuit lateral insulated gate bipolar transistor introduces a low-concentration second conductivity type doped region as a depletion region between the anode region and the drift region. At the same time, the second conductivity type doped region is depleted by a first conductivity type buried region. This is equivalent to increasing the resistance between the anode region and the drift region through the isolation of the depletion region, thus improving the voltage foldback phenomenon of the device.

[0007] In one embodiment, the second conductivity type doped region is used to form a depletion layer during operation, and the first conductivity type buried region is used to assist in the depletion of the second conductivity type doped region during operation.

[0008] In one embodiment, the depletion-type anode short-circuit lateral insulated gate bipolar transistor further includes a first conductivity type doped region, which is disposed on the side of the second conductivity type doped region near the collector region, and the first conductivity type doped region is in direct contact with the second conductivity type doped region. The doping concentration of the first conductivity type doped region is greater than the doping concentration of the drift region, and the majority carrier concentration of the first conductivity type doped region is greater than the majority carrier concentration of the second conductivity type doped region.

[0009] In one embodiment, the first conductivity type doped region is used to assist in depleting the second conductivity type doped region during operation.

[0010] In one embodiment, the depletion-type anode short-circuit lateral insulated gate bipolar transistor further includes an anode channel region having a first conductivity type; the anode channel region is disposed in a second conductivity type doped region and is located between the anode region and the first conductivity type doped region.

[0011] In one embodiment, the anode-short-circuit lateral insulated gate bipolar transistor is an SOI device, and the anode-short-circuit lateral insulated gate bipolar transistor further includes: a substrate; a buried dielectric layer disposed on the substrate; wherein the drift region is disposed on the buried dielectric layer; and the bottom of the first conductivity type doped region extends to the buried dielectric layer.

[0012] In one embodiment, the bottom of the first conductive type burial area extends to the burial medium layer.

[0013] In one embodiment, the depletion-type anode short-circuit lateral insulated gate bipolar transistor further includes: a collector well disposed in the drift region and having a first conductivity type, the collector region being disposed in the collector well; a second conductivity type well region; an emitter substrate leading out and having a second conductivity type, located in the second conductivity type well region; and an emitter region having a first conductivity type, located in the second conductivity type well region.

[0014] In one embodiment, the depletion-type anode short-circuit lateral insulated gate bipolar transistor further includes a gate structure located between the emitter region and the collector region well.

[0015] In one embodiment, the collector well and the first conductivity type doped region are separated by a portion of the drift region.

[0016] In one embodiment, the anode region is located in the second conductivity type doped region.

[0017] In one embodiment, the first conductivity type buried region is located in the second conductivity type doped region.

[0018] In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

[0019] It is also necessary to provide a method for manufacturing a depletion-type anode-short-circuited lateral insulated gate bipolar transistor.

[0020] A method for manufacturing a depletion-type anode short-circuit lateral insulated gate bipolar transistor includes: obtaining a substrate having a drift region and a buried region of a first conductivity type; forming a doped region of a second conductivity type in the substrate by ion implantation, the second conductivity type doped region being in direct contact with the first conductivity type buried region; forming a collector region and an anode region; the collector region being located in the drift region and having a second conductivity type; the anode region having a first conductivity type; the anode region being located above the first conductivity type buried region, a small portion of the second conductivity type doped region being located between the anode region and the drift region; the first conductivity type and the second conductivity type being opposite conductivity types.

[0021] In one embodiment, prior to the steps of forming the current collector region and the anode region, the method further includes a step of forming a first conductivity type doped region in the substrate by ion implantation. The first conductivity type doped region is formed on the side of the second conductivity type doped region close to the current collector region. The first conductivity type doped region is in direct contact with the second conductivity type doped region. The doping concentration of the first conductivity type doped region is greater than the doping concentration of the drift region. The implantation concentration of the first conductivity type doped region is greater than the implantation concentration of the second conductivity type doped region.

[0022] The above-mentioned manufacturing method of depletion-type anode short-circuit lateral insulated gate bipolar transistor introduces a low-concentration second conductivity type doped region as a depletion region between the anode region and the drift region. At the same time, the second conductivity type doped region is depleted by a first conductivity type buried region. This is equivalent to increasing the resistance between the anode region and the drift region through the isolation of the depletion region, thus improving the voltage foldback phenomenon of the device. Attached Figure Description

[0023] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0024] Figure 1 This is a schematic diagram of the structure of a depletion-type anode short-circuited lateral insulated gate bipolar transistor in one embodiment;

[0025] Figure 2 This is a flowchart of a method for manufacturing a depletion-type anode short-circuited lateral insulated gate bipolar transistor in one embodiment. Detailed Implementation

[0026] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0028] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0029] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0031] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0032] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0033] A novel depletion-type PA region anode structure (DNCA-LIGBT) is proposed, in which the potential-controlled PA region is composed of the base region (sub(P-)) within the anode NPN (anode N+ / sub(P-) / Nwell) structure, which serves as the depletion region. This base region is the P- region of the SOI (silicon-on-insulator) substrate during device fabrication. Due to the built-in potential, this base region is in a depletion state during device operation (the concentration of P-type ions in sub(P-) is extremely low), hence it is also called a pro-npn-ligbt. The depletion-type potential-controlled PA region design simplifies the fabrication process and enhances potential control capabilities.

[0034] This application provides a depletion-type anode short-circuit lateral insulated gate bipolar transistor capable of suppressing voltage foldback.

[0035] Figure 1This is a schematic diagram of a depletion-type anode short-circuited lateral insulated-gate bipolar transistor (BMT) in one embodiment, including a drift region 106, a collector region 111, an anode region 112, a second conductivity type doped region 104, and a first conductivity type buried region 103. The drift region 106 has a first conductivity type. The collector region 111, located within the drift region 106, serves as the collector lead of the device and has a second conductivity type. The anode region 112 has a first conductivity type. At least a portion of the second conductivity type doped region 104 is located between the anode region 112 and the drift region 106, thereby separating the anode region 112 from the drift region 106. The first conductivity type buried region 103 is located below the anode region 112 and is in direct contact with the second conductivity type doped region 104. Figure 1 In the illustrated embodiment, the first conductivity type is N-type and the second conductivity type is P-type; in another embodiment of this application, the first conductivity type is P-type and the second conductivity type is N-type.

[0036] In traditional anode-short-circuit LIGBTs, the resistance from the emitter to the drift region is similar to the resistance from the drift region (N-buffer) to the N+ anode region in unipolar mode, resulting in similar voltage division. However, in bipolar mode, the conductivity modulation effect causes a significant reduction in the drift region resistance, leading to voltage foldback. The aforementioned depletion-type anode-short-circuit lateral insulated-gate bipolar transistor introduces a low-concentration second conductivity type doped region 104 as a depletion region between the anode region 112 and the drift region 106. Simultaneously, a first conductivity type buried region 103 assists in the depletion of the second conductivity type doped region 104. This effectively increases the resistance between the anode region 112 and the drift region 106 through the isolation of the depletion region, thus improving the voltage foldback phenomenon.

[0037] exist Figure 1 In the illustrated embodiment, the depletion-type anode short-circuit lateral insulated gate bipolar transistor further includes a first conductivity type doped region 105. The first conductivity type doped region 105 is disposed on the side of the second conductivity type doped region 104 near the collector region 111, and the first conductivity type doped region 105 is in direct contact with the second conductivity type doped region 104. The doping concentration of the first conductivity type doped region 105 is greater than the doping concentration of the drift region 106. The majority carrier concentration of the first conductivity type doped region 105 is greater than the majority carrier concentration of the second conductivity type doped region 104. Figure 1In the illustrated embodiment, the donor impurity concentration of the first conductivity type doped region 105 is greater than the acceptor impurity concentration of the second conductivity type doped region 104. The first conductivity type doped region 105 also assists in the depletion of the second conductivity type doped region 104. In one embodiment of this application, the concentration of the second conductivity type doped region 104 is extremely low, and due to the influence of the built-in potential, it is depleted by the first conductivity type buried region 103 and the first conductivity type doped region 105 in a zero-biased collector state. Through the assisted depletion by the first conductivity type buried region 103 and the first conductivity type doped region 105, the second conductivity type doped region 104 can even become a completely depleted region. In one embodiment of this application, the doping concentration of the first conductivity type doped region 105 is less than the doping concentration of the collector well 107, which can achieve a better effect in assisting the depletion of the second conductivity type doped region 104.

[0038] exist Figure 1 In the illustrated embodiment, the depletion-type anode short-circuit lateral insulated gate bipolar transistor further includes an anode channel region 113. The anode channel region 113 has a first conductivity type, is disposed within a second conductivity type doped region 104, and is located between the anode region 112 and the first conductivity type doped region 105. Since the introduction of the depletion region (second conductivity type doped region 104) has limited effect on minority carrier extraction, the introduction of the anode channel region 113 can reduce the resistance between the anode region 112 and the drift region 106. By adjusting the depth, width, and doping concentration of the anode channel region 113, the resistance between the anode region 112 and the drift region 106 can be adjusted, shortening and effectively controlling the device's turn-off time.

[0039] exist Figure 1 In the illustrated embodiment, the depletion-type anode short-circuit lateral insulated gate bipolar transistor further includes a collector well 107. The collector well 107 is disposed in the drift region 106 and has a first conductivity type. A collector region 111 is disposed in the collector well 107. The presence of the collector well 107 can further improve the breakdown voltage of the device.

[0040] exist Figure 1 In the embodiment shown, the collector well 107 and the first conductivity type doped region 105 are separated by a portion of the drift region 106.

[0041] exist Figure 1 In the illustrated embodiment, the anode region 112 is located in the second conductivity type doped region 104 and is disposed near the upper surface of the second conductivity type doped region 104. The collector region 111 is disposed near the upper surface of the collector region well 107, and the collector region 111 and the anode region 112 are connected together by a metal electrode 117 to form a short-circuit connection.

[0042] exist Figure 1In the illustrated embodiment, the depletion-type anode short-circuit lateral insulated-gate bipolar transistor is an SOI device, including a substrate 101 and a buried dielectric layer 102 on the substrate 101, with a drift region 106 disposed on the buried dielectric layer 102. In one embodiment of this application, the buried dielectric layer 102 is a buried oxide layer, which may be made of silicon oxide, such as silicon dioxide. In one embodiment of this application, the substrate 101 is a silicon substrate of a second conductivity type.

[0043] In one embodiment of this application, the bottom of the first conductivity type doped region 105 extends to the top of the buried dielectric layer 102. In one embodiment of this application, the bottom of the first conductivity type buried region 103 extends to the top of the buried dielectric layer 102. In one embodiment of this application, the first conductivity type buried region 103 is located within the second conductivity type doped region 104.

[0044] The cathode and gate structures of the depletion-type anode short-circuit lateral insulated gate bipolar transistor provided in this application can adopt the cathode and gate structures of LIGBTs known to those skilled in the art, with the cathode structure, gate structure, and the aforementioned anode structure arranged sequentially along the lateral side of the device. Figure 1 In the illustrated embodiment, the anode-short-circuited lateral insulated-gate bipolar transistor further includes a second conductivity type well region 108, an emitter substrate lead-out 109, and an emitter region 110. The collector well 107 is located between the second conductivity type well region 108 and the first conductivity type doped region 105. The emitter substrate lead-out 109 is located in the second conductivity type well region 108 and has a second conductivity type. The emitter region 110 is located in the second conductivity type well region 108, serving as the emitter lead-out of the device, and has a first conductivity type. The second conductivity type well region 108 is the region where the inversion layer channel is formed, directly affecting the gate threshold voltage and also influencing drift region depletion. Figure 1 In the illustrated embodiment, the second conductivity type well region 108 is located in the drift region 106. The emitter region 110 is located between the emitter substrate lead-out 109 and the collector well 107. The emitter substrate lead-out 109 and the emitter region 110 are disposed close to the upper surface of the second conductivity type well region 108. A metal electrode 116 connects the emitter region 110 and the emitter substrate lead-out 109 together to form a short-circuit connection.

[0045] See Figure 1In this embodiment, the gate structure is a planar gate structure disposed between the emitter region 110 and the collector region well 107, including a gate dielectric layer 114 and a gate 115. The gate dielectric layer 114 covers a portion of the second conductivity type well region 108, and the gate 115 is located on the gate dielectric layer 114. In one embodiment, the gate dielectric layer 114 may comprise conventional dielectric materials such as silicon oxides, nitrides, and oxynitrides having a dielectric constant from about 4 to about 20 (measured in vacuum), or the gate dielectric layer 114 may comprise a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs). In one embodiment of this application, the gate 115 is made of polysilicon, and the threshold voltage of the device can be adjusted by doping the polysilicon; in other embodiments, metals, metal nitrides, metal silicides or similar compounds may also be used as the material of the gate 115.

[0046] exist Figure 1 In the embodiment shown, drift region 106 is an N-drift region, emitter region 110 and anode region 112 are both N+ regions, emitter substrate lead-out 109 and collector region 111 are both P+ regions, second conductivity type doped region 104 is a P- region, and first conductivity type buried region 103 is an N-type buried layer.

[0047] This application provides a method for manufacturing a depletion-type anode short-circuit lateral insulated gate bipolar transistor, which can be used to manufacture the depletion-type anode short-circuit lateral insulated gate bipolar transistor described in any of the foregoing embodiments. Figure 2 This is a flowchart of a method for manufacturing a depletion-type anode short-circuited lateral insulated gate bipolar transistor in one embodiment, including the following steps:

[0048] S210, Obtain the substrate.

[0049] A wafer is obtained as a substrate, and the substrate has a drift region of a first conductivity type and a buried region of a first conductivity type.

[0050] In one embodiment of this application, step S210 involves obtaining an SOI wafer on a substrate having a buried dielectric layer, a drift region, and a first conductivity type buried region formed on the buried dielectric layer. In other embodiments, the SOI wafer may be obtained firstly, and then the first conductivity type buried region may be formed on the buried dielectric layer by ion implantation (or high-energy ion implantation).

[0051] In one embodiment of this application, the first conductivity type is N-type and the second conductivity type is P-type; correspondingly, the substrate is a P-type silicon substrate, and the drift region is an N-drift region. In other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type.

[0052] In one embodiment of this application, the burial medium layer is a buried oxide layer, and its material is silicon oxide, such as silicon dioxide.

[0053] S220 is formed in the substrate by ion implantation to create a doped region of the second conductivity type.

[0054] The second conductivity type doped region is in direct contact with the first conductivity type buried region. The second conductivity type doped region may be formed by high-energy ion implantation and / or by push-in after ion implantation. In one embodiment of this application, the first conductivity type buried region is located within the second conductivity type doped region. In one embodiment of this application, the bottom of the first conductivity type buried region extends to the top of the buried dielectric layer.

[0055] S230 forms the collector region and the anode region.

[0056] The current collector and anode regions are formed by photolithography and ion implantation. The current collector region is located in the drift region and has a second conductivity type. The anode region has a first conductivity type and is located above the first conductivity type buried region. At least a portion of the second conductivity type doped region is located between the anode region and the drift region.

[0057] The above-mentioned manufacturing method of depletion-type anode short-circuit lateral insulated gate bipolar transistor introduces a low-concentration second conductivity type doped region as a depletion region between the anode region and the drift region. At the same time, the second conductivity type doped region is depleted by a first conductivity type buried region. This is equivalent to increasing the resistance between the anode region and the drift region through the isolation of the depletion region, thus improving the voltage foldback phenomenon of the device.

[0058] In one embodiment of this application, prior to step S230, a step of forming a first conductivity type doped region in the substrate by ion implantation is included. Specifically, the first conductivity type ions can be implanted into the semiconductor structure on the buried dielectric layer by high-energy ion implantation, and / or a well is pushed in after ion implantation to form the first conductivity type doped region. The first conductivity type doped region is formed on the side of the second conductivity type doped region near the collector region, and the first conductivity type doped region is in direct contact with the second conductivity type doped region. The implantation concentration of the first conductivity type doped region is greater than the implantation concentration of the second conductivity type doped region.

[0059] In one embodiment of this application, prior to step S230, a step of forming a collector well in the drift region by photolithography and ion implantation is included. The collector well has a first conductivity type. The collector region formed in step S230 is formed within the collector well. In one embodiment of this application, the collector well can be formed after the first conductivity type buried region, the first conductivity type doped region, and the second conductivity type doped region are formed.

[0060] In one embodiment of this application, prior to step S230, a step of forming a second conductivity type well region is included. The second conductivity type well region can be formed in the drift region by photolithography and ion implantation. The collector well is located between the second conductivity type well region and the first conductivity type doped region.

[0061] In one embodiment of this application, the method further includes the step of forming an emitter substrate lead-out and an emitter region in a well region of a second conductivity type. The emitter substrate lead-out has a second conductivity type, and the emitter region has a first conductivity type. In one embodiment of this application, the emitter substrate lead-out may be formed simultaneously with the collector region. In one embodiment of this application, the emitter region may be formed simultaneously with the anode region.

[0062] In one embodiment of this application, the method for manufacturing an anode-short-circuit lateral insulated gate bipolar transistor further includes the step of forming a gate structure. A gate dielectric layer can be formed first, and then the gate can be formed on the gate dielectric layer. In one embodiment of this application, the gate dielectric layer covers a portion of the second conductivity type well region. In one embodiment of this application, the gate dielectric layer is made of silicon oxide, such as silicon dioxide; the gate is made of polysilicon. In one embodiment of this application, the gate structure can be formed after the formation of the collector well and the second conductivity type well region, and before step S230.

[0063] In one embodiment of this application, field oxidation can also be performed after the formation of the collector region well and the second conductivity type well region and before the formation of the gate, to form an oxide layer outside the active region.

[0064] In one embodiment of this application, after step S230, a step of forming an interlayer dielectric (ILD) layer on the wafer surface is further included. Then, by an etching process, contact holes penetrating the ILD are etched at the structures that need to be led out to the device surface, and finally metal electrodes (electrodes such as anode region, collector region, emitter region, and emitter substrate leads out) are formed.

[0065] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0066] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0067] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0068] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A depletion-type anode short-circuited lateral insulated gate bipolar transistor, characterized in that, include: The drift region has the first type of conductivity. A current-collecting region, located in the drift region, has a second conductivity type, wherein the first conductivity type and the second conductivity type are opposite conductivity types; The anode region has a first conductivity type; a portion of the drift region is located between the current collector region and the anode region; The second conductivity type doped region is in direct contact with the anode region, and at least a portion of it is located between the anode region and the drift region, with a portion of the second conductivity type doped region located between the collector region and the anode region; the doping concentration of the second conductivity type doped region is less than the doping concentration of the collector region; The first conductivity type buried region is located below the anode region and is in direct contact with the second conductivity type doped region; the majority carrier concentration of the first conductivity type buried region is greater than the majority carrier concentration of the second conductivity type doped region.

2. The depletion-type anode short-circuited lateral insulated gate bipolar transistor according to claim 1, characterized in that, The second conductivity type doped region is used to form a depletion layer during operation, and the first conductivity type buried region is used to assist in the depletion of the second conductivity type doped region during operation.

3. The depletion-type anode short-circuited lateral insulated gate bipolar transistor according to claim 1, characterized in that, It also includes a first conductivity type doped region, which is located on the side of the second conductivity type doped region near the collector region, and the first conductivity type doped region is in direct contact with the second conductivity type doped region. The doping concentration of the first conductivity type doped region is greater than the doping concentration of the drift region, and the majority carrier concentration of the first conductivity type doped region is greater than the majority carrier concentration of the second conductivity type doped region.

4. The depletion-type anode short-circuited lateral insulated gate bipolar transistor according to claim 3, characterized in that, The first conductivity type doped region is used to assist in the depletion of the second conductivity type doped region during operation.

5. The depletion-type anode short-circuited lateral insulated gate bipolar transistor according to claim 3, characterized in that, It also includes an anode channel region having a first conductivity type; the anode channel region is disposed in a second conductivity type doped region and is located between the anode region and the first conductivity type doped region.

6. The depletion-type anode short-circuited lateral insulated gate bipolar transistor according to claim 3, characterized in that, The anode-short-circuited lateral insulated-gate bipolar transistor is an SOI device, and the anode-short-circuited lateral insulated-gate bipolar transistor further includes: Substrate; A buried dielectric layer is disposed on the substrate; The drift region is located on the buried dielectric layer; the bottom of the first conductivity type doped region extends to the buried dielectric layer, and / or the bottom of the first conductivity type buried region extends to the buried dielectric layer.

7. The depletion-type anode short-circuited lateral insulated gate bipolar transistor according to claim 3, characterized in that, Also includes: A collector well, disposed in the drift region, has a first conductivity type, and the collector region is disposed in the collector well; Second type of conductivity well region; The emitter substrate is led out and has a second conductivity type, located in the well region of the second conductivity type; The emitter region, having a first conductivity type, is located within the well region of the second conductivity type.

8. The depletion-type anode short-circuited lateral insulated gate bipolar transistor according to claim 7, characterized in that, The current collector well is separated from the first conductivity type doped region by a portion of the drift region; and / or the anode region is located in the second conductivity type doped region; and / or the first conductivity type buried region is located in the second conductivity type doped region.

9. A method for manufacturing a depletion-type anode short-circuited lateral insulated gate bipolar transistor, comprising: A substrate is obtained, the substrate having a drift region of a first conductivity type and a buried region of a first conductivity type; A second conductivity type doped region is formed in the substrate by ion implantation, and the second conductivity type doped region is in direct contact with the first conductivity type buried region; A current collector region and an anode region are formed; the current collector region is located in the drift region and has a second conductivity type; the anode region has a first conductivity type; the anode region is located above the first conductivity type buried region, a small portion of the second conductivity type doped region is located between the anode region and the drift region, a portion of the drift region is located between the current collector region and the anode region, and a portion of the second conductivity type doped region is located between the current collector region and the anode region; the first conductivity type and the second conductivity type are opposite conductivity types.

10. The method for manufacturing a depletion-type anode short-circuited lateral insulated gate bipolar transistor according to claim 9, characterized in that, Before the steps of forming the current collector region and the anode region, the method further includes the step of forming a first conductivity type doped region in the substrate by ion implantation. The first conductivity type doped region is formed on the side of the second conductivity type doped region close to the current collector region. The first conductivity type doped region is in direct contact with the second conductivity type doped region. The doping concentration of the first conductivity type doped region is greater than the doping concentration of the drift region. The implantation concentration of the first conductivity type doped region is greater than the implantation concentration of the second conductivity type doped region.

Images