A semiconductor structure, a preparation method thereof, and a semiconductor memory

Abstract

This disclosure provides a semiconductor structure and its fabrication method, as well as a semiconductor memory. The semiconductor structure includes: a substrate; a stacked structure formed on the substrate; wherein the stacked structure includes multiple device structures and multiple word line structures, the device structures extending along a first direction, and the word line structures extending along a second direction; the device structures sequentially include a capacitor region and an active region; multiple bit line structures formed in the stacked structure, and the bit line structures extending along a third direction; wherein the bit line structures sequentially pass through active regions arranged along a third direction in different stacked layers, and any two adjacent bit line structures are at least partially staggered along the second direction, the first direction and the second direction are located in a plane parallel to the surface of the substrate, and the third direction is perpendicular to the surface of the substrate. This disclosure can reduce bit line capacitance and improve the sensing margin of the device.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method, and a semiconductor memory. Background Technology

[0002] Sensing margin is one of the important characteristic parameters of Dynamic Random Access Memory (DRAM). Currently, as DRAM device sizes continue to shrink, the sensing margin deteriorates, limiting further improvements in memory performance. Summary of the Invention

[0003] This disclosure provides a semiconductor structure and its fabrication method, as well as a semiconductor memory, which can reduce bit line capacitance and improve the sensing margin of the device.

[0004] In a first aspect, embodiments of this disclosure provide a semiconductor structure, including:

[0005] Substrate;

[0006] A stacked structure formed above the substrate; wherein the stacked structure includes multiple device structures and multiple word line structures, the device structures extending along a first direction, and the word line structures extending along a second direction; the device structures sequentially include a capacitor region and an active region;

[0007] Multiple bit line structures are formed in the stacked structure, and the bit line structures extend along a third direction; wherein the bit line structures pass sequentially through the active regions arranged along the third direction in different stacked layers, wherein any two adjacent bit line structures are at least partially staggered along a second direction, the first direction and the second direction are located in a plane parallel to the surface of the substrate, and the third direction is perpendicular to the surface of the substrate.

[0008] In some embodiments, every n bitline structures form a staggered unit;

[0009] In the first direction, for the first to the a-th bit line structures of the staggered unit, the distance from each bit line structure to the word line structure on the first side gradually increases; for the a-th to the n-th bit line structures of the staggered unit, the distance from each bit line structure to the word line structure on the first side gradually decreases.

[0010] Wherein, the first side is either the extension direction opposite to the first direction or the extension direction along the first direction; a and n are both integers greater than 1, and a is less than n.

[0011] In some embodiments, every n bitline structures form a staggered unit;

[0012] In the first direction, for the staggered unit, the distance from each bit line structure to the word line structure on the first side gradually increases; wherein, the first side is either the extension direction opposite to the first direction or the extension direction along the first direction; n is an integer greater than 1.

[0013] In some embodiments, in the second direction, two adjacent bit line structure portions are staggered;

[0014] The relative area of ​​two adjacent bit line structures is less than one-third of the projected area of ​​the bit line structure.

[0015] In some embodiments, in the second direction, two adjacent bit line structures are completely staggered;

[0016] In this case, the relative area of ​​two adjacent bitline structures is zero.

[0017] In some embodiments, the bit line structure includes a barrier layer outer wall and a metallic material filling the barrier layer outer wall; wherein the barrier layer material includes titanium nitride and the metallic material includes tungsten.

[0018] Secondly, embodiments of this disclosure provide a method for fabricating a semiconductor structure, including:

[0019] Provide substrate;

[0020] An initial stacked structure is formed over the substrate, and the initial stacked structure includes multiple stacked layers;

[0021] Multiple device structures, multiple word line structures, and multiple bit line structures are formed in the initial stacked structure;

[0022] The device structure extends along a first direction, the word line structure extends along a second direction, and the bit line structure extends along a third direction. The device structure sequentially includes a capacitor region and an active region. The bit line structure sequentially passes through the active regions arranged along the third direction in different stacked layers. Any two adjacent bit line structures are at least partially staggered along the second direction. The first direction and the second direction are located in a plane parallel to the surface of the substrate, and the third direction is perpendicular to the surface of the substrate.

[0023] In some embodiments, forming an initial stacked structure over the substrate includes:

[0024] An insulating layer and a silicon layer are sequentially formed on the substrate to obtain the stacked layer;

[0025] The steps of sequentially forming an insulating layer and a silicon layer on the substrate are repeated to form the initial stacked structure;

[0026] Multiple silicide regions are formed in the silicon layer along a second direction, and bit line structures sequentially pass through the silicide regions in different stacked layers.

[0027] In some embodiments, after forming a plurality of silicide regions arranged in a second direction in the silicon layer, the method further includes:

[0028] A mask layer is formed above the initial stacked structure, and a preset pattern is formed on the mask layer; wherein the preset pattern is at least partially staggered along a second direction;

[0029] The preset pattern is transferred to the initial stacked structure using the mask layer, and the mask layer is removed to form multiple trenches; wherein the trenches pass through the insulating layer and the silicide region in sequence;

[0030] The trenches are filled to form multiple bitline structures.

[0031] In some embodiments, the preset pattern includes at least one staggered unit, and each staggered unit includes n bitline patterns;

[0032] In the first direction, for the first to the a-th bit line patterns of the staggered unit, the distance from each bit line pattern to the word line structure on the first side gradually increases; for the a-th to the n-th bit line patterns of the staggered unit, the distance from each bit line pattern to the word line structure on the first side gradually decreases.

[0033] Wherein, the first side is either the extension direction opposite to the first direction or the extension direction along the first direction; a and n are both integers greater than 1, and a is less than n.

[0034] In some embodiments, the preset pattern includes at least one staggered unit, and each staggered unit includes n bitline patterns;

[0035] In the first direction, for the staggered unit, the distance from each line pattern to the word line structure on the first side gradually increases; wherein, the first side is either the extension direction opposite to the first direction or the extension direction along the first direction; n is an integer greater than 1.

[0036] In some embodiments, in the second direction, two adjacent bit line pattern portions are staggered;

[0037] The relative area of ​​two adjacent bit line patterns is less than one-third of the projected area of ​​the bit line pattern.

[0038] In some embodiments, in the second direction, two adjacent bit line patterns are completely staggered;

[0039] In this case, the relative area of ​​two adjacent bitline patterns is zero.

[0040] In some embodiments, the filling process of the trench to form a plurality of the bit line structures includes:

[0041] A barrier layer outer wall is formed in the trench;

[0042] Metal material is filled into the hollow area surrounded by the outer wall of the barrier layer to form multiple bit line structures.

[0043] Thirdly, embodiments of this disclosure provide a semiconductor memory, including the semiconductor structure described in any of the first aspects.

[0044] This disclosure provides a semiconductor structure and its fabrication method, as well as a semiconductor memory. The semiconductor structure includes: a substrate; a stacked structure formed on the substrate; wherein the stacked structure includes multiple device structures and multiple word line structures, the device structures extending along a first direction, and the word line structures extending along a second direction; the device structures sequentially include a capacitor region and an active region; multiple bit line structures formed in the stacked structure, and the bit line structures extending along a third direction; wherein the bit line structures sequentially pass through active regions arranged along the third direction in different stacked layers, and any two adjacent bit line structures are at least partially staggered along the second direction, the first direction and the second direction are located in a plane parallel to the surface of the substrate, and the third direction is perpendicular to the surface of the substrate. In this way, bit line structures at least partially staggered along the second direction are formed in the semiconductor structure, which can reduce bit line capacitance and improve the sensing margin of the device. Attached Figure Description

[0045] Figure 1 A three-dimensional structural diagram of a semiconductor structure;

[0046] Figure 2 This is a three-dimensional structural diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0047] Figure 3 This is a schematic diagram of the composition of a semiconductor structure provided in an embodiment of the present disclosure;

[0048] Figure 4 A schematic diagram of a staggered unit provided in an embodiment of this disclosure. Figure 1 ;

[0049] Figure 5 A schematic diagram of a staggered unit provided in an embodiment of this disclosure. Figure 2 ;

[0050] Figure 6This is a comparative schematic diagram of a bitline structure provided in an embodiment of the present disclosure;

[0051] Figure 7 A schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0052] Figure 8 A schematic diagram of the fabrication process of a semiconductor structure provided in this disclosure embodiment. Figure 1 ;

[0053] Figure 9 A schematic diagram of the fabrication process of a semiconductor structure provided in this disclosure embodiment. Figure 2 ;

[0054] Figure 10 A schematic diagram of the fabrication process of a semiconductor structure provided in this disclosure embodiment. Figure 3 ;

[0055] Figure 11 A schematic diagram of the fabrication process of a semiconductor structure provided in this disclosure embodiment. Figure 4 ;

[0056] Figure 12 A schematic diagram of the fabrication process of a semiconductor structure provided in this disclosure embodiment. Figure 5 ;

[0057] Figure 13 A schematic diagram of the fabrication process of a semiconductor structure provided in this disclosure embodiment. Figure 6 ;

[0058] Figure 14 A schematic diagram of the fabrication process of a semiconductor structure provided in this disclosure embodiment. Figure 7 ;

[0059] Figure 15 A schematic diagram of the fabrication process of a semiconductor structure provided in this disclosure embodiment. Figure 8 ;

[0060] Figure 16 This is a schematic diagram of the composition structure of a semiconductor memory provided in an embodiment of this disclosure. Detailed Implementation

[0061] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings.

[0062] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0063] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0064] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0065] As DRAM device dimensions continue to shrink, the distance between its various structural components becomes increasingly smaller, posing challenges to semiconductor memory manufacturing. (See also...) Figure 1 It shows a three-dimensional structural diagram of a semiconductor structure. For example... Figure 1 As shown, the semiconductor structure includes a substrate (not shown), a word line structure 101, a capacitor region 102, and a bit line structure 103. The word line structure 101 and the active region below it together form a transistor. In this case, the pseudocapacitance of the bit line structure is relatively large, which reduces the sensing margin of the device.

[0066] Based on this, embodiments of this disclosure provide a semiconductor structure, including: a substrate; a stacked structure formed on the substrate; wherein the stacked structure includes multiple device structures and multiple word line structures, the device structures extending along a first direction, and the word line structures extending along a second direction; the device structures sequentially include a capacitor region and an active region; multiple bit line structures formed in the stacked structure, and the bit line structures extending along a third direction; wherein the bit line structures sequentially pass through active regions arranged along a third direction in different stacked layers, and any two adjacent bit line structures are at least partially staggered along the second direction, the first direction and the second direction are located in a plane parallel to the surface of the substrate, and the third direction is perpendicular to the surface of the substrate. In this way, bit line structures at least partially staggered along the second direction are formed in the semiconductor structure, which can reduce bit line capacitance and thereby improve the sensing margin of the device.

[0067] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0068] In one embodiment of this disclosure, see [link to embodiment]. Figure 2 This illustrates a three-dimensional structural diagram of a semiconductor structure provided in an embodiment of this disclosure. For example... Figure 2 As shown, the semiconductor structure 200 may include:

[0069] substrate ( Figure 2 (Not shown);

[0070] A stacked structure formed on a substrate; wherein the stacked structure includes a plurality of device structures 21 and a plurality of word line structures 22, the device structures 21 extending along a first direction and the word line structures 22 extending along a second direction; the device structure 21 includes an active region 211 and a capacitor region 212 in sequence.

[0071] Multiple bit line structures 23 are formed in the stacked structure and extend along a third direction; wherein the bit line structures 23 pass through active regions 211 arranged along the third direction in different stacked layers in sequence, wherein any two adjacent bit line structures 23 are at least partially staggered along a second direction, the first direction and the second direction are located in a plane parallel to the surface of the substrate, and the third direction is perpendicular to the surface of the substrate.

[0072] It should be noted that this semiconductor structure 200 can be applied to Dynamic Random Access Memory (DRAM), such as Three Dimensional DRAM (3D DRAM), in which multiple spatially stacked semiconductor structures 200 are formed. Currently, to improve the sensing margin of a device, the sensing margin can be improved by increasing the capacitor capacitance or by decreasing the bit line capacitance. This embodiment of the present disclosure aims to improve the sensing margin by reducing the bit line capacitance through staggering the bit line structures 23.

[0073] It should be noted that the substrate can be a silicon substrate or other semiconductor elements, such as germanium (Ge), or include semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb), or include other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or combinations thereof. The embodiments disclosed herein do not specifically limit this.

[0074] It should be noted that, as Figure 2As shown, the stacked structure may include a device structure 21, a word line structure 22, and a bit line structure 23. The device structure 21 may also include an active region 211 and a capacitor region 212. The first direction refers to the direction extending along the device structure 21, the second direction refers to the direction extending along the word line structure 22, and the third direction refers to the direction extending along the bit line structure 23.

[0075] The active region 211 can be made of silicon (Si), which can be further divided into multiple doped regions. Different doped regions have different doping types, such as N-type doping (providing free electrons) and P-type doping (providing holes). N-type doping can be doped with pentavalent impurity elements such as phosphorus, antimony, and arsenic; P-type doping can be doped with trivalent impurity elements such as boron, gallium, and indium.

[0076] See Figure 3 This illustrates a schematic diagram of the composition of a semiconductor structure provided in an embodiment of this disclosure. For example... Figure 2 and Figure 3 As shown, each word line structure 22 passes through multiple active regions 211 of the same stacked layer. The active regions 211 located below the word line structure 22 have different doping types than the active regions 211 located on both sides of the word line structure 22, thus forming a transistor. Simultaneously, the word line structure 22 leads out the gate of the transistor. The bit line structure 23 passes through multiple active regions 211 of different stacked layers, thus leading out the drain / source of the transistor. Specifically, in... Figure 2 In this embodiment, two adjacent transistors share a single bit line structure 23. The bit line structures 23 are staggered, which can reduce bit line capacitance and improve the device's sensing margin.

[0077] In a specific example, every n bitline structures 23 can form a staggered unit. In the first direction, for the 1st to the ath bitline structures 23 of the staggered unit, the distance from each bitline structure 23 to the word line structure 22 on the first side gradually increases; for the ath to the nth bitline structures 23 of the staggered unit, the distance from each bitline structure 23 to the word line structure 22 on the first side gradually decreases; wherein, the first side is the extension direction opposite to or along the first direction; a and n are both integers greater than 1, and a is less than n.

[0078] It should be noted that, taking n=5 and a=3 as an example, see [link / reference]. Figure 4 It illustrates a schematic diagram of a staggered unit provided in an embodiment of this disclosure. Figure 1 It should be understood that... Figure 4 for Figure 2 A top view of a staggered cell. (Example) Figure 4As shown, for the 1st to 3rd bit line structures 23, the distance between each bit line structure 23 and the word line structure 22 gradually increases; for the 3rd to 5th bit line structures 23, the distance between each bit line structure 23 and the word line structure 22 gradually decreases. Alternatively, the staggered unit may also include 7 bit line structures 23; correspondingly, for the 1st to 4th bit line structures 23, the distance between each bit line structure 23 and the word line structure 22 gradually increases; for the 4th to 7th bit line structures 23, the distance between each bit line structure 23 and the word line structure 22 gradually decreases; or, the staggered unit may also include 8 bit line structures 23; correspondingly, for the 1st to 4th bit line structures 23, the distance between each bit line structure 23 and the word line structure 22 gradually increases; for the 4th to 8th bit line structures 23, the distance between each bit line structure 23 and the word line structure 22 gradually decreases.

[0079] In another specific example, in the first direction, for staggered units, the distance from each line structure 23 to the word line structure 22 on the first side gradually increases; where the first side is either the extension direction against the first direction or the extension direction along the first direction; n is an integer greater than 1.

[0080] It should be noted that, taking n=5 as an example, see [link / reference]. Figure 5 It illustrates a schematic diagram of a staggered unit provided in an embodiment of this disclosure. Figure 2 .like Figure 5 As shown, the distance between each line structure 23 and the word line structure 22 gradually increases, forming a step-like arrangement.

[0081] Apart from Figure 4 or Figure 5 Besides similar structures, the staggered arrangement of bit line structure 23 has more possibilities, and for the same semiconductor structure, the staggered arrangement of different staggered units can be different. This disclosure does not make specific limitations on the embodiments.

[0082] In some embodiments, in the second direction, two adjacent bit line structures 23 are partially staggered; wherein the relative area of ​​two adjacent bit line structures 23 is less than one-third of the projected area of ​​the bit line structure 23.

[0083] It should be noted that two adjacent bit line structures 23 can be partially staggered, while the relative area remains at a low level, which not only reduces the capacitance, but also reduces the area occupied by the bit line structure 23.

[0084] In other embodiments, in the second direction, two adjacent bit line structures 23 are completely staggered; wherein the relative area of ​​two adjacent bit line structures 23 is zero.

[0085] It should be noted that two adjacent bit line structures 23 can be completely interleaved to achieve the best capacitance reduction effect.

[0086] In some embodiments, the bit line structure 23 further includes a barrier layer outer wall and a metal material filling the barrier layer outer wall; wherein the barrier layer material includes titanium nitride (TiN) and the metal material includes tungsten (W).

[0087] It should be noted that the metallic materials may also include cobalt (Co), copper (Cu), aluminum (Al), etc. The material forming the bit line structure 23 may be a combination of titanium nitride and tungsten, or a combination of other materials. This disclosure does not specifically limit this.

[0088] As can be seen from the above, for semiconductor structure 200, the bit line structures 23 are arranged in an alternating pattern. (See also...) Figure 6 This illustration shows a comparative schematic diagram of a bitline structure provided in an embodiment of this disclosure. Specifically, Figure 6 (a) shows the bitline structure without interleaving. Figure 6 (b) shows the bitline structure 23 with interleaved arrangement. After interleaving... Figure 6 The capacitance value of bit line structure 23 in (b) is Figure 6 The capacitance value of the bit line structure in (a) is 58.4%, and the bit line capacitance is reduced, thereby improving the sensing margin of the semiconductor structure 200.

[0089] This disclosure provides a semiconductor structure, including: a substrate; a stacked structure formed on the substrate; wherein the stacked structure includes multiple device structures and multiple word line structures, the device structures extending along a first direction, and the word line structures extending along a second direction; the device structures sequentially include a capacitor region and an active region; multiple bit line structures formed in the stacked structure, and the bit line structures extending along a third direction; wherein the bit line structures sequentially pass through active regions arranged along the third direction in different stacked layers, and any two adjacent bit line structures are at least partially staggered along the second direction, the first direction and the second direction are located in a plane parallel to the surface of the substrate, and the third direction is perpendicular to the surface of the substrate. Thus, bit line structures at least partially staggered along the second direction are formed in the semiconductor structure, which can reduce bit line capacitance and improve the sensing margin of the device.

[0090] In another embodiment of this disclosure, see Figure 7 This illustration shows a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of this disclosure. Figure 7 As shown, the method may include:

[0091] S301, Provide substrate.

[0092] It should be noted that the preparation method provided in this embodiment is applied to the preparation of the aforementioned semiconductor structure 200, which can be applied in DRAM, such as 3D DRAM.

[0093] In fabricating the semiconductor structure 200, a substrate is first provided. The substrate may be a silicon substrate, or it may include other semiconductor elements, such as germanium (Ge), or include semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or include other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or combinations thereof. This disclosure does not specifically limit the specific application of these elements.

[0094] S302. An initial stacked structure is formed on the substrate, and the initial stacked structure includes multiple stacked layers.

[0095] It should be noted that, see Figure 8 It illustrates a schematic diagram of the fabrication process of a semiconductor structure provided in an embodiment of this disclosure. Figure 1 .exist Figure 8 and subsequent Figures 9-15 In the middle, (a) are all along Figure 3 The cross-sectional view of a-a' in (b) is along Figure 3 A cross-sectional view of line b-b'. It should be understood that... Figure 3 The hollowed-out parts are also filled with material.

[0096] like Figure 8 As shown, after providing the substrate 401, the substrate 401 can first be pre-cleaned, and then an initial stacked structure 40 is formed on the substrate 401. The initial stacked structure 40 includes at least one stacked layer.

[0097] In some embodiments, forming the initial stacked structure over the substrate includes:

[0098] An insulating layer and a silicon layer are sequentially formed on the substrate to obtain a stacked layer;

[0099] The steps of sequentially forming an insulating layer and a silicon layer on the substrate are repeated to form an initial stacked structure;

[0100] Multiple silicide regions are formed in the silicon layer along the second direction, and the bit line structure passes through the silicide regions in different stacked layers in sequence.

[0101] It should be noted that, as Figure 8 As shown, each stacked layer includes an insulating layer 402 and a silicon layer 403, with the silicon layer 403 formed above the insulating layer 402. Specifically, the steps of forming an insulating layer 402 and a silicon layer 403 on top of the substrate 401 are repeated until a stacked layer of the desired number of layers is obtained. In practical applications, the number of stacked layers can be any desired number, and this disclosure does not specifically limit this number.

[0102] It should be noted that the insulating layer 402 can be made of silicon oxide, and the silicon layer 403 can be made of polycrystalline silicon. The insulating layer 402 and the silicon layer 403 can be formed by any of the following deposition processes: epitaxial process, chemical vapor deposition (CVD) process, physical vapor deposition (PVD) process, atomic layer deposition (ALD) process, spin coating process, coating process, or thin film process, etc.; for example, the insulating layer 402 and the silicon layer 403 can be sequentially formed on the semiconductor substrate 401 by an epitaxial process.

[0103] S303. Multiple device structures, multiple word line structures, and multiple bit line structures are formed in the initial stacked structure; wherein, the device structures extend along a first direction, the word line structures extend along a second direction, and the bit line structures extend along a third direction; the device structures sequentially include a capacitor region and an active region; the bit line structures sequentially pass through the active regions arranged along the third direction in different stacked layers, wherein any two adjacent bit line structures are at least partially staggered along the second direction, the first direction and the second direction are located in a plane parallel to the surface of the substrate, and the third direction is perpendicular to the surface of the substrate.

[0104] It should be noted that the order in which multiple device structures, word line structures, and bit line structures are formed in the initial stacking structure can be varied and needs to be determined based on the actual selected process.

[0105] It should be noted that, please refer to Figure 2 , Figure 3 and Figure 8 The silicon layer 403 is subsequently used to form the active regions 211 in the device structure 21. Each word line structure 22 passes through multiple active regions 211 on the same stacked layer. The active regions 211 located below the word line structure 22 have different doping types than the active regions 211 located on both sides of the word line structure 22, thus forming a transistor. The word line structure 22 leads out the gate of the transistor. The bit line structure 23 passes through multiple active regions 211 on different stacked layers, thus leading out the drain / source of the transistor. Specifically, in... Figure 2 In this configuration, two adjacent transistors share a bitline structure 23.

[0106] In some embodiments, after the initial stacked structure 40 is formed, a plurality of silicide regions 404 arranged along a second direction are formed in each silicon layer 403, and the silicide regions 404 are subsequently used to form the bit line structure 23.

[0107] The following exemplarily provides a method for forming a silicide region 404.

[0108] First of all, Figure 8 Based on this, see Figure 9 It illustrates a schematic diagram of the fabrication process of a semiconductor structure provided in an embodiment of this disclosure. Figure 2 .like Figure 9 As shown, after forming the initial stacked structure 40, the initial stacked structure 40 can be subjected to processes such as patterning to form the first trench 406. The patterning process for the initial stacked structure 40 can be as follows: first, a first mask layer is formed above the initial stacked structure 40; then, a first photoresist layer is formed above the first mask layer. The first photoresist layer has a first pattern required to form the first trench 406. The first pattern is transferred to the first mask layer, and the first photoresist layer is removed. Then, using the first mask layer as a mask, the first pattern is transferred back to the initial stacked structure 40, and the first mask layer is removed to form the first trench 406. The removal of the first photoresist layer and the first mask layer can be achieved through etching, and the transfer of the first pattern to the initial stacked structure 40 can also be achieved through etching.

[0109] Secondly, in Figure 9 Based on this, see Figure 10 It illustrates a schematic diagram of the fabrication process of a semiconductor structure provided in an embodiment of this disclosure. Figure 3 .like Figure 10 As shown, after forming the first trench 406, it is necessary to fill the first trench 406 with an insulating material. The insulating material used is the same as the material of the insulating layer 402, which can be silicon oxide. The first trench 406 can be filled using various deposition processes.

[0110] Then, in Figure 10 Based on this, see Figure 11 It illustrates a schematic diagram of the fabrication process of a semiconductor structure provided in an embodiment of this disclosure. Figure 4 .like Figure 11 As shown, after filling the first trench 406, it is necessary to continue forming the second trench 407. The second trench 407 can be formed by etching. An appropriate etching selectivity can be selected to etch away only part of the silicon layer 403, while the insulating layer 402 will not be etched away.

[0111] Finally, Figure 11 Based on this, see Figure 12It illustrates a schematic diagram of the fabrication process of a semiconductor structure provided in an embodiment of this disclosure. Figure 5 .like Figure 12 As shown, after the second trench 407 is formed, it is necessary to fill the second trench 407 with a conductive material, such as metal or polysilicon, to form a silicide region 404. The second trench 407 can be filled by deposition.

[0112] It should be noted that the silicide region 404 can also be formed by metallizing the silicon layer 403 where the bit line structure 23 is to be formed, and then drilling holes in the silicide regions 404 arranged along the second direction to subsequently form the bit line structure 23. In this way, multiple silicide regions 404 are formed by the above method, which can reduce the contact resistance between the bit line structure 23 and the transistor.

[0113] It should also be noted that this application may also omit the silicide region 404, and instead form the bit line structure 23 by directly drilling holes in the silicon layer 403. Furthermore, those skilled in the art may implement this application using any feasible method, and no specific limitations are imposed.

[0114] In some embodiments, after forming a plurality of silicide regions arranged along a second direction in each silicon layer, the method further includes:

[0115] A mask layer is formed above the initial stacked structure, and a preset pattern is formed on the mask layer; wherein the preset pattern is at least partially staggered along a second direction;

[0116] A pre-defined pattern is transferred to the initial stacked structure using a mask layer, and then the mask layer is removed to form multiple trenches; wherein the trenches pass through the insulating layer and the silicide region in sequence;

[0117] The trenches are filled to form multiple bitline structures.

[0118] It should be noted that, in Figure 12 Based on this, see Figure 13 It illustrates a schematic diagram of the fabrication process of a semiconductor structure provided in an embodiment of this disclosure. Figure 6 .like Figure 13 As shown, after forming a plurality of silicide regions 404 arranged along the second direction in each silicon layer 403, a mask layer 408 is first formed on the surface of the initial stacked structure 40, and a preset pattern arranged at least partially staggered along the second direction is formed on the mask layer 408; wherein, the material of the mask layer 408 can be one or more of silicon oxide, silicon nitride, silicon carbide, and silicon oxynitride; the mask layer 408 can be formed by any suitable deposition process.

[0119] exist Figure 13 Based on this, see Figure 14 It illustrates a schematic diagram of the fabrication process of a semiconductor structure provided in an embodiment of this disclosure. Figure 7 .like Figure 14 As shown, after a preset pattern is formed on the mask layer 408, the preset pattern is transferred to the initial stacked structure 40 using the mask layer 408 as a mask, and then the mask layer 408 is removed to obtain the desired result. Figure 14 Multiple trenches 409 are shown. Here, the removal of the mask layer 408 can be achieved through etching, and the transfer of the preset pattern to the initial stacked structure 40 can also be achieved through etching, specifically through dry etching or wet etching. Dry etching can use one or any combination of gases selected from trifluoromethane (CHF3), carbon tetrafluoride (CF4), difluoromethane (CH2F2), hydrobromic acid (HBr), chlorine (Cl2), or sulfur hexafluoride (SF6). Wet etching can use strong acids such as concentrated sulfuric acid, hydrofluoric acid, or concentrated nitric acid.

[0120] It should also be noted that, in Figure 14 In the initial stacked structure 40, the portion located directly below the preset pattern is completely etched to form multiple trenches 409 with a high aspect ratio (HAR), and each trench 409 passes through the insulating layer 402 and the silicide region 404 in sequence.

[0121] exist Figure 14 Based on this, see Figure 15 It illustrates a schematic diagram of the fabrication process of a semiconductor structure provided in an embodiment of this disclosure. Figure 8 .like Figure 15 As shown, after forming the trench 409, the trench 409 needs to be filled to form the bit line structure 23. After forming the bit line structure 23, a chemical mechanical polishing (CMP) process can be performed to make the top surface of the semiconductor structure 200 flat.

[0122] In some embodiments, the filling process of the trench to form multiple bit line structures may include:

[0123] Forming a barrier layer outer wall in the trench;

[0124] Metal material is filled into the hollow area surrounded by the outer wall of the barrier layer to form multiple bit line structures.

[0125] It should be noted that, as Figure 15As shown, the material of the outer wall 4051 of the barrier layer may include titanium nitride, and the metal material 4052 may include tungsten; the metal material 4052 may also include cobalt (Co), copper (Cu), aluminum (Al), etc. The material forming the bit line structure 23 may be a combination of titanium nitride and tungsten, or a combination of other materials. This disclosure does not specifically limit this.

[0126] In particular, in order to form a staggered bit line structure, the preset patterns used to form the groove 409 (which will subsequently form the bit line structure) are staggered, as explained below.

[0127] In some embodiments, the preset patterns are at least partially staggered along a second direction. The preset patterns include at least one staggered unit, and each staggered unit includes n bit line patterns, which correspond to the plurality of bit line structures formed.

[0128] In some embodiments, the preset pattern includes at least one staggered unit, and each staggered unit includes n bit line patterns; in a first direction, for the 1st to the ath bit line patterns of the staggered unit, the distance from each bit line pattern to the word line structure on the first side gradually increases; for the ath to the nth bit line patterns of the staggered unit, the distance from each bit line pattern to the word line structure on the first side gradually decreases; wherein, the first side is an extension direction opposite to the first direction or an extension direction along the first direction; a and n are both integers greater than 1, and a is less than n.

[0129] In some embodiments, the bit line pattern can also form a pattern similar to a stepped arrangement. In some embodiments, the preset pattern includes at least one staggered unit, and each staggered unit includes n bit line patterns. In a first direction, for each staggered unit, the distance from each bit line pattern to the word line structure on the first side gradually increases. Wherein, the first side is the extension direction against the first direction or the extension direction along the first direction; n is an integer greater than 1.

[0130] In some embodiments, in the second direction, two adjacent bit line patterns are partially staggered; wherein the relative area of ​​two adjacent bit line patterns is less than one-third of the projected area of ​​the bit line pattern.

[0131] In some embodiments, in the second direction, two adjacent bit line patterns are completely staggered; wherein the relative area of ​​two adjacent bit line patterns is zero.

[0132] This disclosure provides a method for fabricating a semiconductor structure. The semiconductor structure fabricated using this method first forms an initial stacked structure above a substrate, the initial stacked structure comprising multiple stacked layers. Then, multiple device structures, multiple word line structures, and multiple bit line structures are formed within the initial stacked structure. The device structures extend along a first direction, the word line structures extend along a second direction, and the bit line structures extend along a third direction. Each device structure sequentially includes a capacitance region and an active region. The bit line structures sequentially pass through the active regions arranged along the third direction in different stacked layers. Any two adjacent bit line structures are at least partially staggered along the second direction. The first and second directions are located in a plane parallel to the surface of the substrate, and the third direction is perpendicular to the surface of the substrate. This forms a bit line structure that is at least partially staggered along the second direction in the semiconductor structure, which can reduce bit line capacitance and thus improve the sensing margin of the device.

[0133] In another embodiment of this disclosure, see Figure 16 This illustrates a schematic diagram of the structural composition of a semiconductor memory 400 provided in an embodiment of this disclosure. For example... Figure 16 As shown, the semiconductor memory 400 includes the semiconductor structure 200 described in any of the foregoing embodiments.

[0134] In some embodiments, the semiconductor memory 400 may be 3D DRAM.

[0135] For the semiconductor memory 400, since it includes the semiconductor structure 200 described in the foregoing embodiments, the semiconductor structure includes: a substrate; a stacked structure formed on the substrate; wherein the stacked structure includes multiple device structures and multiple word line structures, the device structures extending along a first direction, and the word line structures extending along a second direction; the device structures sequentially include a capacitor region and an active region; multiple bit line structures formed in the stacked structure, and the bit line structures extending along a third direction; wherein the bit line structures sequentially pass through active regions arranged along a third direction in different stacked layers, and any two adjacent bit line structures are at least partially staggered along the second direction, the first direction and the second direction are located in a plane parallel to the surface of the substrate, and the third direction is perpendicular to the surface of the substrate. Thus, bit line structures arranged at least partially staggered along the second direction are formed in the semiconductor structure, which can reduce bit line capacitance and improve the sensing margin of the device.

[0136] For details not disclosed in the embodiments of this disclosure, please refer to the description of the foregoing embodiments for understanding.

[0137] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0138] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0139] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0140] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0141] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0142] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0143] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A stacked structure formed above the substrate; wherein the stacked structure includes multiple device structures and multiple word line structures, the device structures extending along a first direction, and the word line structures extending along a second direction; the device structures sequentially include a capacitor region and an active region; Multiple bit line structures are formed in the stacked structure, and the bit line structures extend along a third direction; wherein the bit line structures pass sequentially through the active regions arranged along the third direction in different stacked layers, wherein any two adjacent bit line structures are at least partially staggered along a second direction, the first direction and the second direction are located in a plane parallel to the surface of the substrate, and the third direction is perpendicular to the surface of the substrate.

2. The semiconductor structure according to claim 1, characterized in that, Every n bitline structures form a staggered unit; In the first direction, for the first to the a-th bit line structures of the staggered unit, the distance from each bit line structure to the word line structure on the first side gradually increases; for the a-th to the n-th bit line structures of the staggered unit, the distance from each bit line structure to the word line structure on the first side gradually decreases. Wherein, the first side is either the extension direction opposite to the first direction or the extension direction along the first direction; a and n are both integers greater than 1, and a is less than n.

3. The semiconductor structure according to claim 1, characterized in that, Every n bitline structures form a staggered unit; In the first direction, for the staggered unit, the distance from each bit line structure to the word line structure on the first side gradually increases; wherein, the first side is either the extension direction opposite to the first direction or the extension direction along the first direction; n is an integer greater than 1.

4. The semiconductor structure according to claim 2 or 3, characterized in that, In the second direction, two adjacent bit line structure portions are staggered; The relative area of ​​two adjacent bit line structures is less than one-third of the projected area of ​​the bit line structure.

5. The semiconductor structure according to claim 4, characterized in that, In the second direction, two adjacent bit line structures are completely staggered; In this case, the relative area of ​​two adjacent bitline structures is zero.

6. The semiconductor structure according to claim 5, characterized in that, The bit line structure includes a barrier layer outer wall and a metal material filling the barrier layer outer wall; wherein the barrier layer material includes titanium nitride and the metal material includes tungsten.

7. A method for fabricating a semiconductor structure, characterized in that, The method includes: Provide substrate; An initial stacked structure is formed over the substrate, and the initial stacked structure includes multiple stacked layers; Multiple device structures, multiple word line structures, and multiple bit line structures are formed in the initial stacked structure; The device structure extends along a first direction, the word line structure extends along a second direction, and the bit line structure extends along a third direction. The device structure sequentially includes a capacitor region and an active region. The bit line structure sequentially passes through the active regions arranged along the third direction in different stacked layers. Any two adjacent bit line structures are at least partially staggered along the second direction. The first direction and the second direction are located in a plane parallel to the surface of the substrate, and the third direction is perpendicular to the surface of the substrate.

8. The method according to claim 7, characterized in that, The formation of the initial stacked structure over the substrate includes: An insulating layer and a silicon layer are sequentially formed on the substrate to obtain the stacked layer; The steps of sequentially forming an insulating layer and a silicon layer on the substrate are repeated to form the initial stacked structure; Multiple silicide regions are formed in the silicon layer along a second direction, and bit line structures sequentially pass through the silicide regions in different stacked layers.

9. The method according to claim 8, characterized in that, After forming a plurality of silicide regions arranged along a second direction in the silicon layer, the method further includes: A mask layer is formed above the initial stacked structure, and a preset pattern is formed on the mask layer; wherein the preset pattern is at least partially staggered along a second direction; The preset pattern is transferred to the initial stacked structure using the mask layer, and the mask layer is removed to form multiple trenches; wherein the trenches pass through the insulating layer and the silicide region in sequence; The trenches are filled to form multiple bitline structures.

10. The method according to claim 9, characterized in that, The preset pattern includes at least one staggered unit, and each staggered unit includes n bit line patterns. In the first direction, for the first to the a-th bit line patterns of the staggered unit, the distance from each bit line pattern to the word line structure on the first side gradually increases; for the a-th to the n-th bit line patterns of the staggered unit, the distance from each bit line pattern to the word line structure on the first side gradually decreases. Wherein, the first side is either the extension direction opposite to the first direction or the extension direction along the first direction; a and n are both integers greater than 1, and a is less than n.

11. The method according to claim 9, characterized in that, The preset pattern includes at least one staggered unit, and each staggered unit includes n bit line patterns. In the first direction, for the staggered unit, the distance from each line pattern to the word line structure on the first side gradually increases; wherein, the first side is either the extension direction opposite to the first direction or the extension direction along the first direction; n is an integer greater than 1.

12. The method according to claim 10 or 11, characterized in that, In the second direction, two adjacent bit line pattern portions are staggered; The relative area of ​​two adjacent bit line patterns is less than one-third of the projected area of ​​the bit line pattern.

13. The method according to claim 12, characterized in that, In the second direction, two adjacent bit line patterns are completely staggered; In this case, the relative area of ​​two adjacent bitline patterns is zero.

14. The method according to claim 9, characterized in that, The filling process of the trenches to form multiple bitline structures includes: A barrier layer outer wall is formed in the trench; Metal material is filled into the hollow area surrounded by the outer wall of the barrier layer to form multiple bit line structures.

15. A semiconductor memory, characterized in that, Includes the semiconductor structure as described in any one of claims 1 to 6.

Images