Semiconductor structure, method of forming the same, and three-dimensional memory

Abstract

The application discloses a semiconductor structure, a forming method thereof and a three-dimensional memory, and relates to the technical field of semiconductor structures. The forming method of the semiconductor structure comprises the following steps: providing a substrate, wherein the substrate is provided with a bit line metal layer; forming a first support layer, wherein a word line metal layer is formed on the surface of the first support layer; the first support layer supports the word line metal layer; and forming an active layer, wherein the upper surface of the active layer is connected with a storage unit, the lower surface of the active layer is connected with the bit line metal layer, and the active layer at least partially surrounds the word line metal layer. According to the forming method of the semiconductor structure, the process is simple, the active layer of the formed semiconductor structure can at least partially surround the word line metal layer, the performance of the semiconductor structure can be improved, and the semiconductor structure can be further miniaturized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure, a forming method thereof and a three-dimensional memory with the semiconductor structure. BACKGROUND

[0002] The semiconductor structure of the related art has a small channel width. In order to improve the performance of the semiconductor structure, the transistor performance is enhanced by forming a gate-all-around (GAA) transistor architecture. However, the bit line structure in the GAA transistor and the process of forming the word line structure in self-alignment are complex, and it is difficult to form a three-dimensional stacked structure. SUMMARY

[0003] The present application aims to provide a forming method of a semiconductor structure, which is simple in process and can improve the performance of the semiconductor structure by allowing an active layer to at least partially surround a word line metal layer, thereby achieving further miniaturization of the semiconductor structure.

[0004] The forming method of the semiconductor structure according to an embodiment of the present application comprises: providing a substrate, the substrate being provided with a bit line metal layer; forming a first support layer, the first support layer being provided with a word line metal layer on the surface thereof; the first support layer supporting the word line metal layer; forming an active layer, the upper surface of the active layer being connected to a storage unit, the lower surface of the active layer being connected to the bit line metal layer, and the active layer at least partially surrounding the word line metal layer.

[0005] According to some embodiments of the present application, the step of forming the bit line metal layer comprises: forming a bit line trench extending in a first direction on the substrate; and forming the bit line metal layer in the bit line trench.

[0006] According to some embodiments of the present application, the substrate comprises a substrate and an oxide layer formed on the substrate, and the bit line trench is formed in the oxide layer.

[0007] According to some embodiments of the present application, the step of forming the word line metal layer comprises: forming a first sacrificial layer on the surface of the substrate and the bit line metal layer; forming a word line initial metal layer on the surface of the first sacrificial layer and the first support layer; forming a word line isolation trench extending in a second direction, the word line isolation trench penetrating through the word line initial metal layer and the first sacrificial layer to form the word line metal layer on the word line initial metal layer.

[0008] According to some embodiments of the present application, in the step of forming the first support layer, the first support layer is formed in the first sacrificial layer and on the substrate, and after the word line metal layer is formed, the first sacrificial layer is removed, and the first support layer supports the word line metal layer.

[0009] According to some embodiments of the present invention, the first support layer extends along the first direction and is at least partially located within the substrate and formed between the bit line metal layers.

[0010] According to some embodiments of the present invention, the method for forming the semiconductor structure further includes: forming a word line isolation structure within the word line isolation trench.

[0011] According to some embodiments of the present invention, the step of forming an active layer includes: forming a second sacrificial layer on the surface of the word line metal layer; forming a second support layer within the second sacrificial layer; removing the first sacrificial layer and the second sacrificial layer; and forming the active layer on the surface of the bit line metal layer and the surface of the word line metal layer.

[0012] According to some embodiments of the present invention, in the step of forming the word line isolation trench, the word line isolation trench penetrates the second sacrificial layer, the initial word line metal layer and the first sacrificial layer; after removing the first sacrificial layer and the second sacrificial layer, the first support layer, the word line isolation structure and the second support layer support the word line metal layer.

[0013] According to some embodiments of the present invention, before forming the active layer, a gate oxide layer is further formed on the surface of the word line metal layer.

[0014] According to some embodiments of the present invention, the active layer is ion implanted to form source / drain regions.

[0015] According to some embodiments of the present invention, the ion concentrations in the source / drain region and the channel region are different.

[0016] According to some embodiments of the present invention, after forming the active layer, the method further includes forming a capacitor contact layer and a capacitor structure on the surface of the active layer.

[0017] The present invention also proposes a semiconductor structure.

[0018] A semiconductor structure according to an embodiment of the present invention includes: a substrate having a bit line metal layer; a first support layer having a word line metal layer formed on its surface and supporting the word line metal layer; and an active layer having an upper surface connected to a memory cell and a lower surface connected to the bit line metal layer, wherein the active layer at least partially surrounds the word line metal layer.

[0019] According to some embodiments of the present invention, the first support layer is partially located within the substrate and between the bit line metal layers.

[0020] According to some embodiments of the present invention, the semiconductor structure further includes a word line isolation structure formed within the active layer and located between the word line metal layers.

[0021] The present invention also proposes a three-dimensional memory, wherein the three-dimensional memory according to an embodiment of the present invention includes a plurality of semiconductor structures described in any of the above embodiments arranged in a stacked connection.

[0022] According to embodiments of the present invention, a semiconductor structure and its formation method, and a three-dimensional memory having the same, an active layer partially surrounds word lines and at least partially surrounds a metal layer surrounding the word lines, enabling the formation of a vertical-annular-channel (CAA) transistor. This increases the effective channel area of ​​the semiconductor structure, improves channel control capability, and enhances the performance of the semiconductor structure. Furthermore, the semiconductor structure formation method does not require a self-aligned process, and the formation processes of the word line metal layer and bit line metal layer are simple, simplifying the semiconductor structure process. This facilitates the formation of multilayer stacked transistor structures, increases the integration density of the semiconductor structure, and enables further miniaturization of the semiconductor structure size. Attached Figure Description

[0023] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present invention;

[0025] Figures 2-17 These are cross-sectional views corresponding to each step of the method for forming a semiconductor structure according to an embodiment of the present invention;

[0026] Figure label:

[0027] 100: Semiconductor structure;

[0028] 1: Substrate, 11: Substrate, 12: Oxide layer

[0029] 2: Bit line metal layer; 21: Bit line trench;

[0030] 31: First support layer; 32: Second support layer; 33: Word line isolation structure; 34: Second support groove;

[0031] 41: Initial word line metal layer; 42: Word line metal layer; 43: Word line isolation trench; 44: Sub-isolation trench; 45: Gate oxide layer;

[0032] 51: First sacrificial layer; 52: Second sacrificial layer; 53: Third sacrificial layer; 54: Second initial sacrificial layer;

[0033] 6: Active layer; 61: Source / drain region; 611: Source region; 612: Drain region; 62: Channel region.

[0034] 7: Capacitor structure. Detailed Implementation

[0035] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a semiconductor structure 100, its formation method, and a three-dimensional memory proposed in this invention.

[0036] A method for forming a semiconductor structure 100 according to an embodiment of the present invention will now be described with reference to the accompanying drawings.

[0037] like Figure 1 As shown, a method for forming a semiconductor structure 100 according to an embodiment of the present invention may include: step S1: providing a substrate 1, wherein the substrate 1 is provided with a bit line metal layer 2; step S2: forming a first support layer 31, wherein a word line metal layer 42 is formed on the surface of the first support layer 31, and the first support layer 31 supports the word line metal layer 42; step S4: forming an active layer 6, wherein the upper surface of the active layer 6 is connected to a memory cell, the lower surface of the active layer 6 is connected to the bit line metal layer 2, and the active layer 6 at least partially surrounds the word line metal layer 42.

[0038] Figures 2-17 The following are cross-sectional views corresponding to each step of the method for forming a semiconductor structure 100 according to an embodiment of the present invention, with reference to... Figures 2-17 A method for forming a semiconductor structure 100 according to an embodiment of the present invention is described in detail.

[0039] like Figures 2-3 As shown, step S1: Provide a substrate 1, wherein the substrate 1 is provided with a bit line metal layer 2, the bit line metal layer 2 may be formed within the substrate 1 or may be formed on the surface of the substrate 1, as shown in the figure. Figure 3 In the example shown, the bit line metal layer 2 is formed within the embedded substrate 1. In some embodiments of the invention, such as Figure 2As shown, the substrate 1 may include a substrate 11 and an oxide layer 12 formed on the substrate 11. The substrate 11 may be, but is not limited to, a silicon substrate. This specific embodiment uses a silicon substrate 11 as an example for illustration. In other embodiments, the substrate 11 may also be a semiconductor substrate 11 such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 11 is used to support the device structure thereon. The oxide layer 12 may be deposited on the upper surface of the substrate 11 using at least one of chemical vapor deposition, physical vapor deposition, and atomic layer deposition, and a planarization process is performed using chemical mechanical polishing to form the substrate 1. Optionally, the oxide layer 12 may be a silicon oxide layer, in which case multiple bit line metal layers 2 are isolated by the oxide layer 12.

[0040] In some embodiments, such as Figures 3-4 As shown, the substrate 1 is provided with a bit line metal layer 2. The step of forming the bit line metal layer 2 may include: forming a bit line trench 21 extending in a first direction in the substrate 1; and forming the bit line metal layer 2 in the bit line trench 21.

[0041] Specifically, such as Figure 3 As shown, at least one of dry etching or wet etching can be used to etch the substrate 1 to form bit line trenches 21 within the substrate 1. The bit line trenches 21 extend along a first direction, and the bit line trenches 21 can be formed as elongated strips or curved shapes, such as S-shapes, extending along the first direction; the present invention does not particularly limit this. Then, as... Figure 4 As shown, at least one of chemical vapor deposition, physical vapor deposition, and atomic layer deposition can be used to deposit a bit line metal layer 2 within the bit line trench 21, and the bit line metal layer 2 fills the bit line trench 21. In the case of... Figures 1-4 In the example shown, the substrate 1 includes a substrate 11 and an oxide layer 12 formed on the substrate 11. Bit line trenches 21 are formed in the oxide layer 12 and do not penetrate the oxide layer 12. Bit line metal layers 2 are located in the oxide layer 12 and part of the oxide layer 12 is located between the bit line metal layers 2 and the substrate 11. At this time, multiple bit line metal layers 2 are isolated by the oxide layer 12.

[0042] like Figures 5-8 As shown, step S2: A first support layer 31 is formed, and a word line metal layer 42 is formed on the surface of the first support layer 31. The first support layer 31 can be used to support the word line metal layer 42 located above the bit line metal layer 2. The first support layer 31 can be located on the substrate 1, and the word line metal layer 42 is located on the first support layer 31. Figure 5In the example shown, the first support layer 31 may be at least partially located within the substrate 1 and between the bit line metal layers 2, serving as an isolation structure for the subsequently formed active layer 6. The first support layer 31 is an insulating structure, and its height is not lower than the upper surface of the first sacrificial layer 51; for example, the upper surface of the first support layer 31 may be flush with the upper surface of the first sacrificial layer 51.

[0043] In some embodiments of the present invention, combined with Figures 5-8 As shown, the step of forming the word line metal layer 42 may include: forming a first sacrificial layer 51 on the surface of the substrate 1 and the bit line metal layer 2; forming a word line initial metal layer 41 on the surface of the first sacrificial layer 51 and the first support layer 31; forming a word line isolation trench 43 extending in a second direction, the word line isolation trench 43 penetrating the word line initial metal layer 41 and the first sacrificial layer 51, so as to form the word line metal layer 42 on the word line initial metal layer 41.

[0044] Specifically, such as Figure 5 As shown, a first sacrificial layer 51 can be deposited on the substrate 1 and the bit line metal layer 2. The first sacrificial layer 51 covers the upper surface of the bit line metal layer 2 and the exposed upper surface of the substrate 1. The material of the first sacrificial layer 51 can have a high selective etching ratio with the oxide layer 12, so as to facilitate the removal of the first sacrificial layer 51 in subsequent processes and prevent the oxide layer 12 and the bit line metal layer 2 from being etched during the etching of the first sacrificial layer 51, thereby affecting the structure and performance of the semiconductor structure 100.

[0045] like Figures 6-8 As shown, an initial word line metal layer 41 is deposited on the first sacrificial layer 51 and the first support layer 31. The initial word line metal layer 41 covers the upper surfaces of the first sacrificial layer 51 and the first support layer 31. Then, the initial word line metal layer 41 and the first sacrificial layer 51 can be etched to form a plurality of word line isolation trenches 43 extending along the second direction. At the same time, word line metal layers 42 are formed by etching the initial word line metal layer 41. The word line isolation trenches 43 are located between the word line metal layers 42 and penetrate the initial word line metal layer 41 and the first sacrificial layer 51. Both the word line isolation trenches 43 and the word line metal layers 42 extend along the second direction, wherein, as shown... Figure 8 As shown, the second direction can be perpendicular to the first direction.

[0046] In some embodiments of the present invention, the method of forming the semiconductor structure 100 further includes forming a word line isolation structure 33 within a word line isolation trench 43. The word line isolation structure 33 is located between word line metal layers 42 to provide isolation. Further, the word line isolation structure 33 may extend downward into the first sacrificial layer 51, such as... Figure 12As shown, the word line isolation structure 33 can extend downward to the upper surface of the bit line metal layer 2 and the oxide layer 12, so that after the active layer 6 is formed in the subsequent process, the word line isolation structure 33 can form the isolation structure of the active layer 6.

[0047] In some embodiments of the present invention, the first support layer 31 may be formed after the first sacrificial layer 51 is formed and before the initial metal layer 41 for word lines is formed on the surface of the first sacrificial layer 51 and the first support layer 31. The first support layer 31 may be formed within the first sacrificial layer 51 or within the first support layer 31 and the substrate 1, as long as it can serve to support the metal layer 42 for word lines.

[0048] In some specific examples of the present invention, the step of forming the first support layer 31 may include: etching the first sacrificial layer 51 to form a first support groove, and then forming the first support layer 31 in the first support groove. The first support layer 31 is located in the first sacrificial layer 51 and on the substrate 1. After forming the word line metal layer 42, the first sacrificial layer 51 may be removed, and the first support layer 31 is retained to support the word line metal layer 42. The first support layer 31 may be correspondingly formed on the oxide layer 12 between the bit line metal layers 2.

[0049] In other examples of the present invention, the step of forming the first support layer 31 may include: etching the first sacrificial layer 51 and etching downwards to stop within the oxide layer 12 of the substrate 1 to form a first support groove. The first support groove penetrates the first sacrificial layer 51 and is partially located within the oxide layer 12 between the bit line metal layers 2. The first support layer 31 is formed in the first support groove by filling or deposition. Thus, the first support layer 31 is located within the first sacrificial layer 51 and is partially located between the bit line metal layers 2. After the first sacrificial layer 51 is subsequently removed, the first support layer 31 can not only support the word line metal layer 42, but also form an isolation structure of the active layer 6 to play an isolation role, and can reduce signal transmission errors caused by parasitic capacitance between the word line metal layers 42.

[0050] Optionally, such as Figure 5 As shown, the thickness of the portion of the first support layer 31 located within the oxide layer 12 is not less than the thickness of the bit line metal layer 2, and the lower surface of the first support layer 31 is not higher than the lower surface of the bit line metal layer 2, thereby improving the isolation effect of the first support layer 31. Further, the material of the first support layer 31 can be at least one of a nitride material or a silicon oxynitride material. For example, the first support layer 31 can be a silicon nitride material or a silicon oxynitride material, or it can be a stacked material of silicon nitride and silicon oxide.

[0051] In some embodiments of the present invention, combined with Figures 7-15As shown, the steps for forming the active layer 6 may include: forming a second sacrificial layer 52 on the surface of the word line metal layer 42; forming a second support layer 32 within the second sacrificial layer 52; removing the first sacrificial layer 51 and the second sacrificial layer 52; and forming the active layer 6 on the surface of the bit line metal layer 2 and the surface of the word line metal layer 42. Specifically, as... Figures 7-8 As shown, at least one of chemical vapor deposition, physical vapor deposition, and atomic layer deposition can be used to form a second sacrificial layer 52 on the surface of the word line metal layer 42. This exposes the surface of the word line metal layer 42 after the second sacrificial layer 52 is subsequently removed, facilitating the formation of the active layer 6 surrounding the word line metal layer 42. Then, as... Figures 10-11 As shown, by etching the second sacrificial layer 52, a second support groove 34 can be formed within the second sacrificial layer 52, and a second support layer 32 can be formed within the second support groove 34. Then, as... Figures 12-14 As shown, after removing the first sacrificial layer 51 and the second sacrificial layer 52, the first support layer 31 and the second support layer 32 can jointly support the word line metal layer 42, while exposing the surface of the word line metal layer 42 and the upper surface of the bit line metal layer 2, and then as... Figure 15 As shown, an active layer 6 is formed on the upper surface of the bit line metal layer 2 and the surface of the word line metal layer 42. The active layer 6 is located on the surface of the bit line metal layer 2 and at least partially surrounds the word line metal layer 42 to form a vertical annular channel device structure (CAA, Channel-All-Around) transistor, thereby increasing the effective channel area of ​​the semiconductor structure 100, improving the channel control capability, and thus enhancing the performance of the semiconductor structure 100. Moreover, the method of forming the semiconductor structure 100 does not require a self-aligned process, and the formation process of the word line metal layer and the bit line metal layer is simple, which can simplify the semiconductor structure process, facilitate the formation of multilayer stacked transistor structures, improve the integration density of the semiconductor structure, and enable further miniaturization of the semiconductor structure size.

[0052] Optionally, the material of the second support layer 32 can be at least one of nitride material or oxynitride material. For example, the second support layer 32 can be silicon nitride material or silicon oxynitride material, or it can be a stacked material of silicon nitride material or silicon oxide material. The second support layer 32 can be a silicon nitride layer or a silicon oxynitride layer, or the second support layer 32 can also be a stacked composite layer of silicon nitride layer and silicon oxynitride layer.

[0053] Optionally, the active layer 6 can be made of an amorphous material, such as indium gallium zinc oxide (IGZO) or indium aluminum zinc oxide (IAlZO).

[0054] In some specific embodiments of the present invention, such as Figure 7As shown, after forming the initial metal layer 41 of the word line, and before forming the word line isolation trench 43, a second initial sacrificial layer 54 can be formed on the surface of the initial metal layer 41 of the word line. For example... Figure 8 As shown, in the step of forming the word line isolation trench 43, the second initial sacrificial layer 54, the word line initial metal layer 41 and the first sacrificial layer 51 are etched to form the word line isolation trench 43, and at the same time, the word line metal layer 42 and the second sacrificial layer 52 located on the surface of the word line metal layer 42 are formed. The word line isolation trench 43 penetrates the second sacrificial layer 52, the word line initial metal layer 41 and the first sacrificial layer 51.

[0055] In some embodiments of the present invention, such as Figure 9 As shown, a third sacrificial layer 53 can be formed within the word line isolation groove 43, and the third sacrificial layer 53 fills the word line isolation groove 43, as shown. Figure 10 As shown, the third sacrificial layer 53 and the second sacrificial layer 52 located on the upper surface of the word line metal layer 42 are etched to form a second support groove 34. The second support groove 34 is formed on the word line metal layer 42, wherein the second support groove 34 can extend along the first direction. The second support groove 34 is filled to form a second support layer 32. The second support layer 32 is located on the surface of the word line metal layer 42. Optionally, the second support 32 can be disposed vertically corresponding to the first support layer 31.

[0056] Then as Figure 11 As shown, the third sacrificial layer 53 and the second support layer 32 are etched to form a sub-isolation trench 44 within the third sacrificial layer 53. The sub-isolation trench 44 can extend along the second direction. In this step, the sub-isolation trench 44 is located within the third sacrificial layer 53 and within the word line isolation trench 43, and is located between the word line metal layers 42. Figure 11 In the example shown, a third sacrificial layer 53 may be spaced between the sub-isolation trench 44 and the word line metal layer 41. At this time, the first sacrificial layer 51, the third sacrificial layer 53, and the second sacrificial layer 52 together surround the surface of the word line metal layer 42. Specifically, the first sacrificial layer 51 is located on the lower surface of the word line metal layer 42, the second sacrificial layer 52 is located on the upper surface of the word line metal layer 42, and the third sacrificial layer 53 is located on the side of the word line metal layer 42. In this way, the surface of the word line metal layer 42 can be exposed when the first sacrificial layer 51, the third sacrificial layer 53, and the second sacrificial layer 52 are subsequently removed. In the step of forming the active layer 6, the formed active layer 6 can surround and encircle the word line metal layer 42.

[0057] like Figure 12 As shown, the sub-isolation trench 44 is filled to form the word line isolation structure 33, as... Figure 13As shown, after removing the first sacrificial layer 51, the second sacrificial layer 52, and the third sacrificial layer 53, the first support layer 31, the word line isolation structure 33, and the second support layer 32 jointly support the word line metal layer 42. After forming the active layer 6, the first support layer 31, the word line isolation structure 33, and the second support layer 32 can form the isolation structure of the active layer 6, wherein the sub-isolation trenches 44 intersect perpendicularly at the top of the second sacrificial layer 52. Further, as... Figure 12 As shown, the first support layer 31 and the second support layer 32 can both extend along the first direction, and the word line isolation structure 33 can extend along the second direction. In this way, the first support layer 31 and the second support layer 32 are both perpendicular to the word line isolation structure 33, so that the first support layer 31, the second support layer 32 and the word line isolation structure 33 can form a grid structure, which can not only serve as an isolation structure for the active layer 6, but also further improve the support effect for the active layer 6 and the word line metal layer 42, so as to further improve the structural stability of the semiconductor structure 100.

[0058] In some embodiments of the present invention, before forming the active layer 6, after selectively etching away the first sacrificial layer 51 and the second sacrificial layer 52, the first support layer 31, the word line isolation structure 33, and the second support layer 32 are retained. The method for forming the semiconductor structure 100 may further include: forming a gate oxide layer 45 on the surface of the word line metal layer 42 by at least one of chemical vapor deposition, physical vapor deposition, and atomic layer deposition. The gate oxide layer 45 is located on the surface of the word line metal layer 42, and the active layer 6 is formed on the surface of the gate oxide layer 45. The direction of the chemically deposited gas is the second direction, and the gas for depositing the gate oxide layer 45 is introduced through the gap between the word line metal layer 42, the first support layer 31, and the second support layer 32 as the inlet.

[0059] In some embodiments of the present invention, after forming the active layer 6, the method for forming the semiconductor structure 100 of the present invention further includes: ion implantation of the active layer 6 to form a source / drain region 61 and a channel region 62 surrounding the word line metal layer 42. Specifically, an ion implantation device can be used to implant the active layer 6 with ions of different depths, concentrations, and ion types to form the source / drain region 61 and the channel region 62. For example, ion implantation can be performed on a portion of the active layer 6 located on the surface of the bit line metal layer 2 and below the word line metal layer 42 to form a drain 612, ion implantation can be performed on a portion of the active layer 6 located on the word line metal layer 42 to form a source region 611, and ion implantation can be performed on the middle portion of the active layer 6 surrounding the word line metal layer 42 to form a channel region 62 surrounding the word line metal layer 42. In some examples of the present invention, the ion implantation concentrations of the source / drain region 61 and the channel region 62 are different.

[0060] In some embodiments of the present invention, the memory cell may include a capacitor structure, and after forming the active layer 6, the method further includes forming a capacitor contact layer and a capacitor structure 7 on the surface of the active layer 6, wherein the capacitor structure 7 is electrically connected to the active layer 6 through the capacitor contact layer. Furthermore, the semiconductor structures 100 may be stacked. For example, after forming the capacitor structure 7, the semiconductor structure 100 may be further formed on the capacitor structure 7 using the method described above, thereby realizing the formation of a three-dimensional stacked semiconductor memory device.

[0061] In some embodiments of the present invention, the surface of the active layer 6 may also contact other storage units, such as MTJ, phase change memory units, etc.

[0062] The present invention also proposes a semiconductor structure 100, which can be prepared by the semiconductor structure 100 formation method of the above embodiments.

[0063] The semiconductor structure 100 according to an embodiment of the present invention may include a substrate 1, a first support layer 31 and an active layer 6. The substrate 1 is provided with a bit line metal layer 2. A word line metal layer 42 is formed on the surface of the first support layer 31, and the first support layer 31 supports the word line metal layer 42. The upper surface of the active layer 6 is in contact with a memory cell, the lower surface of the active layer 6 is in contact with the bit line metal layer 2, and the active layer 6 at least partially surrounds the word line metal layer 42.

[0064] According to an embodiment of the present invention, in the semiconductor structure 100, the active layer 6 at least partially surrounds the word line metal layer 42, such that the channel region of the semiconductor structure 100 can at least partially surround the word line metal layer 42, thereby increasing the effective width of the channel region and thus improving the performance of the semiconductor structure 100.

[0065] In some embodiments of the present invention, the first support layer 31 is partially located within the substrate 1 and between the bit line metal layers 2, thereby the first support layer 31 can not only support the word line metal layer 42, but also form an isolation structure for the active layer 6.

[0066] In some embodiments of the present invention, the semiconductor structure 100 further includes a word line isolation structure 33, which is formed within the active layer 6 and located between the word line metal layers 42, such that the word line isolation structure 33 and the first support layer 31 can jointly support the word line metal layer 42, and the word line isolation structure 33 and the first support layer 31 can jointly constitute the isolation structure of the active layer 6.

[0067] The present invention also proposes a three-dimensional memory.

[0068] The three-dimensional memory according to an embodiment of the present invention includes a plurality of semiconductor structures 100 of the above embodiments arranged in a stacked manner. The plurality of semiconductor structures 100 are stacked and bonded by a hybrid bonding technology to further increase the storage density per unit area.

[0069] According to embodiments of the present invention, a semiconductor structure 100, its formation method, and a three-dimensional memory having the same, an active layer 6 partially surrounds word lines and at least partially surrounds the surrounding word line metal layer 42, enabling the formation of a vertical annular channel (CAA) transistor. This increases the effective channel area of ​​the semiconductor structure 100 and improves its performance. During operation, charge carriers pass through the annular channel region 62, conducting between the source and drain regions 611. Furthermore, the formation method of the semiconductor structure 100 does not require complex alignment processes, and the formation processes of the word line metal layer and bit line metal layer are simple, simplifying the semiconductor structure manufacturing process. This facilitates the formation of multilayer stacked transistor structures, increases the integration density of the semiconductor structure, and enables further miniaturization of the semiconductor structure size.

[0070] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate having a bit line metal layer; A first support layer is formed, and a word line metal layer is formed on the surface of the first support layer, and the first support layer supports the word line metal layer. An active layer is formed, the upper surface of which is connected to the memory cell, the lower surface of which is connected to the bit line metal layer, and the active layer at least partially surrounds the word line metal layer. The steps for forming the bit line metal layer include: A bitline trench extending in a first direction is formed on the substrate; A bit line metal layer is formed within the bit line trench; The steps for forming the word line metal layer include: A first sacrificial layer is formed on the surface of the substrate and the bit line metal layer; Initial metal layers for word lines are formed on the surfaces of the first sacrificial layer and the first support layer; A word line isolation trench is formed extending in a second direction, the word line isolation trench penetrating the initial word line metal layer and the first sacrificial layer, to form a word line metal layer in the initial word line metal layer.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The substrate includes a substrate and an oxide layer formed on the substrate, wherein the bit line trench is formed within the oxide layer.

3. The method for forming a semiconductor structure according to claim 1, characterized in that, In the step of forming the first support layer, the first support layer is formed within the first sacrificial layer and located on the substrate. After the word line metal layer is formed, the first sacrificial layer is removed, and the first support layer supports the word line metal layer.

4. The method for forming a semiconductor structure according to claim 1, characterized in that, The first support layer extends along the first direction and is at least partially located within the substrate and formed between the bit line metal layers.

5. The method for forming a semiconductor structure according to claim 1, characterized in that, Also includes: A word line isolation structure is formed within the word line isolation groove.

6. The method for forming a semiconductor structure according to claim 5, characterized in that, The steps to form an active layer include: A second sacrificial layer is formed on the surface of the word line metal layer; A second support layer is formed within the second sacrificial layer; Remove the first sacrificial layer and the second sacrificial layer; The active layer is formed on the surface of the bit line metal layer and the surface of the word line metal layer.

7. The method for forming a semiconductor structure according to claim 6, characterized in that, In the step of forming the word line isolation trench, the word line isolation trench penetrates the second sacrificial layer, the initial word line metal layer, and the first sacrificial layer; After the first sacrificial layer and the second sacrificial layer are removed, the first support layer, the word line isolation structure, and the second support layer support the word line metal layer.

8. The method for forming a semiconductor structure according to claim 1, characterized in that, Before forming the active layer, the method further includes forming a gate oxide layer on the surface of the word line metal layer.

9. The method for forming a semiconductor structure according to claim 1, characterized in that, Ion implantation is performed on the active layer to form source / drain regions.

10. The method for forming a semiconductor structure according to claim 9, characterized in that, The ion concentrations in the source / drain region and the channel region are different.

11. The method for forming a semiconductor structure according to claim 1, characterized in that, After forming the active layer, the method further includes forming a capacitor contact layer and a capacitor structure on the surface of the active layer.

12. A semiconductor structure formed using the method for forming a semiconductor structure according to any one of claims 1-11, characterized in that, include: A substrate having a bit line metal layer; A first support layer, on the surface of which a character line metal layer is formed, and the first support layer supports the character line metal layer; An active layer, the upper surface of which is connected to a memory cell, the lower surface of which is connected to the bit line metal layer, and the active layer at least partially surrounds the word line metal layer.

13. The semiconductor structure according to claim 12, characterized in that, The first support layer is located within the substrate and between the bit line metal layers.

14. The semiconductor structure according to claim 12, characterized in that, It also includes a word line isolation structure formed within the active layer and located between the word line metal layers.

15. A three-dimensional memory, characterized in that, The semiconductor structure included in any one of claims 12-14 includes a stacked interconnect configuration.

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